actions,owl-sirq.yaml 1.7 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Actions Semi Owl SoCs SIRQ interrupt controller
  7. maintainers:
  8. - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  9. - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
  10. description: |
  11. This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
  12. and S900) and provides support for handling up to 3 external interrupt lines.
  13. properties:
  14. compatible:
  15. enum:
  16. - actions,s500-sirq
  17. - actions,s700-sirq
  18. - actions,s900-sirq
  19. reg:
  20. maxItems: 1
  21. interrupt-controller: true
  22. '#interrupt-cells':
  23. const: 2
  24. description:
  25. The first cell is the input IRQ number, between 0 and 2, while the second
  26. cell is the trigger type as defined in interrupt.txt in this directory.
  27. interrupts:
  28. description: |
  29. Contains the GIC SPI IRQs mapped to the external interrupt lines.
  30. They shall be specified sequentially from output 0 to 2.
  31. minItems: 3
  32. maxItems: 3
  33. required:
  34. - compatible
  35. - reg
  36. - interrupt-controller
  37. - '#interrupt-cells'
  38. - interrupts
  39. additionalProperties: false
  40. examples:
  41. - |
  42. #include <dt-bindings/interrupt-controller/arm-gic.h>
  43. sirq: interrupt-controller@b01b0200 {
  44. compatible = "actions,s500-sirq";
  45. reg = <0xb01b0200 0x4>;
  46. interrupt-controller;
  47. #interrupt-cells = <2>;
  48. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
  49. <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
  50. <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
  51. };
  52. ...