intel,ce4100-ioapic.yaml 1.6 KB

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  1. # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
  7. maintainers:
  8. - Rahul Tanwar <rtanwar@maxlinear.com>
  9. description: |
  10. Intel's Advanced Programmable Interrupt Controller (APIC) is a
  11. family of interrupt controllers. The APIC is a split
  12. architecture design, with a local component (LAPIC) integrated
  13. into the processor itself and an external I/O APIC. Local APIC
  14. (lapic) receives interrupts from the processor's interrupt pins,
  15. from internal sources and from an external I/O APIC (ioapic).
  16. And it sends these to the processor core for handling.
  17. See [1] Chapter 8 for more details.
  18. Many of the Intel's generic devices like hpet, ioapic, lapic have
  19. the ce4100 name in their compatible property names because they
  20. first appeared in CE4100 SoC.
  21. This schema defines bindings for I/O APIC interrupt controller.
  22. [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
  23. properties:
  24. compatible:
  25. const: intel,ce4100-ioapic
  26. reg:
  27. maxItems: 1
  28. interrupt-controller: true
  29. '#interrupt-cells':
  30. const: 2
  31. interrupts:
  32. maxItems: 1
  33. required:
  34. - compatible
  35. - reg
  36. - interrupt-controller
  37. - '#interrupt-cells'
  38. additionalProperties: false
  39. examples:
  40. - |
  41. ioapic1: interrupt-controller@fec00000 {
  42. compatible = "intel,ce4100-ioapic";
  43. reg = <0xfec00000 0x1000>;
  44. interrupt-controller;
  45. #interrupt-cells = <2>;
  46. };