intel,ce4100-lapic.yaml 2.3 KB

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  1. # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)
  7. maintainers:
  8. - Rahul Tanwar <rtanwar@maxlinear.com>
  9. description: |
  10. Intel's Advanced Programmable Interrupt Controller (APIC) is a
  11. family of interrupt controllers. The APIC is a split
  12. architecture design, with a local component (LAPIC) integrated
  13. into the processor itself and an external I/O APIC. Local APIC
  14. (lapic) receives interrupts from the processor's interrupt pins,
  15. from internal sources and from an external I/O APIC (ioapic).
  16. And it sends these to the processor core for handling.
  17. See [1] Chapter 8 for more details.
  18. Many of the Intel's generic devices like hpet, ioapic, lapic have
  19. the ce4100 name in their compatible property names because they
  20. first appeared in CE4100 SoC.
  21. This schema defines bindings for local APIC interrupt controller.
  22. [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
  23. properties:
  24. compatible:
  25. const: intel,ce4100-lapic
  26. reg:
  27. maxItems: 1
  28. interrupt-controller: true
  29. '#interrupt-cells':
  30. const: 2
  31. intel,virtual-wire-mode:
  32. description: Intel defines a few possible interrupt delivery
  33. modes. With respect to boot/init time, mainly two interrupt
  34. delivery modes are possible.
  35. PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
  36. Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
  37. For ACPI or MPS spec compliant systems, it is figured out by some read
  38. only bit field/s available in their respective defined data structures.
  39. For OF based systems, it is by default set to PIC mode.
  40. But if this optional boolean property is set, then the interrupt delivery
  41. mode is configured to virtual wire compatibility mode.
  42. type: boolean
  43. required:
  44. - compatible
  45. - reg
  46. - interrupt-controller
  47. - '#interrupt-cells'
  48. additionalProperties: false
  49. examples:
  50. - |
  51. lapic0: interrupt-controller@fee00000 {
  52. compatible = "intel,ce4100-lapic";
  53. reg = <0xfee00000 0x1000>;
  54. interrupt-controller;
  55. #interrupt-cells = <2>;
  56. intel,virtual-wire-mode;
  57. };