marvell,mpic.yaml 1.5 KB

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  1. # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller
  7. maintainers:
  8. - Marek Behún <kabel@kernel.org>
  9. description: |
  10. The top-level interrupt controller on Marvell Armada 370 and XP. On these
  11. platforms it also provides inter-processor interrupts.
  12. On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC.
  13. Provides MSI handling for the PCIe controllers.
  14. properties:
  15. compatible:
  16. const: marvell,mpic
  17. reg:
  18. items:
  19. - description: main registers
  20. - description: per-cpu registers
  21. interrupts:
  22. items:
  23. - description: |
  24. Parent interrupt on platforms where MPIC is not the top-level
  25. interrupt controller.
  26. interrupt-controller: true
  27. '#interrupt-cells':
  28. const: 1
  29. msi-controller: true
  30. required:
  31. - compatible
  32. - reg
  33. - interrupt-controller
  34. - '#interrupt-cells'
  35. - msi-controller
  36. additionalProperties: false
  37. examples:
  38. - |
  39. #include <dt-bindings/interrupt-controller/arm-gic.h>
  40. #include <dt-bindings/interrupt-controller/irq.h>
  41. interrupt-controller@20a00 {
  42. compatible = "marvell,mpic";
  43. reg = <0x20a00 0x2d0>, <0x21070 0x58>;
  44. interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
  45. interrupt-controller;
  46. #interrupt-cells = <1>;
  47. msi-controller;
  48. };