microchip,sama7g5-eic.yaml 1.7 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/interrupt-controller/microchip,sama7g5-eic.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Microchip External Interrupt Controller
  7. maintainers:
  8. - Claudiu Beznea <claudiu.beznea@microchip.com>
  9. description:
  10. This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides
  11. support for handling up to 2 external interrupt lines.
  12. properties:
  13. compatible:
  14. enum:
  15. - microchip,sama7g5-eic
  16. reg:
  17. maxItems: 1
  18. interrupt-controller: true
  19. '#interrupt-cells':
  20. const: 2
  21. description:
  22. The first cell is the input IRQ number (between 0 and 1), the second cell
  23. is the trigger type as defined in interrupt.txt present in this directory.
  24. interrupts:
  25. description: |
  26. Contains the GIC SPI IRQs mapped to the external interrupt lines. They
  27. should be specified sequentially from output 0 to output 1.
  28. minItems: 2
  29. maxItems: 2
  30. clocks:
  31. maxItems: 1
  32. clock-names:
  33. const: pclk
  34. required:
  35. - compatible
  36. - reg
  37. - interrupt-controller
  38. - '#interrupt-cells'
  39. - interrupts
  40. - clocks
  41. - clock-names
  42. additionalProperties: false
  43. examples:
  44. - |
  45. #include <dt-bindings/clock/at91.h>
  46. #include <dt-bindings/interrupt-controller/arm-gic.h>
  47. eic: interrupt-controller@e1628000 {
  48. compatible = "microchip,sama7g5-eic";
  49. reg = <0xe1628000 0x100>;
  50. interrupt-parent = <&gic>;
  51. interrupt-controller;
  52. #interrupt-cells = <2>;
  53. interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  54. <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  55. clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
  56. clock-names = "pclk";
  57. };
  58. ...