qcom,mpm.yaml 3.1 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Qualcom MPM Interrupt Controller
  7. maintainers:
  8. - Shawn Guo <shawn.guo@linaro.org>
  9. description:
  10. Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
  11. MSM Power Manager (MPM) that is in always-on domain. In addition to managing
  12. resources during sleep, the hardware also has an interrupt controller that
  13. monitors the interrupts when the system is asleep, wakes up the APSS when
  14. one of these interrupts occur and replays it to GIC interrupt controller
  15. after GIC becomes operational.
  16. allOf:
  17. - $ref: /schemas/interrupt-controller.yaml#
  18. properties:
  19. compatible:
  20. items:
  21. - const: qcom,mpm
  22. reg:
  23. maxItems: 1
  24. description:
  25. Specifies the base address and size of vMPM registers in RPM MSG RAM.
  26. deprecated: true
  27. qcom,rpm-msg-ram:
  28. $ref: /schemas/types.yaml#/definitions/phandle
  29. description:
  30. Phandle to the APSS MPM slice of the RPM Message RAM
  31. interrupts:
  32. maxItems: 1
  33. description:
  34. Specify the IRQ used by RPM to wakeup APSS.
  35. mboxes:
  36. maxItems: 1
  37. description:
  38. Specify the mailbox used to notify RPM for writing vMPM registers.
  39. interrupt-controller: true
  40. '#interrupt-cells':
  41. const: 2
  42. description:
  43. The first cell is the MPM pin number for the interrupt, and the second
  44. is the trigger type.
  45. qcom,mpm-pin-count:
  46. description:
  47. Specify the total MPM pin count that a SoC supports.
  48. $ref: /schemas/types.yaml#/definitions/uint32
  49. qcom,mpm-pin-map:
  50. description:
  51. A set of MPM pin numbers and the corresponding GIC SPIs.
  52. $ref: /schemas/types.yaml#/definitions/uint32-matrix
  53. items:
  54. items:
  55. - description: MPM pin number
  56. - description: GIC SPI number for the MPM pin
  57. '#power-domain-cells':
  58. const: 0
  59. required:
  60. - compatible
  61. - interrupts
  62. - mboxes
  63. - interrupt-controller
  64. - '#interrupt-cells'
  65. - qcom,mpm-pin-count
  66. - qcom,mpm-pin-map
  67. - qcom,rpm-msg-ram
  68. additionalProperties: false
  69. examples:
  70. - |
  71. #include <dt-bindings/interrupt-controller/arm-gic.h>
  72. remoteproc-rpm {
  73. compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
  74. glink-edge {
  75. compatible = "qcom,glink-rpm";
  76. interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
  77. qcom,rpm-msg-ram = <&rpm_msg_ram>;
  78. mboxes = <&apcs_glb 0>;
  79. };
  80. mpm: interrupt-controller {
  81. compatible = "qcom,mpm";
  82. qcom,rpm-msg-ram = <&apss_mpm>;
  83. interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
  84. mboxes = <&apcs_glb 1>;
  85. interrupt-controller;
  86. #interrupt-cells = <2>;
  87. interrupt-parent = <&intc>;
  88. qcom,mpm-pin-count = <96>;
  89. qcom,mpm-pin-map = <2 275>,
  90. <5 296>,
  91. <12 422>,
  92. <24 79>,
  93. <86 183>,
  94. <91 260>;
  95. #power-domain-cells = <0>;
  96. };
  97. };