video-interfaces.yaml 8.1 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Common Properties for Video Receiver and Transmitter Interface Endpoints
  7. maintainers:
  8. - Sakari Ailus <sakari.ailus@linux.intel.com>
  9. - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10. description: |
  11. Video data pipelines usually consist of external devices, e.g. camera sensors,
  12. controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including
  13. video DMA engines and video data processors.
  14. SoC internal blocks are described by DT nodes, placed similarly to other SoC
  15. blocks. External devices are represented as child nodes of their respective
  16. bus controller nodes, e.g. I2C.
  17. Data interfaces on all video devices are described by their child 'port' nodes.
  18. Configuration of a port depends on other devices participating in the data
  19. transfer and is described by 'endpoint' subnodes.
  20. device {
  21. ...
  22. ports {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. port@0 {
  26. ...
  27. endpoint@0 { ... };
  28. endpoint@1 { ... };
  29. };
  30. port@1 { ... };
  31. };
  32. };
  33. If a port can be configured to work with more than one remote device on the same
  34. bus, an 'endpoint' child node must be provided for each of them. If more than
  35. one port is present in a device node or there is more than one endpoint at a
  36. port, or port node needs to be associated with a selected hardware interface,
  37. a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
  38. used.
  39. All 'port' nodes can be grouped under optional 'ports' node, which allows to
  40. specify #address-cells, #size-cells properties independently for the 'port'
  41. and 'endpoint' nodes and any child device nodes a device might have.
  42. Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
  43. phandles. An endpoint subnode of a device contains all properties needed for
  44. configuration of this device for data exchange with other device. In most
  45. cases properties at the peer 'endpoint' nodes will be identical, however they
  46. might need to be different when there is any signal modifications on the bus
  47. between two devices, e.g. there are logic signal inverters on the lines.
  48. It is allowed for multiple endpoints at a port to be active simultaneously,
  49. where supported by a device. For example, in case where a data interface of
  50. a device is partitioned into multiple data busses, e.g. 16-bit input port
  51. divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
  52. and data-shift properties can be used to assign physical data lines to each
  53. endpoint node (logical bus).
  54. Documenting bindings for devices
  55. --------------------------------
  56. All required and optional bindings the device supports shall be explicitly
  57. documented in device DT binding documentation. This also includes port and
  58. endpoint nodes for the device, including unit-addresses and reg properties
  59. where relevant.
  60. allOf:
  61. - $ref: /schemas/graph.yaml#/$defs/endpoint-base
  62. properties:
  63. slave-mode:
  64. type: boolean
  65. description:
  66. Indicates that the link is run in slave mode. The default when this
  67. property is not specified is master mode. In the slave mode horizontal and
  68. vertical synchronization signals are provided to the slave device (data
  69. source) by the master device (data sink). In the master mode the data
  70. source device is also the source of the synchronization signals.
  71. bus-type:
  72. $ref: /schemas/types.yaml#/definitions/uint32
  73. enum:
  74. - 1 # MIPI CSI-2 C-PHY
  75. - 2 # MIPI CSI1
  76. - 3 # CCP2
  77. - 4 # MIPI CSI-2 D-PHY
  78. - 5 # Parallel
  79. - 6 # BT.656
  80. - 7 # DPI
  81. description:
  82. Data bus type.
  83. bus-width:
  84. $ref: /schemas/types.yaml#/definitions/uint32
  85. maximum: 64
  86. description:
  87. Number of data lines actively used, valid for the parallel busses.
  88. data-shift:
  89. $ref: /schemas/types.yaml#/definitions/uint32
  90. maximum: 64
  91. description:
  92. On the parallel data busses, if bus-width is used to specify the number of
  93. data lines, data-shift can be used to specify which data lines are used,
  94. e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used.
  95. hsync-active:
  96. $ref: /schemas/types.yaml#/definitions/uint32
  97. enum: [ 0, 1 ]
  98. description:
  99. Active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
  100. vsync-active:
  101. $ref: /schemas/types.yaml#/definitions/uint32
  102. enum: [ 0, 1 ]
  103. description:
  104. Active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. Note,
  105. that if HSYNC and VSYNC polarities are not specified, embedded
  106. synchronization may be required, where supported.
  107. data-active:
  108. $ref: /schemas/types.yaml#/definitions/uint32
  109. enum: [ 0, 1 ]
  110. description:
  111. Similar to HSYNC and VSYNC, specifies data line polarity.
  112. data-enable-active:
  113. $ref: /schemas/types.yaml#/definitions/uint32
  114. enum: [ 0, 1 ]
  115. description:
  116. Similar to HSYNC and VSYNC, specifies the data enable signal polarity.
  117. field-even-active:
  118. $ref: /schemas/types.yaml#/definitions/uint32
  119. enum: [ 0, 1 ]
  120. description:
  121. Field signal level during the even field data transmission.
  122. pclk-sample:
  123. $ref: /schemas/types.yaml#/definitions/uint32
  124. enum: [ 0, 1, 2 ]
  125. description:
  126. Sample data on falling (0), rising (1) or both (2) edges of the pixel
  127. clock signal.
  128. sync-on-green-active:
  129. $ref: /schemas/types.yaml#/definitions/uint32
  130. enum: [ 0, 1 ]
  131. description:
  132. Active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively.
  133. data-lanes:
  134. $ref: /schemas/types.yaml#/definitions/uint32-array
  135. minItems: 1
  136. maxItems: 8
  137. uniqueItems: true
  138. items:
  139. # Assume up to 9 physical lane indices
  140. maximum: 8
  141. description:
  142. An array of physical data lane indexes. Position of an entry determines
  143. the logical lane number, while the value of an entry indicates physical
  144. lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
  145. assuming the clock lane is on hardware lane 0. If the hardware does not
  146. support lane reordering, monotonically incremented values shall be used
  147. from 0 or 1 onwards, depending on whether or not there is also a clock
  148. lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
  149. clock-lanes:
  150. $ref: /schemas/types.yaml#/definitions/uint32
  151. # Assume up to 9 physical lane indices
  152. maximum: 8
  153. description:
  154. Physical clock lane index. Position of an entry determines the logical
  155. lane number, while the value of an entry indicates physical lane, e.g. for
  156. a MIPI CSI-2 bus we could have "clock-lanes = <0>;", which places the
  157. clock lane on hardware lane 0. This property is valid for serial busses
  158. only (e.g. MIPI CSI-2).
  159. clock-noncontinuous:
  160. type: boolean
  161. description:
  162. Allow MIPI CSI-2 non-continuous clock mode.
  163. link-frequencies:
  164. $ref: /schemas/types.yaml#/definitions/uint64-array
  165. description:
  166. Allowed data bus frequencies. For MIPI CSI-2, for instance, this is the
  167. actual frequency of the bus, not bits per clock per lane value. An array
  168. of 64-bit unsigned integers.
  169. lane-polarities:
  170. $ref: /schemas/types.yaml#/definitions/uint32-array
  171. minItems: 1
  172. maxItems: 9
  173. items:
  174. enum: [ 0, 1 ]
  175. description:
  176. An array of polarities of the lanes starting from the clock lane and
  177. followed by the data lanes in the same order as in data-lanes. Valid
  178. values are 0 (normal) and 1 (inverted). The length of the array should be
  179. the combined length of data-lanes and clock-lanes properties. If the
  180. lane-polarities property is omitted, the value must be interpreted as 0
  181. (normal). This property is valid for serial busses only.
  182. strobe:
  183. $ref: /schemas/types.yaml#/definitions/uint32
  184. enum: [ 0, 1 ]
  185. description:
  186. Whether the clock signal is used as clock (0) or strobe (1). Used with
  187. CCP2, for instance.
  188. additionalProperties: true