sifive-serial.yaml 1.4 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: SiFive asynchronous serial interface (UART)
  7. maintainers:
  8. - Pragnesh Patel <pragnesh.patel@sifive.com>
  9. - Paul Walmsley <paul.walmsley@sifive.com>
  10. - Palmer Dabbelt <palmer@sifive.com>
  11. allOf:
  12. - $ref: serial.yaml#
  13. properties:
  14. compatible:
  15. items:
  16. - enum:
  17. - sifive,fu540-c000-uart
  18. - sifive,fu740-c000-uart
  19. - canaan,k210-uarths
  20. - const: sifive,uart0
  21. description:
  22. Should be something similar to "sifive,<chip>-uart"
  23. for the UART as integrated on a particular chip,
  24. and "sifive,uart<version>" for the general UART IP
  25. block programming model.
  26. UART HDL that corresponds to the IP block version
  27. numbers can be found here -
  28. https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
  29. reg:
  30. maxItems: 1
  31. interrupts:
  32. maxItems: 1
  33. clocks:
  34. maxItems: 1
  35. required:
  36. - compatible
  37. - reg
  38. - interrupts
  39. - clocks
  40. unevaluatedProperties: false
  41. examples:
  42. - |
  43. #include <dt-bindings/clock/sifive-fu540-prci.h>
  44. serial@10010000 {
  45. compatible = "sifive,fu540-c000-uart", "sifive,uart0";
  46. interrupt-parent = <&plic0>;
  47. interrupts = <80>;
  48. reg = <0x10010000 0x1000>;
  49. clocks = <&prci FU540_PRCI_CLK_TLCLK>;
  50. };
  51. ...