arm,arch_timer_mmio.yaml 3.2 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: ARM memory mapped architected timer
  7. maintainers:
  8. - Marc Zyngier <marc.zyngier@arm.com>
  9. - Mark Rutland <mark.rutland@arm.com>
  10. description: |+
  11. ARM cores may have a memory mapped architected timer, which provides up to 8
  12. frames with a physical and optional virtual timer per frame.
  13. The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
  14. properties:
  15. compatible:
  16. items:
  17. - enum:
  18. - arm,armv7-timer-mem
  19. reg:
  20. maxItems: 1
  21. description: The control frame base address
  22. '#address-cells':
  23. enum: [1, 2]
  24. '#size-cells':
  25. const: 1
  26. ranges: true
  27. clock-frequency:
  28. description: The frequency of the main counter, in Hz. Should be present
  29. only where necessary to work around broken firmware which does not configure
  30. CNTFRQ on all CPUs to a uniform correct value. Use of this property is
  31. strongly discouraged; fix your firmware unless absolutely impossible.
  32. always-on:
  33. type: boolean
  34. description: If present, the timer is powered through an always-on power
  35. domain, therefore it never loses context.
  36. arm,cpu-registers-not-fw-configured:
  37. type: boolean
  38. description: Firmware does not initialize any of the generic timer CPU
  39. registers, which contain their architecturally-defined reset values. Only
  40. supported for 32-bit systems which follow the ARMv7 architected reset
  41. values.
  42. arm,no-tick-in-suspend:
  43. type: boolean
  44. description: The main counter does not tick when the system is in
  45. low-power system suspend on some SoCs. This behavior does not match the
  46. Architecture Reference Manual's specification that the system counter "must
  47. be implemented in an always-on power domain."
  48. patternProperties:
  49. '^frame@[0-9a-f]+$':
  50. type: object
  51. additionalProperties: false
  52. description: A timer node has up to 8 frame sub-nodes, each with the following properties.
  53. properties:
  54. frame-number:
  55. $ref: /schemas/types.yaml#/definitions/uint32
  56. minimum: 0
  57. maximum: 7
  58. interrupts:
  59. minItems: 1
  60. items:
  61. - description: physical timer irq
  62. - description: virtual timer irq
  63. reg:
  64. minItems: 1
  65. items:
  66. - description: 1st view base address
  67. - description: 2nd optional view base address
  68. required:
  69. - frame-number
  70. - interrupts
  71. - reg
  72. required:
  73. - compatible
  74. - reg
  75. - '#address-cells'
  76. - '#size-cells'
  77. additionalProperties: false
  78. examples:
  79. - |
  80. timer@f0000000 {
  81. compatible = "arm,armv7-timer-mem";
  82. #address-cells = <1>;
  83. #size-cells = <1>;
  84. ranges = <0 0xf0001000 0x1000>;
  85. reg = <0xf0000000 0x1000>;
  86. clock-frequency = <50000000>;
  87. frame@0 {
  88. frame-number = <0>;
  89. interrupts = <0 13 0x8>,
  90. <0 14 0x8>;
  91. reg = <0x0000 0x1000>,
  92. <0x1000 0x1000>;
  93. };
  94. frame@2000 {
  95. frame-number = <1>;
  96. interrupts = <0 15 0x8>;
  97. reg = <0x2000 0x1000>;
  98. };
  99. };
  100. ...