renesas,ostm.yaml 1.8 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/timer/renesas,ostm.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Renesas OS Timer (OSTM)
  7. maintainers:
  8. - Chris Brandt <chris.brandt@renesas.com>
  9. - Geert Uytterhoeven <geert+renesas@glider.be>
  10. description:
  11. The OSTM is a multi-channel 32-bit timer/counter with fixed clock source that
  12. can operate in either interval count down timer or free-running compare match
  13. mode.
  14. Channels are independent from each other.
  15. properties:
  16. compatible:
  17. items:
  18. - enum:
  19. - renesas,r7s72100-ostm # RZ/A1H
  20. - renesas,r7s9210-ostm # RZ/A2M
  21. - renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five
  22. - renesas,r9a07g044-ostm # RZ/G2{L,LC}
  23. - renesas,r9a07g054-ostm # RZ/V2L
  24. - renesas,r9a09g057-ostm # RZ/V2H(P)
  25. - const: renesas,ostm # Generic
  26. reg:
  27. maxItems: 1
  28. interrupts:
  29. maxItems: 1
  30. clocks:
  31. maxItems: 1
  32. power-domains:
  33. maxItems: 1
  34. resets:
  35. maxItems: 1
  36. required:
  37. - compatible
  38. - reg
  39. - interrupts
  40. - clocks
  41. - power-domains
  42. if:
  43. properties:
  44. compatible:
  45. contains:
  46. enum:
  47. - renesas,r9a07g043-ostm
  48. - renesas,r9a07g044-ostm
  49. - renesas,r9a07g054-ostm
  50. - renesas,r9a09g057-ostm
  51. then:
  52. required:
  53. - resets
  54. additionalProperties: false
  55. examples:
  56. - |
  57. #include <dt-bindings/clock/r7s72100-clock.h>
  58. #include <dt-bindings/interrupt-controller/arm-gic.h>
  59. ostm0: timer@fcfec000 {
  60. compatible = "renesas,r7s72100-ostm", "renesas,ostm";
  61. reg = <0xfcfec000 0x30>;
  62. interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
  63. clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
  64. power-domains = <&cpg_clocks>;
  65. };