tegra20-trimslice.dts 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/leds/common.h>
  5. #include "tegra20.dtsi"
  6. #include "tegra20-cpu-opp.dtsi"
  7. / {
  8. model = "Compulab TrimSlice board";
  9. compatible = "compulab,trimslice", "nvidia,tegra20";
  10. aliases {
  11. rtc0 = "/i2c@7000c500/rtc@56";
  12. rtc1 = "/rtc@7000e000";
  13. serial0 = &uarta;
  14. };
  15. chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. memory@0 {
  19. reg = <0x00000000 0x40000000>;
  20. };
  21. host1x@50000000 {
  22. hdmi@54280000 {
  23. status = "okay";
  24. vdd-supply = <&hdmi_vdd_reg>;
  25. pll-supply = <&hdmi_pll_reg>;
  26. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  27. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  28. GPIO_ACTIVE_HIGH>;
  29. };
  30. };
  31. pinmux@70000014 {
  32. pinctrl-names = "default";
  33. pinctrl-0 = <&state_default>;
  34. state_default: pinmux {
  35. ata {
  36. nvidia,pins = "ata";
  37. nvidia,function = "ide";
  38. };
  39. atb {
  40. nvidia,pins = "atb", "gma";
  41. nvidia,function = "sdio4";
  42. };
  43. atc {
  44. nvidia,pins = "atc", "gmb";
  45. nvidia,function = "nand";
  46. };
  47. atd {
  48. nvidia,pins = "atd", "ate", "gme", "pta";
  49. nvidia,function = "gmi";
  50. };
  51. cdev1 {
  52. nvidia,pins = "cdev1";
  53. nvidia,function = "plla_out";
  54. };
  55. cdev2 {
  56. nvidia,pins = "cdev2";
  57. nvidia,function = "pllp_out4";
  58. };
  59. crtp {
  60. nvidia,pins = "crtp";
  61. nvidia,function = "crt";
  62. };
  63. csus {
  64. nvidia,pins = "csus";
  65. nvidia,function = "vi_sensor_clk";
  66. };
  67. dap1 {
  68. nvidia,pins = "dap1";
  69. nvidia,function = "dap1";
  70. };
  71. dap2 {
  72. nvidia,pins = "dap2";
  73. nvidia,function = "dap2";
  74. };
  75. dap3 {
  76. nvidia,pins = "dap3";
  77. nvidia,function = "dap3";
  78. };
  79. dap4 {
  80. nvidia,pins = "dap4";
  81. nvidia,function = "dap4";
  82. };
  83. ddc {
  84. nvidia,pins = "ddc";
  85. nvidia,function = "i2c2";
  86. };
  87. dta {
  88. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  89. nvidia,function = "vi";
  90. };
  91. dtf {
  92. nvidia,pins = "dtf";
  93. nvidia,function = "i2c3";
  94. };
  95. gmc {
  96. nvidia,pins = "gmc", "gmd";
  97. nvidia,function = "sflash";
  98. };
  99. gpu {
  100. nvidia,pins = "gpu";
  101. nvidia,function = "uarta";
  102. };
  103. gpu7 {
  104. nvidia,pins = "gpu7";
  105. nvidia,function = "rtck";
  106. };
  107. gpv {
  108. nvidia,pins = "gpv", "slxa", "slxk";
  109. nvidia,function = "pcie";
  110. };
  111. hdint {
  112. nvidia,pins = "hdint";
  113. nvidia,function = "hdmi";
  114. };
  115. i2cp {
  116. nvidia,pins = "i2cp";
  117. nvidia,function = "i2cp";
  118. };
  119. irrx {
  120. nvidia,pins = "irrx", "irtx";
  121. nvidia,function = "uartb";
  122. };
  123. kbca {
  124. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  125. "kbce", "kbcf";
  126. nvidia,function = "kbc";
  127. };
  128. lcsn {
  129. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  130. "ld3", "ld4", "ld5", "ld6", "ld7",
  131. "ld8", "ld9", "ld10", "ld11", "ld12",
  132. "ld13", "ld14", "ld15", "ld16", "ld17",
  133. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  134. "lhs", "lm0", "lm1", "lpp", "lpw0",
  135. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  136. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  137. "lvs";
  138. nvidia,function = "displaya";
  139. };
  140. owc {
  141. nvidia,pins = "owc", "uac";
  142. nvidia,function = "rsvd2";
  143. };
  144. pmc {
  145. nvidia,pins = "pmc";
  146. nvidia,function = "pwr_on";
  147. };
  148. rm {
  149. nvidia,pins = "rm";
  150. nvidia,function = "i2c1";
  151. };
  152. sdb {
  153. nvidia,pins = "sdb", "sdc", "sdd";
  154. nvidia,function = "pwm";
  155. };
  156. sdio1 {
  157. nvidia,pins = "sdio1";
  158. nvidia,function = "sdio1";
  159. };
  160. slxc {
  161. nvidia,pins = "slxc", "slxd";
  162. nvidia,function = "sdio3";
  163. };
  164. spdi {
  165. nvidia,pins = "spdi", "spdo";
  166. nvidia,function = "spdif";
  167. };
  168. spia {
  169. nvidia,pins = "spia", "spib", "spic";
  170. nvidia,function = "spi2";
  171. };
  172. spid {
  173. nvidia,pins = "spid", "spie", "spif";
  174. nvidia,function = "spi1";
  175. };
  176. spig {
  177. nvidia,pins = "spig", "spih";
  178. nvidia,function = "spi2_alt";
  179. };
  180. uaa {
  181. nvidia,pins = "uaa", "uab", "uda";
  182. nvidia,function = "ulpi";
  183. };
  184. uad {
  185. nvidia,pins = "uad";
  186. nvidia,function = "irda";
  187. };
  188. uca {
  189. nvidia,pins = "uca", "ucb";
  190. nvidia,function = "uartc";
  191. };
  192. conf_ata {
  193. nvidia,pins = "ata", "atc", "atd", "ate",
  194. "crtp", "dap2", "dap3", "dap4", "dta",
  195. "dtb", "dtc", "dtd", "gmb", "gme",
  196. "i2cp", "pta", "slxc", "slxd", "spdi",
  197. "spdo", "uda";
  198. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  199. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  200. };
  201. conf_atb {
  202. nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
  203. "dte", "gma", "gmc", "gmd", "gpu",
  204. "gpu7", "gpv", "sdio1", "slxa", "slxk",
  205. "uac";
  206. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  207. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  208. };
  209. conf_ck32 {
  210. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  211. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  212. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  213. };
  214. conf_csus {
  215. nvidia,pins = "csus", "spia", "spib",
  216. "spid", "spif";
  217. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  218. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  219. };
  220. conf_ddc {
  221. nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
  222. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  223. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  224. };
  225. conf_hdint {
  226. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  227. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  228. "lvp0", "pmc";
  229. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  230. };
  231. conf_irrx {
  232. nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
  233. "kbcc", "kbcd", "kbce", "kbcf", "owc",
  234. "spic", "spie", "spig", "spih", "uaa",
  235. "uab", "uad", "uca", "ucb";
  236. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  237. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  238. };
  239. conf_lc {
  240. nvidia,pins = "lc", "ls";
  241. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  242. };
  243. conf_ld0 {
  244. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  245. "ld5", "ld6", "ld7", "ld8", "ld9",
  246. "ld10", "ld11", "ld12", "ld13", "ld14",
  247. "ld15", "ld16", "ld17", "ldi", "lhp0",
  248. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  249. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  250. "lvs", "sdb";
  251. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  252. };
  253. conf_ld17_0 {
  254. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  255. "ld23_22";
  256. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  257. };
  258. conf_spif {
  259. nvidia,pins = "spif";
  260. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  261. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  262. };
  263. };
  264. };
  265. i2s@70002800 {
  266. status = "okay";
  267. };
  268. serial@70006000 {
  269. /delete-property/ dmas;
  270. /delete-property/ dma-names;
  271. status = "okay";
  272. };
  273. dvi_ddc: i2c@7000c000 {
  274. status = "okay";
  275. clock-frequency = <100000>;
  276. };
  277. spi@7000c380 {
  278. status = "okay";
  279. spi-max-frequency = <48000000>;
  280. flash@0 {
  281. compatible = "winbond,w25q80bl", "jedec,spi-nor";
  282. reg = <0>;
  283. spi-max-frequency = <48000000>;
  284. };
  285. };
  286. hdmi_ddc: i2c@7000c400 {
  287. status = "okay";
  288. clock-frequency = <100000>;
  289. };
  290. i2c@7000c500 {
  291. status = "okay";
  292. clock-frequency = <400000>;
  293. codec: codec@1a {
  294. compatible = "ti,tlv320aic23";
  295. reg = <0x1a>;
  296. };
  297. rtc@56 {
  298. compatible = "emmicro,em3027";
  299. reg = <0x56>;
  300. };
  301. };
  302. pmc@7000e400 {
  303. nvidia,suspend-mode = <1>;
  304. nvidia,cpu-pwr-good-time = <5000>;
  305. nvidia,cpu-pwr-off-time = <5000>;
  306. nvidia,core-pwr-good-time = <3845 3845>;
  307. nvidia,core-pwr-off-time = <3875>;
  308. nvidia,sys-clock-req-active-high;
  309. core-supply = <&vdd_core>;
  310. };
  311. pcie@80003000 {
  312. status = "okay";
  313. avdd-pex-supply = <&pci_vdd_reg>;
  314. vdd-pex-supply = <&pci_vdd_reg>;
  315. avdd-pex-pll-supply = <&pci_vdd_reg>;
  316. avdd-plle-supply = <&pci_vdd_reg>;
  317. vddio-pex-clk-supply = <&pci_clk_reg>;
  318. pci@1,0 {
  319. status = "okay";
  320. };
  321. };
  322. usb@c5000000 {
  323. status = "okay";
  324. };
  325. usb-phy@c5000000 {
  326. status = "okay";
  327. vbus-supply = <&vbus_reg>;
  328. };
  329. usb@c5004000 {
  330. status = "okay";
  331. };
  332. usb-phy@c5004000 {
  333. status = "okay";
  334. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  335. GPIO_ACTIVE_LOW>;
  336. };
  337. usb@c5008000 {
  338. status = "okay";
  339. };
  340. usb-phy@c5008000 {
  341. status = "okay";
  342. };
  343. mmc@c8000000 {
  344. status = "okay";
  345. broken-cd;
  346. bus-width = <4>;
  347. };
  348. mmc@c8000600 {
  349. status = "okay";
  350. cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
  351. wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
  352. bus-width = <4>;
  353. };
  354. clk32k_in: clock-32k {
  355. compatible = "fixed-clock";
  356. clock-frequency = <32768>;
  357. #clock-cells = <0>;
  358. };
  359. cpus {
  360. cpu0: cpu@0 {
  361. operating-points-v2 = <&cpu0_opp_table>;
  362. };
  363. cpu@1 {
  364. operating-points-v2 = <&cpu0_opp_table>;
  365. };
  366. };
  367. gpio-keys {
  368. compatible = "gpio-keys";
  369. key-power {
  370. label = "Power";
  371. gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
  372. linux,code = <KEY_POWER>;
  373. wakeup-source;
  374. };
  375. };
  376. leds {
  377. compatible = "gpio-leds";
  378. led-ds2 {
  379. color = <LED_COLOR_ID_GREEN>;
  380. function = LED_FUNCTION_INDICATOR;
  381. function-enumerator = <2>;
  382. gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_LOW>;
  383. };
  384. led-ds3 {
  385. color = <LED_COLOR_ID_GREEN>;
  386. function = LED_FUNCTION_INDICATOR;
  387. function-enumerator = <3>;
  388. gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>;
  389. };
  390. };
  391. poweroff {
  392. compatible = "gpio-poweroff";
  393. gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
  394. };
  395. hdmi_vdd_reg: regulator-hdmi {
  396. compatible = "regulator-fixed";
  397. regulator-name = "avdd_hdmi";
  398. regulator-min-microvolt = <3300000>;
  399. regulator-max-microvolt = <3300000>;
  400. regulator-always-on;
  401. };
  402. hdmi_pll_reg: regulator-hdmipll {
  403. compatible = "regulator-fixed";
  404. regulator-name = "avdd_hdmi_pll";
  405. regulator-min-microvolt = <1800000>;
  406. regulator-max-microvolt = <1800000>;
  407. regulator-always-on;
  408. };
  409. vbus_reg: regulator-vbus {
  410. compatible = "regulator-fixed";
  411. regulator-name = "usb1_vbus";
  412. regulator-min-microvolt = <5000000>;
  413. regulator-max-microvolt = <5000000>;
  414. enable-active-high;
  415. gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
  416. regulator-always-on;
  417. regulator-boot-on;
  418. };
  419. pci_clk_reg: regulator-pciclk {
  420. compatible = "regulator-fixed";
  421. regulator-name = "pci_clk";
  422. regulator-min-microvolt = <3300000>;
  423. regulator-max-microvolt = <3300000>;
  424. regulator-always-on;
  425. };
  426. pci_vdd_reg: regulator-pcivdd {
  427. compatible = "regulator-fixed";
  428. regulator-name = "pci_vdd";
  429. regulator-min-microvolt = <1050000>;
  430. regulator-max-microvolt = <1050000>;
  431. regulator-always-on;
  432. };
  433. vdd_core: regulator-core {
  434. compatible = "regulator-fixed";
  435. regulator-name = "vdd_core";
  436. regulator-min-microvolt = <1300000>;
  437. regulator-max-microvolt = <1300000>;
  438. regulator-always-on;
  439. };
  440. sound {
  441. compatible = "nvidia,tegra-audio-trimslice";
  442. nvidia,i2s-controller = <&tegra_i2s1>;
  443. nvidia,audio-codec = <&codec>;
  444. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  445. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  446. <&tegra_car TEGRA20_CLK_CDEV1>;
  447. clock-names = "pll_a", "pll_a_out0", "mclk";
  448. };
  449. };