socfpga_agilex_n6000.dts 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2021-2022, Intel Corporation
  4. */
  5. #include "socfpga_agilex.dtsi"
  6. / {
  7. model = "SoCFPGA Agilex n6000";
  8. compatible = "intel,socfpga-agilex-n6000", "intel,socfpga-agilex";
  9. aliases {
  10. serial0 = &uart1;
  11. serial1 = &uart0;
  12. ethernet0 = &gmac0;
  13. ethernet1 = &gmac1;
  14. ethernet2 = &gmac2;
  15. };
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. memory@80000000 {
  20. device_type = "memory";
  21. /* We expect the bootloader to fill in the reg */
  22. reg = <0 0x80000000 0 0>;
  23. };
  24. soc@0 {
  25. bus@80000000 {
  26. compatible = "simple-bus";
  27. reg = <0x80000000 0x60000000>,
  28. <0xf9000000 0x00100000>;
  29. reg-names = "axi_h2f", "axi_h2f_lw";
  30. #address-cells = <2>;
  31. #size-cells = <1>;
  32. ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
  33. dma-controller@0 {
  34. compatible = "intel,hps-copy-engine";
  35. reg = <0x00000000 0x00000000 0x00001000>;
  36. #dma-cells = <1>;
  37. };
  38. };
  39. };
  40. };
  41. &osc1 {
  42. clock-frequency = <25000000>;
  43. };
  44. &uart0 {
  45. status = "okay";
  46. };
  47. &uart1 {
  48. status = "okay";
  49. };
  50. &watchdog0 {
  51. status = "okay";
  52. };
  53. &fpga_mgr {
  54. status = "disabled";
  55. };