addrspace.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
  4. *
  5. * Derived from MIPS:
  6. * Copyright (C) 1996, 99 Ralf Baechle
  7. * Copyright (C) 2000, 2002 Maciej W. Rozycki
  8. * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
  9. */
  10. #ifndef _ASM_ADDRSPACE_H
  11. #define _ASM_ADDRSPACE_H
  12. #include <linux/const.h>
  13. #include <linux/sizes.h>
  14. #include <asm/loongarch.h>
  15. /*
  16. * This gives the physical RAM offset.
  17. */
  18. #ifndef __ASSEMBLY__
  19. #ifndef PHYS_OFFSET
  20. #define PHYS_OFFSET _UL(0)
  21. #endif
  22. extern unsigned long vm_map_base;
  23. #endif /* __ASSEMBLY__ */
  24. #ifndef IO_BASE
  25. #define IO_BASE CSR_DMW0_BASE
  26. #endif
  27. #ifndef CACHE_BASE
  28. #define CACHE_BASE CSR_DMW1_BASE
  29. #endif
  30. #ifndef UNCACHE_BASE
  31. #define UNCACHE_BASE CSR_DMW0_BASE
  32. #endif
  33. #ifndef WRITECOMBINE_BASE
  34. #define WRITECOMBINE_BASE CSR_DMW2_BASE
  35. #endif
  36. #define DMW_PABITS 48
  37. #define TO_PHYS_MASK ((1ULL << DMW_PABITS) - 1)
  38. /*
  39. * Memory above this physical address will be considered highmem.
  40. */
  41. #ifndef HIGHMEM_START
  42. #define HIGHMEM_START (_UL(1) << _UL(DMW_PABITS))
  43. #endif
  44. #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
  45. #define TO_CACHE(x) (CACHE_BASE | ((x) & TO_PHYS_MASK))
  46. #define TO_UNCACHE(x) (UNCACHE_BASE | ((x) & TO_PHYS_MASK))
  47. /*
  48. * This handles the memory map.
  49. */
  50. #ifndef PAGE_OFFSET
  51. #define PAGE_OFFSET (CACHE_BASE + PHYS_OFFSET)
  52. #endif
  53. #ifndef FIXADDR_TOP
  54. #define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
  55. #endif
  56. #ifdef __ASSEMBLY__
  57. #define _ATYPE_
  58. #define _ATYPE32_
  59. #define _ATYPE64_
  60. #else
  61. #define _ATYPE_ __PTRDIFF_TYPE__
  62. #define _ATYPE32_ int
  63. #define _ATYPE64_ __s64
  64. #endif
  65. #ifdef CONFIG_64BIT
  66. #define _CONST64_(x) _UL(x)
  67. #else
  68. #define _CONST64_(x) _ULL(x)
  69. #endif
  70. /*
  71. * 32/64-bit LoongArch address spaces
  72. */
  73. #ifdef __ASSEMBLY__
  74. #define _ACAST32_
  75. #define _ACAST64_
  76. #else
  77. #define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
  78. #define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
  79. #endif
  80. #ifdef CONFIG_32BIT
  81. #define UVRANGE 0x00000000
  82. #define KPRANGE0 0x80000000
  83. #define KPRANGE1 0xa0000000
  84. #define KVRANGE 0xc0000000
  85. #else
  86. #define XUVRANGE _CONST64_(0x0000000000000000)
  87. #define XSPRANGE _CONST64_(0x4000000000000000)
  88. #define XKPRANGE _CONST64_(0x8000000000000000)
  89. #define XKVRANGE _CONST64_(0xc000000000000000)
  90. #endif
  91. /*
  92. * Returns the physical address of a KPRANGEx / XKPRANGE address
  93. */
  94. #define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK)
  95. /*
  96. * On LoongArch, I/O ports mappring is following:
  97. *
  98. * | .... |
  99. * |-----------------------|
  100. * | pci io ports(16K~32M) |
  101. * |-----------------------|
  102. * | isa io ports(0 ~16K) |
  103. * PCI_IOBASE ->|-----------------------|
  104. * | .... |
  105. */
  106. #define PCI_IOBASE ((void __iomem *)(vm_map_base + (2 * PAGE_SIZE)))
  107. #define PCI_IOSIZE SZ_32M
  108. #define ISA_IOSIZE SZ_16K
  109. #define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
  110. #define PHYS_LINK_KADDR PHYSADDR(VMLINUX_LOAD_ADDRESS)
  111. #endif /* _ASM_ADDRSPACE_H */