cpu-info.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
  4. */
  5. #ifndef __ASM_CPU_INFO_H
  6. #define __ASM_CPU_INFO_H
  7. #include <linux/cache.h>
  8. #include <linux/types.h>
  9. #include <asm/loongarch.h>
  10. /* cache_desc->flags */
  11. enum {
  12. CACHE_PRESENT = (1 << 0),
  13. CACHE_PRIVATE = (1 << 1), /* core private cache */
  14. CACHE_INCLUSIVE = (1 << 2), /* include the inner level caches */
  15. };
  16. /*
  17. * Descriptor for a cache
  18. */
  19. struct cache_desc {
  20. unsigned char type;
  21. unsigned char level;
  22. unsigned short sets; /* Number of lines per set */
  23. unsigned char ways; /* Number of ways */
  24. unsigned char linesz; /* Size of line in bytes */
  25. unsigned char flags; /* Flags describing cache properties */
  26. };
  27. #define CACHE_LEVEL_MAX 3
  28. #define CACHE_LEAVES_MAX 6
  29. struct cpuinfo_loongarch {
  30. u64 asid_cache;
  31. unsigned long asid_mask;
  32. /*
  33. * Capability and feature descriptor structure for LoongArch CPU
  34. */
  35. unsigned long long options;
  36. unsigned int processor_id;
  37. unsigned int fpu_vers;
  38. unsigned int fpu_csr0;
  39. unsigned int fpu_mask;
  40. unsigned int cputype;
  41. int isa_level;
  42. int tlbsize;
  43. int tlbsizemtlb;
  44. int tlbsizestlbsets;
  45. int tlbsizestlbways;
  46. int cache_leaves_present; /* number of cache_leaves[] elements */
  47. struct cache_desc cache_leaves[CACHE_LEAVES_MAX];
  48. int core; /* physical core number in package */
  49. int package;/* physical package number */
  50. int global_id; /* physical global thread number */
  51. int vabits; /* Virtual Address size in bits */
  52. int pabits; /* Physical Address size in bits */
  53. unsigned int ksave_mask; /* Usable KSave mask. */
  54. unsigned int watch_dreg_count; /* Number data breakpoints */
  55. unsigned int watch_ireg_count; /* Number instruction breakpoints */
  56. unsigned int watch_reg_use_cnt; /* min(NUM_WATCH_REGS, watch_dreg_count + watch_ireg_count), Usable by ptrace */
  57. } __aligned(SMP_CACHE_BYTES);
  58. extern struct cpuinfo_loongarch cpu_data[];
  59. #define boot_cpu_data cpu_data[0]
  60. #define current_cpu_data cpu_data[smp_processor_id()]
  61. #define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
  62. extern void cpu_probe(void);
  63. extern const char *__cpu_family[];
  64. extern const char *__cpu_full_name[];
  65. #define cpu_family_string() __cpu_family[raw_smp_processor_id()]
  66. #define cpu_full_name_string() __cpu_full_name[raw_smp_processor_id()]
  67. struct seq_file;
  68. struct notifier_block;
  69. extern int register_proc_cpuinfo_notifier(struct notifier_block *nb);
  70. extern int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v);
  71. #define proc_cpuinfo_notifier(fn, pri) \
  72. ({ \
  73. static struct notifier_block fn##_nb = { \
  74. .notifier_call = fn, \
  75. .priority = pri \
  76. }; \
  77. \
  78. register_proc_cpuinfo_notifier(&fn##_nb); \
  79. })
  80. struct proc_cpuinfo_notifier_args {
  81. struct seq_file *m;
  82. unsigned long n;
  83. };
  84. static inline bool cpus_are_siblings(int cpua, int cpub)
  85. {
  86. struct cpuinfo_loongarch *infoa = &cpu_data[cpua];
  87. struct cpuinfo_loongarch *infob = &cpu_data[cpub];
  88. if (infoa->package != infob->package)
  89. return false;
  90. if (infoa->core != infob->core)
  91. return false;
  92. return true;
  93. }
  94. static inline unsigned long cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo)
  95. {
  96. return cpuinfo->asid_mask;
  97. }
  98. static inline void set_cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo,
  99. unsigned long asid_mask)
  100. {
  101. cpuinfo->asid_mask = asid_mask;
  102. }
  103. #endif /* __ASM_CPU_INFO_H */