ocelot_pcb120.dts 2.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2017 Microsemi Corporation */
  3. /dts-v1/;
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/interrupt-controller/irq.h>
  6. #include <dt-bindings/phy/phy-ocelot-serdes.h>
  7. #include "ocelot.dtsi"
  8. / {
  9. compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
  10. chosen {
  11. stdout-path = "serial0:115200n8";
  12. };
  13. memory@0 {
  14. device_type = "memory";
  15. reg = <0x0 0x0e000000>;
  16. };
  17. };
  18. &gpio {
  19. phy_int_pins: phy-int-pins {
  20. pins = "GPIO_4";
  21. function = "gpio";
  22. };
  23. phy_load_save_pins: phy-load-save-pins {
  24. pins = "GPIO_10";
  25. function = "ptp2";
  26. };
  27. };
  28. &mdio0 {
  29. status = "okay";
  30. };
  31. &mdio1 {
  32. status = "okay";
  33. pinctrl-names = "default";
  34. pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>;
  35. phy7: ethernet-phy@0 {
  36. reg = <0>;
  37. interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
  38. interrupt-parent = <&gpio>;
  39. load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
  40. };
  41. phy6: ethernet-phy@1 {
  42. reg = <1>;
  43. interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
  44. interrupt-parent = <&gpio>;
  45. load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
  46. };
  47. phy5: ethernet-phy@2 {
  48. reg = <2>;
  49. interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
  50. interrupt-parent = <&gpio>;
  51. load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
  52. };
  53. phy4: ethernet-phy@3 {
  54. reg = <3>;
  55. interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
  56. interrupt-parent = <&gpio>;
  57. load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
  58. };
  59. };
  60. &port0 {
  61. status = "okay";
  62. phy-handle = <&phy0>;
  63. phy-mode = "internal";
  64. };
  65. &port1 {
  66. status = "okay";
  67. phy-handle = <&phy1>;
  68. phy-mode = "internal";
  69. };
  70. &port2 {
  71. status = "okay";
  72. phy-handle = <&phy2>;
  73. phy-mode = "internal";
  74. };
  75. &port3 {
  76. status = "okay";
  77. phy-handle = <&phy3>;
  78. phy-mode = "internal";
  79. };
  80. &port4 {
  81. status = "okay";
  82. phy-handle = <&phy7>;
  83. phy-mode = "sgmii";
  84. phys = <&serdes 4 SERDES1G(2)>;
  85. };
  86. &port5 {
  87. status = "okay";
  88. phy-handle = <&phy4>;
  89. phy-mode = "sgmii";
  90. phys = <&serdes 5 SERDES1G(5)>;
  91. };
  92. &port6 {
  93. status = "okay";
  94. phy-handle = <&phy6>;
  95. phy-mode = "sgmii";
  96. phys = <&serdes 6 SERDES1G(3)>;
  97. };
  98. &port9 {
  99. status = "okay";
  100. phy-handle = <&phy5>;
  101. phy-mode = "sgmii";
  102. phys = <&serdes 9 SERDES1G(4)>;
  103. };
  104. &uart0 {
  105. status = "okay";
  106. };
  107. &uart2 {
  108. status = "okay";
  109. };