Kconfig 3.0 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. config SIBYTE_SB1250
  3. bool
  4. select CEVT_SB1250
  5. select CSRC_SB1250
  6. select HAVE_PCI
  7. select IRQ_MIPS_CPU
  8. select SIBYTE_ENABLE_LDT_IF_PCI
  9. select SIBYTE_HAS_ZBUS_PROFILING
  10. select SIBYTE_SB1xxx_SOC
  11. select SYS_SUPPORTS_SMP
  12. config SIBYTE_BCM1125
  13. bool
  14. select CEVT_SB1250
  15. select CSRC_SB1250
  16. select HAVE_PCI
  17. select IRQ_MIPS_CPU
  18. select SIBYTE_BCM112X
  19. select SIBYTE_HAS_ZBUS_PROFILING
  20. select SIBYTE_SB1xxx_SOC
  21. config SIBYTE_BCM112X
  22. bool
  23. select CEVT_SB1250
  24. select CSRC_SB1250
  25. select IRQ_MIPS_CPU
  26. select SIBYTE_SB1xxx_SOC
  27. select SIBYTE_HAS_ZBUS_PROFILING
  28. config SIBYTE_BCM1x80
  29. bool
  30. select CEVT_BCM1480
  31. select CSRC_BCM1480
  32. select HAVE_PCI
  33. select IRQ_MIPS_CPU
  34. select SIBYTE_HAS_ZBUS_PROFILING
  35. select SIBYTE_SB1xxx_SOC
  36. select SYS_SUPPORTS_SMP
  37. config SIBYTE_SB1xxx_SOC
  38. bool
  39. select IRQ_MIPS_CPU
  40. select SWAP_IO_SPACE
  41. select SYS_SUPPORTS_32BIT_KERNEL
  42. select SYS_SUPPORTS_64BIT_KERNEL
  43. select FW_CFE
  44. select SYS_HAS_EARLY_PRINTK
  45. choice
  46. prompt "SiByte SOC Stepping"
  47. depends on SIBYTE_SB1xxx_SOC
  48. config CPU_SB1_PASS_2_1250
  49. bool "1250 An"
  50. depends on SIBYTE_SB1250
  51. select CPU_SB1_PASS_2
  52. help
  53. Also called BCM1250 Pass 2
  54. config CPU_SB1_PASS_2_2
  55. bool "1250 Bn"
  56. depends on SIBYTE_SB1250
  57. select CPU_HAS_PREFETCH
  58. help
  59. Also called BCM1250 Pass 2.2
  60. config CPU_SB1_PASS_4
  61. bool "1250 Cn"
  62. depends on SIBYTE_SB1250
  63. select CPU_HAS_PREFETCH
  64. help
  65. Also called BCM1250 Pass 3
  66. config CPU_SB1_PASS_2_112x
  67. bool "112x Hybrid"
  68. depends on SIBYTE_BCM112X
  69. select CPU_SB1_PASS_2
  70. config CPU_SB1_PASS_3
  71. bool "112x An"
  72. depends on SIBYTE_BCM112X
  73. select CPU_HAS_PREFETCH
  74. endchoice
  75. config CPU_SB1_PASS_2
  76. bool
  77. config SIBYTE_HAS_LDT
  78. bool
  79. config SIBYTE_ENABLE_LDT_IF_PCI
  80. bool
  81. select SIBYTE_HAS_LDT if PCI
  82. config SB1_CEX_ALWAYS_FATAL
  83. bool "All cache exceptions considered fatal (no recovery attempted)"
  84. depends on SIBYTE_SB1xxx_SOC
  85. config SB1_CERR_STALL
  86. bool "Stall (rather than panic) on fatal cache error"
  87. depends on SIBYTE_SB1xxx_SOC
  88. config SIBYTE_CFE_CONSOLE
  89. bool "Use firmware console"
  90. depends on SIBYTE_SB1xxx_SOC
  91. help
  92. Use the CFE API's console write routines during boot. Other console
  93. options (VT console, sb1250 duart console, etc.) should not be
  94. configured.
  95. config SIBYTE_BUS_WATCHER
  96. bool "Support for Bus Watcher statistics"
  97. depends on SIBYTE_SB1xxx_SOC && \
  98. (SIBYTE_BCM112X || SIBYTE_SB1250 || SIBYTE_BCM1x80)
  99. help
  100. Handle and keep statistics on the bus error interrupts (COR_ECC,
  101. BAD_ECC, IO_BUS).
  102. config SIBYTE_BW_TRACE
  103. bool "Capture bus trace before bus error"
  104. depends on SIBYTE_BUS_WATCHER
  105. help
  106. Run a continuous bus trace, dumping the raw data as soon as
  107. a ZBbus error is detected. Cannot work if ZBbus profiling
  108. is turned on, and also will interfere with JTAG-based trace
  109. buffer activity. Raw buffer data is dumped to console, and
  110. must be processed off-line.
  111. config SIBYTE_TBPROF
  112. tristate "Support for ZBbus profiling"
  113. depends on SIBYTE_HAS_ZBUS_PROFILING
  114. config SIBYTE_HAS_ZBUS_PROFILING
  115. bool