spu_base.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Low-level SPU handling
  4. *
  5. * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
  6. *
  7. * Author: Arnd Bergmann <arndb@de.ibm.com>
  8. */
  9. #undef DEBUG
  10. #include <linux/interrupt.h>
  11. #include <linux/list.h>
  12. #include <linux/init.h>
  13. #include <linux/ptrace.h>
  14. #include <linux/slab.h>
  15. #include <linux/wait.h>
  16. #include <linux/mm.h>
  17. #include <linux/io.h>
  18. #include <linux/mutex.h>
  19. #include <linux/linux_logo.h>
  20. #include <linux/syscore_ops.h>
  21. #include <asm/spu.h>
  22. #include <asm/spu_priv1.h>
  23. #include <asm/spu_csa.h>
  24. #include <asm/xmon.h>
  25. #include <asm/kexec.h>
  26. const struct spu_management_ops *spu_management_ops;
  27. EXPORT_SYMBOL_GPL(spu_management_ops);
  28. const struct spu_priv1_ops *spu_priv1_ops;
  29. EXPORT_SYMBOL_GPL(spu_priv1_ops);
  30. struct cbe_spu_info cbe_spu_info[MAX_NUMNODES];
  31. EXPORT_SYMBOL_GPL(cbe_spu_info);
  32. /*
  33. * The spufs fault-handling code needs to call force_sig_fault to raise signals
  34. * on DMA errors. Export it here to avoid general kernel-wide access to this
  35. * function
  36. */
  37. EXPORT_SYMBOL_GPL(force_sig_fault);
  38. /*
  39. * Protects cbe_spu_info and spu->number.
  40. */
  41. static DEFINE_SPINLOCK(spu_lock);
  42. /*
  43. * List of all spus in the system.
  44. *
  45. * This list is iterated by callers from irq context and callers that
  46. * want to sleep. Thus modifications need to be done with both
  47. * spu_full_list_lock and spu_full_list_mutex held, while iterating
  48. * through it requires either of these locks.
  49. *
  50. * In addition spu_full_list_lock protects all assignments to
  51. * spu->mm.
  52. */
  53. static LIST_HEAD(spu_full_list);
  54. static DEFINE_SPINLOCK(spu_full_list_lock);
  55. static DEFINE_MUTEX(spu_full_list_mutex);
  56. void spu_invalidate_slbs(struct spu *spu)
  57. {
  58. struct spu_priv2 __iomem *priv2 = spu->priv2;
  59. unsigned long flags;
  60. spin_lock_irqsave(&spu->register_lock, flags);
  61. if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK)
  62. out_be64(&priv2->slb_invalidate_all_W, 0UL);
  63. spin_unlock_irqrestore(&spu->register_lock, flags);
  64. }
  65. EXPORT_SYMBOL_GPL(spu_invalidate_slbs);
  66. /* This is called by the MM core when a segment size is changed, to
  67. * request a flush of all the SPEs using a given mm
  68. */
  69. void spu_flush_all_slbs(struct mm_struct *mm)
  70. {
  71. struct spu *spu;
  72. unsigned long flags;
  73. spin_lock_irqsave(&spu_full_list_lock, flags);
  74. list_for_each_entry(spu, &spu_full_list, full_list) {
  75. if (spu->mm == mm)
  76. spu_invalidate_slbs(spu);
  77. }
  78. spin_unlock_irqrestore(&spu_full_list_lock, flags);
  79. }
  80. /* The hack below stinks... try to do something better one of
  81. * these days... Does it even work properly with NR_CPUS == 1 ?
  82. */
  83. static inline void mm_needs_global_tlbie(struct mm_struct *mm)
  84. {
  85. int nr = (NR_CPUS > 1) ? NR_CPUS : NR_CPUS + 1;
  86. /* Global TLBIE broadcast required with SPEs. */
  87. bitmap_fill(cpumask_bits(mm_cpumask(mm)), nr);
  88. }
  89. void spu_associate_mm(struct spu *spu, struct mm_struct *mm)
  90. {
  91. unsigned long flags;
  92. spin_lock_irqsave(&spu_full_list_lock, flags);
  93. spu->mm = mm;
  94. spin_unlock_irqrestore(&spu_full_list_lock, flags);
  95. if (mm)
  96. mm_needs_global_tlbie(mm);
  97. }
  98. EXPORT_SYMBOL_GPL(spu_associate_mm);
  99. int spu_64k_pages_available(void)
  100. {
  101. return mmu_psize_defs[MMU_PAGE_64K].shift != 0;
  102. }
  103. EXPORT_SYMBOL_GPL(spu_64k_pages_available);
  104. static void spu_restart_dma(struct spu *spu)
  105. {
  106. struct spu_priv2 __iomem *priv2 = spu->priv2;
  107. if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))
  108. out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
  109. else {
  110. set_bit(SPU_CONTEXT_FAULT_PENDING, &spu->flags);
  111. mb();
  112. }
  113. }
  114. static inline void spu_load_slb(struct spu *spu, int slbe, struct copro_slb *slb)
  115. {
  116. struct spu_priv2 __iomem *priv2 = spu->priv2;
  117. pr_debug("%s: adding SLB[%d] 0x%016llx 0x%016llx\n",
  118. __func__, slbe, slb->vsid, slb->esid);
  119. out_be64(&priv2->slb_index_W, slbe);
  120. /* set invalid before writing vsid */
  121. out_be64(&priv2->slb_esid_RW, 0);
  122. /* now it's safe to write the vsid */
  123. out_be64(&priv2->slb_vsid_RW, slb->vsid);
  124. /* setting the new esid makes the entry valid again */
  125. out_be64(&priv2->slb_esid_RW, slb->esid);
  126. }
  127. static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
  128. {
  129. struct copro_slb slb;
  130. int ret;
  131. ret = copro_calculate_slb(spu->mm, ea, &slb);
  132. if (ret)
  133. return ret;
  134. spu_load_slb(spu, spu->slb_replace, &slb);
  135. spu->slb_replace++;
  136. if (spu->slb_replace >= 8)
  137. spu->slb_replace = 0;
  138. spu_restart_dma(spu);
  139. spu->stats.slb_flt++;
  140. return 0;
  141. }
  142. extern int hash_page(unsigned long ea, unsigned long access,
  143. unsigned long trap, unsigned long dsisr); //XXX
  144. static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
  145. {
  146. int ret;
  147. pr_debug("%s, %llx, %lx\n", __func__, dsisr, ea);
  148. /*
  149. * Handle kernel space hash faults immediately. User hash
  150. * faults need to be deferred to process context.
  151. */
  152. if ((dsisr & MFC_DSISR_PTE_NOT_FOUND) &&
  153. (get_region_id(ea) != USER_REGION_ID)) {
  154. spin_unlock(&spu->register_lock);
  155. ret = hash_page(ea,
  156. _PAGE_PRESENT | _PAGE_READ | _PAGE_PRIVILEGED,
  157. 0x300, dsisr);
  158. spin_lock(&spu->register_lock);
  159. if (!ret) {
  160. spu_restart_dma(spu);
  161. return 0;
  162. }
  163. }
  164. spu->class_1_dar = ea;
  165. spu->class_1_dsisr = dsisr;
  166. spu->stop_callback(spu, 1);
  167. spu->class_1_dar = 0;
  168. spu->class_1_dsisr = 0;
  169. return 0;
  170. }
  171. static void __spu_kernel_slb(void *addr, struct copro_slb *slb)
  172. {
  173. unsigned long ea = (unsigned long)addr;
  174. u64 llp;
  175. if (get_region_id(ea) == LINEAR_MAP_REGION_ID)
  176. llp = mmu_psize_defs[mmu_linear_psize].sllp;
  177. else
  178. llp = mmu_psize_defs[mmu_virtual_psize].sllp;
  179. slb->vsid = (get_kernel_vsid(ea, MMU_SEGSIZE_256M) << SLB_VSID_SHIFT) |
  180. SLB_VSID_KERNEL | llp;
  181. slb->esid = (ea & ESID_MASK) | SLB_ESID_V;
  182. }
  183. /**
  184. * Given an array of @nr_slbs SLB entries, @slbs, return non-zero if the
  185. * address @new_addr is present.
  186. */
  187. static inline int __slb_present(struct copro_slb *slbs, int nr_slbs,
  188. void *new_addr)
  189. {
  190. unsigned long ea = (unsigned long)new_addr;
  191. int i;
  192. for (i = 0; i < nr_slbs; i++)
  193. if (!((slbs[i].esid ^ ea) & ESID_MASK))
  194. return 1;
  195. return 0;
  196. }
  197. /**
  198. * Setup the SPU kernel SLBs, in preparation for a context save/restore. We
  199. * need to map both the context save area, and the save/restore code.
  200. *
  201. * Because the lscsa and code may cross segment boundaries, we check to see
  202. * if mappings are required for the start and end of each range. We currently
  203. * assume that the mappings are smaller that one segment - if not, something
  204. * is seriously wrong.
  205. */
  206. void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
  207. void *code, int code_size)
  208. {
  209. struct copro_slb slbs[4];
  210. int i, nr_slbs = 0;
  211. /* start and end addresses of both mappings */
  212. void *addrs[] = {
  213. lscsa, (void *)lscsa + sizeof(*lscsa) - 1,
  214. code, code + code_size - 1
  215. };
  216. /* check the set of addresses, and create a new entry in the slbs array
  217. * if there isn't already a SLB for that address */
  218. for (i = 0; i < ARRAY_SIZE(addrs); i++) {
  219. if (__slb_present(slbs, nr_slbs, addrs[i]))
  220. continue;
  221. __spu_kernel_slb(addrs[i], &slbs[nr_slbs]);
  222. nr_slbs++;
  223. }
  224. spin_lock_irq(&spu->register_lock);
  225. /* Add the set of SLBs */
  226. for (i = 0; i < nr_slbs; i++)
  227. spu_load_slb(spu, i, &slbs[i]);
  228. spin_unlock_irq(&spu->register_lock);
  229. }
  230. EXPORT_SYMBOL_GPL(spu_setup_kernel_slbs);
  231. static irqreturn_t
  232. spu_irq_class_0(int irq, void *data)
  233. {
  234. struct spu *spu;
  235. unsigned long stat, mask;
  236. spu = data;
  237. spin_lock(&spu->register_lock);
  238. mask = spu_int_mask_get(spu, 0);
  239. stat = spu_int_stat_get(spu, 0) & mask;
  240. spu->class_0_pending |= stat;
  241. spu->class_0_dar = spu_mfc_dar_get(spu);
  242. spu->stop_callback(spu, 0);
  243. spu->class_0_pending = 0;
  244. spu->class_0_dar = 0;
  245. spu_int_stat_clear(spu, 0, stat);
  246. spin_unlock(&spu->register_lock);
  247. return IRQ_HANDLED;
  248. }
  249. static irqreturn_t
  250. spu_irq_class_1(int irq, void *data)
  251. {
  252. struct spu *spu;
  253. unsigned long stat, mask, dar, dsisr;
  254. spu = data;
  255. /* atomically read & clear class1 status. */
  256. spin_lock(&spu->register_lock);
  257. mask = spu_int_mask_get(spu, 1);
  258. stat = spu_int_stat_get(spu, 1) & mask;
  259. dar = spu_mfc_dar_get(spu);
  260. dsisr = spu_mfc_dsisr_get(spu);
  261. if (stat & CLASS1_STORAGE_FAULT_INTR)
  262. spu_mfc_dsisr_set(spu, 0ul);
  263. spu_int_stat_clear(spu, 1, stat);
  264. pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat,
  265. dar, dsisr);
  266. if (stat & CLASS1_SEGMENT_FAULT_INTR)
  267. __spu_trap_data_seg(spu, dar);
  268. if (stat & CLASS1_STORAGE_FAULT_INTR)
  269. __spu_trap_data_map(spu, dar, dsisr);
  270. spu->class_1_dsisr = 0;
  271. spu->class_1_dar = 0;
  272. spin_unlock(&spu->register_lock);
  273. return stat ? IRQ_HANDLED : IRQ_NONE;
  274. }
  275. static irqreturn_t
  276. spu_irq_class_2(int irq, void *data)
  277. {
  278. struct spu *spu;
  279. unsigned long stat;
  280. unsigned long mask;
  281. const int mailbox_intrs =
  282. CLASS2_MAILBOX_THRESHOLD_INTR | CLASS2_MAILBOX_INTR;
  283. spu = data;
  284. spin_lock(&spu->register_lock);
  285. stat = spu_int_stat_get(spu, 2);
  286. mask = spu_int_mask_get(spu, 2);
  287. /* ignore interrupts we're not waiting for */
  288. stat &= mask;
  289. /* mailbox interrupts are level triggered. mask them now before
  290. * acknowledging */
  291. if (stat & mailbox_intrs)
  292. spu_int_mask_and(spu, 2, ~(stat & mailbox_intrs));
  293. /* acknowledge all interrupts before the callbacks */
  294. spu_int_stat_clear(spu, 2, stat);
  295. pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);
  296. if (stat & CLASS2_MAILBOX_INTR)
  297. spu->ibox_callback(spu);
  298. if (stat & CLASS2_SPU_STOP_INTR)
  299. spu->stop_callback(spu, 2);
  300. if (stat & CLASS2_SPU_HALT_INTR)
  301. spu->stop_callback(spu, 2);
  302. if (stat & CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR)
  303. spu->mfc_callback(spu);
  304. if (stat & CLASS2_MAILBOX_THRESHOLD_INTR)
  305. spu->wbox_callback(spu);
  306. spu->stats.class2_intr++;
  307. spin_unlock(&spu->register_lock);
  308. return stat ? IRQ_HANDLED : IRQ_NONE;
  309. }
  310. static int __init spu_request_irqs(struct spu *spu)
  311. {
  312. int ret = 0;
  313. if (spu->irqs[0]) {
  314. snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0",
  315. spu->number);
  316. ret = request_irq(spu->irqs[0], spu_irq_class_0,
  317. 0, spu->irq_c0, spu);
  318. if (ret)
  319. goto bail0;
  320. }
  321. if (spu->irqs[1]) {
  322. snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1",
  323. spu->number);
  324. ret = request_irq(spu->irqs[1], spu_irq_class_1,
  325. 0, spu->irq_c1, spu);
  326. if (ret)
  327. goto bail1;
  328. }
  329. if (spu->irqs[2]) {
  330. snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2",
  331. spu->number);
  332. ret = request_irq(spu->irqs[2], spu_irq_class_2,
  333. 0, spu->irq_c2, spu);
  334. if (ret)
  335. goto bail2;
  336. }
  337. return 0;
  338. bail2:
  339. if (spu->irqs[1])
  340. free_irq(spu->irqs[1], spu);
  341. bail1:
  342. if (spu->irqs[0])
  343. free_irq(spu->irqs[0], spu);
  344. bail0:
  345. return ret;
  346. }
  347. static void spu_free_irqs(struct spu *spu)
  348. {
  349. if (spu->irqs[0])
  350. free_irq(spu->irqs[0], spu);
  351. if (spu->irqs[1])
  352. free_irq(spu->irqs[1], spu);
  353. if (spu->irqs[2])
  354. free_irq(spu->irqs[2], spu);
  355. }
  356. void spu_init_channels(struct spu *spu)
  357. {
  358. static const struct {
  359. unsigned channel;
  360. unsigned count;
  361. } zero_list[] = {
  362. { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
  363. { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
  364. }, count_list[] = {
  365. { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
  366. { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
  367. { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
  368. };
  369. struct spu_priv2 __iomem *priv2;
  370. int i;
  371. priv2 = spu->priv2;
  372. /* initialize all channel data to zero */
  373. for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
  374. int count;
  375. out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
  376. for (count = 0; count < zero_list[i].count; count++)
  377. out_be64(&priv2->spu_chnldata_RW, 0);
  378. }
  379. /* initialize channel counts to meaningful values */
  380. for (i = 0; i < ARRAY_SIZE(count_list); i++) {
  381. out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
  382. out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
  383. }
  384. }
  385. EXPORT_SYMBOL_GPL(spu_init_channels);
  386. static struct bus_type spu_subsys = {
  387. .name = "spu",
  388. .dev_name = "spu",
  389. };
  390. int spu_add_dev_attr(struct device_attribute *attr)
  391. {
  392. struct spu *spu;
  393. mutex_lock(&spu_full_list_mutex);
  394. list_for_each_entry(spu, &spu_full_list, full_list)
  395. device_create_file(&spu->dev, attr);
  396. mutex_unlock(&spu_full_list_mutex);
  397. return 0;
  398. }
  399. EXPORT_SYMBOL_GPL(spu_add_dev_attr);
  400. int spu_add_dev_attr_group(const struct attribute_group *attrs)
  401. {
  402. struct spu *spu;
  403. int rc = 0;
  404. mutex_lock(&spu_full_list_mutex);
  405. list_for_each_entry(spu, &spu_full_list, full_list) {
  406. rc = sysfs_create_group(&spu->dev.kobj, attrs);
  407. /* we're in trouble here, but try unwinding anyway */
  408. if (rc) {
  409. printk(KERN_ERR "%s: can't create sysfs group '%s'\n",
  410. __func__, attrs->name);
  411. list_for_each_entry_continue_reverse(spu,
  412. &spu_full_list, full_list)
  413. sysfs_remove_group(&spu->dev.kobj, attrs);
  414. break;
  415. }
  416. }
  417. mutex_unlock(&spu_full_list_mutex);
  418. return rc;
  419. }
  420. EXPORT_SYMBOL_GPL(spu_add_dev_attr_group);
  421. void spu_remove_dev_attr(struct device_attribute *attr)
  422. {
  423. struct spu *spu;
  424. mutex_lock(&spu_full_list_mutex);
  425. list_for_each_entry(spu, &spu_full_list, full_list)
  426. device_remove_file(&spu->dev, attr);
  427. mutex_unlock(&spu_full_list_mutex);
  428. }
  429. EXPORT_SYMBOL_GPL(spu_remove_dev_attr);
  430. void spu_remove_dev_attr_group(const struct attribute_group *attrs)
  431. {
  432. struct spu *spu;
  433. mutex_lock(&spu_full_list_mutex);
  434. list_for_each_entry(spu, &spu_full_list, full_list)
  435. sysfs_remove_group(&spu->dev.kobj, attrs);
  436. mutex_unlock(&spu_full_list_mutex);
  437. }
  438. EXPORT_SYMBOL_GPL(spu_remove_dev_attr_group);
  439. static int __init spu_create_dev(struct spu *spu)
  440. {
  441. int ret;
  442. spu->dev.id = spu->number;
  443. spu->dev.bus = &spu_subsys;
  444. ret = device_register(&spu->dev);
  445. if (ret) {
  446. printk(KERN_ERR "Can't register SPU %d with sysfs\n",
  447. spu->number);
  448. return ret;
  449. }
  450. sysfs_add_device_to_node(&spu->dev, spu->node);
  451. return 0;
  452. }
  453. static int __init create_spu(void *data)
  454. {
  455. struct spu *spu;
  456. int ret;
  457. static int number;
  458. unsigned long flags;
  459. ret = -ENOMEM;
  460. spu = kzalloc(sizeof (*spu), GFP_KERNEL);
  461. if (!spu)
  462. goto out;
  463. spu->alloc_state = SPU_FREE;
  464. spin_lock_init(&spu->register_lock);
  465. spin_lock(&spu_lock);
  466. spu->number = number++;
  467. spin_unlock(&spu_lock);
  468. ret = spu_create_spu(spu, data);
  469. if (ret)
  470. goto out_free;
  471. spu_mfc_sdr_setup(spu);
  472. spu_mfc_sr1_set(spu, 0x33);
  473. ret = spu_request_irqs(spu);
  474. if (ret)
  475. goto out_destroy;
  476. ret = spu_create_dev(spu);
  477. if (ret)
  478. goto out_free_irqs;
  479. mutex_lock(&cbe_spu_info[spu->node].list_mutex);
  480. list_add(&spu->cbe_list, &cbe_spu_info[spu->node].spus);
  481. cbe_spu_info[spu->node].n_spus++;
  482. mutex_unlock(&cbe_spu_info[spu->node].list_mutex);
  483. mutex_lock(&spu_full_list_mutex);
  484. spin_lock_irqsave(&spu_full_list_lock, flags);
  485. list_add(&spu->full_list, &spu_full_list);
  486. spin_unlock_irqrestore(&spu_full_list_lock, flags);
  487. mutex_unlock(&spu_full_list_mutex);
  488. spu->stats.util_state = SPU_UTIL_IDLE_LOADED;
  489. spu->stats.tstamp = ktime_get_ns();
  490. INIT_LIST_HEAD(&spu->aff_list);
  491. goto out;
  492. out_free_irqs:
  493. spu_free_irqs(spu);
  494. out_destroy:
  495. spu_destroy_spu(spu);
  496. out_free:
  497. kfree(spu);
  498. out:
  499. return ret;
  500. }
  501. static const char *spu_state_names[] = {
  502. "user", "system", "iowait", "idle"
  503. };
  504. static unsigned long long spu_acct_time(struct spu *spu,
  505. enum spu_utilization_state state)
  506. {
  507. unsigned long long time = spu->stats.times[state];
  508. /*
  509. * If the spu is idle or the context is stopped, utilization
  510. * statistics are not updated. Apply the time delta from the
  511. * last recorded state of the spu.
  512. */
  513. if (spu->stats.util_state == state)
  514. time += ktime_get_ns() - spu->stats.tstamp;
  515. return time / NSEC_PER_MSEC;
  516. }
  517. static ssize_t spu_stat_show(struct device *dev,
  518. struct device_attribute *attr, char *buf)
  519. {
  520. struct spu *spu = container_of(dev, struct spu, dev);
  521. return sprintf(buf, "%s %llu %llu %llu %llu "
  522. "%llu %llu %llu %llu %llu %llu %llu %llu\n",
  523. spu_state_names[spu->stats.util_state],
  524. spu_acct_time(spu, SPU_UTIL_USER),
  525. spu_acct_time(spu, SPU_UTIL_SYSTEM),
  526. spu_acct_time(spu, SPU_UTIL_IOWAIT),
  527. spu_acct_time(spu, SPU_UTIL_IDLE_LOADED),
  528. spu->stats.vol_ctx_switch,
  529. spu->stats.invol_ctx_switch,
  530. spu->stats.slb_flt,
  531. spu->stats.hash_flt,
  532. spu->stats.min_flt,
  533. spu->stats.maj_flt,
  534. spu->stats.class2_intr,
  535. spu->stats.libassist);
  536. }
  537. static DEVICE_ATTR(stat, 0444, spu_stat_show, NULL);
  538. #ifdef CONFIG_KEXEC_CORE
  539. struct crash_spu_info {
  540. struct spu *spu;
  541. u32 saved_spu_runcntl_RW;
  542. u32 saved_spu_status_R;
  543. u32 saved_spu_npc_RW;
  544. u64 saved_mfc_sr1_RW;
  545. u64 saved_mfc_dar;
  546. u64 saved_mfc_dsisr;
  547. };
  548. #define CRASH_NUM_SPUS 16 /* Enough for current hardware */
  549. static struct crash_spu_info crash_spu_info[CRASH_NUM_SPUS];
  550. static void crash_kexec_stop_spus(void)
  551. {
  552. struct spu *spu;
  553. int i;
  554. u64 tmp;
  555. for (i = 0; i < CRASH_NUM_SPUS; i++) {
  556. if (!crash_spu_info[i].spu)
  557. continue;
  558. spu = crash_spu_info[i].spu;
  559. crash_spu_info[i].saved_spu_runcntl_RW =
  560. in_be32(&spu->problem->spu_runcntl_RW);
  561. crash_spu_info[i].saved_spu_status_R =
  562. in_be32(&spu->problem->spu_status_R);
  563. crash_spu_info[i].saved_spu_npc_RW =
  564. in_be32(&spu->problem->spu_npc_RW);
  565. crash_spu_info[i].saved_mfc_dar = spu_mfc_dar_get(spu);
  566. crash_spu_info[i].saved_mfc_dsisr = spu_mfc_dsisr_get(spu);
  567. tmp = spu_mfc_sr1_get(spu);
  568. crash_spu_info[i].saved_mfc_sr1_RW = tmp;
  569. tmp &= ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
  570. spu_mfc_sr1_set(spu, tmp);
  571. __delay(200);
  572. }
  573. }
  574. static void __init crash_register_spus(struct list_head *list)
  575. {
  576. struct spu *spu;
  577. int ret;
  578. list_for_each_entry(spu, list, full_list) {
  579. if (WARN_ON(spu->number >= CRASH_NUM_SPUS))
  580. continue;
  581. crash_spu_info[spu->number].spu = spu;
  582. }
  583. ret = crash_shutdown_register(&crash_kexec_stop_spus);
  584. if (ret)
  585. printk(KERN_ERR "Could not register SPU crash handler");
  586. }
  587. #else
  588. static inline void crash_register_spus(struct list_head *list)
  589. {
  590. }
  591. #endif
  592. static void spu_shutdown(void)
  593. {
  594. struct spu *spu;
  595. mutex_lock(&spu_full_list_mutex);
  596. list_for_each_entry(spu, &spu_full_list, full_list) {
  597. spu_free_irqs(spu);
  598. spu_destroy_spu(spu);
  599. }
  600. mutex_unlock(&spu_full_list_mutex);
  601. }
  602. static struct syscore_ops spu_syscore_ops = {
  603. .shutdown = spu_shutdown,
  604. };
  605. static int __init init_spu_base(void)
  606. {
  607. int i, ret = 0;
  608. for (i = 0; i < MAX_NUMNODES; i++) {
  609. mutex_init(&cbe_spu_info[i].list_mutex);
  610. INIT_LIST_HEAD(&cbe_spu_info[i].spus);
  611. }
  612. if (!spu_management_ops)
  613. goto out;
  614. /* create system subsystem for spus */
  615. ret = subsys_system_register(&spu_subsys, NULL);
  616. if (ret)
  617. goto out;
  618. ret = spu_enumerate_spus(create_spu);
  619. if (ret < 0) {
  620. printk(KERN_WARNING "%s: Error initializing spus\n",
  621. __func__);
  622. goto out_unregister_subsys;
  623. }
  624. if (ret > 0)
  625. fb_append_extra_logo(&logo_spe_clut224, ret);
  626. mutex_lock(&spu_full_list_mutex);
  627. xmon_register_spus(&spu_full_list);
  628. crash_register_spus(&spu_full_list);
  629. mutex_unlock(&spu_full_list_mutex);
  630. spu_add_dev_attr(&dev_attr_stat);
  631. register_syscore_ops(&spu_syscore_ops);
  632. spu_init_affinity();
  633. return 0;
  634. out_unregister_subsys:
  635. bus_unregister(&spu_subsys);
  636. out:
  637. return ret;
  638. }
  639. device_initcall(init_spu_base);