mmu.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Western Digital Corporation or its affiliates.
  4. *
  5. * Authors:
  6. * Anup Patel <anup.patel@wdc.com>
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/errno.h>
  10. #include <linux/err.h>
  11. #include <linux/hugetlb.h>
  12. #include <linux/module.h>
  13. #include <linux/uaccess.h>
  14. #include <linux/vmalloc.h>
  15. #include <linux/kvm_host.h>
  16. #include <linux/sched/signal.h>
  17. #include <asm/csr.h>
  18. #include <asm/page.h>
  19. #include <asm/pgtable.h>
  20. #ifdef CONFIG_64BIT
  21. static unsigned long gstage_mode __ro_after_init = (HGATP_MODE_SV39X4 << HGATP_MODE_SHIFT);
  22. static unsigned long gstage_pgd_levels __ro_after_init = 3;
  23. #define gstage_index_bits 9
  24. #else
  25. static unsigned long gstage_mode __ro_after_init = (HGATP_MODE_SV32X4 << HGATP_MODE_SHIFT);
  26. static unsigned long gstage_pgd_levels __ro_after_init = 2;
  27. #define gstage_index_bits 10
  28. #endif
  29. #define gstage_pgd_xbits 2
  30. #define gstage_pgd_size (1UL << (HGATP_PAGE_SHIFT + gstage_pgd_xbits))
  31. #define gstage_gpa_bits (HGATP_PAGE_SHIFT + \
  32. (gstage_pgd_levels * gstage_index_bits) + \
  33. gstage_pgd_xbits)
  34. #define gstage_gpa_size ((gpa_t)(1ULL << gstage_gpa_bits))
  35. #define gstage_pte_leaf(__ptep) \
  36. (pte_val(*(__ptep)) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC))
  37. static inline unsigned long gstage_pte_index(gpa_t addr, u32 level)
  38. {
  39. unsigned long mask;
  40. unsigned long shift = HGATP_PAGE_SHIFT + (gstage_index_bits * level);
  41. if (level == (gstage_pgd_levels - 1))
  42. mask = (PTRS_PER_PTE * (1UL << gstage_pgd_xbits)) - 1;
  43. else
  44. mask = PTRS_PER_PTE - 1;
  45. return (addr >> shift) & mask;
  46. }
  47. static inline unsigned long gstage_pte_page_vaddr(pte_t pte)
  48. {
  49. return (unsigned long)pfn_to_virt(__page_val_to_pfn(pte_val(pte)));
  50. }
  51. static int gstage_page_size_to_level(unsigned long page_size, u32 *out_level)
  52. {
  53. u32 i;
  54. unsigned long psz = 1UL << 12;
  55. for (i = 0; i < gstage_pgd_levels; i++) {
  56. if (page_size == (psz << (i * gstage_index_bits))) {
  57. *out_level = i;
  58. return 0;
  59. }
  60. }
  61. return -EINVAL;
  62. }
  63. static int gstage_level_to_page_order(u32 level, unsigned long *out_pgorder)
  64. {
  65. if (gstage_pgd_levels < level)
  66. return -EINVAL;
  67. *out_pgorder = 12 + (level * gstage_index_bits);
  68. return 0;
  69. }
  70. static int gstage_level_to_page_size(u32 level, unsigned long *out_pgsize)
  71. {
  72. int rc;
  73. unsigned long page_order = PAGE_SHIFT;
  74. rc = gstage_level_to_page_order(level, &page_order);
  75. if (rc)
  76. return rc;
  77. *out_pgsize = BIT(page_order);
  78. return 0;
  79. }
  80. static bool gstage_get_leaf_entry(struct kvm *kvm, gpa_t addr,
  81. pte_t **ptepp, u32 *ptep_level)
  82. {
  83. pte_t *ptep;
  84. u32 current_level = gstage_pgd_levels - 1;
  85. *ptep_level = current_level;
  86. ptep = (pte_t *)kvm->arch.pgd;
  87. ptep = &ptep[gstage_pte_index(addr, current_level)];
  88. while (ptep && pte_val(ptep_get(ptep))) {
  89. if (gstage_pte_leaf(ptep)) {
  90. *ptep_level = current_level;
  91. *ptepp = ptep;
  92. return true;
  93. }
  94. if (current_level) {
  95. current_level--;
  96. *ptep_level = current_level;
  97. ptep = (pte_t *)gstage_pte_page_vaddr(ptep_get(ptep));
  98. ptep = &ptep[gstage_pte_index(addr, current_level)];
  99. } else {
  100. ptep = NULL;
  101. }
  102. }
  103. return false;
  104. }
  105. static void gstage_remote_tlb_flush(struct kvm *kvm, u32 level, gpa_t addr)
  106. {
  107. unsigned long order = PAGE_SHIFT;
  108. if (gstage_level_to_page_order(level, &order))
  109. return;
  110. addr &= ~(BIT(order) - 1);
  111. kvm_riscv_hfence_gvma_vmid_gpa(kvm, -1UL, 0, addr, BIT(order), order);
  112. }
  113. static int gstage_set_pte(struct kvm *kvm, u32 level,
  114. struct kvm_mmu_memory_cache *pcache,
  115. gpa_t addr, const pte_t *new_pte)
  116. {
  117. u32 current_level = gstage_pgd_levels - 1;
  118. pte_t *next_ptep = (pte_t *)kvm->arch.pgd;
  119. pte_t *ptep = &next_ptep[gstage_pte_index(addr, current_level)];
  120. if (current_level < level)
  121. return -EINVAL;
  122. while (current_level != level) {
  123. if (gstage_pte_leaf(ptep))
  124. return -EEXIST;
  125. if (!pte_val(ptep_get(ptep))) {
  126. if (!pcache)
  127. return -ENOMEM;
  128. next_ptep = kvm_mmu_memory_cache_alloc(pcache);
  129. if (!next_ptep)
  130. return -ENOMEM;
  131. set_pte(ptep, pfn_pte(PFN_DOWN(__pa(next_ptep)),
  132. __pgprot(_PAGE_TABLE)));
  133. } else {
  134. if (gstage_pte_leaf(ptep))
  135. return -EEXIST;
  136. next_ptep = (pte_t *)gstage_pte_page_vaddr(ptep_get(ptep));
  137. }
  138. current_level--;
  139. ptep = &next_ptep[gstage_pte_index(addr, current_level)];
  140. }
  141. set_pte(ptep, *new_pte);
  142. if (gstage_pte_leaf(ptep))
  143. gstage_remote_tlb_flush(kvm, current_level, addr);
  144. return 0;
  145. }
  146. static int gstage_map_page(struct kvm *kvm,
  147. struct kvm_mmu_memory_cache *pcache,
  148. gpa_t gpa, phys_addr_t hpa,
  149. unsigned long page_size,
  150. bool page_rdonly, bool page_exec)
  151. {
  152. int ret;
  153. u32 level = 0;
  154. pte_t new_pte;
  155. pgprot_t prot;
  156. ret = gstage_page_size_to_level(page_size, &level);
  157. if (ret)
  158. return ret;
  159. /*
  160. * A RISC-V implementation can choose to either:
  161. * 1) Update 'A' and 'D' PTE bits in hardware
  162. * 2) Generate page fault when 'A' and/or 'D' bits are not set
  163. * PTE so that software can update these bits.
  164. *
  165. * We support both options mentioned above. To achieve this, we
  166. * always set 'A' and 'D' PTE bits at time of creating G-stage
  167. * mapping. To support KVM dirty page logging with both options
  168. * mentioned above, we will write-protect G-stage PTEs to track
  169. * dirty pages.
  170. */
  171. if (page_exec) {
  172. if (page_rdonly)
  173. prot = PAGE_READ_EXEC;
  174. else
  175. prot = PAGE_WRITE_EXEC;
  176. } else {
  177. if (page_rdonly)
  178. prot = PAGE_READ;
  179. else
  180. prot = PAGE_WRITE;
  181. }
  182. new_pte = pfn_pte(PFN_DOWN(hpa), prot);
  183. new_pte = pte_mkdirty(new_pte);
  184. return gstage_set_pte(kvm, level, pcache, gpa, &new_pte);
  185. }
  186. enum gstage_op {
  187. GSTAGE_OP_NOP = 0, /* Nothing */
  188. GSTAGE_OP_CLEAR, /* Clear/Unmap */
  189. GSTAGE_OP_WP, /* Write-protect */
  190. };
  191. static void gstage_op_pte(struct kvm *kvm, gpa_t addr,
  192. pte_t *ptep, u32 ptep_level, enum gstage_op op)
  193. {
  194. int i, ret;
  195. pte_t *next_ptep;
  196. u32 next_ptep_level;
  197. unsigned long next_page_size, page_size;
  198. ret = gstage_level_to_page_size(ptep_level, &page_size);
  199. if (ret)
  200. return;
  201. BUG_ON(addr & (page_size - 1));
  202. if (!pte_val(ptep_get(ptep)))
  203. return;
  204. if (ptep_level && !gstage_pte_leaf(ptep)) {
  205. next_ptep = (pte_t *)gstage_pte_page_vaddr(ptep_get(ptep));
  206. next_ptep_level = ptep_level - 1;
  207. ret = gstage_level_to_page_size(next_ptep_level,
  208. &next_page_size);
  209. if (ret)
  210. return;
  211. if (op == GSTAGE_OP_CLEAR)
  212. set_pte(ptep, __pte(0));
  213. for (i = 0; i < PTRS_PER_PTE; i++)
  214. gstage_op_pte(kvm, addr + i * next_page_size,
  215. &next_ptep[i], next_ptep_level, op);
  216. if (op == GSTAGE_OP_CLEAR)
  217. put_page(virt_to_page(next_ptep));
  218. } else {
  219. if (op == GSTAGE_OP_CLEAR)
  220. set_pte(ptep, __pte(0));
  221. else if (op == GSTAGE_OP_WP)
  222. set_pte(ptep, __pte(pte_val(ptep_get(ptep)) & ~_PAGE_WRITE));
  223. gstage_remote_tlb_flush(kvm, ptep_level, addr);
  224. }
  225. }
  226. static void gstage_unmap_range(struct kvm *kvm, gpa_t start,
  227. gpa_t size, bool may_block)
  228. {
  229. int ret;
  230. pte_t *ptep;
  231. u32 ptep_level;
  232. bool found_leaf;
  233. unsigned long page_size;
  234. gpa_t addr = start, end = start + size;
  235. while (addr < end) {
  236. found_leaf = gstage_get_leaf_entry(kvm, addr,
  237. &ptep, &ptep_level);
  238. ret = gstage_level_to_page_size(ptep_level, &page_size);
  239. if (ret)
  240. break;
  241. if (!found_leaf)
  242. goto next;
  243. if (!(addr & (page_size - 1)) && ((end - addr) >= page_size))
  244. gstage_op_pte(kvm, addr, ptep,
  245. ptep_level, GSTAGE_OP_CLEAR);
  246. next:
  247. addr += page_size;
  248. /*
  249. * If the range is too large, release the kvm->mmu_lock
  250. * to prevent starvation and lockup detector warnings.
  251. */
  252. if (may_block && addr < end)
  253. cond_resched_lock(&kvm->mmu_lock);
  254. }
  255. }
  256. static void gstage_wp_range(struct kvm *kvm, gpa_t start, gpa_t end)
  257. {
  258. int ret;
  259. pte_t *ptep;
  260. u32 ptep_level;
  261. bool found_leaf;
  262. gpa_t addr = start;
  263. unsigned long page_size;
  264. while (addr < end) {
  265. found_leaf = gstage_get_leaf_entry(kvm, addr,
  266. &ptep, &ptep_level);
  267. ret = gstage_level_to_page_size(ptep_level, &page_size);
  268. if (ret)
  269. break;
  270. if (!found_leaf)
  271. goto next;
  272. if (!(addr & (page_size - 1)) && ((end - addr) >= page_size))
  273. gstage_op_pte(kvm, addr, ptep,
  274. ptep_level, GSTAGE_OP_WP);
  275. next:
  276. addr += page_size;
  277. }
  278. }
  279. static void gstage_wp_memory_region(struct kvm *kvm, int slot)
  280. {
  281. struct kvm_memslots *slots = kvm_memslots(kvm);
  282. struct kvm_memory_slot *memslot = id_to_memslot(slots, slot);
  283. phys_addr_t start = memslot->base_gfn << PAGE_SHIFT;
  284. phys_addr_t end = (memslot->base_gfn + memslot->npages) << PAGE_SHIFT;
  285. spin_lock(&kvm->mmu_lock);
  286. gstage_wp_range(kvm, start, end);
  287. spin_unlock(&kvm->mmu_lock);
  288. kvm_flush_remote_tlbs(kvm);
  289. }
  290. int kvm_riscv_gstage_ioremap(struct kvm *kvm, gpa_t gpa,
  291. phys_addr_t hpa, unsigned long size,
  292. bool writable, bool in_atomic)
  293. {
  294. pte_t pte;
  295. int ret = 0;
  296. unsigned long pfn;
  297. phys_addr_t addr, end;
  298. struct kvm_mmu_memory_cache pcache = {
  299. .gfp_custom = (in_atomic) ? GFP_ATOMIC | __GFP_ACCOUNT : 0,
  300. .gfp_zero = __GFP_ZERO,
  301. };
  302. end = (gpa + size + PAGE_SIZE - 1) & PAGE_MASK;
  303. pfn = __phys_to_pfn(hpa);
  304. for (addr = gpa; addr < end; addr += PAGE_SIZE) {
  305. pte = pfn_pte(pfn, PAGE_KERNEL_IO);
  306. if (!writable)
  307. pte = pte_wrprotect(pte);
  308. ret = kvm_mmu_topup_memory_cache(&pcache, gstage_pgd_levels);
  309. if (ret)
  310. goto out;
  311. spin_lock(&kvm->mmu_lock);
  312. ret = gstage_set_pte(kvm, 0, &pcache, addr, &pte);
  313. spin_unlock(&kvm->mmu_lock);
  314. if (ret)
  315. goto out;
  316. pfn++;
  317. }
  318. out:
  319. kvm_mmu_free_memory_cache(&pcache);
  320. return ret;
  321. }
  322. void kvm_riscv_gstage_iounmap(struct kvm *kvm, gpa_t gpa, unsigned long size)
  323. {
  324. spin_lock(&kvm->mmu_lock);
  325. gstage_unmap_range(kvm, gpa, size, false);
  326. spin_unlock(&kvm->mmu_lock);
  327. }
  328. void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
  329. struct kvm_memory_slot *slot,
  330. gfn_t gfn_offset,
  331. unsigned long mask)
  332. {
  333. phys_addr_t base_gfn = slot->base_gfn + gfn_offset;
  334. phys_addr_t start = (base_gfn + __ffs(mask)) << PAGE_SHIFT;
  335. phys_addr_t end = (base_gfn + __fls(mask) + 1) << PAGE_SHIFT;
  336. gstage_wp_range(kvm, start, end);
  337. }
  338. void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
  339. {
  340. }
  341. void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free)
  342. {
  343. }
  344. void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
  345. {
  346. }
  347. void kvm_arch_flush_shadow_all(struct kvm *kvm)
  348. {
  349. kvm_riscv_gstage_free_pgd(kvm);
  350. }
  351. void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
  352. struct kvm_memory_slot *slot)
  353. {
  354. gpa_t gpa = slot->base_gfn << PAGE_SHIFT;
  355. phys_addr_t size = slot->npages << PAGE_SHIFT;
  356. spin_lock(&kvm->mmu_lock);
  357. gstage_unmap_range(kvm, gpa, size, false);
  358. spin_unlock(&kvm->mmu_lock);
  359. }
  360. void kvm_arch_commit_memory_region(struct kvm *kvm,
  361. struct kvm_memory_slot *old,
  362. const struct kvm_memory_slot *new,
  363. enum kvm_mr_change change)
  364. {
  365. /*
  366. * At this point memslot has been committed and there is an
  367. * allocated dirty_bitmap[], dirty pages will be tracked while
  368. * the memory slot is write protected.
  369. */
  370. if (change != KVM_MR_DELETE && new->flags & KVM_MEM_LOG_DIRTY_PAGES)
  371. gstage_wp_memory_region(kvm, new->id);
  372. }
  373. int kvm_arch_prepare_memory_region(struct kvm *kvm,
  374. const struct kvm_memory_slot *old,
  375. struct kvm_memory_slot *new,
  376. enum kvm_mr_change change)
  377. {
  378. hva_t hva, reg_end, size;
  379. gpa_t base_gpa;
  380. bool writable;
  381. int ret = 0;
  382. if (change != KVM_MR_CREATE && change != KVM_MR_MOVE &&
  383. change != KVM_MR_FLAGS_ONLY)
  384. return 0;
  385. /*
  386. * Prevent userspace from creating a memory region outside of the GPA
  387. * space addressable by the KVM guest GPA space.
  388. */
  389. if ((new->base_gfn + new->npages) >=
  390. (gstage_gpa_size >> PAGE_SHIFT))
  391. return -EFAULT;
  392. hva = new->userspace_addr;
  393. size = new->npages << PAGE_SHIFT;
  394. reg_end = hva + size;
  395. base_gpa = new->base_gfn << PAGE_SHIFT;
  396. writable = !(new->flags & KVM_MEM_READONLY);
  397. mmap_read_lock(current->mm);
  398. /*
  399. * A memory region could potentially cover multiple VMAs, and
  400. * any holes between them, so iterate over all of them to find
  401. * out if we can map any of them right now.
  402. *
  403. * +--------------------------------------------+
  404. * +---------------+----------------+ +----------------+
  405. * | : VMA 1 | VMA 2 | | VMA 3 : |
  406. * +---------------+----------------+ +----------------+
  407. * | memory region |
  408. * +--------------------------------------------+
  409. */
  410. do {
  411. struct vm_area_struct *vma = find_vma(current->mm, hva);
  412. hva_t vm_start, vm_end;
  413. if (!vma || vma->vm_start >= reg_end)
  414. break;
  415. /*
  416. * Mapping a read-only VMA is only allowed if the
  417. * memory region is configured as read-only.
  418. */
  419. if (writable && !(vma->vm_flags & VM_WRITE)) {
  420. ret = -EPERM;
  421. break;
  422. }
  423. /* Take the intersection of this VMA with the memory region */
  424. vm_start = max(hva, vma->vm_start);
  425. vm_end = min(reg_end, vma->vm_end);
  426. if (vma->vm_flags & VM_PFNMAP) {
  427. gpa_t gpa = base_gpa + (vm_start - hva);
  428. phys_addr_t pa;
  429. pa = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT;
  430. pa += vm_start - vma->vm_start;
  431. /* IO region dirty page logging not allowed */
  432. if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
  433. ret = -EINVAL;
  434. goto out;
  435. }
  436. ret = kvm_riscv_gstage_ioremap(kvm, gpa, pa,
  437. vm_end - vm_start,
  438. writable, false);
  439. if (ret)
  440. break;
  441. }
  442. hva = vm_end;
  443. } while (hva < reg_end);
  444. if (change == KVM_MR_FLAGS_ONLY)
  445. goto out;
  446. if (ret)
  447. kvm_riscv_gstage_iounmap(kvm, base_gpa, size);
  448. out:
  449. mmap_read_unlock(current->mm);
  450. return ret;
  451. }
  452. bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
  453. {
  454. if (!kvm->arch.pgd)
  455. return false;
  456. gstage_unmap_range(kvm, range->start << PAGE_SHIFT,
  457. (range->end - range->start) << PAGE_SHIFT,
  458. range->may_block);
  459. return false;
  460. }
  461. bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
  462. {
  463. pte_t *ptep;
  464. u32 ptep_level = 0;
  465. u64 size = (range->end - range->start) << PAGE_SHIFT;
  466. if (!kvm->arch.pgd)
  467. return false;
  468. WARN_ON(size != PAGE_SIZE && size != PMD_SIZE && size != PUD_SIZE);
  469. if (!gstage_get_leaf_entry(kvm, range->start << PAGE_SHIFT,
  470. &ptep, &ptep_level))
  471. return false;
  472. return ptep_test_and_clear_young(NULL, 0, ptep);
  473. }
  474. bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
  475. {
  476. pte_t *ptep;
  477. u32 ptep_level = 0;
  478. u64 size = (range->end - range->start) << PAGE_SHIFT;
  479. if (!kvm->arch.pgd)
  480. return false;
  481. WARN_ON(size != PAGE_SIZE && size != PMD_SIZE && size != PUD_SIZE);
  482. if (!gstage_get_leaf_entry(kvm, range->start << PAGE_SHIFT,
  483. &ptep, &ptep_level))
  484. return false;
  485. return pte_young(ptep_get(ptep));
  486. }
  487. int kvm_riscv_gstage_map(struct kvm_vcpu *vcpu,
  488. struct kvm_memory_slot *memslot,
  489. gpa_t gpa, unsigned long hva, bool is_write)
  490. {
  491. int ret;
  492. kvm_pfn_t hfn;
  493. bool writable;
  494. short vma_pageshift;
  495. gfn_t gfn = gpa >> PAGE_SHIFT;
  496. struct vm_area_struct *vma;
  497. struct kvm *kvm = vcpu->kvm;
  498. struct kvm_mmu_memory_cache *pcache = &vcpu->arch.mmu_page_cache;
  499. bool logging = (memslot->dirty_bitmap &&
  500. !(memslot->flags & KVM_MEM_READONLY)) ? true : false;
  501. unsigned long vma_pagesize, mmu_seq;
  502. /* We need minimum second+third level pages */
  503. ret = kvm_mmu_topup_memory_cache(pcache, gstage_pgd_levels);
  504. if (ret) {
  505. kvm_err("Failed to topup G-stage cache\n");
  506. return ret;
  507. }
  508. mmap_read_lock(current->mm);
  509. vma = vma_lookup(current->mm, hva);
  510. if (unlikely(!vma)) {
  511. kvm_err("Failed to find VMA for hva 0x%lx\n", hva);
  512. mmap_read_unlock(current->mm);
  513. return -EFAULT;
  514. }
  515. if (is_vm_hugetlb_page(vma))
  516. vma_pageshift = huge_page_shift(hstate_vma(vma));
  517. else
  518. vma_pageshift = PAGE_SHIFT;
  519. vma_pagesize = 1ULL << vma_pageshift;
  520. if (logging || (vma->vm_flags & VM_PFNMAP))
  521. vma_pagesize = PAGE_SIZE;
  522. if (vma_pagesize == PMD_SIZE || vma_pagesize == PUD_SIZE)
  523. gfn = (gpa & huge_page_mask(hstate_vma(vma))) >> PAGE_SHIFT;
  524. /*
  525. * Read mmu_invalidate_seq so that KVM can detect if the results of
  526. * vma_lookup() or gfn_to_pfn_prot() become stale priort to acquiring
  527. * kvm->mmu_lock.
  528. *
  529. * Rely on mmap_read_unlock() for an implicit smp_rmb(), which pairs
  530. * with the smp_wmb() in kvm_mmu_invalidate_end().
  531. */
  532. mmu_seq = kvm->mmu_invalidate_seq;
  533. mmap_read_unlock(current->mm);
  534. if (vma_pagesize != PUD_SIZE &&
  535. vma_pagesize != PMD_SIZE &&
  536. vma_pagesize != PAGE_SIZE) {
  537. kvm_err("Invalid VMA page size 0x%lx\n", vma_pagesize);
  538. return -EFAULT;
  539. }
  540. hfn = gfn_to_pfn_prot(kvm, gfn, is_write, &writable);
  541. if (hfn == KVM_PFN_ERR_HWPOISON) {
  542. send_sig_mceerr(BUS_MCEERR_AR, (void __user *)hva,
  543. vma_pageshift, current);
  544. return 0;
  545. }
  546. if (is_error_noslot_pfn(hfn))
  547. return -EFAULT;
  548. /*
  549. * If logging is active then we allow writable pages only
  550. * for write faults.
  551. */
  552. if (logging && !is_write)
  553. writable = false;
  554. spin_lock(&kvm->mmu_lock);
  555. if (mmu_invalidate_retry(kvm, mmu_seq))
  556. goto out_unlock;
  557. if (writable) {
  558. kvm_set_pfn_dirty(hfn);
  559. mark_page_dirty(kvm, gfn);
  560. ret = gstage_map_page(kvm, pcache, gpa, hfn << PAGE_SHIFT,
  561. vma_pagesize, false, true);
  562. } else {
  563. ret = gstage_map_page(kvm, pcache, gpa, hfn << PAGE_SHIFT,
  564. vma_pagesize, true, true);
  565. }
  566. if (ret)
  567. kvm_err("Failed to map in G-stage\n");
  568. out_unlock:
  569. spin_unlock(&kvm->mmu_lock);
  570. kvm_set_pfn_accessed(hfn);
  571. kvm_release_pfn_clean(hfn);
  572. return ret;
  573. }
  574. int kvm_riscv_gstage_alloc_pgd(struct kvm *kvm)
  575. {
  576. struct page *pgd_page;
  577. if (kvm->arch.pgd != NULL) {
  578. kvm_err("kvm_arch already initialized?\n");
  579. return -EINVAL;
  580. }
  581. pgd_page = alloc_pages(GFP_KERNEL | __GFP_ZERO,
  582. get_order(gstage_pgd_size));
  583. if (!pgd_page)
  584. return -ENOMEM;
  585. kvm->arch.pgd = page_to_virt(pgd_page);
  586. kvm->arch.pgd_phys = page_to_phys(pgd_page);
  587. return 0;
  588. }
  589. void kvm_riscv_gstage_free_pgd(struct kvm *kvm)
  590. {
  591. void *pgd = NULL;
  592. spin_lock(&kvm->mmu_lock);
  593. if (kvm->arch.pgd) {
  594. gstage_unmap_range(kvm, 0UL, gstage_gpa_size, false);
  595. pgd = READ_ONCE(kvm->arch.pgd);
  596. kvm->arch.pgd = NULL;
  597. kvm->arch.pgd_phys = 0;
  598. }
  599. spin_unlock(&kvm->mmu_lock);
  600. if (pgd)
  601. free_pages((unsigned long)pgd, get_order(gstage_pgd_size));
  602. }
  603. void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu)
  604. {
  605. unsigned long hgatp = gstage_mode;
  606. struct kvm_arch *k = &vcpu->kvm->arch;
  607. hgatp |= (READ_ONCE(k->vmid.vmid) << HGATP_VMID_SHIFT) & HGATP_VMID;
  608. hgatp |= (k->pgd_phys >> PAGE_SHIFT) & HGATP_PPN;
  609. csr_write(CSR_HGATP, hgatp);
  610. if (!kvm_riscv_gstage_vmid_bits())
  611. kvm_riscv_local_hfence_gvma_all();
  612. }
  613. void __init kvm_riscv_gstage_mode_detect(void)
  614. {
  615. #ifdef CONFIG_64BIT
  616. /* Try Sv57x4 G-stage mode */
  617. csr_write(CSR_HGATP, HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT);
  618. if ((csr_read(CSR_HGATP) >> HGATP_MODE_SHIFT) == HGATP_MODE_SV57X4) {
  619. gstage_mode = (HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT);
  620. gstage_pgd_levels = 5;
  621. goto skip_sv48x4_test;
  622. }
  623. /* Try Sv48x4 G-stage mode */
  624. csr_write(CSR_HGATP, HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT);
  625. if ((csr_read(CSR_HGATP) >> HGATP_MODE_SHIFT) == HGATP_MODE_SV48X4) {
  626. gstage_mode = (HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT);
  627. gstage_pgd_levels = 4;
  628. }
  629. skip_sv48x4_test:
  630. csr_write(CSR_HGATP, 0);
  631. kvm_riscv_local_hfence_gvma_all();
  632. #endif
  633. }
  634. unsigned long __init kvm_riscv_gstage_mode(void)
  635. {
  636. return gstage_mode >> HGATP_MODE_SHIFT;
  637. }
  638. int kvm_riscv_gstage_gpa_bits(void)
  639. {
  640. return gstage_gpa_bits;
  641. }