ivpu_pm.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2020-2024 Intel Corporation
  4. */
  5. #include <linux/highmem.h>
  6. #include <linux/moduleparam.h>
  7. #include <linux/pci.h>
  8. #include <linux/pm_runtime.h>
  9. #include <linux/reboot.h>
  10. #include "ivpu_coredump.h"
  11. #include "ivpu_drv.h"
  12. #include "ivpu_fw.h"
  13. #include "ivpu_fw_log.h"
  14. #include "ivpu_hw.h"
  15. #include "ivpu_ipc.h"
  16. #include "ivpu_job.h"
  17. #include "ivpu_jsm_msg.h"
  18. #include "ivpu_mmu.h"
  19. #include "ivpu_ms.h"
  20. #include "ivpu_pm.h"
  21. #include "vpu_boot_api.h"
  22. static bool ivpu_disable_recovery;
  23. module_param_named_unsafe(disable_recovery, ivpu_disable_recovery, bool, 0644);
  24. MODULE_PARM_DESC(disable_recovery, "Disables recovery when NPU hang is detected");
  25. static unsigned long ivpu_tdr_timeout_ms;
  26. module_param_named(tdr_timeout_ms, ivpu_tdr_timeout_ms, ulong, 0644);
  27. MODULE_PARM_DESC(tdr_timeout_ms, "Timeout for device hang detection, in milliseconds, 0 - default");
  28. #define PM_RESCHEDULE_LIMIT 5
  29. static void ivpu_pm_prepare_cold_boot(struct ivpu_device *vdev)
  30. {
  31. struct ivpu_fw_info *fw = vdev->fw;
  32. ivpu_cmdq_reset_all_contexts(vdev);
  33. ivpu_ipc_reset(vdev);
  34. ivpu_fw_log_reset(vdev);
  35. ivpu_fw_load(vdev);
  36. fw->entry_point = fw->cold_boot_entry_point;
  37. }
  38. static void ivpu_pm_prepare_warm_boot(struct ivpu_device *vdev)
  39. {
  40. struct ivpu_fw_info *fw = vdev->fw;
  41. struct vpu_boot_params *bp = ivpu_bo_vaddr(fw->mem);
  42. if (!bp->save_restore_ret_address) {
  43. ivpu_pm_prepare_cold_boot(vdev);
  44. return;
  45. }
  46. ivpu_dbg(vdev, FW_BOOT, "Save/restore entry point %llx", bp->save_restore_ret_address);
  47. fw->entry_point = bp->save_restore_ret_address;
  48. }
  49. static int ivpu_suspend(struct ivpu_device *vdev)
  50. {
  51. int ret;
  52. ivpu_prepare_for_reset(vdev);
  53. ret = ivpu_shutdown(vdev);
  54. if (ret)
  55. ivpu_err(vdev, "Failed to shutdown NPU: %d\n", ret);
  56. return ret;
  57. }
  58. static int ivpu_resume(struct ivpu_device *vdev)
  59. {
  60. int ret;
  61. retry:
  62. pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D0);
  63. pci_restore_state(to_pci_dev(vdev->drm.dev));
  64. ret = ivpu_hw_power_up(vdev);
  65. if (ret) {
  66. ivpu_err(vdev, "Failed to power up HW: %d\n", ret);
  67. goto err_power_down;
  68. }
  69. ret = ivpu_mmu_enable(vdev);
  70. if (ret) {
  71. ivpu_err(vdev, "Failed to resume MMU: %d\n", ret);
  72. goto err_power_down;
  73. }
  74. ret = ivpu_boot(vdev);
  75. if (ret)
  76. goto err_mmu_disable;
  77. return 0;
  78. err_mmu_disable:
  79. ivpu_mmu_disable(vdev);
  80. err_power_down:
  81. ivpu_hw_power_down(vdev);
  82. pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot);
  83. if (!ivpu_fw_is_cold_boot(vdev)) {
  84. ivpu_pm_prepare_cold_boot(vdev);
  85. goto retry;
  86. } else {
  87. ivpu_err(vdev, "Failed to resume the FW: %d\n", ret);
  88. }
  89. return ret;
  90. }
  91. static void ivpu_pm_reset_begin(struct ivpu_device *vdev)
  92. {
  93. pm_runtime_disable(vdev->drm.dev);
  94. atomic_inc(&vdev->pm->reset_counter);
  95. atomic_set(&vdev->pm->reset_pending, 1);
  96. down_write(&vdev->pm->reset_lock);
  97. }
  98. static void ivpu_pm_reset_complete(struct ivpu_device *vdev)
  99. {
  100. int ret;
  101. ivpu_pm_prepare_cold_boot(vdev);
  102. ivpu_jobs_abort_all(vdev);
  103. ivpu_ms_cleanup_all(vdev);
  104. ret = ivpu_resume(vdev);
  105. if (ret) {
  106. ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
  107. pm_runtime_set_suspended(vdev->drm.dev);
  108. } else {
  109. pm_runtime_set_active(vdev->drm.dev);
  110. }
  111. up_write(&vdev->pm->reset_lock);
  112. atomic_set(&vdev->pm->reset_pending, 0);
  113. pm_runtime_mark_last_busy(vdev->drm.dev);
  114. pm_runtime_enable(vdev->drm.dev);
  115. }
  116. static void ivpu_pm_recovery_work(struct work_struct *work)
  117. {
  118. struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, recovery_work);
  119. struct ivpu_device *vdev = pm->vdev;
  120. char *evt[2] = {"IVPU_PM_EVENT=IVPU_RECOVER", NULL};
  121. ivpu_err(vdev, "Recovering the NPU (reset #%d)\n", atomic_read(&vdev->pm->reset_counter));
  122. ivpu_pm_reset_begin(vdev);
  123. if (!pm_runtime_status_suspended(vdev->drm.dev)) {
  124. ivpu_jsm_state_dump(vdev);
  125. ivpu_dev_coredump(vdev);
  126. ivpu_suspend(vdev);
  127. }
  128. ivpu_pm_reset_complete(vdev);
  129. kobject_uevent_env(&vdev->drm.dev->kobj, KOBJ_CHANGE, evt);
  130. }
  131. void ivpu_pm_trigger_recovery(struct ivpu_device *vdev, const char *reason)
  132. {
  133. ivpu_err(vdev, "Recovery triggered by %s\n", reason);
  134. if (ivpu_disable_recovery) {
  135. ivpu_err(vdev, "Recovery not available when disable_recovery param is set\n");
  136. return;
  137. }
  138. if (ivpu_is_fpga(vdev)) {
  139. ivpu_err(vdev, "Recovery not available on FPGA\n");
  140. return;
  141. }
  142. /* Trigger recovery if it's not in progress */
  143. if (atomic_cmpxchg(&vdev->pm->reset_pending, 0, 1) == 0) {
  144. ivpu_hw_diagnose_failure(vdev);
  145. ivpu_hw_irq_disable(vdev); /* Disable IRQ early to protect from IRQ storm */
  146. queue_work(system_long_wq, &vdev->pm->recovery_work);
  147. }
  148. }
  149. static void ivpu_job_timeout_work(struct work_struct *work)
  150. {
  151. struct ivpu_pm_info *pm = container_of(work, struct ivpu_pm_info, job_timeout_work.work);
  152. struct ivpu_device *vdev = pm->vdev;
  153. ivpu_pm_trigger_recovery(vdev, "TDR");
  154. }
  155. void ivpu_start_job_timeout_detection(struct ivpu_device *vdev)
  156. {
  157. unsigned long timeout_ms = ivpu_tdr_timeout_ms ? ivpu_tdr_timeout_ms : vdev->timeout.tdr;
  158. /* No-op if already queued */
  159. queue_delayed_work(system_wq, &vdev->pm->job_timeout_work, msecs_to_jiffies(timeout_ms));
  160. }
  161. void ivpu_stop_job_timeout_detection(struct ivpu_device *vdev)
  162. {
  163. cancel_delayed_work_sync(&vdev->pm->job_timeout_work);
  164. }
  165. int ivpu_pm_suspend_cb(struct device *dev)
  166. {
  167. struct drm_device *drm = dev_get_drvdata(dev);
  168. struct ivpu_device *vdev = to_ivpu_device(drm);
  169. unsigned long timeout;
  170. ivpu_dbg(vdev, PM, "Suspend..\n");
  171. timeout = jiffies + msecs_to_jiffies(vdev->timeout.tdr);
  172. while (!ivpu_hw_is_idle(vdev)) {
  173. cond_resched();
  174. if (time_after_eq(jiffies, timeout)) {
  175. ivpu_err(vdev, "Failed to enter idle on system suspend\n");
  176. return -EBUSY;
  177. }
  178. }
  179. ivpu_jsm_pwr_d0i3_enter(vdev);
  180. ivpu_suspend(vdev);
  181. ivpu_pm_prepare_warm_boot(vdev);
  182. ivpu_dbg(vdev, PM, "Suspend done.\n");
  183. return 0;
  184. }
  185. int ivpu_pm_resume_cb(struct device *dev)
  186. {
  187. struct drm_device *drm = dev_get_drvdata(dev);
  188. struct ivpu_device *vdev = to_ivpu_device(drm);
  189. int ret;
  190. ivpu_dbg(vdev, PM, "Resume..\n");
  191. ret = ivpu_resume(vdev);
  192. if (ret)
  193. ivpu_err(vdev, "Failed to resume: %d\n", ret);
  194. ivpu_dbg(vdev, PM, "Resume done.\n");
  195. return ret;
  196. }
  197. int ivpu_pm_runtime_suspend_cb(struct device *dev)
  198. {
  199. struct drm_device *drm = dev_get_drvdata(dev);
  200. struct ivpu_device *vdev = to_ivpu_device(drm);
  201. int ret, ret_d0i3;
  202. bool is_idle;
  203. drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa));
  204. drm_WARN_ON(&vdev->drm, work_pending(&vdev->pm->recovery_work));
  205. ivpu_dbg(vdev, PM, "Runtime suspend..\n");
  206. ivpu_mmu_disable(vdev);
  207. is_idle = ivpu_hw_is_idle(vdev) || vdev->pm->dct_active_percent;
  208. if (!is_idle)
  209. ivpu_err(vdev, "NPU is not idle before autosuspend\n");
  210. ret_d0i3 = ivpu_jsm_pwr_d0i3_enter(vdev);
  211. if (ret_d0i3)
  212. ivpu_err(vdev, "Failed to prepare for d0i3: %d\n", ret_d0i3);
  213. ret = ivpu_suspend(vdev);
  214. if (ret)
  215. ivpu_err(vdev, "Failed to suspend NPU: %d\n", ret);
  216. if (!is_idle || ret_d0i3) {
  217. ivpu_err(vdev, "Forcing cold boot due to previous errors\n");
  218. atomic_inc(&vdev->pm->reset_counter);
  219. ivpu_dev_coredump(vdev);
  220. ivpu_pm_prepare_cold_boot(vdev);
  221. } else {
  222. ivpu_pm_prepare_warm_boot(vdev);
  223. }
  224. ivpu_dbg(vdev, PM, "Runtime suspend done.\n");
  225. return 0;
  226. }
  227. int ivpu_pm_runtime_resume_cb(struct device *dev)
  228. {
  229. struct drm_device *drm = dev_get_drvdata(dev);
  230. struct ivpu_device *vdev = to_ivpu_device(drm);
  231. int ret;
  232. ivpu_dbg(vdev, PM, "Runtime resume..\n");
  233. ret = ivpu_resume(vdev);
  234. if (ret)
  235. ivpu_err(vdev, "Failed to set RESUME state: %d\n", ret);
  236. ivpu_dbg(vdev, PM, "Runtime resume done.\n");
  237. return ret;
  238. }
  239. int ivpu_rpm_get(struct ivpu_device *vdev)
  240. {
  241. int ret;
  242. ret = pm_runtime_resume_and_get(vdev->drm.dev);
  243. if (ret < 0) {
  244. ivpu_err(vdev, "Failed to resume NPU: %d\n", ret);
  245. pm_runtime_set_suspended(vdev->drm.dev);
  246. }
  247. return ret;
  248. }
  249. void ivpu_rpm_put(struct ivpu_device *vdev)
  250. {
  251. pm_runtime_mark_last_busy(vdev->drm.dev);
  252. pm_runtime_put_autosuspend(vdev->drm.dev);
  253. }
  254. void ivpu_pm_reset_prepare_cb(struct pci_dev *pdev)
  255. {
  256. struct ivpu_device *vdev = pci_get_drvdata(pdev);
  257. ivpu_dbg(vdev, PM, "Pre-reset..\n");
  258. ivpu_pm_reset_begin(vdev);
  259. if (!pm_runtime_status_suspended(vdev->drm.dev)) {
  260. ivpu_prepare_for_reset(vdev);
  261. ivpu_hw_reset(vdev);
  262. }
  263. ivpu_dbg(vdev, PM, "Pre-reset done.\n");
  264. }
  265. void ivpu_pm_reset_done_cb(struct pci_dev *pdev)
  266. {
  267. struct ivpu_device *vdev = pci_get_drvdata(pdev);
  268. ivpu_dbg(vdev, PM, "Post-reset..\n");
  269. ivpu_pm_reset_complete(vdev);
  270. ivpu_dbg(vdev, PM, "Post-reset done.\n");
  271. }
  272. void ivpu_pm_init(struct ivpu_device *vdev)
  273. {
  274. struct device *dev = vdev->drm.dev;
  275. struct ivpu_pm_info *pm = vdev->pm;
  276. int delay;
  277. pm->vdev = vdev;
  278. init_rwsem(&pm->reset_lock);
  279. atomic_set(&pm->reset_pending, 0);
  280. atomic_set(&pm->reset_counter, 0);
  281. INIT_WORK(&pm->recovery_work, ivpu_pm_recovery_work);
  282. INIT_DELAYED_WORK(&pm->job_timeout_work, ivpu_job_timeout_work);
  283. if (ivpu_disable_recovery)
  284. delay = -1;
  285. else
  286. delay = vdev->timeout.autosuspend;
  287. pm_runtime_use_autosuspend(dev);
  288. pm_runtime_set_autosuspend_delay(dev, delay);
  289. pm_runtime_set_active(dev);
  290. ivpu_dbg(vdev, PM, "Autosuspend delay = %d\n", delay);
  291. }
  292. void ivpu_pm_disable_recovery(struct ivpu_device *vdev)
  293. {
  294. drm_WARN_ON(&vdev->drm, delayed_work_pending(&vdev->pm->job_timeout_work));
  295. disable_work_sync(&vdev->pm->recovery_work);
  296. }
  297. void ivpu_pm_enable(struct ivpu_device *vdev)
  298. {
  299. struct device *dev = vdev->drm.dev;
  300. pm_runtime_allow(dev);
  301. pm_runtime_mark_last_busy(dev);
  302. pm_runtime_put_autosuspend(dev);
  303. }
  304. void ivpu_pm_disable(struct ivpu_device *vdev)
  305. {
  306. pm_runtime_get_noresume(vdev->drm.dev);
  307. pm_runtime_forbid(vdev->drm.dev);
  308. }
  309. int ivpu_pm_dct_init(struct ivpu_device *vdev)
  310. {
  311. if (vdev->pm->dct_active_percent)
  312. return ivpu_pm_dct_enable(vdev, vdev->pm->dct_active_percent);
  313. return 0;
  314. }
  315. int ivpu_pm_dct_enable(struct ivpu_device *vdev, u8 active_percent)
  316. {
  317. u32 active_us, inactive_us;
  318. int ret;
  319. if (active_percent == 0 || active_percent > 100)
  320. return -EINVAL;
  321. active_us = (DCT_PERIOD_US * active_percent) / 100;
  322. inactive_us = DCT_PERIOD_US - active_us;
  323. vdev->pm->dct_active_percent = active_percent;
  324. ivpu_dbg(vdev, PM, "DCT requested %u%% (D0: %uus, D0i2: %uus)\n",
  325. active_percent, active_us, inactive_us);
  326. ret = ivpu_jsm_dct_enable(vdev, active_us, inactive_us);
  327. if (ret) {
  328. ivpu_err_ratelimited(vdev, "Filed to enable DCT: %d\n", ret);
  329. return ret;
  330. }
  331. return 0;
  332. }
  333. int ivpu_pm_dct_disable(struct ivpu_device *vdev)
  334. {
  335. int ret;
  336. vdev->pm->dct_active_percent = 0;
  337. ivpu_dbg(vdev, PM, "DCT requested to be disabled\n");
  338. ret = ivpu_jsm_dct_disable(vdev);
  339. if (ret) {
  340. ivpu_err_ratelimited(vdev, "Filed to disable DCT: %d\n", ret);
  341. return ret;
  342. }
  343. return 0;
  344. }
  345. void ivpu_pm_dct_irq_thread_handler(struct ivpu_device *vdev)
  346. {
  347. bool enable;
  348. int ret;
  349. if (ivpu_hw_btrs_dct_get_request(vdev, &enable))
  350. return;
  351. if (enable)
  352. ret = ivpu_pm_dct_enable(vdev, DCT_DEFAULT_ACTIVE_PERCENT);
  353. else
  354. ret = ivpu_pm_dct_disable(vdev);
  355. if (!ret)
  356. ivpu_hw_btrs_dct_set_status(vdev, enable, vdev->pm->dct_active_percent);
  357. }