tpm2-cmd.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2014, 2015 Intel Corporation
  4. *
  5. * Authors:
  6. * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
  7. *
  8. * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  9. *
  10. * This file contains TPM2 protocol implementations of the commands
  11. * used by the kernel internally.
  12. */
  13. #include "tpm.h"
  14. #include <crypto/hash_info.h>
  15. static bool disable_pcr_integrity;
  16. module_param(disable_pcr_integrity, bool, 0444);
  17. MODULE_PARM_DESC(disable_pcr_integrity, "Disable integrity protection of TPM2_PCR_Extend");
  18. static struct tpm2_hash tpm2_hash_map[] = {
  19. {HASH_ALGO_SHA1, TPM_ALG_SHA1},
  20. {HASH_ALGO_SHA256, TPM_ALG_SHA256},
  21. {HASH_ALGO_SHA384, TPM_ALG_SHA384},
  22. {HASH_ALGO_SHA512, TPM_ALG_SHA512},
  23. {HASH_ALGO_SM3_256, TPM_ALG_SM3_256},
  24. };
  25. int tpm2_get_timeouts(struct tpm_chip *chip)
  26. {
  27. /* Fixed timeouts for TPM2 */
  28. chip->timeout_a = msecs_to_jiffies(TPM2_TIMEOUT_A);
  29. chip->timeout_b = msecs_to_jiffies(TPM2_TIMEOUT_B);
  30. chip->timeout_c = msecs_to_jiffies(TPM2_TIMEOUT_C);
  31. chip->timeout_d = msecs_to_jiffies(TPM2_TIMEOUT_D);
  32. /* PTP spec timeouts */
  33. chip->duration[TPM_SHORT] = msecs_to_jiffies(TPM2_DURATION_SHORT);
  34. chip->duration[TPM_MEDIUM] = msecs_to_jiffies(TPM2_DURATION_MEDIUM);
  35. chip->duration[TPM_LONG] = msecs_to_jiffies(TPM2_DURATION_LONG);
  36. /* Key creation commands long timeouts */
  37. chip->duration[TPM_LONG_LONG] =
  38. msecs_to_jiffies(TPM2_DURATION_LONG_LONG);
  39. chip->flags |= TPM_CHIP_FLAG_HAVE_TIMEOUTS;
  40. return 0;
  41. }
  42. /**
  43. * tpm2_ordinal_duration_index() - returns an index to the chip duration table
  44. * @ordinal: TPM command ordinal.
  45. *
  46. * The function returns an index to the chip duration table
  47. * (enum tpm_duration), that describes the maximum amount of
  48. * time the chip could take to return the result for a particular ordinal.
  49. *
  50. * The values of the MEDIUM, and LONG durations are taken
  51. * from the PC Client Profile (PTP) specification (750, 2000 msec)
  52. *
  53. * LONG_LONG is for commands that generates keys which empirically takes
  54. * a longer time on some systems.
  55. *
  56. * Return:
  57. * * TPM_MEDIUM
  58. * * TPM_LONG
  59. * * TPM_LONG_LONG
  60. * * TPM_UNDEFINED
  61. */
  62. static u8 tpm2_ordinal_duration_index(u32 ordinal)
  63. {
  64. switch (ordinal) {
  65. /* Startup */
  66. case TPM2_CC_STARTUP: /* 144 */
  67. return TPM_MEDIUM;
  68. case TPM2_CC_SELF_TEST: /* 143 */
  69. return TPM_LONG;
  70. case TPM2_CC_GET_RANDOM: /* 17B */
  71. return TPM_LONG;
  72. case TPM2_CC_SEQUENCE_UPDATE: /* 15C */
  73. return TPM_MEDIUM;
  74. case TPM2_CC_SEQUENCE_COMPLETE: /* 13E */
  75. return TPM_MEDIUM;
  76. case TPM2_CC_EVENT_SEQUENCE_COMPLETE: /* 185 */
  77. return TPM_MEDIUM;
  78. case TPM2_CC_HASH_SEQUENCE_START: /* 186 */
  79. return TPM_MEDIUM;
  80. case TPM2_CC_VERIFY_SIGNATURE: /* 177 */
  81. return TPM_LONG_LONG;
  82. case TPM2_CC_PCR_EXTEND: /* 182 */
  83. return TPM_MEDIUM;
  84. case TPM2_CC_HIERARCHY_CONTROL: /* 121 */
  85. return TPM_LONG;
  86. case TPM2_CC_HIERARCHY_CHANGE_AUTH: /* 129 */
  87. return TPM_LONG;
  88. case TPM2_CC_GET_CAPABILITY: /* 17A */
  89. return TPM_MEDIUM;
  90. case TPM2_CC_NV_READ: /* 14E */
  91. return TPM_LONG;
  92. case TPM2_CC_CREATE_PRIMARY: /* 131 */
  93. return TPM_LONG_LONG;
  94. case TPM2_CC_CREATE: /* 153 */
  95. return TPM_LONG_LONG;
  96. case TPM2_CC_CREATE_LOADED: /* 191 */
  97. return TPM_LONG_LONG;
  98. default:
  99. return TPM_UNDEFINED;
  100. }
  101. }
  102. /**
  103. * tpm2_calc_ordinal_duration() - calculate the maximum command duration
  104. * @chip: TPM chip to use.
  105. * @ordinal: TPM command ordinal.
  106. *
  107. * The function returns the maximum amount of time the chip could take
  108. * to return the result for a particular ordinal in jiffies.
  109. *
  110. * Return: A maximal duration time for an ordinal in jiffies.
  111. */
  112. unsigned long tpm2_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal)
  113. {
  114. unsigned int index;
  115. index = tpm2_ordinal_duration_index(ordinal);
  116. if (index != TPM_UNDEFINED)
  117. return chip->duration[index];
  118. else
  119. return msecs_to_jiffies(TPM2_DURATION_DEFAULT);
  120. }
  121. struct tpm2_pcr_read_out {
  122. __be32 update_cnt;
  123. __be32 pcr_selects_cnt;
  124. __be16 hash_alg;
  125. u8 pcr_select_size;
  126. u8 pcr_select[TPM2_PCR_SELECT_MIN];
  127. __be32 digests_cnt;
  128. __be16 digest_size;
  129. u8 digest[];
  130. } __packed;
  131. /**
  132. * tpm2_pcr_read() - read a PCR value
  133. * @chip: TPM chip to use.
  134. * @pcr_idx: index of the PCR to read.
  135. * @digest: PCR bank and buffer current PCR value is written to.
  136. * @digest_size_ptr: pointer to variable that stores the digest size.
  137. *
  138. * Return: Same as with tpm_transmit_cmd.
  139. */
  140. int tpm2_pcr_read(struct tpm_chip *chip, u32 pcr_idx,
  141. struct tpm_digest *digest, u16 *digest_size_ptr)
  142. {
  143. int i;
  144. int rc;
  145. struct tpm_buf buf;
  146. struct tpm2_pcr_read_out *out;
  147. u8 pcr_select[TPM2_PCR_SELECT_MIN] = {0};
  148. u16 digest_size;
  149. u16 expected_digest_size = 0;
  150. if (pcr_idx >= TPM2_PLATFORM_PCR)
  151. return -EINVAL;
  152. if (!digest_size_ptr) {
  153. for (i = 0; i < chip->nr_allocated_banks &&
  154. chip->allocated_banks[i].alg_id != digest->alg_id; i++)
  155. ;
  156. if (i == chip->nr_allocated_banks)
  157. return -EINVAL;
  158. expected_digest_size = chip->allocated_banks[i].digest_size;
  159. }
  160. rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_PCR_READ);
  161. if (rc)
  162. return rc;
  163. pcr_select[pcr_idx >> 3] = 1 << (pcr_idx & 0x7);
  164. tpm_buf_append_u32(&buf, 1);
  165. tpm_buf_append_u16(&buf, digest->alg_id);
  166. tpm_buf_append_u8(&buf, TPM2_PCR_SELECT_MIN);
  167. tpm_buf_append(&buf, (const unsigned char *)pcr_select,
  168. sizeof(pcr_select));
  169. rc = tpm_transmit_cmd(chip, &buf, 0, "attempting to read a pcr value");
  170. if (rc)
  171. goto out;
  172. out = (struct tpm2_pcr_read_out *)&buf.data[TPM_HEADER_SIZE];
  173. digest_size = be16_to_cpu(out->digest_size);
  174. if (digest_size > sizeof(digest->digest) ||
  175. (!digest_size_ptr && digest_size != expected_digest_size)) {
  176. rc = -EINVAL;
  177. goto out;
  178. }
  179. if (digest_size_ptr)
  180. *digest_size_ptr = digest_size;
  181. memcpy(digest->digest, out->digest, digest_size);
  182. out:
  183. tpm_buf_destroy(&buf);
  184. return rc;
  185. }
  186. /**
  187. * tpm2_pcr_extend() - extend a PCR value
  188. *
  189. * @chip: TPM chip to use.
  190. * @pcr_idx: index of the PCR.
  191. * @digests: list of pcr banks and corresponding digest values to extend.
  192. *
  193. * Return: Same as with tpm_transmit_cmd.
  194. */
  195. int tpm2_pcr_extend(struct tpm_chip *chip, u32 pcr_idx,
  196. struct tpm_digest *digests)
  197. {
  198. struct tpm_buf buf;
  199. int rc;
  200. int i;
  201. if (!disable_pcr_integrity) {
  202. rc = tpm2_start_auth_session(chip);
  203. if (rc)
  204. return rc;
  205. }
  206. rc = tpm_buf_init(&buf, TPM2_ST_SESSIONS, TPM2_CC_PCR_EXTEND);
  207. if (rc) {
  208. if (!disable_pcr_integrity)
  209. tpm2_end_auth_session(chip);
  210. return rc;
  211. }
  212. if (!disable_pcr_integrity) {
  213. tpm_buf_append_name(chip, &buf, pcr_idx, NULL);
  214. tpm_buf_append_hmac_session(chip, &buf, 0, NULL, 0);
  215. } else {
  216. tpm_buf_append_handle(chip, &buf, pcr_idx);
  217. tpm_buf_append_auth(chip, &buf, 0, NULL, 0);
  218. }
  219. tpm_buf_append_u32(&buf, chip->nr_allocated_banks);
  220. for (i = 0; i < chip->nr_allocated_banks; i++) {
  221. tpm_buf_append_u16(&buf, digests[i].alg_id);
  222. tpm_buf_append(&buf, (const unsigned char *)&digests[i].digest,
  223. chip->allocated_banks[i].digest_size);
  224. }
  225. if (!disable_pcr_integrity)
  226. tpm_buf_fill_hmac_session(chip, &buf);
  227. rc = tpm_transmit_cmd(chip, &buf, 0, "attempting extend a PCR value");
  228. if (!disable_pcr_integrity)
  229. rc = tpm_buf_check_hmac_response(chip, &buf, rc);
  230. tpm_buf_destroy(&buf);
  231. return rc;
  232. }
  233. struct tpm2_get_random_out {
  234. __be16 size;
  235. u8 buffer[TPM_MAX_RNG_DATA];
  236. } __packed;
  237. /**
  238. * tpm2_get_random() - get random bytes from the TPM RNG
  239. *
  240. * @chip: a &tpm_chip instance
  241. * @dest: destination buffer
  242. * @max: the max number of random bytes to pull
  243. *
  244. * Return:
  245. * size of the buffer on success,
  246. * -errno otherwise (positive TPM return codes are masked to -EIO)
  247. */
  248. int tpm2_get_random(struct tpm_chip *chip, u8 *dest, size_t max)
  249. {
  250. struct tpm2_get_random_out *out;
  251. struct tpm_header *head;
  252. struct tpm_buf buf;
  253. u32 recd;
  254. u32 num_bytes = max;
  255. int err;
  256. int total = 0;
  257. int retries = 5;
  258. u8 *dest_ptr = dest;
  259. off_t offset;
  260. if (!num_bytes || max > TPM_MAX_RNG_DATA)
  261. return -EINVAL;
  262. err = tpm2_start_auth_session(chip);
  263. if (err)
  264. return err;
  265. err = tpm_buf_init(&buf, 0, 0);
  266. if (err) {
  267. tpm2_end_auth_session(chip);
  268. return err;
  269. }
  270. do {
  271. tpm_buf_reset(&buf, TPM2_ST_SESSIONS, TPM2_CC_GET_RANDOM);
  272. tpm_buf_append_hmac_session_opt(chip, &buf, TPM2_SA_ENCRYPT
  273. | TPM2_SA_CONTINUE_SESSION,
  274. NULL, 0);
  275. tpm_buf_append_u16(&buf, num_bytes);
  276. tpm_buf_fill_hmac_session(chip, &buf);
  277. err = tpm_transmit_cmd(chip, &buf,
  278. offsetof(struct tpm2_get_random_out,
  279. buffer),
  280. "attempting get random");
  281. err = tpm_buf_check_hmac_response(chip, &buf, err);
  282. if (err) {
  283. if (err > 0)
  284. err = -EIO;
  285. goto out;
  286. }
  287. head = (struct tpm_header *)buf.data;
  288. offset = TPM_HEADER_SIZE;
  289. /* Skip the parameter size field: */
  290. if (be16_to_cpu(head->tag) == TPM2_ST_SESSIONS)
  291. offset += 4;
  292. out = (struct tpm2_get_random_out *)&buf.data[offset];
  293. recd = min_t(u32, be16_to_cpu(out->size), num_bytes);
  294. if (tpm_buf_length(&buf) <
  295. TPM_HEADER_SIZE +
  296. offsetof(struct tpm2_get_random_out, buffer) +
  297. recd) {
  298. err = -EFAULT;
  299. goto out;
  300. }
  301. memcpy(dest_ptr, out->buffer, recd);
  302. dest_ptr += recd;
  303. total += recd;
  304. num_bytes -= recd;
  305. } while (retries-- && total < max);
  306. tpm_buf_destroy(&buf);
  307. tpm2_end_auth_session(chip);
  308. return total ? total : -EIO;
  309. out:
  310. tpm_buf_destroy(&buf);
  311. tpm2_end_auth_session(chip);
  312. return err;
  313. }
  314. /**
  315. * tpm2_flush_context() - execute a TPM2_FlushContext command
  316. * @chip: TPM chip to use
  317. * @handle: context handle
  318. */
  319. void tpm2_flush_context(struct tpm_chip *chip, u32 handle)
  320. {
  321. struct tpm_buf buf;
  322. int rc;
  323. rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_FLUSH_CONTEXT);
  324. if (rc) {
  325. dev_warn(&chip->dev, "0x%08x was not flushed, out of memory\n",
  326. handle);
  327. return;
  328. }
  329. tpm_buf_append_u32(&buf, handle);
  330. tpm_transmit_cmd(chip, &buf, 0, "flushing context");
  331. tpm_buf_destroy(&buf);
  332. }
  333. EXPORT_SYMBOL_GPL(tpm2_flush_context);
  334. struct tpm2_get_cap_out {
  335. u8 more_data;
  336. __be32 subcap_id;
  337. __be32 property_cnt;
  338. __be32 property_id;
  339. __be32 value;
  340. } __packed;
  341. /**
  342. * tpm2_get_tpm_pt() - get value of a TPM_CAP_TPM_PROPERTIES type property
  343. * @chip: a &tpm_chip instance
  344. * @property_id: property ID.
  345. * @value: output variable.
  346. * @desc: passed to tpm_transmit_cmd()
  347. *
  348. * Return:
  349. * 0 on success,
  350. * -errno or a TPM return code otherwise
  351. */
  352. ssize_t tpm2_get_tpm_pt(struct tpm_chip *chip, u32 property_id, u32 *value,
  353. const char *desc)
  354. {
  355. struct tpm2_get_cap_out *out;
  356. struct tpm_buf buf;
  357. int rc;
  358. rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_CAPABILITY);
  359. if (rc)
  360. return rc;
  361. tpm_buf_append_u32(&buf, TPM2_CAP_TPM_PROPERTIES);
  362. tpm_buf_append_u32(&buf, property_id);
  363. tpm_buf_append_u32(&buf, 1);
  364. rc = tpm_transmit_cmd(chip, &buf, 0, NULL);
  365. if (!rc) {
  366. out = (struct tpm2_get_cap_out *)
  367. &buf.data[TPM_HEADER_SIZE];
  368. /*
  369. * To prevent failing boot up of some systems, Infineon TPM2.0
  370. * returns SUCCESS on TPM2_Startup in field upgrade mode. Also
  371. * the TPM2_Getcapability command returns a zero length list
  372. * in field upgrade mode.
  373. */
  374. if (be32_to_cpu(out->property_cnt) > 0)
  375. *value = be32_to_cpu(out->value);
  376. else
  377. rc = -ENODATA;
  378. }
  379. tpm_buf_destroy(&buf);
  380. return rc;
  381. }
  382. EXPORT_SYMBOL_GPL(tpm2_get_tpm_pt);
  383. /**
  384. * tpm2_shutdown() - send a TPM shutdown command
  385. *
  386. * Sends a TPM shutdown command. The shutdown command is used in call
  387. * sites where the system is going down. If it fails, there is not much
  388. * that can be done except print an error message.
  389. *
  390. * @chip: a &tpm_chip instance
  391. * @shutdown_type: TPM_SU_CLEAR or TPM_SU_STATE.
  392. */
  393. void tpm2_shutdown(struct tpm_chip *chip, u16 shutdown_type)
  394. {
  395. struct tpm_buf buf;
  396. int rc;
  397. rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_SHUTDOWN);
  398. if (rc)
  399. return;
  400. tpm_buf_append_u16(&buf, shutdown_type);
  401. tpm_transmit_cmd(chip, &buf, 0, "stopping the TPM");
  402. tpm_buf_destroy(&buf);
  403. }
  404. /**
  405. * tpm2_do_selftest() - ensure that all self tests have passed
  406. *
  407. * @chip: TPM chip to use
  408. *
  409. * Return: Same as with tpm_transmit_cmd.
  410. *
  411. * The TPM can either run all self tests synchronously and then return
  412. * RC_SUCCESS once all tests were successful. Or it can choose to run the tests
  413. * asynchronously and return RC_TESTING immediately while the self tests still
  414. * execute in the background. This function handles both cases and waits until
  415. * all tests have completed.
  416. */
  417. static int tpm2_do_selftest(struct tpm_chip *chip)
  418. {
  419. struct tpm_buf buf;
  420. int full;
  421. int rc;
  422. for (full = 0; full < 2; full++) {
  423. rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_SELF_TEST);
  424. if (rc)
  425. return rc;
  426. tpm_buf_append_u8(&buf, full);
  427. rc = tpm_transmit_cmd(chip, &buf, 0,
  428. "attempting the self test");
  429. tpm_buf_destroy(&buf);
  430. if (rc == TPM2_RC_TESTING)
  431. rc = TPM2_RC_SUCCESS;
  432. if (rc == TPM2_RC_INITIALIZE || rc == TPM2_RC_SUCCESS)
  433. return rc;
  434. }
  435. return rc;
  436. }
  437. /**
  438. * tpm2_probe() - probe for the TPM 2.0 protocol
  439. * @chip: a &tpm_chip instance
  440. *
  441. * Send an idempotent TPM 2.0 command and see whether there is TPM2 chip in the
  442. * other end based on the response tag. The flag TPM_CHIP_FLAG_TPM2 is set by
  443. * this function if this is the case.
  444. *
  445. * Return:
  446. * 0 on success,
  447. * -errno otherwise
  448. */
  449. int tpm2_probe(struct tpm_chip *chip)
  450. {
  451. struct tpm_header *out;
  452. struct tpm_buf buf;
  453. int rc;
  454. rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_CAPABILITY);
  455. if (rc)
  456. return rc;
  457. tpm_buf_append_u32(&buf, TPM2_CAP_TPM_PROPERTIES);
  458. tpm_buf_append_u32(&buf, TPM_PT_TOTAL_COMMANDS);
  459. tpm_buf_append_u32(&buf, 1);
  460. rc = tpm_transmit_cmd(chip, &buf, 0, NULL);
  461. /* We ignore TPM return codes on purpose. */
  462. if (rc >= 0) {
  463. out = (struct tpm_header *)buf.data;
  464. if (be16_to_cpu(out->tag) == TPM2_ST_NO_SESSIONS)
  465. chip->flags |= TPM_CHIP_FLAG_TPM2;
  466. }
  467. tpm_buf_destroy(&buf);
  468. return 0;
  469. }
  470. EXPORT_SYMBOL_GPL(tpm2_probe);
  471. static int tpm2_init_bank_info(struct tpm_chip *chip, u32 bank_index)
  472. {
  473. struct tpm_bank_info *bank = chip->allocated_banks + bank_index;
  474. struct tpm_digest digest = { .alg_id = bank->alg_id };
  475. int i;
  476. /*
  477. * Avoid unnecessary PCR read operations to reduce overhead
  478. * and obtain identifiers of the crypto subsystem.
  479. */
  480. for (i = 0; i < ARRAY_SIZE(tpm2_hash_map); i++) {
  481. enum hash_algo crypto_algo = tpm2_hash_map[i].crypto_id;
  482. if (bank->alg_id != tpm2_hash_map[i].tpm_id)
  483. continue;
  484. bank->digest_size = hash_digest_size[crypto_algo];
  485. bank->crypto_id = crypto_algo;
  486. return 0;
  487. }
  488. bank->crypto_id = HASH_ALGO__LAST;
  489. return tpm2_pcr_read(chip, 0, &digest, &bank->digest_size);
  490. }
  491. struct tpm2_pcr_selection {
  492. __be16 hash_alg;
  493. u8 size_of_select;
  494. u8 pcr_select[3];
  495. } __packed;
  496. ssize_t tpm2_get_pcr_allocation(struct tpm_chip *chip)
  497. {
  498. struct tpm2_pcr_selection pcr_selection;
  499. struct tpm_buf buf;
  500. void *marker;
  501. void *end;
  502. void *pcr_select_offset;
  503. u32 sizeof_pcr_selection;
  504. u32 nr_possible_banks;
  505. u32 nr_alloc_banks = 0;
  506. u16 hash_alg;
  507. u32 rsp_len;
  508. int rc;
  509. int i = 0;
  510. rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_CAPABILITY);
  511. if (rc)
  512. return rc;
  513. tpm_buf_append_u32(&buf, TPM2_CAP_PCRS);
  514. tpm_buf_append_u32(&buf, 0);
  515. tpm_buf_append_u32(&buf, 1);
  516. rc = tpm_transmit_cmd(chip, &buf, 9, "get tpm pcr allocation");
  517. if (rc)
  518. goto out;
  519. nr_possible_banks = be32_to_cpup(
  520. (__be32 *)&buf.data[TPM_HEADER_SIZE + 5]);
  521. chip->allocated_banks = kcalloc(nr_possible_banks,
  522. sizeof(*chip->allocated_banks),
  523. GFP_KERNEL);
  524. if (!chip->allocated_banks) {
  525. rc = -ENOMEM;
  526. goto out;
  527. }
  528. marker = &buf.data[TPM_HEADER_SIZE + 9];
  529. rsp_len = be32_to_cpup((__be32 *)&buf.data[2]);
  530. end = &buf.data[rsp_len];
  531. for (i = 0; i < nr_possible_banks; i++) {
  532. pcr_select_offset = marker +
  533. offsetof(struct tpm2_pcr_selection, size_of_select);
  534. if (pcr_select_offset >= end) {
  535. rc = -EFAULT;
  536. break;
  537. }
  538. memcpy(&pcr_selection, marker, sizeof(pcr_selection));
  539. hash_alg = be16_to_cpu(pcr_selection.hash_alg);
  540. pcr_select_offset = memchr_inv(pcr_selection.pcr_select, 0,
  541. pcr_selection.size_of_select);
  542. if (pcr_select_offset) {
  543. chip->allocated_banks[nr_alloc_banks].alg_id = hash_alg;
  544. rc = tpm2_init_bank_info(chip, nr_alloc_banks);
  545. if (rc < 0)
  546. break;
  547. nr_alloc_banks++;
  548. }
  549. sizeof_pcr_selection = sizeof(pcr_selection.hash_alg) +
  550. sizeof(pcr_selection.size_of_select) +
  551. pcr_selection.size_of_select;
  552. marker = marker + sizeof_pcr_selection;
  553. }
  554. chip->nr_allocated_banks = nr_alloc_banks;
  555. out:
  556. tpm_buf_destroy(&buf);
  557. return rc;
  558. }
  559. int tpm2_get_cc_attrs_tbl(struct tpm_chip *chip)
  560. {
  561. struct tpm_buf buf;
  562. u32 nr_commands;
  563. __be32 *attrs;
  564. u32 cc;
  565. int i;
  566. int rc;
  567. rc = tpm2_get_tpm_pt(chip, TPM_PT_TOTAL_COMMANDS, &nr_commands, NULL);
  568. if (rc)
  569. goto out;
  570. if (nr_commands > 0xFFFFF) {
  571. rc = -EFAULT;
  572. goto out;
  573. }
  574. chip->cc_attrs_tbl = devm_kcalloc(&chip->dev, 4, nr_commands,
  575. GFP_KERNEL);
  576. if (!chip->cc_attrs_tbl) {
  577. rc = -ENOMEM;
  578. goto out;
  579. }
  580. rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_CAPABILITY);
  581. if (rc)
  582. goto out;
  583. tpm_buf_append_u32(&buf, TPM2_CAP_COMMANDS);
  584. tpm_buf_append_u32(&buf, TPM2_CC_FIRST);
  585. tpm_buf_append_u32(&buf, nr_commands);
  586. rc = tpm_transmit_cmd(chip, &buf, 9 + 4 * nr_commands, NULL);
  587. if (rc) {
  588. tpm_buf_destroy(&buf);
  589. goto out;
  590. }
  591. if (nr_commands !=
  592. be32_to_cpup((__be32 *)&buf.data[TPM_HEADER_SIZE + 5])) {
  593. rc = -EFAULT;
  594. tpm_buf_destroy(&buf);
  595. goto out;
  596. }
  597. chip->nr_commands = nr_commands;
  598. attrs = (__be32 *)&buf.data[TPM_HEADER_SIZE + 9];
  599. for (i = 0; i < nr_commands; i++, attrs++) {
  600. chip->cc_attrs_tbl[i] = be32_to_cpup(attrs);
  601. cc = chip->cc_attrs_tbl[i] & 0xFFFF;
  602. if (cc == TPM2_CC_CONTEXT_SAVE || cc == TPM2_CC_FLUSH_CONTEXT) {
  603. chip->cc_attrs_tbl[i] &=
  604. ~(GENMASK(2, 0) << TPM2_CC_ATTR_CHANDLES);
  605. chip->cc_attrs_tbl[i] |= 1 << TPM2_CC_ATTR_CHANDLES;
  606. }
  607. }
  608. tpm_buf_destroy(&buf);
  609. out:
  610. if (rc > 0)
  611. rc = -ENODEV;
  612. return rc;
  613. }
  614. EXPORT_SYMBOL_GPL(tpm2_get_cc_attrs_tbl);
  615. /**
  616. * tpm2_startup - turn on the TPM
  617. * @chip: TPM chip to use
  618. *
  619. * Normally the firmware should start the TPM. This function is provided as a
  620. * workaround if this does not happen. A legal case for this could be for
  621. * example when a TPM emulator is used.
  622. *
  623. * Return: same as tpm_transmit_cmd()
  624. */
  625. static int tpm2_startup(struct tpm_chip *chip)
  626. {
  627. struct tpm_buf buf;
  628. int rc;
  629. dev_info(&chip->dev, "starting up the TPM manually\n");
  630. rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_STARTUP);
  631. if (rc < 0)
  632. return rc;
  633. tpm_buf_append_u16(&buf, TPM2_SU_CLEAR);
  634. rc = tpm_transmit_cmd(chip, &buf, 0, "attempting to start the TPM");
  635. tpm_buf_destroy(&buf);
  636. return rc;
  637. }
  638. /**
  639. * tpm2_auto_startup - Perform the standard automatic TPM initialization
  640. * sequence
  641. * @chip: TPM chip to use
  642. *
  643. * Returns 0 on success, < 0 in case of fatal error.
  644. */
  645. int tpm2_auto_startup(struct tpm_chip *chip)
  646. {
  647. int rc;
  648. rc = tpm2_get_timeouts(chip);
  649. if (rc)
  650. goto out;
  651. rc = tpm2_do_selftest(chip);
  652. if (rc && rc != TPM2_RC_INITIALIZE)
  653. goto out;
  654. if (rc == TPM2_RC_INITIALIZE) {
  655. rc = tpm2_startup(chip);
  656. if (rc)
  657. goto out;
  658. rc = tpm2_do_selftest(chip);
  659. if (rc)
  660. goto out;
  661. }
  662. rc = tpm2_get_cc_attrs_tbl(chip);
  663. if (rc == TPM2_RC_FAILURE || (rc < 0 && rc != -ENOMEM)) {
  664. dev_info(&chip->dev,
  665. "TPM in field failure mode, requires firmware upgrade\n");
  666. chip->flags |= TPM_CHIP_FLAG_FIRMWARE_UPGRADE;
  667. rc = 0;
  668. }
  669. if (rc)
  670. goto out;
  671. rc = tpm2_sessions_init(chip);
  672. out:
  673. /*
  674. * Infineon TPM in field upgrade mode will return no data for the number
  675. * of supported commands.
  676. */
  677. if (rc == TPM2_RC_UPGRADE || rc == -ENODATA) {
  678. dev_info(&chip->dev, "TPM in field upgrade mode, requires firmware upgrade\n");
  679. chip->flags |= TPM_CHIP_FLAG_FIRMWARE_UPGRADE;
  680. rc = 0;
  681. }
  682. if (rc > 0)
  683. rc = -ENODEV;
  684. return rc;
  685. }
  686. int tpm2_find_cc(struct tpm_chip *chip, u32 cc)
  687. {
  688. u32 cc_mask;
  689. int i;
  690. cc_mask = 1 << TPM2_CC_ATTR_VENDOR | GENMASK(15, 0);
  691. for (i = 0; i < chip->nr_commands; i++)
  692. if (cc == (chip->cc_attrs_tbl[i] & cc_mask))
  693. return i;
  694. return -1;
  695. }