freesync.c 44 KB

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  1. /*
  2. * Copyright 2016-2023 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: AMD
  23. *
  24. */
  25. #include "dm_services.h"
  26. #include "dc.h"
  27. #include "mod_freesync.h"
  28. #include "core_types.h"
  29. #define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32
  30. #define MIN_REFRESH_RANGE 10
  31. /* Refresh rate ramp at a fixed rate of 65 Hz/second */
  32. #define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
  33. /* Number of elements in the render times cache array */
  34. #define RENDER_TIMES_MAX_COUNT 10
  35. /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
  36. #define BTR_MAX_MARGIN 2500
  37. /* Threshold to change BTR multiplier (to avoid frequent changes) */
  38. #define BTR_DRIFT_MARGIN 2000
  39. /* Threshold to exit fixed refresh rate */
  40. #define FIXED_REFRESH_EXIT_MARGIN_IN_HZ 1
  41. /* Number of consecutive frames to check before entering/exiting fixed refresh */
  42. #define FIXED_REFRESH_ENTER_FRAME_COUNT 5
  43. #define FIXED_REFRESH_EXIT_FRAME_COUNT 10
  44. /* Flip interval workaround constants */
  45. #define VSYNCS_BETWEEN_FLIP_THRESHOLD 2
  46. #define FREESYNC_CONSEC_FLIP_AFTER_VSYNC 5
  47. #define FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US 500
  48. struct core_freesync {
  49. struct mod_freesync public;
  50. struct dc *dc;
  51. };
  52. #define MOD_FREESYNC_TO_CORE(mod_freesync)\
  53. container_of(mod_freesync, struct core_freesync, public)
  54. struct mod_freesync *mod_freesync_create(struct dc *dc)
  55. {
  56. struct core_freesync *core_freesync =
  57. kzalloc(sizeof(struct core_freesync), GFP_KERNEL);
  58. if (core_freesync == NULL)
  59. goto fail_alloc_context;
  60. if (dc == NULL)
  61. goto fail_construct;
  62. core_freesync->dc = dc;
  63. return &core_freesync->public;
  64. fail_construct:
  65. kfree(core_freesync);
  66. fail_alloc_context:
  67. return NULL;
  68. }
  69. void mod_freesync_destroy(struct mod_freesync *mod_freesync)
  70. {
  71. struct core_freesync *core_freesync = NULL;
  72. if (mod_freesync == NULL)
  73. return;
  74. core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
  75. kfree(core_freesync);
  76. }
  77. #if 0 /* Unused currently */
  78. static unsigned int calc_refresh_in_uhz_from_duration(
  79. unsigned int duration_in_ns)
  80. {
  81. unsigned int refresh_in_uhz =
  82. ((unsigned int)(div64_u64((1000000000ULL * 1000000),
  83. duration_in_ns)));
  84. return refresh_in_uhz;
  85. }
  86. #endif
  87. static unsigned int calc_duration_in_us_from_refresh_in_uhz(
  88. unsigned int refresh_in_uhz)
  89. {
  90. unsigned int duration_in_us =
  91. ((unsigned int)(div64_u64((1000000000ULL * 1000),
  92. refresh_in_uhz)));
  93. return duration_in_us;
  94. }
  95. static unsigned int calc_duration_in_us_from_v_total(
  96. const struct dc_stream_state *stream,
  97. const struct mod_vrr_params *in_vrr,
  98. unsigned int v_total)
  99. {
  100. unsigned int duration_in_us =
  101. (unsigned int)(div64_u64(((unsigned long long)(v_total)
  102. * 10000) * stream->timing.h_total,
  103. stream->timing.pix_clk_100hz));
  104. return duration_in_us;
  105. }
  106. static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)
  107. {
  108. unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total;
  109. if (stream->ctx->dc->caps.vtotal_limited_by_fp2) {
  110. max_hw_v_total -= stream->timing.v_front_porch + 1;
  111. }
  112. return max_hw_v_total;
  113. }
  114. unsigned int mod_freesync_calc_v_total_from_refresh(
  115. const struct dc_stream_state *stream,
  116. unsigned int refresh_in_uhz)
  117. {
  118. unsigned int v_total;
  119. unsigned int frame_duration_in_ns;
  120. frame_duration_in_ns =
  121. ((unsigned int)(div64_u64((1000000000ULL * 1000000),
  122. refresh_in_uhz)));
  123. v_total = div64_u64(div64_u64(((unsigned long long)(
  124. frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
  125. stream->timing.h_total) + 500000, 1000000);
  126. /* v_total cannot be less than nominal */
  127. if (v_total < stream->timing.v_total) {
  128. ASSERT(v_total < stream->timing.v_total);
  129. v_total = stream->timing.v_total;
  130. }
  131. return v_total;
  132. }
  133. static unsigned int calc_v_total_from_duration(
  134. const struct dc_stream_state *stream,
  135. const struct mod_vrr_params *vrr,
  136. unsigned int duration_in_us)
  137. {
  138. unsigned int v_total = 0;
  139. if (duration_in_us < vrr->min_duration_in_us)
  140. duration_in_us = vrr->min_duration_in_us;
  141. if (duration_in_us > vrr->max_duration_in_us)
  142. duration_in_us = vrr->max_duration_in_us;
  143. if (dc_is_hdmi_signal(stream->signal)) { // change for HDMI to comply with spec
  144. uint32_t h_total_up_scaled;
  145. h_total_up_scaled = stream->timing.h_total * 10000;
  146. v_total = div_u64((unsigned long long)duration_in_us
  147. * stream->timing.pix_clk_100hz + (h_total_up_scaled - 1),
  148. h_total_up_scaled); //ceiling for MMax and MMin for MVRR
  149. } else {
  150. v_total = div64_u64(div64_u64(((unsigned long long)(
  151. duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
  152. stream->timing.h_total), 1000);
  153. }
  154. /* v_total cannot be less than nominal */
  155. if (v_total < stream->timing.v_total) {
  156. ASSERT(v_total < stream->timing.v_total);
  157. v_total = stream->timing.v_total;
  158. }
  159. return v_total;
  160. }
  161. static void update_v_total_for_static_ramp(
  162. struct core_freesync *core_freesync,
  163. const struct dc_stream_state *stream,
  164. struct mod_vrr_params *in_out_vrr)
  165. {
  166. unsigned int v_total = 0;
  167. unsigned int current_duration_in_us =
  168. calc_duration_in_us_from_v_total(
  169. stream, in_out_vrr,
  170. in_out_vrr->adjust.v_total_max);
  171. unsigned int target_duration_in_us =
  172. calc_duration_in_us_from_refresh_in_uhz(
  173. in_out_vrr->fixed.target_refresh_in_uhz);
  174. bool ramp_direction_is_up = (current_duration_in_us >
  175. target_duration_in_us) ? true : false;
  176. /* Calculate ratio between new and current frame duration with 3 digit */
  177. unsigned int frame_duration_ratio = div64_u64(1000000,
  178. (1000 + div64_u64(((unsigned long long)(
  179. STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) *
  180. current_duration_in_us),
  181. 1000000)));
  182. /* Calculate delta between new and current frame duration in us */
  183. unsigned int frame_duration_delta = div64_u64(((unsigned long long)(
  184. current_duration_in_us) *
  185. (1000 - frame_duration_ratio)), 1000);
  186. /* Adjust frame duration delta based on ratio between current and
  187. * standard frame duration (frame duration at 60 Hz refresh rate).
  188. */
  189. unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)(
  190. frame_duration_delta) * current_duration_in_us), 16666);
  191. /* Going to a higher refresh rate (lower frame duration) */
  192. if (ramp_direction_is_up) {
  193. /* Reduce frame duration */
  194. current_duration_in_us -= ramp_rate_interpolated;
  195. /* Adjust for frame duration below min */
  196. if (current_duration_in_us <= target_duration_in_us) {
  197. in_out_vrr->fixed.ramping_active = false;
  198. in_out_vrr->fixed.ramping_done = true;
  199. current_duration_in_us =
  200. calc_duration_in_us_from_refresh_in_uhz(
  201. in_out_vrr->fixed.target_refresh_in_uhz);
  202. }
  203. /* Going to a lower refresh rate (larger frame duration) */
  204. } else {
  205. /* Increase frame duration */
  206. current_duration_in_us += ramp_rate_interpolated;
  207. /* Adjust for frame duration above max */
  208. if (current_duration_in_us >= target_duration_in_us) {
  209. in_out_vrr->fixed.ramping_active = false;
  210. in_out_vrr->fixed.ramping_done = true;
  211. current_duration_in_us =
  212. calc_duration_in_us_from_refresh_in_uhz(
  213. in_out_vrr->fixed.target_refresh_in_uhz);
  214. }
  215. }
  216. v_total = div64_u64(div64_u64(((unsigned long long)(
  217. current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
  218. stream->timing.h_total), 1000);
  219. /* v_total cannot be less than nominal */
  220. if (v_total < stream->timing.v_total)
  221. v_total = stream->timing.v_total;
  222. in_out_vrr->adjust.v_total_min = v_total;
  223. in_out_vrr->adjust.v_total_max = v_total;
  224. }
  225. static void apply_below_the_range(struct core_freesync *core_freesync,
  226. const struct dc_stream_state *stream,
  227. unsigned int last_render_time_in_us,
  228. struct mod_vrr_params *in_out_vrr)
  229. {
  230. unsigned int inserted_frame_duration_in_us = 0;
  231. unsigned int mid_point_frames_ceil = 0;
  232. unsigned int mid_point_frames_floor = 0;
  233. unsigned int frame_time_in_us = 0;
  234. unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
  235. unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
  236. unsigned int frames_to_insert = 0;
  237. unsigned int delta_from_mid_point_delta_in_us;
  238. unsigned int max_render_time_in_us =
  239. in_out_vrr->max_duration_in_us - in_out_vrr->btr.margin_in_us;
  240. /* Program BTR */
  241. if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < max_render_time_in_us) {
  242. /* Exit Below the Range */
  243. if (in_out_vrr->btr.btr_active) {
  244. in_out_vrr->btr.frame_counter = 0;
  245. in_out_vrr->btr.btr_active = false;
  246. }
  247. } else if (last_render_time_in_us > (max_render_time_in_us + in_out_vrr->btr.margin_in_us / 2)) {
  248. /* Enter Below the Range */
  249. if (!in_out_vrr->btr.btr_active)
  250. in_out_vrr->btr.btr_active = true;
  251. }
  252. /* BTR set to "not active" so disengage */
  253. if (!in_out_vrr->btr.btr_active) {
  254. in_out_vrr->btr.inserted_duration_in_us = 0;
  255. in_out_vrr->btr.frames_to_insert = 0;
  256. in_out_vrr->btr.frame_counter = 0;
  257. /* Restore FreeSync */
  258. in_out_vrr->adjust.v_total_min =
  259. mod_freesync_calc_v_total_from_refresh(stream,
  260. in_out_vrr->max_refresh_in_uhz);
  261. in_out_vrr->adjust.v_total_max =
  262. mod_freesync_calc_v_total_from_refresh(stream,
  263. in_out_vrr->min_refresh_in_uhz);
  264. /* BTR set to "active" so engage */
  265. } else {
  266. /* Calculate number of midPoint frames that could fit within
  267. * the render time interval - take ceil of this value
  268. */
  269. mid_point_frames_ceil = (last_render_time_in_us +
  270. in_out_vrr->btr.mid_point_in_us - 1) /
  271. in_out_vrr->btr.mid_point_in_us;
  272. if (mid_point_frames_ceil > 0) {
  273. frame_time_in_us = last_render_time_in_us /
  274. mid_point_frames_ceil;
  275. delta_from_mid_point_in_us_1 =
  276. (in_out_vrr->btr.mid_point_in_us >
  277. frame_time_in_us) ?
  278. (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
  279. (frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
  280. }
  281. /* Calculate number of midPoint frames that could fit within
  282. * the render time interval - take floor of this value
  283. */
  284. mid_point_frames_floor = last_render_time_in_us /
  285. in_out_vrr->btr.mid_point_in_us;
  286. if (mid_point_frames_floor > 0) {
  287. frame_time_in_us = last_render_time_in_us /
  288. mid_point_frames_floor;
  289. delta_from_mid_point_in_us_2 =
  290. (in_out_vrr->btr.mid_point_in_us >
  291. frame_time_in_us) ?
  292. (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
  293. (frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
  294. }
  295. /* Choose number of frames to insert based on how close it
  296. * can get to the mid point of the variable range.
  297. * - Delta for CEIL: delta_from_mid_point_in_us_1
  298. * - Delta for FLOOR: delta_from_mid_point_in_us_2
  299. */
  300. if (mid_point_frames_ceil &&
  301. (last_render_time_in_us / mid_point_frames_ceil) <
  302. in_out_vrr->min_duration_in_us) {
  303. /* Check for out of range.
  304. * If using CEIL produces a value that is out of range,
  305. * then we are forced to use FLOOR.
  306. */
  307. frames_to_insert = mid_point_frames_floor;
  308. } else if (mid_point_frames_floor < 2) {
  309. /* Check if FLOOR would result in non-LFC. In this case
  310. * choose to use CEIL
  311. */
  312. frames_to_insert = mid_point_frames_ceil;
  313. } else if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
  314. /* If choosing CEIL results in a frame duration that is
  315. * closer to the mid point of the range.
  316. * Choose CEIL
  317. */
  318. frames_to_insert = mid_point_frames_ceil;
  319. } else {
  320. /* If choosing FLOOR results in a frame duration that is
  321. * closer to the mid point of the range.
  322. * Choose FLOOR
  323. */
  324. frames_to_insert = mid_point_frames_floor;
  325. }
  326. /* Prefer current frame multiplier when BTR is enabled unless it drifts
  327. * too far from the midpoint
  328. */
  329. if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
  330. delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
  331. delta_from_mid_point_in_us_1;
  332. } else {
  333. delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 -
  334. delta_from_mid_point_in_us_2;
  335. }
  336. if (in_out_vrr->btr.frames_to_insert != 0 &&
  337. delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {
  338. if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <
  339. max_render_time_in_us) &&
  340. ((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) >
  341. in_out_vrr->min_duration_in_us))
  342. frames_to_insert = in_out_vrr->btr.frames_to_insert;
  343. }
  344. /* Either we've calculated the number of frames to insert,
  345. * or we need to insert min duration frames
  346. */
  347. if (frames_to_insert &&
  348. (last_render_time_in_us / frames_to_insert) <
  349. in_out_vrr->min_duration_in_us){
  350. frames_to_insert -= (frames_to_insert > 1) ?
  351. 1 : 0;
  352. }
  353. if (frames_to_insert > 0)
  354. inserted_frame_duration_in_us = last_render_time_in_us /
  355. frames_to_insert;
  356. if (inserted_frame_duration_in_us < in_out_vrr->min_duration_in_us)
  357. inserted_frame_duration_in_us = in_out_vrr->min_duration_in_us;
  358. /* Cache the calculated variables */
  359. in_out_vrr->btr.inserted_duration_in_us =
  360. inserted_frame_duration_in_us;
  361. in_out_vrr->btr.frames_to_insert = frames_to_insert;
  362. in_out_vrr->btr.frame_counter = frames_to_insert;
  363. }
  364. }
  365. static void apply_fixed_refresh(struct core_freesync *core_freesync,
  366. const struct dc_stream_state *stream,
  367. unsigned int last_render_time_in_us,
  368. struct mod_vrr_params *in_out_vrr)
  369. {
  370. bool update = false;
  371. unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
  372. /* Compute the exit refresh rate and exit frame duration */
  373. unsigned int exit_refresh_rate_in_milli_hz = ((1000000000/max_render_time_in_us)
  374. + (1000*FIXED_REFRESH_EXIT_MARGIN_IN_HZ));
  375. unsigned int exit_frame_duration_in_us = 1000000000/exit_refresh_rate_in_milli_hz;
  376. if (last_render_time_in_us < exit_frame_duration_in_us) {
  377. /* Exit Fixed Refresh mode */
  378. if (in_out_vrr->fixed.fixed_active) {
  379. in_out_vrr->fixed.frame_counter++;
  380. if (in_out_vrr->fixed.frame_counter >
  381. FIXED_REFRESH_EXIT_FRAME_COUNT) {
  382. in_out_vrr->fixed.frame_counter = 0;
  383. in_out_vrr->fixed.fixed_active = false;
  384. in_out_vrr->fixed.target_refresh_in_uhz = 0;
  385. update = true;
  386. }
  387. } else
  388. in_out_vrr->fixed.frame_counter = 0;
  389. } else if (last_render_time_in_us > max_render_time_in_us) {
  390. /* Enter Fixed Refresh mode */
  391. if (!in_out_vrr->fixed.fixed_active) {
  392. in_out_vrr->fixed.frame_counter++;
  393. if (in_out_vrr->fixed.frame_counter >
  394. FIXED_REFRESH_ENTER_FRAME_COUNT) {
  395. in_out_vrr->fixed.frame_counter = 0;
  396. in_out_vrr->fixed.fixed_active = true;
  397. in_out_vrr->fixed.target_refresh_in_uhz =
  398. in_out_vrr->max_refresh_in_uhz;
  399. update = true;
  400. }
  401. } else
  402. in_out_vrr->fixed.frame_counter = 0;
  403. }
  404. if (update) {
  405. if (in_out_vrr->fixed.fixed_active) {
  406. in_out_vrr->adjust.v_total_min =
  407. mod_freesync_calc_v_total_from_refresh(
  408. stream, in_out_vrr->max_refresh_in_uhz);
  409. in_out_vrr->adjust.v_total_max =
  410. in_out_vrr->adjust.v_total_min;
  411. } else {
  412. in_out_vrr->adjust.v_total_min =
  413. mod_freesync_calc_v_total_from_refresh(stream,
  414. in_out_vrr->max_refresh_in_uhz);
  415. in_out_vrr->adjust.v_total_max =
  416. mod_freesync_calc_v_total_from_refresh(stream,
  417. in_out_vrr->min_refresh_in_uhz);
  418. }
  419. }
  420. }
  421. static void determine_flip_interval_workaround_req(struct mod_vrr_params *in_vrr,
  422. unsigned int curr_time_stamp_in_us)
  423. {
  424. in_vrr->flip_interval.vsync_to_flip_in_us = curr_time_stamp_in_us -
  425. in_vrr->flip_interval.v_update_timestamp_in_us;
  426. /* Determine conditions for stopping workaround */
  427. if (in_vrr->flip_interval.flip_interval_workaround_active &&
  428. in_vrr->flip_interval.vsyncs_between_flip < VSYNCS_BETWEEN_FLIP_THRESHOLD &&
  429. in_vrr->flip_interval.vsync_to_flip_in_us > FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {
  430. in_vrr->flip_interval.flip_interval_detect_counter = 0;
  431. in_vrr->flip_interval.program_flip_interval_workaround = true;
  432. in_vrr->flip_interval.flip_interval_workaround_active = false;
  433. } else {
  434. /* Determine conditions for starting workaround */
  435. if (in_vrr->flip_interval.vsyncs_between_flip >= VSYNCS_BETWEEN_FLIP_THRESHOLD &&
  436. in_vrr->flip_interval.vsync_to_flip_in_us < FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {
  437. /* Increase flip interval counter we have 2 vsyncs between flips and
  438. * vsync to flip interval is less than 500us
  439. */
  440. in_vrr->flip_interval.flip_interval_detect_counter++;
  441. if (in_vrr->flip_interval.flip_interval_detect_counter > FREESYNC_CONSEC_FLIP_AFTER_VSYNC) {
  442. /* Start workaround if we detect 5 consecutive instances of the above case */
  443. in_vrr->flip_interval.program_flip_interval_workaround = true;
  444. in_vrr->flip_interval.flip_interval_workaround_active = true;
  445. }
  446. } else {
  447. /* Reset the flip interval counter if we condition is no longer met */
  448. in_vrr->flip_interval.flip_interval_detect_counter = 0;
  449. }
  450. }
  451. in_vrr->flip_interval.vsyncs_between_flip = 0;
  452. }
  453. static bool vrr_settings_require_update(struct core_freesync *core_freesync,
  454. struct mod_freesync_config *in_config,
  455. unsigned int min_refresh_in_uhz,
  456. unsigned int max_refresh_in_uhz,
  457. struct mod_vrr_params *in_vrr)
  458. {
  459. if (in_vrr->state != in_config->state) {
  460. return true;
  461. } else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED &&
  462. in_vrr->fixed.target_refresh_in_uhz !=
  463. in_config->fixed_refresh_in_uhz) {
  464. return true;
  465. } else if (in_vrr->min_refresh_in_uhz != min_refresh_in_uhz) {
  466. return true;
  467. } else if (in_vrr->max_refresh_in_uhz != max_refresh_in_uhz) {
  468. return true;
  469. }
  470. return false;
  471. }
  472. bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
  473. const struct dc_stream_state *stream,
  474. unsigned int *vmin,
  475. unsigned int *vmax)
  476. {
  477. *vmin = stream->adjust.v_total_min;
  478. *vmax = stream->adjust.v_total_max;
  479. return true;
  480. }
  481. bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
  482. struct dc_stream_state *stream,
  483. unsigned int *nom_v_pos,
  484. unsigned int *v_pos)
  485. {
  486. struct core_freesync *core_freesync = NULL;
  487. struct crtc_position position;
  488. if (mod_freesync == NULL)
  489. return false;
  490. core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
  491. if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1,
  492. &position.vertical_count,
  493. &position.nominal_vcount)) {
  494. *nom_v_pos = position.nominal_vcount;
  495. *v_pos = position.vertical_count;
  496. return true;
  497. }
  498. return false;
  499. }
  500. static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
  501. struct dc_info_packet *infopacket,
  502. bool freesync_on_desktop)
  503. {
  504. /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
  505. infopacket->sb[1] = 0x1A;
  506. /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
  507. infopacket->sb[2] = 0x00;
  508. /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
  509. infopacket->sb[3] = 0x00;
  510. /* PB4 = Reserved */
  511. /* PB5 = Reserved */
  512. /* PB6 = [Bits 7:3 = Reserved] */
  513. /* PB6 = [Bit 0 = FreeSync Supported] */
  514. if (vrr->state != VRR_STATE_UNSUPPORTED)
  515. infopacket->sb[6] |= 0x01;
  516. /* PB6 = [Bit 1 = FreeSync Enabled] */
  517. if (vrr->state != VRR_STATE_DISABLED &&
  518. vrr->state != VRR_STATE_UNSUPPORTED)
  519. infopacket->sb[6] |= 0x02;
  520. if (freesync_on_desktop) {
  521. /* PB6 = [Bit 2 = FreeSync Active] */
  522. if (vrr->state != VRR_STATE_DISABLED &&
  523. vrr->state != VRR_STATE_UNSUPPORTED)
  524. infopacket->sb[6] |= 0x04;
  525. } else {
  526. if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
  527. vrr->state == VRR_STATE_ACTIVE_FIXED)
  528. infopacket->sb[6] |= 0x04;
  529. }
  530. // For v1 & 2 infoframes program nominal if non-fs mode, otherwise full range
  531. /* PB7 = FreeSync Minimum refresh rate (Hz) */
  532. if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
  533. vrr->state == VRR_STATE_ACTIVE_FIXED) {
  534. infopacket->sb[7] = (unsigned char)((vrr->min_refresh_in_uhz + 500000) / 1000000);
  535. } else {
  536. infopacket->sb[7] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
  537. }
  538. /* PB8 = FreeSync Maximum refresh rate (Hz)
  539. * Note: We should never go above the field rate of the mode timing set.
  540. */
  541. infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
  542. }
  543. static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
  544. struct dc_info_packet *infopacket,
  545. bool freesync_on_desktop)
  546. {
  547. unsigned int min_refresh;
  548. unsigned int max_refresh;
  549. unsigned int fixed_refresh;
  550. unsigned int min_programmed;
  551. /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
  552. infopacket->sb[1] = 0x1A;
  553. /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
  554. infopacket->sb[2] = 0x00;
  555. /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
  556. infopacket->sb[3] = 0x00;
  557. /* PB4 = Reserved */
  558. /* PB5 = Reserved */
  559. /* PB6 = [Bits 7:3 = Reserved] */
  560. /* PB6 = [Bit 0 = FreeSync Supported] */
  561. if (vrr->state != VRR_STATE_UNSUPPORTED)
  562. infopacket->sb[6] |= 0x01;
  563. /* PB6 = [Bit 1 = FreeSync Enabled] */
  564. if (vrr->state != VRR_STATE_DISABLED &&
  565. vrr->state != VRR_STATE_UNSUPPORTED)
  566. infopacket->sb[6] |= 0x02;
  567. /* PB6 = [Bit 2 = FreeSync Active] */
  568. if (freesync_on_desktop) {
  569. if (vrr->state != VRR_STATE_DISABLED &&
  570. vrr->state != VRR_STATE_UNSUPPORTED)
  571. infopacket->sb[6] |= 0x04;
  572. } else {
  573. if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
  574. vrr->state == VRR_STATE_ACTIVE_FIXED)
  575. infopacket->sb[6] |= 0x04;
  576. }
  577. min_refresh = (vrr->min_refresh_in_uhz + 500000) / 1000000;
  578. max_refresh = (vrr->max_refresh_in_uhz + 500000) / 1000000;
  579. fixed_refresh = (vrr->fixed_refresh_in_uhz + 500000) / 1000000;
  580. min_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh :
  581. (vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? min_refresh :
  582. (vrr->state == VRR_STATE_INACTIVE) ? min_refresh :
  583. max_refresh; // Non-fs case, program nominal range
  584. /* PB7 = FreeSync Minimum refresh rate (Hz) */
  585. infopacket->sb[7] = min_programmed & 0xFF;
  586. /* PB8 = FreeSync Maximum refresh rate (Hz) */
  587. infopacket->sb[8] = max_refresh & 0xFF;
  588. /* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 9:8 */
  589. infopacket->sb[11] = (min_programmed >> 8) & 0x03;
  590. /* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 9:8 */
  591. infopacket->sb[12] = (max_refresh >> 8) & 0x03;
  592. /* PB16 : Reserved bits 7:1, FixedRate bit 0 */
  593. infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0;
  594. }
  595. static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
  596. struct dc_info_packet *infopacket)
  597. {
  598. if (app_tf != TRANSFER_FUNC_UNKNOWN) {
  599. infopacket->valid = true;
  600. if (app_tf == TRANSFER_FUNC_PQ2084)
  601. infopacket->sb[9] |= 0x20; // PB9 = [Bit 5 = PQ EOTF Active]
  602. else {
  603. infopacket->sb[6] |= 0x08; // PB6 = [Bit 3 = Native Color Active]
  604. if (app_tf == TRANSFER_FUNC_GAMMA_22)
  605. infopacket->sb[9] |= 0x04; // PB9 = [Bit 2 = Gamma 2.2 EOTF Active]
  606. }
  607. }
  608. }
  609. static void build_vrr_infopacket_header_v1(enum signal_type signal,
  610. struct dc_info_packet *infopacket,
  611. unsigned int *payload_size)
  612. {
  613. if (dc_is_hdmi_signal(signal)) {
  614. /* HEADER */
  615. /* HB0 = Packet Type = 0x83 (Source Product
  616. * Descriptor InfoFrame)
  617. */
  618. infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
  619. /* HB1 = Version = 0x01 */
  620. infopacket->hb1 = 0x01;
  621. /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
  622. infopacket->hb2 = 0x08;
  623. *payload_size = 0x08;
  624. } else if (dc_is_dp_signal(signal)) {
  625. /* HEADER */
  626. /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
  627. * when used to associate audio related info packets
  628. */
  629. infopacket->hb0 = 0x00;
  630. /* HB1 = Packet Type = 0x83 (Source Product
  631. * Descriptor InfoFrame)
  632. */
  633. infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
  634. /* HB2 = [Bits 7:0 = Least significant eight bits -
  635. * For INFOFRAME, the value must be 1Bh]
  636. */
  637. infopacket->hb2 = 0x1B;
  638. /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
  639. * [Bits 1:0 = Most significant two bits = 0x00]
  640. */
  641. infopacket->hb3 = 0x04;
  642. *payload_size = 0x1B;
  643. }
  644. }
  645. static void build_vrr_infopacket_header_v2(enum signal_type signal,
  646. struct dc_info_packet *infopacket,
  647. unsigned int *payload_size)
  648. {
  649. if (dc_is_hdmi_signal(signal)) {
  650. /* HEADER */
  651. /* HB0 = Packet Type = 0x83 (Source Product
  652. * Descriptor InfoFrame)
  653. */
  654. infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
  655. /* HB1 = Version = 0x02 */
  656. infopacket->hb1 = 0x02;
  657. /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x09] */
  658. infopacket->hb2 = 0x09;
  659. *payload_size = 0x09;
  660. } else if (dc_is_dp_signal(signal)) {
  661. /* HEADER */
  662. /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
  663. * when used to associate audio related info packets
  664. */
  665. infopacket->hb0 = 0x00;
  666. /* HB1 = Packet Type = 0x83 (Source Product
  667. * Descriptor InfoFrame)
  668. */
  669. infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
  670. /* HB2 = [Bits 7:0 = Least significant eight bits -
  671. * For INFOFRAME, the value must be 1Bh]
  672. */
  673. infopacket->hb2 = 0x1B;
  674. /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
  675. * [Bits 1:0 = Most significant two bits = 0x00]
  676. */
  677. infopacket->hb3 = 0x08;
  678. *payload_size = 0x1B;
  679. }
  680. }
  681. static void build_vrr_infopacket_header_v3(enum signal_type signal,
  682. struct dc_info_packet *infopacket,
  683. unsigned int *payload_size)
  684. {
  685. unsigned char version;
  686. version = 3;
  687. if (dc_is_hdmi_signal(signal)) {
  688. /* HEADER */
  689. /* HB0 = Packet Type = 0x83 (Source Product
  690. * Descriptor InfoFrame)
  691. */
  692. infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
  693. /* HB1 = Version = 0x03 */
  694. infopacket->hb1 = version;
  695. /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length] */
  696. infopacket->hb2 = 0x10;
  697. *payload_size = 0x10;
  698. } else if (dc_is_dp_signal(signal)) {
  699. /* HEADER */
  700. /* HB0 = Secondary-data Packet ID = 0 - Only non-zero
  701. * when used to associate audio related info packets
  702. */
  703. infopacket->hb0 = 0x00;
  704. /* HB1 = Packet Type = 0x83 (Source Product
  705. * Descriptor InfoFrame)
  706. */
  707. infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
  708. /* HB2 = [Bits 7:0 = Least significant eight bits -
  709. * For INFOFRAME, the value must be 1Bh]
  710. */
  711. infopacket->hb2 = 0x1B;
  712. /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
  713. * [Bits 1:0 = Most significant two bits = 0x00]
  714. */
  715. infopacket->hb3 = (version & 0x3F) << 2;
  716. *payload_size = 0x1B;
  717. }
  718. }
  719. static void build_vrr_infopacket_checksum(unsigned int *payload_size,
  720. struct dc_info_packet *infopacket)
  721. {
  722. /* Calculate checksum */
  723. unsigned int idx = 0;
  724. unsigned char checksum = 0;
  725. checksum += infopacket->hb0;
  726. checksum += infopacket->hb1;
  727. checksum += infopacket->hb2;
  728. checksum += infopacket->hb3;
  729. for (idx = 1; idx <= *payload_size; idx++)
  730. checksum += infopacket->sb[idx];
  731. /* PB0 = Checksum (one byte complement) */
  732. infopacket->sb[0] = (unsigned char)(0x100 - checksum);
  733. infopacket->valid = true;
  734. }
  735. static void build_vrr_infopacket_v1(enum signal_type signal,
  736. const struct mod_vrr_params *vrr,
  737. struct dc_info_packet *infopacket,
  738. bool freesync_on_desktop)
  739. {
  740. /* SPD info packet for FreeSync */
  741. unsigned int payload_size = 0;
  742. build_vrr_infopacket_header_v1(signal, infopacket, &payload_size);
  743. build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
  744. build_vrr_infopacket_checksum(&payload_size, infopacket);
  745. infopacket->valid = true;
  746. }
  747. static void build_vrr_infopacket_v2(enum signal_type signal,
  748. const struct mod_vrr_params *vrr,
  749. enum color_transfer_func app_tf,
  750. struct dc_info_packet *infopacket,
  751. bool freesync_on_desktop)
  752. {
  753. unsigned int payload_size = 0;
  754. build_vrr_infopacket_header_v2(signal, infopacket, &payload_size);
  755. build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
  756. build_vrr_infopacket_fs2_data(app_tf, infopacket);
  757. build_vrr_infopacket_checksum(&payload_size, infopacket);
  758. infopacket->valid = true;
  759. }
  760. static void build_vrr_infopacket_v3(enum signal_type signal,
  761. const struct mod_vrr_params *vrr,
  762. enum color_transfer_func app_tf,
  763. struct dc_info_packet *infopacket,
  764. bool freesync_on_desktop)
  765. {
  766. unsigned int payload_size = 0;
  767. build_vrr_infopacket_header_v3(signal, infopacket, &payload_size);
  768. build_vrr_infopacket_data_v3(vrr, infopacket, freesync_on_desktop);
  769. build_vrr_infopacket_fs2_data(app_tf, infopacket);
  770. build_vrr_infopacket_checksum(&payload_size, infopacket);
  771. infopacket->valid = true;
  772. }
  773. static void build_vrr_infopacket_sdp_v1_3(enum vrr_packet_type packet_type,
  774. struct dc_info_packet *infopacket)
  775. {
  776. uint8_t idx = 0, size = 0;
  777. size = ((packet_type == PACKET_TYPE_FS_V1) ? 0x08 :
  778. (packet_type == PACKET_TYPE_FS_V3) ? 0x10 :
  779. 0x09);
  780. for (idx = infopacket->hb2; idx > 1; idx--) // Data Byte Count: 0x1B
  781. infopacket->sb[idx] = infopacket->sb[idx-1];
  782. infopacket->sb[1] = size; // Length
  783. infopacket->sb[0] = (infopacket->hb3 >> 2) & 0x3F;//Version
  784. infopacket->hb3 = (0x13 << 2); // Header,SDP 1.3
  785. infopacket->hb2 = 0x1D;
  786. }
  787. void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
  788. const struct dc_stream_state *stream,
  789. const struct mod_vrr_params *vrr,
  790. enum vrr_packet_type packet_type,
  791. enum color_transfer_func app_tf,
  792. struct dc_info_packet *infopacket,
  793. bool pack_sdp_v1_3)
  794. {
  795. /* SPD info packet for FreeSync
  796. * VTEM info packet for HdmiVRR
  797. * Check if Freesync is supported. Return if false. If true,
  798. * set the corresponding bit in the info packet
  799. */
  800. if (!vrr->send_info_frame)
  801. return;
  802. switch (packet_type) {
  803. case PACKET_TYPE_FS_V3:
  804. build_vrr_infopacket_v3(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
  805. break;
  806. case PACKET_TYPE_FS_V2:
  807. build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
  808. break;
  809. case PACKET_TYPE_VRR:
  810. case PACKET_TYPE_FS_V1:
  811. default:
  812. build_vrr_infopacket_v1(stream->signal, vrr, infopacket, stream->freesync_on_desktop);
  813. }
  814. if (true == pack_sdp_v1_3 &&
  815. true == dc_is_dp_signal(stream->signal) &&
  816. packet_type != PACKET_TYPE_VRR &&
  817. packet_type != PACKET_TYPE_VTEM)
  818. build_vrr_infopacket_sdp_v1_3(packet_type, infopacket);
  819. }
  820. void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
  821. const struct dc_stream_state *stream,
  822. struct mod_freesync_config *in_config,
  823. struct mod_vrr_params *in_out_vrr)
  824. {
  825. struct core_freesync *core_freesync = NULL;
  826. unsigned long long nominal_field_rate_in_uhz = 0;
  827. unsigned long long rounded_nominal_in_uhz = 0;
  828. unsigned int refresh_range = 0;
  829. unsigned long long min_refresh_in_uhz = 0;
  830. unsigned long long max_refresh_in_uhz = 0;
  831. unsigned long long min_hardware_refresh_in_uhz = 0;
  832. if (mod_freesync == NULL)
  833. return;
  834. core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
  835. /* Calculate nominal field rate for stream */
  836. nominal_field_rate_in_uhz =
  837. mod_freesync_calc_nominal_field_rate(stream);
  838. if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {
  839. min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
  840. (stream->timing.h_total * (long long)calc_max_hardware_v_total(stream)));
  841. }
  842. /* Limit minimum refresh rate to what can be supported by hardware */
  843. min_refresh_in_uhz = min_hardware_refresh_in_uhz > in_config->min_refresh_in_uhz ?
  844. min_hardware_refresh_in_uhz : in_config->min_refresh_in_uhz;
  845. max_refresh_in_uhz = in_config->max_refresh_in_uhz;
  846. /* Full range may be larger than current video timing, so cap at nominal */
  847. if (max_refresh_in_uhz > nominal_field_rate_in_uhz)
  848. max_refresh_in_uhz = nominal_field_rate_in_uhz;
  849. /* Full range may be larger than current video timing, so cap at nominal */
  850. if (min_refresh_in_uhz > max_refresh_in_uhz)
  851. min_refresh_in_uhz = max_refresh_in_uhz;
  852. /* If a monitor reports exactly max refresh of 2x of min, enforce it on nominal */
  853. rounded_nominal_in_uhz =
  854. div_u64(nominal_field_rate_in_uhz + 50000, 100000) * 100000;
  855. if (in_config->max_refresh_in_uhz == (2 * in_config->min_refresh_in_uhz) &&
  856. in_config->max_refresh_in_uhz == rounded_nominal_in_uhz)
  857. min_refresh_in_uhz = div_u64(nominal_field_rate_in_uhz, 2);
  858. if (!vrr_settings_require_update(core_freesync,
  859. in_config, (unsigned int)min_refresh_in_uhz, (unsigned int)max_refresh_in_uhz,
  860. in_out_vrr))
  861. return;
  862. in_out_vrr->state = in_config->state;
  863. in_out_vrr->send_info_frame = in_config->vsif_supported;
  864. if (in_config->state == VRR_STATE_UNSUPPORTED) {
  865. in_out_vrr->state = VRR_STATE_UNSUPPORTED;
  866. in_out_vrr->supported = false;
  867. in_out_vrr->adjust.v_total_min = stream->timing.v_total;
  868. in_out_vrr->adjust.v_total_max = stream->timing.v_total;
  869. return;
  870. } else {
  871. in_out_vrr->min_refresh_in_uhz = (unsigned int)min_refresh_in_uhz;
  872. in_out_vrr->max_duration_in_us =
  873. calc_duration_in_us_from_refresh_in_uhz(
  874. (unsigned int)min_refresh_in_uhz);
  875. in_out_vrr->max_refresh_in_uhz = (unsigned int)max_refresh_in_uhz;
  876. in_out_vrr->min_duration_in_us =
  877. calc_duration_in_us_from_refresh_in_uhz(
  878. (unsigned int)max_refresh_in_uhz);
  879. if (in_config->state == VRR_STATE_ACTIVE_FIXED)
  880. in_out_vrr->fixed_refresh_in_uhz = in_config->fixed_refresh_in_uhz;
  881. else
  882. in_out_vrr->fixed_refresh_in_uhz = 0;
  883. refresh_range = div_u64(in_out_vrr->max_refresh_in_uhz + 500000, 1000000) -
  884. div_u64(in_out_vrr->min_refresh_in_uhz + 500000, 1000000);
  885. in_out_vrr->supported = true;
  886. }
  887. in_out_vrr->fixed.ramping_active = in_config->ramping;
  888. in_out_vrr->btr.btr_enabled = in_config->btr;
  889. if (in_out_vrr->max_refresh_in_uhz < (2 * in_out_vrr->min_refresh_in_uhz))
  890. in_out_vrr->btr.btr_enabled = false;
  891. else {
  892. in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
  893. 2 * in_out_vrr->min_duration_in_us;
  894. if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN)
  895. in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN;
  896. }
  897. in_out_vrr->btr.btr_active = false;
  898. in_out_vrr->btr.inserted_duration_in_us = 0;
  899. in_out_vrr->btr.frames_to_insert = 0;
  900. in_out_vrr->btr.frame_counter = 0;
  901. in_out_vrr->fixed.fixed_active = false;
  902. in_out_vrr->fixed.target_refresh_in_uhz = 0;
  903. in_out_vrr->btr.mid_point_in_us =
  904. (in_out_vrr->min_duration_in_us +
  905. in_out_vrr->max_duration_in_us) / 2;
  906. if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {
  907. in_out_vrr->adjust.v_total_min = stream->timing.v_total;
  908. in_out_vrr->adjust.v_total_max = stream->timing.v_total;
  909. } else if (in_out_vrr->state == VRR_STATE_DISABLED) {
  910. in_out_vrr->adjust.v_total_min = stream->timing.v_total;
  911. in_out_vrr->adjust.v_total_max = stream->timing.v_total;
  912. } else if (in_out_vrr->state == VRR_STATE_INACTIVE) {
  913. in_out_vrr->adjust.v_total_min = stream->timing.v_total;
  914. in_out_vrr->adjust.v_total_max = stream->timing.v_total;
  915. } else if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
  916. refresh_range >= MIN_REFRESH_RANGE) {
  917. in_out_vrr->adjust.v_total_min =
  918. mod_freesync_calc_v_total_from_refresh(stream,
  919. in_out_vrr->max_refresh_in_uhz);
  920. in_out_vrr->adjust.v_total_max =
  921. mod_freesync_calc_v_total_from_refresh(stream,
  922. in_out_vrr->min_refresh_in_uhz);
  923. } else if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED) {
  924. in_out_vrr->fixed.target_refresh_in_uhz =
  925. in_out_vrr->fixed_refresh_in_uhz;
  926. if (in_out_vrr->fixed.ramping_active &&
  927. in_out_vrr->fixed.fixed_active) {
  928. /* Do not update vtotals if ramping is already active
  929. * in order to continue ramp from current refresh.
  930. */
  931. in_out_vrr->fixed.fixed_active = true;
  932. } else {
  933. in_out_vrr->fixed.fixed_active = true;
  934. in_out_vrr->adjust.v_total_min =
  935. mod_freesync_calc_v_total_from_refresh(stream,
  936. in_out_vrr->fixed.target_refresh_in_uhz);
  937. in_out_vrr->adjust.v_total_max =
  938. in_out_vrr->adjust.v_total_min;
  939. }
  940. } else {
  941. in_out_vrr->state = VRR_STATE_INACTIVE;
  942. in_out_vrr->adjust.v_total_min = stream->timing.v_total;
  943. in_out_vrr->adjust.v_total_max = stream->timing.v_total;
  944. }
  945. in_out_vrr->adjust.allow_otg_v_count_halt = (in_config->state == VRR_STATE_ACTIVE_FIXED) ? true : false;
  946. }
  947. void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
  948. const struct dc_plane_state *plane,
  949. const struct dc_stream_state *stream,
  950. unsigned int curr_time_stamp_in_us,
  951. struct mod_vrr_params *in_out_vrr)
  952. {
  953. struct core_freesync *core_freesync = NULL;
  954. unsigned int last_render_time_in_us = 0;
  955. if (mod_freesync == NULL)
  956. return;
  957. core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
  958. if (in_out_vrr->supported &&
  959. in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) {
  960. last_render_time_in_us = curr_time_stamp_in_us -
  961. plane->time.prev_update_time_in_us;
  962. if (in_out_vrr->btr.btr_enabled) {
  963. apply_below_the_range(core_freesync,
  964. stream,
  965. last_render_time_in_us,
  966. in_out_vrr);
  967. } else {
  968. apply_fixed_refresh(core_freesync,
  969. stream,
  970. last_render_time_in_us,
  971. in_out_vrr);
  972. }
  973. determine_flip_interval_workaround_req(in_out_vrr,
  974. curr_time_stamp_in_us);
  975. }
  976. }
  977. void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
  978. const struct dc_stream_state *stream,
  979. struct mod_vrr_params *in_out_vrr)
  980. {
  981. struct core_freesync *core_freesync = NULL;
  982. unsigned int cur_timestamp_in_us;
  983. unsigned long long cur_tick;
  984. if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))
  985. return;
  986. core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
  987. if (in_out_vrr->supported == false)
  988. return;
  989. cur_tick = dm_get_timestamp(core_freesync->dc->ctx);
  990. cur_timestamp_in_us = (unsigned int)
  991. div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);
  992. in_out_vrr->flip_interval.vsyncs_between_flip++;
  993. in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
  994. if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
  995. (in_out_vrr->flip_interval.flip_interval_workaround_active ||
  996. (!in_out_vrr->flip_interval.flip_interval_workaround_active &&
  997. in_out_vrr->flip_interval.program_flip_interval_workaround))) {
  998. // set freesync vmin vmax to nominal for workaround
  999. in_out_vrr->adjust.v_total_min =
  1000. mod_freesync_calc_v_total_from_refresh(
  1001. stream, in_out_vrr->max_refresh_in_uhz);
  1002. in_out_vrr->adjust.v_total_max =
  1003. in_out_vrr->adjust.v_total_min;
  1004. in_out_vrr->flip_interval.program_flip_interval_workaround = false;
  1005. in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = true;
  1006. return;
  1007. }
  1008. if (in_out_vrr->state != VRR_STATE_ACTIVE_VARIABLE &&
  1009. in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup) {
  1010. in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = false;
  1011. in_out_vrr->flip_interval.flip_interval_detect_counter = 0;
  1012. in_out_vrr->flip_interval.vsyncs_between_flip = 0;
  1013. in_out_vrr->flip_interval.vsync_to_flip_in_us = 0;
  1014. }
  1015. /* Below the Range Logic */
  1016. /* Only execute if in fullscreen mode */
  1017. if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
  1018. in_out_vrr->btr.btr_active) {
  1019. /* TODO: pass in flag for Pre-DCE12 ASIC
  1020. * in order for frame variable duration to take affect,
  1021. * it needs to be done one VSYNC early, which is at
  1022. * frameCounter == 1.
  1023. * For DCE12 and newer updates to V_TOTAL_MIN/MAX
  1024. * will take affect on current frame
  1025. */
  1026. if (in_out_vrr->btr.frames_to_insert ==
  1027. in_out_vrr->btr.frame_counter) {
  1028. in_out_vrr->adjust.v_total_min =
  1029. calc_v_total_from_duration(stream,
  1030. in_out_vrr,
  1031. in_out_vrr->btr.inserted_duration_in_us);
  1032. in_out_vrr->adjust.v_total_max =
  1033. in_out_vrr->adjust.v_total_min;
  1034. }
  1035. if (in_out_vrr->btr.frame_counter > 0)
  1036. in_out_vrr->btr.frame_counter--;
  1037. /* Restore FreeSync */
  1038. if (in_out_vrr->btr.frame_counter == 0) {
  1039. in_out_vrr->adjust.v_total_min =
  1040. mod_freesync_calc_v_total_from_refresh(stream,
  1041. in_out_vrr->max_refresh_in_uhz);
  1042. in_out_vrr->adjust.v_total_max =
  1043. mod_freesync_calc_v_total_from_refresh(stream,
  1044. in_out_vrr->min_refresh_in_uhz);
  1045. }
  1046. }
  1047. /* If in fullscreen freesync mode or in video, do not program
  1048. * static screen ramp values
  1049. */
  1050. if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE)
  1051. in_out_vrr->fixed.ramping_active = false;
  1052. /* Gradual Static Screen Ramping Logic
  1053. * Execute if ramp is active and user enabled freesync static screen
  1054. */
  1055. if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED &&
  1056. in_out_vrr->fixed.ramping_active) {
  1057. update_v_total_for_static_ramp(
  1058. core_freesync, stream, in_out_vrr);
  1059. }
  1060. }
  1061. void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
  1062. const struct mod_vrr_params *vrr,
  1063. unsigned int *v_total_min, unsigned int *v_total_max,
  1064. unsigned int *event_triggers,
  1065. unsigned int *window_min, unsigned int *window_max,
  1066. unsigned int *lfc_mid_point_in_us,
  1067. unsigned int *inserted_frames,
  1068. unsigned int *inserted_duration_in_us)
  1069. {
  1070. if (mod_freesync == NULL)
  1071. return;
  1072. if (vrr->supported) {
  1073. *v_total_min = vrr->adjust.v_total_min;
  1074. *v_total_max = vrr->adjust.v_total_max;
  1075. *event_triggers = 0;
  1076. *lfc_mid_point_in_us = vrr->btr.mid_point_in_us;
  1077. *inserted_frames = vrr->btr.frames_to_insert;
  1078. *inserted_duration_in_us = vrr->btr.inserted_duration_in_us;
  1079. }
  1080. }
  1081. unsigned long long mod_freesync_calc_nominal_field_rate(
  1082. const struct dc_stream_state *stream)
  1083. {
  1084. unsigned long long nominal_field_rate_in_uhz = 0;
  1085. unsigned int total = stream->timing.h_total * stream->timing.v_total;
  1086. /* Calculate nominal field rate for stream, rounded up to nearest integer */
  1087. nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz;
  1088. nominal_field_rate_in_uhz *= 100000000ULL;
  1089. nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz, total);
  1090. return nominal_field_rate_in_uhz;
  1091. }
  1092. unsigned long long mod_freesync_calc_field_rate_from_timing(
  1093. unsigned int vtotal, unsigned int htotal, unsigned int pix_clk)
  1094. {
  1095. unsigned long long field_rate_in_uhz = 0;
  1096. unsigned int total = htotal * vtotal;
  1097. /* Calculate nominal field rate for stream, rounded up to nearest integer */
  1098. field_rate_in_uhz = pix_clk;
  1099. field_rate_in_uhz *= 1000000ULL;
  1100. field_rate_in_uhz = div_u64(field_rate_in_uhz, total);
  1101. return field_rate_in_uhz;
  1102. }
  1103. bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr)
  1104. {
  1105. return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED);
  1106. }
  1107. bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz,
  1108. uint32_t max_refresh_cap_in_uhz,
  1109. uint32_t nominal_field_rate_in_uhz)
  1110. {
  1111. /* Typically nominal refresh calculated can have some fractional part.
  1112. * Allow for some rounding error of actual video timing by taking floor
  1113. * of caps and request. Round the nominal refresh rate.
  1114. *
  1115. * Dividing will convert everything to units in Hz although input
  1116. * variable name is in uHz!
  1117. *
  1118. * Also note, this takes care of rounding error on the nominal refresh
  1119. * so by rounding error we only expect it to be off by a small amount,
  1120. * such as < 0.1 Hz. i.e. 143.9xxx or 144.1xxx.
  1121. *
  1122. * Example 1. Caps Min = 40 Hz, Max = 144 Hz
  1123. * Request Min = 40 Hz, Max = 144 Hz
  1124. * Nominal = 143.5x Hz rounded to 144 Hz
  1125. * This function should allow this as valid request
  1126. *
  1127. * Example 2. Caps Min = 40 Hz, Max = 144 Hz
  1128. * Request Min = 40 Hz, Max = 144 Hz
  1129. * Nominal = 144.4x Hz rounded to 144 Hz
  1130. * This function should allow this as valid request
  1131. *
  1132. * Example 3. Caps Min = 40 Hz, Max = 144 Hz
  1133. * Request Min = 40 Hz, Max = 144 Hz
  1134. * Nominal = 120.xx Hz rounded to 120 Hz
  1135. * This function should return NOT valid since the requested
  1136. * max is greater than current timing's nominal
  1137. *
  1138. * Example 4. Caps Min = 40 Hz, Max = 120 Hz
  1139. * Request Min = 40 Hz, Max = 120 Hz
  1140. * Nominal = 144.xx Hz rounded to 144 Hz
  1141. * This function should return NOT valid since the nominal
  1142. * is greater than the capability's max refresh
  1143. */
  1144. nominal_field_rate_in_uhz =
  1145. div_u64(nominal_field_rate_in_uhz + 500000, 1000000);
  1146. min_refresh_cap_in_uhz /= 1000000;
  1147. max_refresh_cap_in_uhz /= 1000000;
  1148. /* Check nominal is within range */
  1149. if (nominal_field_rate_in_uhz > max_refresh_cap_in_uhz ||
  1150. nominal_field_rate_in_uhz < min_refresh_cap_in_uhz)
  1151. return false;
  1152. /* If nominal is less than max, limit the max allowed refresh rate */
  1153. if (nominal_field_rate_in_uhz < max_refresh_cap_in_uhz)
  1154. max_refresh_cap_in_uhz = nominal_field_rate_in_uhz;
  1155. /* Check min is within range */
  1156. if (min_refresh_cap_in_uhz > max_refresh_cap_in_uhz)
  1157. return false;
  1158. /* For variable range, check for at least 10 Hz range */
  1159. if (nominal_field_rate_in_uhz - min_refresh_cap_in_uhz < 10)
  1160. return false;
  1161. return true;
  1162. }