amdgpu_pm.h 4.1 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #ifndef __AMDGPU_PM_H__
  24. #define __AMDGPU_PM_H__
  25. struct cg_flag_name {
  26. u64 flag;
  27. const char *name;
  28. };
  29. enum amdgpu_device_attr_flags {
  30. ATTR_FLAG_BASIC = (1 << 0),
  31. ATTR_FLAG_ONEVF = (1 << 16),
  32. };
  33. #define ATTR_FLAG_TYPE_MASK (0x0000ffff)
  34. #define ATTR_FLAG_MODE_MASK (0xffff0000)
  35. #define ATTR_FLAG_MASK_ALL (0xffffffff)
  36. enum amdgpu_device_attr_states {
  37. ATTR_STATE_UNSUPPORTED = 0,
  38. ATTR_STATE_SUPPORTED,
  39. };
  40. enum amdgpu_device_attr_id {
  41. device_attr_id__unknown = -1,
  42. device_attr_id__power_dpm_state = 0,
  43. device_attr_id__power_dpm_force_performance_level,
  44. device_attr_id__pp_num_states,
  45. device_attr_id__pp_cur_state,
  46. device_attr_id__pp_force_state,
  47. device_attr_id__pp_table,
  48. device_attr_id__pp_dpm_sclk,
  49. device_attr_id__pp_dpm_mclk,
  50. device_attr_id__pp_dpm_socclk,
  51. device_attr_id__pp_dpm_fclk,
  52. device_attr_id__pp_dpm_vclk,
  53. device_attr_id__pp_dpm_vclk1,
  54. device_attr_id__pp_dpm_dclk,
  55. device_attr_id__pp_dpm_dclk1,
  56. device_attr_id__pp_dpm_dcefclk,
  57. device_attr_id__pp_dpm_pcie,
  58. device_attr_id__pp_sclk_od,
  59. device_attr_id__pp_mclk_od,
  60. device_attr_id__pp_power_profile_mode,
  61. device_attr_id__pp_od_clk_voltage,
  62. device_attr_id__gpu_busy_percent,
  63. device_attr_id__mem_busy_percent,
  64. device_attr_id__vcn_busy_percent,
  65. device_attr_id__pcie_bw,
  66. device_attr_id__pp_features,
  67. device_attr_id__unique_id,
  68. device_attr_id__thermal_throttling_logging,
  69. device_attr_id__apu_thermal_cap,
  70. device_attr_id__gpu_metrics,
  71. device_attr_id__smartshift_apu_power,
  72. device_attr_id__smartshift_dgpu_power,
  73. device_attr_id__smartshift_bias,
  74. device_attr_id__pm_metrics,
  75. device_attr_id__count,
  76. };
  77. struct amdgpu_device_attr {
  78. struct device_attribute dev_attr;
  79. enum amdgpu_device_attr_id attr_id;
  80. enum amdgpu_device_attr_flags flags;
  81. int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
  82. uint32_t mask, enum amdgpu_device_attr_states *states);
  83. };
  84. struct amdgpu_device_attr_entry {
  85. struct list_head entry;
  86. struct amdgpu_device_attr *attr;
  87. };
  88. #define to_amdgpu_device_attr(_dev_attr) \
  89. container_of(_dev_attr, struct amdgpu_device_attr, dev_attr)
  90. #define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \
  91. { .dev_attr = __ATTR(_name, _mode, _show, _store), \
  92. .attr_id = device_attr_id__##_name, \
  93. .flags = _flags, \
  94. ##__VA_ARGS__, }
  95. #define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...) \
  96. __AMDGPU_DEVICE_ATTR(_name, _mode, \
  97. amdgpu_get_##_name, amdgpu_set_##_name, \
  98. _flags, ##__VA_ARGS__)
  99. #define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...) \
  100. AMDGPU_DEVICE_ATTR(_name, S_IRUGO | S_IWUSR, \
  101. _flags, ##__VA_ARGS__)
  102. #define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...) \
  103. __AMDGPU_DEVICE_ATTR(_name, S_IRUGO, \
  104. amdgpu_get_##_name, NULL, \
  105. _flags, ##__VA_ARGS__)
  106. int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);
  107. int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev);
  108. void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);
  109. void amdgpu_pm_virt_sysfs_fini(struct amdgpu_device *adev);
  110. void amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  111. #endif