aspeed_gfx_drv.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. // Copyright 2018 IBM Corporation
  3. #include <linux/clk.h>
  4. #include <linux/dma-mapping.h>
  5. #include <linux/irq.h>
  6. #include <linux/mfd/syscon.h>
  7. #include <linux/module.h>
  8. #include <linux/mod_devicetable.h>
  9. #include <linux/of_reserved_mem.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/property.h>
  12. #include <linux/regmap.h>
  13. #include <linux/reset.h>
  14. #include <drm/drm_atomic_helper.h>
  15. #include <drm/drm_device.h>
  16. #include <drm/drm_fbdev_dma.h>
  17. #include <drm/drm_gem_dma_helper.h>
  18. #include <drm/drm_gem_framebuffer_helper.h>
  19. #include <drm/drm_module.h>
  20. #include <drm/drm_probe_helper.h>
  21. #include <drm/drm_simple_kms_helper.h>
  22. #include <drm/drm_vblank.h>
  23. #include <drm/drm_drv.h>
  24. #include "aspeed_gfx.h"
  25. /**
  26. * DOC: ASPEED GFX Driver
  27. *
  28. * This driver is for the ASPEED BMC SoC's 'GFX' display hardware, also called
  29. * the 'SOC Display Controller' in the datasheet. This driver runs on the ARM
  30. * based BMC systems, unlike the ast driver which runs on a host CPU and is for
  31. * a PCIe graphics device.
  32. *
  33. * The AST2500 supports a total of 3 output paths:
  34. *
  35. * 1. VGA output, the output target can choose either or both to the DAC
  36. * or DVO interface.
  37. *
  38. * 2. Graphics CRT output, the output target can choose either or both to
  39. * the DAC or DVO interface.
  40. *
  41. * 3. Video input from DVO, the video input can be used for video engine
  42. * capture or DAC display output.
  43. *
  44. * Output options are selected in SCU2C.
  45. *
  46. * The "VGA mode" device is the PCI attached controller. The "Graphics CRT"
  47. * is the ARM's internal display controller.
  48. *
  49. * The driver only supports a simple configuration consisting of a 40MHz
  50. * pixel clock, fixed by hardware limitations, and the VGA output path.
  51. *
  52. * The driver was written with the 'AST2500 Software Programming Guide' v17,
  53. * which is available under NDA from ASPEED.
  54. */
  55. struct aspeed_gfx_config {
  56. u32 dac_reg; /* DAC register in SCU */
  57. u32 int_clear_reg; /* Interrupt clear register */
  58. u32 vga_scratch_reg; /* VGA scratch register in SCU */
  59. u32 throd_val; /* Default Threshold Seting */
  60. u32 scan_line_max; /* Max memory size of one scan line */
  61. };
  62. static const struct aspeed_gfx_config ast2400_config = {
  63. .dac_reg = 0x2c,
  64. .int_clear_reg = 0x60,
  65. .vga_scratch_reg = 0x50,
  66. .throd_val = CRT_THROD_LOW(0x1e) | CRT_THROD_HIGH(0x12),
  67. .scan_line_max = 64,
  68. };
  69. static const struct aspeed_gfx_config ast2500_config = {
  70. .dac_reg = 0x2c,
  71. .int_clear_reg = 0x60,
  72. .vga_scratch_reg = 0x50,
  73. .throd_val = CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3c),
  74. .scan_line_max = 128,
  75. };
  76. static const struct aspeed_gfx_config ast2600_config = {
  77. .dac_reg = 0xc0,
  78. .int_clear_reg = 0x68,
  79. .vga_scratch_reg = 0x50,
  80. .throd_val = CRT_THROD_LOW(0x50) | CRT_THROD_HIGH(0x70),
  81. .scan_line_max = 128,
  82. };
  83. static const struct of_device_id aspeed_gfx_match[] = {
  84. { .compatible = "aspeed,ast2400-gfx", .data = &ast2400_config },
  85. { .compatible = "aspeed,ast2500-gfx", .data = &ast2500_config },
  86. { .compatible = "aspeed,ast2600-gfx", .data = &ast2600_config },
  87. { },
  88. };
  89. MODULE_DEVICE_TABLE(of, aspeed_gfx_match);
  90. static const struct drm_mode_config_funcs aspeed_gfx_mode_config_funcs = {
  91. .fb_create = drm_gem_fb_create,
  92. .atomic_check = drm_atomic_helper_check,
  93. .atomic_commit = drm_atomic_helper_commit,
  94. };
  95. static int aspeed_gfx_setup_mode_config(struct drm_device *drm)
  96. {
  97. int ret;
  98. ret = drmm_mode_config_init(drm);
  99. if (ret)
  100. return ret;
  101. drm->mode_config.min_width = 0;
  102. drm->mode_config.min_height = 0;
  103. drm->mode_config.max_width = 800;
  104. drm->mode_config.max_height = 600;
  105. drm->mode_config.funcs = &aspeed_gfx_mode_config_funcs;
  106. return ret;
  107. }
  108. static irqreturn_t aspeed_gfx_irq_handler(int irq, void *data)
  109. {
  110. struct drm_device *drm = data;
  111. struct aspeed_gfx *priv = to_aspeed_gfx(drm);
  112. u32 reg;
  113. reg = readl(priv->base + CRT_CTRL1);
  114. if (reg & CRT_CTRL_VERTICAL_INTR_STS) {
  115. drm_crtc_handle_vblank(&priv->pipe.crtc);
  116. writel(reg, priv->base + priv->int_clr_reg);
  117. return IRQ_HANDLED;
  118. }
  119. return IRQ_NONE;
  120. }
  121. static int aspeed_gfx_load(struct drm_device *drm)
  122. {
  123. struct platform_device *pdev = to_platform_device(drm->dev);
  124. struct aspeed_gfx *priv = to_aspeed_gfx(drm);
  125. struct device_node *np = pdev->dev.of_node;
  126. const struct aspeed_gfx_config *config;
  127. struct resource *res;
  128. int ret;
  129. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  130. priv->base = devm_ioremap_resource(drm->dev, res);
  131. if (IS_ERR(priv->base))
  132. return PTR_ERR(priv->base);
  133. config = device_get_match_data(&pdev->dev);
  134. if (!config)
  135. return -EINVAL;
  136. priv->dac_reg = config->dac_reg;
  137. priv->int_clr_reg = config->int_clear_reg;
  138. priv->vga_scratch_reg = config->vga_scratch_reg;
  139. priv->throd_val = config->throd_val;
  140. priv->scan_line_max = config->scan_line_max;
  141. priv->scu = syscon_regmap_lookup_by_phandle(np, "syscon");
  142. if (IS_ERR(priv->scu)) {
  143. priv->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2500-scu");
  144. if (IS_ERR(priv->scu)) {
  145. dev_err(&pdev->dev, "failed to find SCU regmap\n");
  146. return PTR_ERR(priv->scu);
  147. }
  148. }
  149. ret = of_reserved_mem_device_init(drm->dev);
  150. if (ret) {
  151. dev_err(&pdev->dev,
  152. "failed to initialize reserved mem: %d\n", ret);
  153. return ret;
  154. }
  155. ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
  156. if (ret) {
  157. dev_err(&pdev->dev, "failed to set DMA mask: %d\n", ret);
  158. return ret;
  159. }
  160. priv->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
  161. if (IS_ERR(priv->rst)) {
  162. dev_err(&pdev->dev,
  163. "missing or invalid reset controller device tree entry");
  164. return PTR_ERR(priv->rst);
  165. }
  166. reset_control_deassert(priv->rst);
  167. priv->clk = devm_clk_get(drm->dev, NULL);
  168. if (IS_ERR(priv->clk)) {
  169. dev_err(&pdev->dev,
  170. "missing or invalid clk device tree entry");
  171. return PTR_ERR(priv->clk);
  172. }
  173. clk_prepare_enable(priv->clk);
  174. /* Sanitize control registers */
  175. writel(0, priv->base + CRT_CTRL1);
  176. writel(0, priv->base + CRT_CTRL2);
  177. ret = aspeed_gfx_setup_mode_config(drm);
  178. if (ret < 0)
  179. return ret;
  180. ret = drm_vblank_init(drm, 1);
  181. if (ret < 0) {
  182. dev_err(drm->dev, "Failed to initialise vblank\n");
  183. return ret;
  184. }
  185. ret = aspeed_gfx_create_output(drm);
  186. if (ret < 0) {
  187. dev_err(drm->dev, "Failed to create outputs\n");
  188. return ret;
  189. }
  190. ret = aspeed_gfx_create_pipe(drm);
  191. if (ret < 0) {
  192. dev_err(drm->dev, "Cannot setup simple display pipe\n");
  193. return ret;
  194. }
  195. ret = devm_request_irq(drm->dev, platform_get_irq(pdev, 0),
  196. aspeed_gfx_irq_handler, 0, "aspeed gfx", drm);
  197. if (ret < 0) {
  198. dev_err(drm->dev, "Failed to install IRQ handler\n");
  199. return ret;
  200. }
  201. drm_mode_config_reset(drm);
  202. return 0;
  203. }
  204. static void aspeed_gfx_unload(struct drm_device *drm)
  205. {
  206. drm_kms_helper_poll_fini(drm);
  207. }
  208. DEFINE_DRM_GEM_DMA_FOPS(fops);
  209. static const struct drm_driver aspeed_gfx_driver = {
  210. .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
  211. DRM_GEM_DMA_DRIVER_OPS,
  212. .fops = &fops,
  213. .name = "aspeed-gfx-drm",
  214. .desc = "ASPEED GFX DRM",
  215. .date = "20180319",
  216. .major = 1,
  217. .minor = 0,
  218. };
  219. static ssize_t dac_mux_store(struct device *dev, struct device_attribute *attr,
  220. const char *buf, size_t count)
  221. {
  222. struct aspeed_gfx *priv = dev_get_drvdata(dev);
  223. u32 val;
  224. int rc;
  225. rc = kstrtou32(buf, 0, &val);
  226. if (rc)
  227. return rc;
  228. if (val > 3)
  229. return -EINVAL;
  230. rc = regmap_update_bits(priv->scu, priv->dac_reg, 0x30000, val << 16);
  231. if (rc < 0)
  232. return 0;
  233. return count;
  234. }
  235. static ssize_t dac_mux_show(struct device *dev, struct device_attribute *attr, char *buf)
  236. {
  237. struct aspeed_gfx *priv = dev_get_drvdata(dev);
  238. u32 reg;
  239. int rc;
  240. rc = regmap_read(priv->scu, priv->dac_reg, &reg);
  241. if (rc)
  242. return rc;
  243. return sprintf(buf, "%u\n", (reg >> 16) & 0x3);
  244. }
  245. static DEVICE_ATTR_RW(dac_mux);
  246. static ssize_t
  247. vga_pw_show(struct device *dev, struct device_attribute *attr, char *buf)
  248. {
  249. struct aspeed_gfx *priv = dev_get_drvdata(dev);
  250. u32 reg;
  251. int rc;
  252. rc = regmap_read(priv->scu, priv->vga_scratch_reg, &reg);
  253. if (rc)
  254. return rc;
  255. return sprintf(buf, "%u\n", reg);
  256. }
  257. static DEVICE_ATTR_RO(vga_pw);
  258. static struct attribute *aspeed_sysfs_entries[] = {
  259. &dev_attr_vga_pw.attr,
  260. &dev_attr_dac_mux.attr,
  261. NULL,
  262. };
  263. static struct attribute_group aspeed_sysfs_attr_group = {
  264. .attrs = aspeed_sysfs_entries,
  265. };
  266. static int aspeed_gfx_probe(struct platform_device *pdev)
  267. {
  268. struct aspeed_gfx *priv;
  269. int ret;
  270. priv = devm_drm_dev_alloc(&pdev->dev, &aspeed_gfx_driver,
  271. struct aspeed_gfx, drm);
  272. if (IS_ERR(priv))
  273. return PTR_ERR(priv);
  274. ret = aspeed_gfx_load(&priv->drm);
  275. if (ret)
  276. return ret;
  277. platform_set_drvdata(pdev, priv);
  278. ret = sysfs_create_group(&pdev->dev.kobj, &aspeed_sysfs_attr_group);
  279. if (ret)
  280. return ret;
  281. ret = drm_dev_register(&priv->drm, 0);
  282. if (ret)
  283. goto err_unload;
  284. drm_fbdev_dma_setup(&priv->drm, 32);
  285. return 0;
  286. err_unload:
  287. sysfs_remove_group(&pdev->dev.kobj, &aspeed_sysfs_attr_group);
  288. aspeed_gfx_unload(&priv->drm);
  289. return ret;
  290. }
  291. static void aspeed_gfx_remove(struct platform_device *pdev)
  292. {
  293. struct drm_device *drm = platform_get_drvdata(pdev);
  294. sysfs_remove_group(&pdev->dev.kobj, &aspeed_sysfs_attr_group);
  295. drm_dev_unregister(drm);
  296. aspeed_gfx_unload(drm);
  297. drm_atomic_helper_shutdown(drm);
  298. }
  299. static void aspeed_gfx_shutdown(struct platform_device *pdev)
  300. {
  301. drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
  302. }
  303. static struct platform_driver aspeed_gfx_platform_driver = {
  304. .probe = aspeed_gfx_probe,
  305. .remove_new = aspeed_gfx_remove,
  306. .shutdown = aspeed_gfx_shutdown,
  307. .driver = {
  308. .name = "aspeed_gfx",
  309. .of_match_table = aspeed_gfx_match,
  310. },
  311. };
  312. drm_module_platform_driver(aspeed_gfx_platform_driver);
  313. MODULE_AUTHOR("Joel Stanley <joel@jms.id.au>");
  314. MODULE_DESCRIPTION("ASPEED BMC DRM/KMS driver");
  315. MODULE_LICENSE("GPL");