exynos_drm_g2d.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics Co.Ltd
  4. * Authors: Joonyoung Shim <jy0922.shim@samsung.com>
  5. */
  6. #include <linux/refcount.h>
  7. #include <linux/clk.h>
  8. #include <linux/component.h>
  9. #include <linux/delay.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/err.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/kernel.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/slab.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/workqueue.h>
  21. #include <drm/drm_file.h>
  22. #include <drm/exynos_drm.h>
  23. #include "exynos_drm_drv.h"
  24. #include "exynos_drm_g2d.h"
  25. #include "exynos_drm_gem.h"
  26. #define G2D_HW_MAJOR_VER 4
  27. #define G2D_HW_MINOR_VER 1
  28. /* vaild register range set from user: 0x0104 ~ 0x0880 */
  29. #define G2D_VALID_START 0x0104
  30. #define G2D_VALID_END 0x0880
  31. /* general registers */
  32. #define G2D_SOFT_RESET 0x0000
  33. #define G2D_INTEN 0x0004
  34. #define G2D_INTC_PEND 0x000C
  35. #define G2D_DMA_SFR_BASE_ADDR 0x0080
  36. #define G2D_DMA_COMMAND 0x0084
  37. #define G2D_DMA_STATUS 0x008C
  38. #define G2D_DMA_HOLD_CMD 0x0090
  39. /* command registers */
  40. #define G2D_BITBLT_START 0x0100
  41. /* registers for base address */
  42. #define G2D_SRC_BASE_ADDR 0x0304
  43. #define G2D_SRC_STRIDE 0x0308
  44. #define G2D_SRC_COLOR_MODE 0x030C
  45. #define G2D_SRC_LEFT_TOP 0x0310
  46. #define G2D_SRC_RIGHT_BOTTOM 0x0314
  47. #define G2D_SRC_PLANE2_BASE_ADDR 0x0318
  48. #define G2D_DST_BASE_ADDR 0x0404
  49. #define G2D_DST_STRIDE 0x0408
  50. #define G2D_DST_COLOR_MODE 0x040C
  51. #define G2D_DST_LEFT_TOP 0x0410
  52. #define G2D_DST_RIGHT_BOTTOM 0x0414
  53. #define G2D_DST_PLANE2_BASE_ADDR 0x0418
  54. #define G2D_PAT_BASE_ADDR 0x0500
  55. #define G2D_MSK_BASE_ADDR 0x0520
  56. /* G2D_SOFT_RESET */
  57. #define G2D_SFRCLEAR (1 << 1)
  58. #define G2D_R (1 << 0)
  59. /* G2D_INTEN */
  60. #define G2D_INTEN_ACF (1 << 3)
  61. #define G2D_INTEN_UCF (1 << 2)
  62. #define G2D_INTEN_GCF (1 << 1)
  63. #define G2D_INTEN_SCF (1 << 0)
  64. /* G2D_INTC_PEND */
  65. #define G2D_INTP_ACMD_FIN (1 << 3)
  66. #define G2D_INTP_UCMD_FIN (1 << 2)
  67. #define G2D_INTP_GCMD_FIN (1 << 1)
  68. #define G2D_INTP_SCMD_FIN (1 << 0)
  69. /* G2D_DMA_COMMAND */
  70. #define G2D_DMA_HALT (1 << 2)
  71. #define G2D_DMA_CONTINUE (1 << 1)
  72. #define G2D_DMA_START (1 << 0)
  73. /* G2D_DMA_STATUS */
  74. #define G2D_DMA_LIST_DONE_COUNT (0xFF << 17)
  75. #define G2D_DMA_BITBLT_DONE_COUNT (0xFFFF << 1)
  76. #define G2D_DMA_DONE (1 << 0)
  77. #define G2D_DMA_LIST_DONE_COUNT_OFFSET 17
  78. /* G2D_DMA_HOLD_CMD */
  79. #define G2D_USER_HOLD (1 << 2)
  80. #define G2D_LIST_HOLD (1 << 1)
  81. #define G2D_BITBLT_HOLD (1 << 0)
  82. /* G2D_BITBLT_START */
  83. #define G2D_START_CASESEL (1 << 2)
  84. #define G2D_START_NHOLT (1 << 1)
  85. #define G2D_START_BITBLT (1 << 0)
  86. /* buffer color format */
  87. #define G2D_FMT_XRGB8888 0
  88. #define G2D_FMT_ARGB8888 1
  89. #define G2D_FMT_RGB565 2
  90. #define G2D_FMT_XRGB1555 3
  91. #define G2D_FMT_ARGB1555 4
  92. #define G2D_FMT_XRGB4444 5
  93. #define G2D_FMT_ARGB4444 6
  94. #define G2D_FMT_PACKED_RGB888 7
  95. #define G2D_FMT_A8 11
  96. #define G2D_FMT_L8 12
  97. /* buffer valid length */
  98. #define G2D_LEN_MIN 1
  99. #define G2D_LEN_MAX 8000
  100. #define G2D_CMDLIST_SIZE (PAGE_SIZE / 4)
  101. #define G2D_CMDLIST_NUM 64
  102. #define G2D_CMDLIST_POOL_SIZE (G2D_CMDLIST_SIZE * G2D_CMDLIST_NUM)
  103. #define G2D_CMDLIST_DATA_NUM (G2D_CMDLIST_SIZE / sizeof(u32) - 2)
  104. /* maximum buffer pool size of userptr is 64MB as default */
  105. #define MAX_POOL (64 * 1024 * 1024)
  106. enum {
  107. BUF_TYPE_GEM = 1,
  108. BUF_TYPE_USERPTR,
  109. };
  110. enum g2d_reg_type {
  111. REG_TYPE_NONE = -1,
  112. REG_TYPE_SRC,
  113. REG_TYPE_SRC_PLANE2,
  114. REG_TYPE_DST,
  115. REG_TYPE_DST_PLANE2,
  116. REG_TYPE_PAT,
  117. REG_TYPE_MSK,
  118. MAX_REG_TYPE_NR
  119. };
  120. enum g2d_flag_bits {
  121. /*
  122. * If set, suspends the runqueue worker after the currently
  123. * processed node is finished.
  124. */
  125. G2D_BIT_SUSPEND_RUNQUEUE,
  126. /*
  127. * If set, indicates that the engine is currently busy.
  128. */
  129. G2D_BIT_ENGINE_BUSY,
  130. };
  131. /* cmdlist data structure */
  132. struct g2d_cmdlist {
  133. u32 head;
  134. unsigned long data[G2D_CMDLIST_DATA_NUM];
  135. u32 last; /* last data offset */
  136. };
  137. /*
  138. * A structure of buffer description
  139. *
  140. * @format: color format
  141. * @stride: buffer stride/pitch in bytes
  142. * @left_x: the x coordinates of left top corner
  143. * @top_y: the y coordinates of left top corner
  144. * @right_x: the x coordinates of right bottom corner
  145. * @bottom_y: the y coordinates of right bottom corner
  146. *
  147. */
  148. struct g2d_buf_desc {
  149. unsigned int format;
  150. unsigned int stride;
  151. unsigned int left_x;
  152. unsigned int top_y;
  153. unsigned int right_x;
  154. unsigned int bottom_y;
  155. };
  156. /*
  157. * A structure of buffer information
  158. *
  159. * @map_nr: manages the number of mapped buffers
  160. * @reg_types: stores regitster type in the order of requested command
  161. * @handles: stores buffer handle in its reg_type position
  162. * @types: stores buffer type in its reg_type position
  163. * @descs: stores buffer description in its reg_type position
  164. *
  165. */
  166. struct g2d_buf_info {
  167. unsigned int map_nr;
  168. enum g2d_reg_type reg_types[MAX_REG_TYPE_NR];
  169. void *obj[MAX_REG_TYPE_NR];
  170. unsigned int types[MAX_REG_TYPE_NR];
  171. struct g2d_buf_desc descs[MAX_REG_TYPE_NR];
  172. };
  173. struct drm_exynos_pending_g2d_event {
  174. struct drm_pending_event base;
  175. struct drm_exynos_g2d_event event;
  176. };
  177. struct g2d_cmdlist_userptr {
  178. struct list_head list;
  179. dma_addr_t dma_addr;
  180. unsigned long userptr;
  181. unsigned long size;
  182. struct page **pages;
  183. unsigned int npages;
  184. struct sg_table *sgt;
  185. refcount_t refcount;
  186. bool in_pool;
  187. bool out_of_list;
  188. };
  189. struct g2d_cmdlist_node {
  190. struct list_head list;
  191. struct g2d_cmdlist *cmdlist;
  192. dma_addr_t dma_addr;
  193. struct g2d_buf_info buf_info;
  194. struct drm_exynos_pending_g2d_event *event;
  195. };
  196. struct g2d_runqueue_node {
  197. struct list_head list;
  198. struct list_head run_cmdlist;
  199. struct list_head event_list;
  200. struct drm_file *filp;
  201. pid_t pid;
  202. struct completion complete;
  203. int async;
  204. };
  205. struct g2d_data {
  206. struct device *dev;
  207. void *dma_priv;
  208. struct clk *gate_clk;
  209. void __iomem *regs;
  210. int irq;
  211. struct workqueue_struct *g2d_workq;
  212. struct work_struct runqueue_work;
  213. struct drm_device *drm_dev;
  214. unsigned long flags;
  215. /* cmdlist */
  216. struct g2d_cmdlist_node *cmdlist_node;
  217. struct list_head free_cmdlist;
  218. struct mutex cmdlist_mutex;
  219. dma_addr_t cmdlist_pool;
  220. void *cmdlist_pool_virt;
  221. unsigned long cmdlist_dma_attrs;
  222. /* runqueue*/
  223. struct g2d_runqueue_node *runqueue_node;
  224. struct list_head runqueue;
  225. struct mutex runqueue_mutex;
  226. struct kmem_cache *runqueue_slab;
  227. unsigned long current_pool;
  228. unsigned long max_pool;
  229. };
  230. static inline void g2d_hw_reset(struct g2d_data *g2d)
  231. {
  232. writel(G2D_R | G2D_SFRCLEAR, g2d->regs + G2D_SOFT_RESET);
  233. clear_bit(G2D_BIT_ENGINE_BUSY, &g2d->flags);
  234. }
  235. static int g2d_init_cmdlist(struct g2d_data *g2d)
  236. {
  237. struct device *dev = g2d->dev;
  238. struct g2d_cmdlist_node *node;
  239. int nr;
  240. int ret;
  241. struct g2d_buf_info *buf_info;
  242. g2d->cmdlist_dma_attrs = DMA_ATTR_WRITE_COMBINE;
  243. g2d->cmdlist_pool_virt = dma_alloc_attrs(to_dma_dev(g2d->drm_dev),
  244. G2D_CMDLIST_POOL_SIZE,
  245. &g2d->cmdlist_pool, GFP_KERNEL,
  246. g2d->cmdlist_dma_attrs);
  247. if (!g2d->cmdlist_pool_virt) {
  248. dev_err(dev, "failed to allocate dma memory\n");
  249. return -ENOMEM;
  250. }
  251. node = kcalloc(G2D_CMDLIST_NUM, sizeof(*node), GFP_KERNEL);
  252. if (!node) {
  253. ret = -ENOMEM;
  254. goto err;
  255. }
  256. for (nr = 0; nr < G2D_CMDLIST_NUM; nr++) {
  257. unsigned int i;
  258. node[nr].cmdlist =
  259. g2d->cmdlist_pool_virt + nr * G2D_CMDLIST_SIZE;
  260. node[nr].dma_addr =
  261. g2d->cmdlist_pool + nr * G2D_CMDLIST_SIZE;
  262. buf_info = &node[nr].buf_info;
  263. for (i = 0; i < MAX_REG_TYPE_NR; i++)
  264. buf_info->reg_types[i] = REG_TYPE_NONE;
  265. list_add_tail(&node[nr].list, &g2d->free_cmdlist);
  266. }
  267. return 0;
  268. err:
  269. dma_free_attrs(to_dma_dev(g2d->drm_dev), G2D_CMDLIST_POOL_SIZE,
  270. g2d->cmdlist_pool_virt,
  271. g2d->cmdlist_pool, g2d->cmdlist_dma_attrs);
  272. return ret;
  273. }
  274. static void g2d_fini_cmdlist(struct g2d_data *g2d)
  275. {
  276. kfree(g2d->cmdlist_node);
  277. if (g2d->cmdlist_pool_virt && g2d->cmdlist_pool) {
  278. dma_free_attrs(to_dma_dev(g2d->drm_dev),
  279. G2D_CMDLIST_POOL_SIZE,
  280. g2d->cmdlist_pool_virt,
  281. g2d->cmdlist_pool, g2d->cmdlist_dma_attrs);
  282. }
  283. }
  284. static struct g2d_cmdlist_node *g2d_get_cmdlist(struct g2d_data *g2d)
  285. {
  286. struct device *dev = g2d->dev;
  287. struct g2d_cmdlist_node *node;
  288. mutex_lock(&g2d->cmdlist_mutex);
  289. if (list_empty(&g2d->free_cmdlist)) {
  290. dev_err(dev, "there is no free cmdlist\n");
  291. mutex_unlock(&g2d->cmdlist_mutex);
  292. return NULL;
  293. }
  294. node = list_first_entry(&g2d->free_cmdlist, struct g2d_cmdlist_node,
  295. list);
  296. list_del_init(&node->list);
  297. mutex_unlock(&g2d->cmdlist_mutex);
  298. return node;
  299. }
  300. static void g2d_put_cmdlist(struct g2d_data *g2d, struct g2d_cmdlist_node *node)
  301. {
  302. mutex_lock(&g2d->cmdlist_mutex);
  303. list_move_tail(&node->list, &g2d->free_cmdlist);
  304. mutex_unlock(&g2d->cmdlist_mutex);
  305. }
  306. static void g2d_add_cmdlist_to_inuse(struct drm_exynos_file_private *file_priv,
  307. struct g2d_cmdlist_node *node)
  308. {
  309. struct g2d_cmdlist_node *lnode;
  310. if (list_empty(&file_priv->inuse_cmdlist))
  311. goto add_to_list;
  312. /* this links to base address of new cmdlist */
  313. lnode = list_entry(file_priv->inuse_cmdlist.prev,
  314. struct g2d_cmdlist_node, list);
  315. lnode->cmdlist->data[lnode->cmdlist->last] = node->dma_addr;
  316. add_to_list:
  317. list_add_tail(&node->list, &file_priv->inuse_cmdlist);
  318. if (node->event)
  319. list_add_tail(&node->event->base.link, &file_priv->event_list);
  320. }
  321. static void g2d_userptr_put_dma_addr(struct g2d_data *g2d,
  322. void *obj,
  323. bool force)
  324. {
  325. struct g2d_cmdlist_userptr *g2d_userptr = obj;
  326. if (!obj)
  327. return;
  328. if (force)
  329. goto out;
  330. refcount_dec(&g2d_userptr->refcount);
  331. if (refcount_read(&g2d_userptr->refcount) > 0)
  332. return;
  333. if (g2d_userptr->in_pool)
  334. return;
  335. out:
  336. dma_unmap_sgtable(to_dma_dev(g2d->drm_dev), g2d_userptr->sgt,
  337. DMA_BIDIRECTIONAL, 0);
  338. unpin_user_pages_dirty_lock(g2d_userptr->pages, g2d_userptr->npages,
  339. true);
  340. kvfree(g2d_userptr->pages);
  341. if (!g2d_userptr->out_of_list)
  342. list_del_init(&g2d_userptr->list);
  343. sg_free_table(g2d_userptr->sgt);
  344. kfree(g2d_userptr->sgt);
  345. kfree(g2d_userptr);
  346. }
  347. static dma_addr_t *g2d_userptr_get_dma_addr(struct g2d_data *g2d,
  348. unsigned long userptr,
  349. unsigned long size,
  350. struct drm_file *filp,
  351. void **obj)
  352. {
  353. struct drm_exynos_file_private *file_priv = filp->driver_priv;
  354. struct g2d_cmdlist_userptr *g2d_userptr;
  355. struct sg_table *sgt;
  356. unsigned long start, end;
  357. unsigned int npages, offset;
  358. int ret;
  359. if (!size) {
  360. DRM_DEV_ERROR(g2d->dev, "invalid userptr size.\n");
  361. return ERR_PTR(-EINVAL);
  362. }
  363. /* check if userptr already exists in userptr_list. */
  364. list_for_each_entry(g2d_userptr, &file_priv->userptr_list, list) {
  365. if (g2d_userptr->userptr == userptr) {
  366. /*
  367. * also check size because there could be same address
  368. * and different size.
  369. */
  370. if (g2d_userptr->size == size) {
  371. refcount_inc(&g2d_userptr->refcount);
  372. *obj = g2d_userptr;
  373. return &g2d_userptr->dma_addr;
  374. }
  375. /*
  376. * at this moment, maybe g2d dma is accessing this
  377. * g2d_userptr memory region so just remove this
  378. * g2d_userptr object from userptr_list not to be
  379. * referred again and also except it the userptr
  380. * pool to be released after the dma access completion.
  381. */
  382. g2d_userptr->out_of_list = true;
  383. g2d_userptr->in_pool = false;
  384. list_del_init(&g2d_userptr->list);
  385. break;
  386. }
  387. }
  388. g2d_userptr = kzalloc(sizeof(*g2d_userptr), GFP_KERNEL);
  389. if (!g2d_userptr)
  390. return ERR_PTR(-ENOMEM);
  391. refcount_set(&g2d_userptr->refcount, 1);
  392. g2d_userptr->size = size;
  393. start = userptr & PAGE_MASK;
  394. offset = userptr & ~PAGE_MASK;
  395. end = PAGE_ALIGN(userptr + size);
  396. npages = (end - start) >> PAGE_SHIFT;
  397. g2d_userptr->pages = kvmalloc_array(npages, sizeof(*g2d_userptr->pages),
  398. GFP_KERNEL);
  399. if (!g2d_userptr->pages) {
  400. ret = -ENOMEM;
  401. goto err_free;
  402. }
  403. ret = pin_user_pages_fast(start, npages,
  404. FOLL_WRITE | FOLL_LONGTERM,
  405. g2d_userptr->pages);
  406. if (ret != npages) {
  407. DRM_DEV_ERROR(g2d->dev,
  408. "failed to get user pages from userptr.\n");
  409. if (ret < 0)
  410. goto err_destroy_pages;
  411. npages = ret;
  412. ret = -EFAULT;
  413. goto err_unpin_pages;
  414. }
  415. g2d_userptr->npages = npages;
  416. sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
  417. if (!sgt) {
  418. ret = -ENOMEM;
  419. goto err_unpin_pages;
  420. }
  421. ret = sg_alloc_table_from_pages(sgt,
  422. g2d_userptr->pages,
  423. npages, offset, size, GFP_KERNEL);
  424. if (ret < 0) {
  425. DRM_DEV_ERROR(g2d->dev, "failed to get sgt from pages.\n");
  426. goto err_free_sgt;
  427. }
  428. g2d_userptr->sgt = sgt;
  429. ret = dma_map_sgtable(to_dma_dev(g2d->drm_dev), sgt,
  430. DMA_BIDIRECTIONAL, 0);
  431. if (ret) {
  432. DRM_DEV_ERROR(g2d->dev, "failed to map sgt with dma region.\n");
  433. goto err_sg_free_table;
  434. }
  435. g2d_userptr->dma_addr = sgt->sgl[0].dma_address;
  436. g2d_userptr->userptr = userptr;
  437. list_add_tail(&g2d_userptr->list, &file_priv->userptr_list);
  438. if (g2d->current_pool + (npages << PAGE_SHIFT) < g2d->max_pool) {
  439. g2d->current_pool += npages << PAGE_SHIFT;
  440. g2d_userptr->in_pool = true;
  441. }
  442. *obj = g2d_userptr;
  443. return &g2d_userptr->dma_addr;
  444. err_sg_free_table:
  445. sg_free_table(sgt);
  446. err_free_sgt:
  447. kfree(sgt);
  448. err_unpin_pages:
  449. unpin_user_pages(g2d_userptr->pages, npages);
  450. err_destroy_pages:
  451. kvfree(g2d_userptr->pages);
  452. err_free:
  453. kfree(g2d_userptr);
  454. return ERR_PTR(ret);
  455. }
  456. static void g2d_userptr_free_all(struct g2d_data *g2d, struct drm_file *filp)
  457. {
  458. struct drm_exynos_file_private *file_priv = filp->driver_priv;
  459. struct g2d_cmdlist_userptr *g2d_userptr, *n;
  460. list_for_each_entry_safe(g2d_userptr, n, &file_priv->userptr_list, list)
  461. if (g2d_userptr->in_pool)
  462. g2d_userptr_put_dma_addr(g2d, g2d_userptr, true);
  463. g2d->current_pool = 0;
  464. }
  465. static enum g2d_reg_type g2d_get_reg_type(struct g2d_data *g2d, int reg_offset)
  466. {
  467. enum g2d_reg_type reg_type;
  468. switch (reg_offset) {
  469. case G2D_SRC_BASE_ADDR:
  470. case G2D_SRC_STRIDE:
  471. case G2D_SRC_COLOR_MODE:
  472. case G2D_SRC_LEFT_TOP:
  473. case G2D_SRC_RIGHT_BOTTOM:
  474. reg_type = REG_TYPE_SRC;
  475. break;
  476. case G2D_SRC_PLANE2_BASE_ADDR:
  477. reg_type = REG_TYPE_SRC_PLANE2;
  478. break;
  479. case G2D_DST_BASE_ADDR:
  480. case G2D_DST_STRIDE:
  481. case G2D_DST_COLOR_MODE:
  482. case G2D_DST_LEFT_TOP:
  483. case G2D_DST_RIGHT_BOTTOM:
  484. reg_type = REG_TYPE_DST;
  485. break;
  486. case G2D_DST_PLANE2_BASE_ADDR:
  487. reg_type = REG_TYPE_DST_PLANE2;
  488. break;
  489. case G2D_PAT_BASE_ADDR:
  490. reg_type = REG_TYPE_PAT;
  491. break;
  492. case G2D_MSK_BASE_ADDR:
  493. reg_type = REG_TYPE_MSK;
  494. break;
  495. default:
  496. reg_type = REG_TYPE_NONE;
  497. DRM_DEV_ERROR(g2d->dev, "Unknown register offset![%d]\n",
  498. reg_offset);
  499. break;
  500. }
  501. return reg_type;
  502. }
  503. static unsigned long g2d_get_buf_bpp(unsigned int format)
  504. {
  505. unsigned long bpp;
  506. switch (format) {
  507. case G2D_FMT_XRGB8888:
  508. case G2D_FMT_ARGB8888:
  509. bpp = 4;
  510. break;
  511. case G2D_FMT_RGB565:
  512. case G2D_FMT_XRGB1555:
  513. case G2D_FMT_ARGB1555:
  514. case G2D_FMT_XRGB4444:
  515. case G2D_FMT_ARGB4444:
  516. bpp = 2;
  517. break;
  518. case G2D_FMT_PACKED_RGB888:
  519. bpp = 3;
  520. break;
  521. default:
  522. bpp = 1;
  523. break;
  524. }
  525. return bpp;
  526. }
  527. static bool g2d_check_buf_desc_is_valid(struct g2d_data *g2d,
  528. struct g2d_buf_desc *buf_desc,
  529. enum g2d_reg_type reg_type,
  530. unsigned long size)
  531. {
  532. int width, height;
  533. unsigned long bpp, last_pos;
  534. /*
  535. * check source and destination buffers only.
  536. * so the others are always valid.
  537. */
  538. if (reg_type != REG_TYPE_SRC && reg_type != REG_TYPE_DST)
  539. return true;
  540. /* This check also makes sure that right_x > left_x. */
  541. width = (int)buf_desc->right_x - (int)buf_desc->left_x;
  542. if (width < G2D_LEN_MIN || width > G2D_LEN_MAX) {
  543. DRM_DEV_ERROR(g2d->dev, "width[%d] is out of range!\n", width);
  544. return false;
  545. }
  546. /* This check also makes sure that bottom_y > top_y. */
  547. height = (int)buf_desc->bottom_y - (int)buf_desc->top_y;
  548. if (height < G2D_LEN_MIN || height > G2D_LEN_MAX) {
  549. DRM_DEV_ERROR(g2d->dev,
  550. "height[%d] is out of range!\n", height);
  551. return false;
  552. }
  553. bpp = g2d_get_buf_bpp(buf_desc->format);
  554. /* Compute the position of the last byte that the engine accesses. */
  555. last_pos = ((unsigned long)buf_desc->bottom_y - 1) *
  556. (unsigned long)buf_desc->stride +
  557. (unsigned long)buf_desc->right_x * bpp - 1;
  558. /*
  559. * Since right_x > left_x and bottom_y > top_y we already know
  560. * that the first_pos < last_pos (first_pos being the position
  561. * of the first byte the engine accesses), it just remains to
  562. * check if last_pos is smaller then the buffer size.
  563. */
  564. if (last_pos >= size) {
  565. DRM_DEV_ERROR(g2d->dev, "last engine access position [%lu] "
  566. "is out of range [%lu]!\n", last_pos, size);
  567. return false;
  568. }
  569. return true;
  570. }
  571. static int g2d_map_cmdlist_gem(struct g2d_data *g2d,
  572. struct g2d_cmdlist_node *node,
  573. struct drm_device *drm_dev,
  574. struct drm_file *file)
  575. {
  576. struct g2d_cmdlist *cmdlist = node->cmdlist;
  577. struct g2d_buf_info *buf_info = &node->buf_info;
  578. int offset;
  579. int ret;
  580. int i;
  581. for (i = 0; i < buf_info->map_nr; i++) {
  582. struct g2d_buf_desc *buf_desc;
  583. enum g2d_reg_type reg_type;
  584. int reg_pos;
  585. unsigned long handle;
  586. dma_addr_t *addr;
  587. reg_pos = cmdlist->last - 2 * (i + 1);
  588. offset = cmdlist->data[reg_pos];
  589. handle = cmdlist->data[reg_pos + 1];
  590. reg_type = g2d_get_reg_type(g2d, offset);
  591. if (reg_type == REG_TYPE_NONE) {
  592. ret = -EFAULT;
  593. goto err;
  594. }
  595. buf_desc = &buf_info->descs[reg_type];
  596. if (buf_info->types[reg_type] == BUF_TYPE_GEM) {
  597. struct exynos_drm_gem *exynos_gem;
  598. exynos_gem = exynos_drm_gem_get(file, handle);
  599. if (!exynos_gem) {
  600. ret = -EFAULT;
  601. goto err;
  602. }
  603. if (!g2d_check_buf_desc_is_valid(g2d, buf_desc,
  604. reg_type, exynos_gem->size)) {
  605. exynos_drm_gem_put(exynos_gem);
  606. ret = -EFAULT;
  607. goto err;
  608. }
  609. addr = &exynos_gem->dma_addr;
  610. buf_info->obj[reg_type] = exynos_gem;
  611. } else {
  612. struct drm_exynos_g2d_userptr g2d_userptr;
  613. if (copy_from_user(&g2d_userptr, (void __user *)handle,
  614. sizeof(struct drm_exynos_g2d_userptr))) {
  615. ret = -EFAULT;
  616. goto err;
  617. }
  618. if (!g2d_check_buf_desc_is_valid(g2d, buf_desc,
  619. reg_type,
  620. g2d_userptr.size)) {
  621. ret = -EFAULT;
  622. goto err;
  623. }
  624. addr = g2d_userptr_get_dma_addr(g2d,
  625. g2d_userptr.userptr,
  626. g2d_userptr.size,
  627. file,
  628. &buf_info->obj[reg_type]);
  629. if (IS_ERR(addr)) {
  630. ret = -EFAULT;
  631. goto err;
  632. }
  633. }
  634. cmdlist->data[reg_pos + 1] = *addr;
  635. buf_info->reg_types[i] = reg_type;
  636. }
  637. return 0;
  638. err:
  639. buf_info->map_nr = i;
  640. return ret;
  641. }
  642. static void g2d_unmap_cmdlist_gem(struct g2d_data *g2d,
  643. struct g2d_cmdlist_node *node,
  644. struct drm_file *filp)
  645. {
  646. struct g2d_buf_info *buf_info = &node->buf_info;
  647. int i;
  648. for (i = 0; i < buf_info->map_nr; i++) {
  649. struct g2d_buf_desc *buf_desc;
  650. enum g2d_reg_type reg_type;
  651. void *obj;
  652. reg_type = buf_info->reg_types[i];
  653. buf_desc = &buf_info->descs[reg_type];
  654. obj = buf_info->obj[reg_type];
  655. if (buf_info->types[reg_type] == BUF_TYPE_GEM)
  656. exynos_drm_gem_put(obj);
  657. else
  658. g2d_userptr_put_dma_addr(g2d, obj, false);
  659. buf_info->reg_types[i] = REG_TYPE_NONE;
  660. buf_info->obj[reg_type] = NULL;
  661. buf_info->types[reg_type] = 0;
  662. memset(buf_desc, 0x00, sizeof(*buf_desc));
  663. }
  664. buf_info->map_nr = 0;
  665. }
  666. static void g2d_dma_start(struct g2d_data *g2d,
  667. struct g2d_runqueue_node *runqueue_node)
  668. {
  669. struct g2d_cmdlist_node *node =
  670. list_first_entry(&runqueue_node->run_cmdlist,
  671. struct g2d_cmdlist_node, list);
  672. set_bit(G2D_BIT_ENGINE_BUSY, &g2d->flags);
  673. writel_relaxed(node->dma_addr, g2d->regs + G2D_DMA_SFR_BASE_ADDR);
  674. writel_relaxed(G2D_DMA_START, g2d->regs + G2D_DMA_COMMAND);
  675. }
  676. static struct g2d_runqueue_node *g2d_get_runqueue_node(struct g2d_data *g2d)
  677. {
  678. struct g2d_runqueue_node *runqueue_node;
  679. if (list_empty(&g2d->runqueue))
  680. return NULL;
  681. runqueue_node = list_first_entry(&g2d->runqueue,
  682. struct g2d_runqueue_node, list);
  683. list_del_init(&runqueue_node->list);
  684. return runqueue_node;
  685. }
  686. static void g2d_free_runqueue_node(struct g2d_data *g2d,
  687. struct g2d_runqueue_node *runqueue_node)
  688. {
  689. struct g2d_cmdlist_node *node;
  690. mutex_lock(&g2d->cmdlist_mutex);
  691. /*
  692. * commands in run_cmdlist have been completed so unmap all gem
  693. * objects in each command node so that they are unreferenced.
  694. */
  695. list_for_each_entry(node, &runqueue_node->run_cmdlist, list)
  696. g2d_unmap_cmdlist_gem(g2d, node, runqueue_node->filp);
  697. list_splice_tail_init(&runqueue_node->run_cmdlist, &g2d->free_cmdlist);
  698. mutex_unlock(&g2d->cmdlist_mutex);
  699. kmem_cache_free(g2d->runqueue_slab, runqueue_node);
  700. }
  701. /**
  702. * g2d_remove_runqueue_nodes - remove items from the list of runqueue nodes
  703. * @g2d: G2D state object
  704. * @file: if not zero, only remove items with this DRM file
  705. *
  706. * Has to be called under runqueue lock.
  707. */
  708. static void g2d_remove_runqueue_nodes(struct g2d_data *g2d, struct drm_file *file)
  709. {
  710. struct g2d_runqueue_node *node, *n;
  711. if (list_empty(&g2d->runqueue))
  712. return;
  713. list_for_each_entry_safe(node, n, &g2d->runqueue, list) {
  714. if (file && node->filp != file)
  715. continue;
  716. list_del_init(&node->list);
  717. g2d_free_runqueue_node(g2d, node);
  718. }
  719. }
  720. static void g2d_runqueue_worker(struct work_struct *work)
  721. {
  722. struct g2d_data *g2d = container_of(work, struct g2d_data,
  723. runqueue_work);
  724. struct g2d_runqueue_node *runqueue_node;
  725. /*
  726. * The engine is busy and the completion of the current node is going
  727. * to poke the runqueue worker, so nothing to do here.
  728. */
  729. if (test_bit(G2D_BIT_ENGINE_BUSY, &g2d->flags))
  730. return;
  731. mutex_lock(&g2d->runqueue_mutex);
  732. runqueue_node = g2d->runqueue_node;
  733. g2d->runqueue_node = NULL;
  734. if (runqueue_node) {
  735. pm_runtime_mark_last_busy(g2d->dev);
  736. pm_runtime_put_autosuspend(g2d->dev);
  737. complete(&runqueue_node->complete);
  738. if (runqueue_node->async)
  739. g2d_free_runqueue_node(g2d, runqueue_node);
  740. }
  741. if (!test_bit(G2D_BIT_SUSPEND_RUNQUEUE, &g2d->flags)) {
  742. g2d->runqueue_node = g2d_get_runqueue_node(g2d);
  743. if (g2d->runqueue_node) {
  744. int ret;
  745. ret = pm_runtime_resume_and_get(g2d->dev);
  746. if (ret < 0) {
  747. dev_err(g2d->dev, "failed to enable G2D device.\n");
  748. goto out;
  749. }
  750. g2d_dma_start(g2d, g2d->runqueue_node);
  751. }
  752. }
  753. out:
  754. mutex_unlock(&g2d->runqueue_mutex);
  755. }
  756. static void g2d_finish_event(struct g2d_data *g2d, u32 cmdlist_no)
  757. {
  758. struct drm_device *drm_dev = g2d->drm_dev;
  759. struct g2d_runqueue_node *runqueue_node = g2d->runqueue_node;
  760. struct drm_exynos_pending_g2d_event *e;
  761. struct timespec64 now;
  762. if (list_empty(&runqueue_node->event_list))
  763. return;
  764. e = list_first_entry(&runqueue_node->event_list,
  765. struct drm_exynos_pending_g2d_event, base.link);
  766. ktime_get_ts64(&now);
  767. e->event.tv_sec = now.tv_sec;
  768. e->event.tv_usec = now.tv_nsec / NSEC_PER_USEC;
  769. e->event.cmdlist_no = cmdlist_no;
  770. drm_send_event(drm_dev, &e->base);
  771. }
  772. static irqreturn_t g2d_irq_handler(int irq, void *dev_id)
  773. {
  774. struct g2d_data *g2d = dev_id;
  775. u32 pending;
  776. pending = readl_relaxed(g2d->regs + G2D_INTC_PEND);
  777. if (pending)
  778. writel_relaxed(pending, g2d->regs + G2D_INTC_PEND);
  779. if (pending & G2D_INTP_GCMD_FIN) {
  780. u32 cmdlist_no = readl_relaxed(g2d->regs + G2D_DMA_STATUS);
  781. cmdlist_no = (cmdlist_no & G2D_DMA_LIST_DONE_COUNT) >>
  782. G2D_DMA_LIST_DONE_COUNT_OFFSET;
  783. g2d_finish_event(g2d, cmdlist_no);
  784. writel_relaxed(0, g2d->regs + G2D_DMA_HOLD_CMD);
  785. if (!(pending & G2D_INTP_ACMD_FIN)) {
  786. writel_relaxed(G2D_DMA_CONTINUE,
  787. g2d->regs + G2D_DMA_COMMAND);
  788. }
  789. }
  790. if (pending & G2D_INTP_ACMD_FIN) {
  791. clear_bit(G2D_BIT_ENGINE_BUSY, &g2d->flags);
  792. queue_work(g2d->g2d_workq, &g2d->runqueue_work);
  793. }
  794. return IRQ_HANDLED;
  795. }
  796. /**
  797. * g2d_wait_finish - wait for the G2D engine to finish the current runqueue node
  798. * @g2d: G2D state object
  799. * @file: if not zero, only wait if the current runqueue node belongs
  800. * to the DRM file
  801. *
  802. * Should the engine not become idle after a 100ms timeout, a hardware
  803. * reset is issued.
  804. */
  805. static void g2d_wait_finish(struct g2d_data *g2d, struct drm_file *file)
  806. {
  807. struct device *dev = g2d->dev;
  808. struct g2d_runqueue_node *runqueue_node = NULL;
  809. unsigned int tries = 10;
  810. mutex_lock(&g2d->runqueue_mutex);
  811. /* If no node is currently processed, we have nothing to do. */
  812. if (!g2d->runqueue_node)
  813. goto out;
  814. runqueue_node = g2d->runqueue_node;
  815. /* Check if the currently processed item belongs to us. */
  816. if (file && runqueue_node->filp != file)
  817. goto out;
  818. mutex_unlock(&g2d->runqueue_mutex);
  819. /* Wait for the G2D engine to finish. */
  820. while (tries-- && (g2d->runqueue_node == runqueue_node))
  821. mdelay(10);
  822. mutex_lock(&g2d->runqueue_mutex);
  823. if (g2d->runqueue_node != runqueue_node)
  824. goto out;
  825. dev_err(dev, "wait timed out, resetting engine...\n");
  826. g2d_hw_reset(g2d);
  827. /*
  828. * After the hardware reset of the engine we are going to loose
  829. * the IRQ which triggers the PM runtime put().
  830. * So do this manually here.
  831. */
  832. pm_runtime_mark_last_busy(dev);
  833. pm_runtime_put_autosuspend(dev);
  834. complete(&runqueue_node->complete);
  835. if (runqueue_node->async)
  836. g2d_free_runqueue_node(g2d, runqueue_node);
  837. out:
  838. mutex_unlock(&g2d->runqueue_mutex);
  839. }
  840. static int g2d_check_reg_offset(struct g2d_data *g2d,
  841. struct g2d_cmdlist_node *node,
  842. int nr, bool for_addr)
  843. {
  844. struct g2d_cmdlist *cmdlist = node->cmdlist;
  845. int reg_offset;
  846. int index;
  847. int i;
  848. for (i = 0; i < nr; i++) {
  849. struct g2d_buf_info *buf_info = &node->buf_info;
  850. struct g2d_buf_desc *buf_desc;
  851. enum g2d_reg_type reg_type;
  852. unsigned long value;
  853. index = cmdlist->last - 2 * (i + 1);
  854. reg_offset = cmdlist->data[index] & ~0xfffff000;
  855. if (reg_offset < G2D_VALID_START || reg_offset > G2D_VALID_END)
  856. goto err;
  857. if (reg_offset % 4)
  858. goto err;
  859. switch (reg_offset) {
  860. case G2D_SRC_BASE_ADDR:
  861. case G2D_SRC_PLANE2_BASE_ADDR:
  862. case G2D_DST_BASE_ADDR:
  863. case G2D_DST_PLANE2_BASE_ADDR:
  864. case G2D_PAT_BASE_ADDR:
  865. case G2D_MSK_BASE_ADDR:
  866. if (!for_addr)
  867. goto err;
  868. reg_type = g2d_get_reg_type(g2d, reg_offset);
  869. /* check userptr buffer type. */
  870. if ((cmdlist->data[index] & ~0x7fffffff) >> 31) {
  871. buf_info->types[reg_type] = BUF_TYPE_USERPTR;
  872. cmdlist->data[index] &= ~G2D_BUF_USERPTR;
  873. } else
  874. buf_info->types[reg_type] = BUF_TYPE_GEM;
  875. break;
  876. case G2D_SRC_STRIDE:
  877. case G2D_DST_STRIDE:
  878. if (for_addr)
  879. goto err;
  880. reg_type = g2d_get_reg_type(g2d, reg_offset);
  881. buf_desc = &buf_info->descs[reg_type];
  882. buf_desc->stride = cmdlist->data[index + 1];
  883. break;
  884. case G2D_SRC_COLOR_MODE:
  885. case G2D_DST_COLOR_MODE:
  886. if (for_addr)
  887. goto err;
  888. reg_type = g2d_get_reg_type(g2d, reg_offset);
  889. buf_desc = &buf_info->descs[reg_type];
  890. value = cmdlist->data[index + 1];
  891. buf_desc->format = value & 0xf;
  892. break;
  893. case G2D_SRC_LEFT_TOP:
  894. case G2D_DST_LEFT_TOP:
  895. if (for_addr)
  896. goto err;
  897. reg_type = g2d_get_reg_type(g2d, reg_offset);
  898. buf_desc = &buf_info->descs[reg_type];
  899. value = cmdlist->data[index + 1];
  900. buf_desc->left_x = value & 0x1fff;
  901. buf_desc->top_y = (value & 0x1fff0000) >> 16;
  902. break;
  903. case G2D_SRC_RIGHT_BOTTOM:
  904. case G2D_DST_RIGHT_BOTTOM:
  905. if (for_addr)
  906. goto err;
  907. reg_type = g2d_get_reg_type(g2d, reg_offset);
  908. buf_desc = &buf_info->descs[reg_type];
  909. value = cmdlist->data[index + 1];
  910. buf_desc->right_x = value & 0x1fff;
  911. buf_desc->bottom_y = (value & 0x1fff0000) >> 16;
  912. break;
  913. default:
  914. if (for_addr)
  915. goto err;
  916. break;
  917. }
  918. }
  919. return 0;
  920. err:
  921. dev_err(g2d->dev, "Bad register offset: 0x%lx\n", cmdlist->data[index]);
  922. return -EINVAL;
  923. }
  924. /* ioctl functions */
  925. int exynos_g2d_get_ver_ioctl(struct drm_device *drm_dev, void *data,
  926. struct drm_file *file)
  927. {
  928. struct drm_exynos_g2d_get_ver *ver = data;
  929. ver->major = G2D_HW_MAJOR_VER;
  930. ver->minor = G2D_HW_MINOR_VER;
  931. return 0;
  932. }
  933. int exynos_g2d_set_cmdlist_ioctl(struct drm_device *drm_dev, void *data,
  934. struct drm_file *file)
  935. {
  936. struct drm_exynos_file_private *file_priv = file->driver_priv;
  937. struct exynos_drm_private *priv = drm_dev->dev_private;
  938. struct g2d_data *g2d = dev_get_drvdata(priv->g2d_dev);
  939. struct drm_exynos_g2d_set_cmdlist *req = data;
  940. struct drm_exynos_g2d_cmd *cmd;
  941. struct drm_exynos_pending_g2d_event *e;
  942. struct g2d_cmdlist_node *node;
  943. struct g2d_cmdlist *cmdlist;
  944. int size;
  945. int ret;
  946. node = g2d_get_cmdlist(g2d);
  947. if (!node)
  948. return -ENOMEM;
  949. /*
  950. * To avoid an integer overflow for the later size computations, we
  951. * enforce a maximum number of submitted commands here. This limit is
  952. * sufficient for all conceivable usage cases of the G2D.
  953. */
  954. if (req->cmd_nr > G2D_CMDLIST_DATA_NUM ||
  955. req->cmd_buf_nr > G2D_CMDLIST_DATA_NUM) {
  956. dev_err(g2d->dev, "number of submitted G2D commands exceeds limit\n");
  957. return -EINVAL;
  958. }
  959. node->event = NULL;
  960. if (req->event_type != G2D_EVENT_NOT) {
  961. e = kzalloc(sizeof(*node->event), GFP_KERNEL);
  962. if (!e) {
  963. ret = -ENOMEM;
  964. goto err;
  965. }
  966. e->event.base.type = DRM_EXYNOS_G2D_EVENT;
  967. e->event.base.length = sizeof(e->event);
  968. e->event.user_data = req->user_data;
  969. ret = drm_event_reserve_init(drm_dev, file, &e->base, &e->event.base);
  970. if (ret) {
  971. kfree(e);
  972. goto err;
  973. }
  974. node->event = e;
  975. }
  976. cmdlist = node->cmdlist;
  977. cmdlist->last = 0;
  978. /*
  979. * If don't clear SFR registers, the cmdlist is affected by register
  980. * values of previous cmdlist. G2D hw executes SFR clear command and
  981. * a next command at the same time then the next command is ignored and
  982. * is executed rightly from next next command, so needs a dummy command
  983. * to next command of SFR clear command.
  984. */
  985. cmdlist->data[cmdlist->last++] = G2D_SOFT_RESET;
  986. cmdlist->data[cmdlist->last++] = G2D_SFRCLEAR;
  987. cmdlist->data[cmdlist->last++] = G2D_SRC_BASE_ADDR;
  988. cmdlist->data[cmdlist->last++] = 0;
  989. /*
  990. * 'LIST_HOLD' command should be set to the DMA_HOLD_CMD_REG
  991. * and GCF bit should be set to INTEN register if user wants
  992. * G2D interrupt event once current command list execution is
  993. * finished.
  994. * Otherwise only ACF bit should be set to INTEN register so
  995. * that one interrupt is occurred after all command lists
  996. * have been completed.
  997. */
  998. if (node->event) {
  999. cmdlist->data[cmdlist->last++] = G2D_INTEN;
  1000. cmdlist->data[cmdlist->last++] = G2D_INTEN_ACF | G2D_INTEN_GCF;
  1001. cmdlist->data[cmdlist->last++] = G2D_DMA_HOLD_CMD;
  1002. cmdlist->data[cmdlist->last++] = G2D_LIST_HOLD;
  1003. } else {
  1004. cmdlist->data[cmdlist->last++] = G2D_INTEN;
  1005. cmdlist->data[cmdlist->last++] = G2D_INTEN_ACF;
  1006. }
  1007. /*
  1008. * Check the size of cmdlist. The 2 that is added last comes from
  1009. * the implicit G2D_BITBLT_START that is appended once we have
  1010. * checked all the submitted commands.
  1011. */
  1012. size = cmdlist->last + req->cmd_nr * 2 + req->cmd_buf_nr * 2 + 2;
  1013. if (size > G2D_CMDLIST_DATA_NUM) {
  1014. dev_err(g2d->dev, "cmdlist size is too big\n");
  1015. ret = -EINVAL;
  1016. goto err_free_event;
  1017. }
  1018. cmd = (struct drm_exynos_g2d_cmd *)(unsigned long)req->cmd;
  1019. if (copy_from_user(cmdlist->data + cmdlist->last,
  1020. (void __user *)cmd,
  1021. sizeof(*cmd) * req->cmd_nr)) {
  1022. ret = -EFAULT;
  1023. goto err_free_event;
  1024. }
  1025. cmdlist->last += req->cmd_nr * 2;
  1026. ret = g2d_check_reg_offset(g2d, node, req->cmd_nr, false);
  1027. if (ret < 0)
  1028. goto err_free_event;
  1029. node->buf_info.map_nr = req->cmd_buf_nr;
  1030. if (req->cmd_buf_nr) {
  1031. struct drm_exynos_g2d_cmd *cmd_buf;
  1032. cmd_buf = (struct drm_exynos_g2d_cmd *)
  1033. (unsigned long)req->cmd_buf;
  1034. if (copy_from_user(cmdlist->data + cmdlist->last,
  1035. (void __user *)cmd_buf,
  1036. sizeof(*cmd_buf) * req->cmd_buf_nr)) {
  1037. ret = -EFAULT;
  1038. goto err_free_event;
  1039. }
  1040. cmdlist->last += req->cmd_buf_nr * 2;
  1041. ret = g2d_check_reg_offset(g2d, node, req->cmd_buf_nr, true);
  1042. if (ret < 0)
  1043. goto err_free_event;
  1044. ret = g2d_map_cmdlist_gem(g2d, node, drm_dev, file);
  1045. if (ret < 0)
  1046. goto err_unmap;
  1047. }
  1048. cmdlist->data[cmdlist->last++] = G2D_BITBLT_START;
  1049. cmdlist->data[cmdlist->last++] = G2D_START_BITBLT;
  1050. /* head */
  1051. cmdlist->head = cmdlist->last / 2;
  1052. /* tail */
  1053. cmdlist->data[cmdlist->last] = 0;
  1054. g2d_add_cmdlist_to_inuse(file_priv, node);
  1055. return 0;
  1056. err_unmap:
  1057. g2d_unmap_cmdlist_gem(g2d, node, file);
  1058. err_free_event:
  1059. if (node->event)
  1060. drm_event_cancel_free(drm_dev, &node->event->base);
  1061. err:
  1062. g2d_put_cmdlist(g2d, node);
  1063. return ret;
  1064. }
  1065. int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data,
  1066. struct drm_file *file)
  1067. {
  1068. struct drm_exynos_file_private *file_priv = file->driver_priv;
  1069. struct exynos_drm_private *priv = drm_dev->dev_private;
  1070. struct g2d_data *g2d = dev_get_drvdata(priv->g2d_dev);
  1071. struct drm_exynos_g2d_exec *req = data;
  1072. struct g2d_runqueue_node *runqueue_node;
  1073. struct list_head *run_cmdlist;
  1074. struct list_head *event_list;
  1075. runqueue_node = kmem_cache_alloc(g2d->runqueue_slab, GFP_KERNEL);
  1076. if (!runqueue_node)
  1077. return -ENOMEM;
  1078. run_cmdlist = &runqueue_node->run_cmdlist;
  1079. event_list = &runqueue_node->event_list;
  1080. INIT_LIST_HEAD(run_cmdlist);
  1081. INIT_LIST_HEAD(event_list);
  1082. init_completion(&runqueue_node->complete);
  1083. runqueue_node->async = req->async;
  1084. list_splice_init(&file_priv->inuse_cmdlist, run_cmdlist);
  1085. list_splice_init(&file_priv->event_list, event_list);
  1086. if (list_empty(run_cmdlist)) {
  1087. dev_err(g2d->dev, "there is no inuse cmdlist\n");
  1088. kmem_cache_free(g2d->runqueue_slab, runqueue_node);
  1089. return -EPERM;
  1090. }
  1091. mutex_lock(&g2d->runqueue_mutex);
  1092. runqueue_node->pid = current->pid;
  1093. runqueue_node->filp = file;
  1094. list_add_tail(&runqueue_node->list, &g2d->runqueue);
  1095. mutex_unlock(&g2d->runqueue_mutex);
  1096. /* Let the runqueue know that there is work to do. */
  1097. queue_work(g2d->g2d_workq, &g2d->runqueue_work);
  1098. if (req->async)
  1099. goto out;
  1100. wait_for_completion(&runqueue_node->complete);
  1101. g2d_free_runqueue_node(g2d, runqueue_node);
  1102. out:
  1103. return 0;
  1104. }
  1105. int g2d_open(struct drm_device *drm_dev, struct drm_file *file)
  1106. {
  1107. struct drm_exynos_file_private *file_priv = file->driver_priv;
  1108. INIT_LIST_HEAD(&file_priv->inuse_cmdlist);
  1109. INIT_LIST_HEAD(&file_priv->event_list);
  1110. INIT_LIST_HEAD(&file_priv->userptr_list);
  1111. return 0;
  1112. }
  1113. void g2d_close(struct drm_device *drm_dev, struct drm_file *file)
  1114. {
  1115. struct drm_exynos_file_private *file_priv = file->driver_priv;
  1116. struct exynos_drm_private *priv = drm_dev->dev_private;
  1117. struct g2d_data *g2d;
  1118. struct g2d_cmdlist_node *node, *n;
  1119. if (!priv->g2d_dev)
  1120. return;
  1121. g2d = dev_get_drvdata(priv->g2d_dev);
  1122. /* Remove the runqueue nodes that belong to us. */
  1123. mutex_lock(&g2d->runqueue_mutex);
  1124. g2d_remove_runqueue_nodes(g2d, file);
  1125. mutex_unlock(&g2d->runqueue_mutex);
  1126. /*
  1127. * Wait for the runqueue worker to finish its current node.
  1128. * After this the engine should no longer be accessing any
  1129. * memory belonging to us.
  1130. */
  1131. g2d_wait_finish(g2d, file);
  1132. /*
  1133. * Even after the engine is idle, there might still be stale cmdlists
  1134. * (i.e. cmdlisst which we submitted but never executed) around, with
  1135. * their corresponding GEM/userptr buffers.
  1136. * Properly unmap these buffers here.
  1137. */
  1138. mutex_lock(&g2d->cmdlist_mutex);
  1139. list_for_each_entry_safe(node, n, &file_priv->inuse_cmdlist, list) {
  1140. g2d_unmap_cmdlist_gem(g2d, node, file);
  1141. list_move_tail(&node->list, &g2d->free_cmdlist);
  1142. }
  1143. mutex_unlock(&g2d->cmdlist_mutex);
  1144. /* release all g2d_userptr in pool. */
  1145. g2d_userptr_free_all(g2d, file);
  1146. }
  1147. static int g2d_bind(struct device *dev, struct device *master, void *data)
  1148. {
  1149. struct g2d_data *g2d = dev_get_drvdata(dev);
  1150. struct drm_device *drm_dev = data;
  1151. struct exynos_drm_private *priv = drm_dev->dev_private;
  1152. int ret;
  1153. g2d->drm_dev = drm_dev;
  1154. /* allocate dma-aware cmdlist buffer. */
  1155. ret = g2d_init_cmdlist(g2d);
  1156. if (ret < 0) {
  1157. dev_err(dev, "cmdlist init failed\n");
  1158. return ret;
  1159. }
  1160. ret = exynos_drm_register_dma(drm_dev, dev, &g2d->dma_priv);
  1161. if (ret < 0) {
  1162. dev_err(dev, "failed to enable iommu.\n");
  1163. g2d_fini_cmdlist(g2d);
  1164. return ret;
  1165. }
  1166. priv->g2d_dev = dev;
  1167. dev_info(dev, "The Exynos G2D (ver %d.%d) successfully registered.\n",
  1168. G2D_HW_MAJOR_VER, G2D_HW_MINOR_VER);
  1169. return 0;
  1170. }
  1171. static void g2d_unbind(struct device *dev, struct device *master, void *data)
  1172. {
  1173. struct g2d_data *g2d = dev_get_drvdata(dev);
  1174. struct drm_device *drm_dev = data;
  1175. struct exynos_drm_private *priv = drm_dev->dev_private;
  1176. /* Suspend operation and wait for engine idle. */
  1177. set_bit(G2D_BIT_SUSPEND_RUNQUEUE, &g2d->flags);
  1178. g2d_wait_finish(g2d, NULL);
  1179. priv->g2d_dev = NULL;
  1180. cancel_work_sync(&g2d->runqueue_work);
  1181. exynos_drm_unregister_dma(g2d->drm_dev, dev, &g2d->dma_priv);
  1182. }
  1183. static const struct component_ops g2d_component_ops = {
  1184. .bind = g2d_bind,
  1185. .unbind = g2d_unbind,
  1186. };
  1187. static int g2d_probe(struct platform_device *pdev)
  1188. {
  1189. struct device *dev = &pdev->dev;
  1190. struct g2d_data *g2d;
  1191. int ret;
  1192. g2d = devm_kzalloc(dev, sizeof(*g2d), GFP_KERNEL);
  1193. if (!g2d)
  1194. return -ENOMEM;
  1195. g2d->runqueue_slab = kmem_cache_create("g2d_runqueue_slab",
  1196. sizeof(struct g2d_runqueue_node), 0, 0, NULL);
  1197. if (!g2d->runqueue_slab)
  1198. return -ENOMEM;
  1199. g2d->dev = dev;
  1200. g2d->g2d_workq = create_singlethread_workqueue("g2d");
  1201. if (!g2d->g2d_workq) {
  1202. dev_err(dev, "failed to create workqueue\n");
  1203. ret = -EINVAL;
  1204. goto err_destroy_slab;
  1205. }
  1206. INIT_WORK(&g2d->runqueue_work, g2d_runqueue_worker);
  1207. INIT_LIST_HEAD(&g2d->free_cmdlist);
  1208. INIT_LIST_HEAD(&g2d->runqueue);
  1209. mutex_init(&g2d->cmdlist_mutex);
  1210. mutex_init(&g2d->runqueue_mutex);
  1211. g2d->gate_clk = devm_clk_get(dev, "fimg2d");
  1212. if (IS_ERR(g2d->gate_clk)) {
  1213. dev_err(dev, "failed to get gate clock\n");
  1214. ret = PTR_ERR(g2d->gate_clk);
  1215. goto err_destroy_workqueue;
  1216. }
  1217. pm_runtime_use_autosuspend(dev);
  1218. pm_runtime_set_autosuspend_delay(dev, 2000);
  1219. pm_runtime_enable(dev);
  1220. clear_bit(G2D_BIT_SUSPEND_RUNQUEUE, &g2d->flags);
  1221. clear_bit(G2D_BIT_ENGINE_BUSY, &g2d->flags);
  1222. g2d->regs = devm_platform_ioremap_resource(pdev, 0);
  1223. if (IS_ERR(g2d->regs)) {
  1224. ret = PTR_ERR(g2d->regs);
  1225. goto err_put_clk;
  1226. }
  1227. g2d->irq = platform_get_irq(pdev, 0);
  1228. if (g2d->irq < 0) {
  1229. ret = g2d->irq;
  1230. goto err_put_clk;
  1231. }
  1232. ret = devm_request_irq(dev, g2d->irq, g2d_irq_handler, 0,
  1233. "drm_g2d", g2d);
  1234. if (ret < 0) {
  1235. dev_err(dev, "irq request failed\n");
  1236. goto err_put_clk;
  1237. }
  1238. g2d->max_pool = MAX_POOL;
  1239. platform_set_drvdata(pdev, g2d);
  1240. ret = component_add(dev, &g2d_component_ops);
  1241. if (ret < 0) {
  1242. dev_err(dev, "failed to register drm g2d device\n");
  1243. goto err_put_clk;
  1244. }
  1245. return 0;
  1246. err_put_clk:
  1247. pm_runtime_disable(dev);
  1248. err_destroy_workqueue:
  1249. destroy_workqueue(g2d->g2d_workq);
  1250. err_destroy_slab:
  1251. kmem_cache_destroy(g2d->runqueue_slab);
  1252. return ret;
  1253. }
  1254. static void g2d_remove(struct platform_device *pdev)
  1255. {
  1256. struct g2d_data *g2d = platform_get_drvdata(pdev);
  1257. component_del(&pdev->dev, &g2d_component_ops);
  1258. /* There should be no locking needed here. */
  1259. g2d_remove_runqueue_nodes(g2d, NULL);
  1260. pm_runtime_dont_use_autosuspend(&pdev->dev);
  1261. pm_runtime_disable(&pdev->dev);
  1262. g2d_fini_cmdlist(g2d);
  1263. destroy_workqueue(g2d->g2d_workq);
  1264. kmem_cache_destroy(g2d->runqueue_slab);
  1265. }
  1266. static int g2d_suspend(struct device *dev)
  1267. {
  1268. struct g2d_data *g2d = dev_get_drvdata(dev);
  1269. /*
  1270. * Suspend the runqueue worker operation and wait until the G2D
  1271. * engine is idle.
  1272. */
  1273. set_bit(G2D_BIT_SUSPEND_RUNQUEUE, &g2d->flags);
  1274. g2d_wait_finish(g2d, NULL);
  1275. flush_work(&g2d->runqueue_work);
  1276. return 0;
  1277. }
  1278. static int g2d_resume(struct device *dev)
  1279. {
  1280. struct g2d_data *g2d = dev_get_drvdata(dev);
  1281. clear_bit(G2D_BIT_SUSPEND_RUNQUEUE, &g2d->flags);
  1282. queue_work(g2d->g2d_workq, &g2d->runqueue_work);
  1283. return 0;
  1284. }
  1285. static int g2d_runtime_suspend(struct device *dev)
  1286. {
  1287. struct g2d_data *g2d = dev_get_drvdata(dev);
  1288. clk_disable_unprepare(g2d->gate_clk);
  1289. return 0;
  1290. }
  1291. static int g2d_runtime_resume(struct device *dev)
  1292. {
  1293. struct g2d_data *g2d = dev_get_drvdata(dev);
  1294. int ret;
  1295. ret = clk_prepare_enable(g2d->gate_clk);
  1296. if (ret < 0)
  1297. dev_warn(dev, "failed to enable clock.\n");
  1298. return ret;
  1299. }
  1300. static const struct dev_pm_ops g2d_pm_ops = {
  1301. SYSTEM_SLEEP_PM_OPS(g2d_suspend, g2d_resume)
  1302. RUNTIME_PM_OPS(g2d_runtime_suspend, g2d_runtime_resume, NULL)
  1303. };
  1304. static const struct of_device_id exynos_g2d_match[] = {
  1305. { .compatible = "samsung,exynos5250-g2d" },
  1306. { .compatible = "samsung,exynos4212-g2d" },
  1307. {},
  1308. };
  1309. MODULE_DEVICE_TABLE(of, exynos_g2d_match);
  1310. struct platform_driver g2d_driver = {
  1311. .probe = g2d_probe,
  1312. .remove_new = g2d_remove,
  1313. .driver = {
  1314. .name = "exynos-drm-g2d",
  1315. .pm = pm_ptr(&g2d_pm_ops),
  1316. .of_match_table = exynos_g2d_match,
  1317. },
  1318. };