fsl_dcu_drm_plane.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. *
  5. * Freescale DCU drm device driver
  6. */
  7. #include <linux/regmap.h>
  8. #include <drm/drm_atomic.h>
  9. #include <drm/drm_atomic_helper.h>
  10. #include <drm/drm_crtc.h>
  11. #include <drm/drm_fb_dma_helper.h>
  12. #include <drm/drm_fourcc.h>
  13. #include <drm/drm_framebuffer.h>
  14. #include <drm/drm_gem_dma_helper.h>
  15. #include <drm/drm_plane_helper.h>
  16. #include <drm/drm_probe_helper.h>
  17. #include "fsl_dcu_drm_drv.h"
  18. #include "fsl_dcu_drm_plane.h"
  19. static int fsl_dcu_drm_plane_index(struct drm_plane *plane)
  20. {
  21. struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
  22. unsigned int total_layer = fsl_dev->soc->total_layer;
  23. unsigned int index;
  24. index = drm_plane_index(plane);
  25. if (index < total_layer)
  26. return total_layer - index - 1;
  27. dev_err(fsl_dev->dev, "No more layer left\n");
  28. return -EINVAL;
  29. }
  30. static int fsl_dcu_drm_plane_atomic_check(struct drm_plane *plane,
  31. struct drm_atomic_state *state)
  32. {
  33. struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
  34. plane);
  35. struct drm_framebuffer *fb = new_plane_state->fb;
  36. if (!new_plane_state->fb || !new_plane_state->crtc)
  37. return 0;
  38. switch (fb->format->format) {
  39. case DRM_FORMAT_RGB565:
  40. case DRM_FORMAT_RGB888:
  41. case DRM_FORMAT_XRGB8888:
  42. case DRM_FORMAT_ARGB8888:
  43. case DRM_FORMAT_XRGB4444:
  44. case DRM_FORMAT_ARGB4444:
  45. case DRM_FORMAT_XRGB1555:
  46. case DRM_FORMAT_ARGB1555:
  47. case DRM_FORMAT_YUV422:
  48. return 0;
  49. default:
  50. return -EINVAL;
  51. }
  52. }
  53. static void fsl_dcu_drm_plane_atomic_disable(struct drm_plane *plane,
  54. struct drm_atomic_state *state)
  55. {
  56. struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
  57. unsigned int value;
  58. int index;
  59. index = fsl_dcu_drm_plane_index(plane);
  60. if (index < 0)
  61. return;
  62. regmap_read(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), &value);
  63. value &= ~DCU_LAYER_EN;
  64. regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), value);
  65. }
  66. static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane,
  67. struct drm_atomic_state *state)
  68. {
  69. struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
  70. struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
  71. plane);
  72. struct drm_framebuffer *fb = plane->state->fb;
  73. struct drm_gem_dma_object *gem;
  74. unsigned int alpha = DCU_LAYER_AB_NONE, bpp;
  75. int index;
  76. if (!fb)
  77. return;
  78. index = fsl_dcu_drm_plane_index(plane);
  79. if (index < 0)
  80. return;
  81. gem = drm_fb_dma_get_gem_obj(fb, 0);
  82. switch (fb->format->format) {
  83. case DRM_FORMAT_RGB565:
  84. bpp = FSL_DCU_RGB565;
  85. break;
  86. case DRM_FORMAT_RGB888:
  87. bpp = FSL_DCU_RGB888;
  88. break;
  89. case DRM_FORMAT_ARGB8888:
  90. alpha = DCU_LAYER_AB_WHOLE_FRAME;
  91. fallthrough;
  92. case DRM_FORMAT_XRGB8888:
  93. bpp = FSL_DCU_ARGB8888;
  94. break;
  95. case DRM_FORMAT_ARGB4444:
  96. alpha = DCU_LAYER_AB_WHOLE_FRAME;
  97. fallthrough;
  98. case DRM_FORMAT_XRGB4444:
  99. bpp = FSL_DCU_ARGB4444;
  100. break;
  101. case DRM_FORMAT_ARGB1555:
  102. alpha = DCU_LAYER_AB_WHOLE_FRAME;
  103. fallthrough;
  104. case DRM_FORMAT_XRGB1555:
  105. bpp = FSL_DCU_ARGB1555;
  106. break;
  107. case DRM_FORMAT_YUV422:
  108. bpp = FSL_DCU_YUV422;
  109. break;
  110. default:
  111. return;
  112. }
  113. regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 1),
  114. DCU_LAYER_HEIGHT(new_state->crtc_h) |
  115. DCU_LAYER_WIDTH(new_state->crtc_w));
  116. regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 2),
  117. DCU_LAYER_POSY(new_state->crtc_y) |
  118. DCU_LAYER_POSX(new_state->crtc_x));
  119. regmap_write(fsl_dev->regmap,
  120. DCU_CTRLDESCLN(index, 3), gem->dma_addr);
  121. regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4),
  122. DCU_LAYER_EN |
  123. DCU_LAYER_TRANS(0xff) |
  124. DCU_LAYER_BPP(bpp) |
  125. alpha);
  126. regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 5),
  127. DCU_LAYER_CKMAX_R(0xFF) |
  128. DCU_LAYER_CKMAX_G(0xFF) |
  129. DCU_LAYER_CKMAX_B(0xFF));
  130. regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 6),
  131. DCU_LAYER_CKMIN_R(0) |
  132. DCU_LAYER_CKMIN_G(0) |
  133. DCU_LAYER_CKMIN_B(0));
  134. regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 7), 0);
  135. regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 8),
  136. DCU_LAYER_FG_FCOLOR(0));
  137. regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 9),
  138. DCU_LAYER_BG_BCOLOR(0));
  139. if (!strcmp(fsl_dev->soc->name, "ls1021a")) {
  140. regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 10),
  141. DCU_LAYER_POST_SKIP(0) |
  142. DCU_LAYER_PRE_SKIP(0));
  143. }
  144. return;
  145. }
  146. static const struct drm_plane_helper_funcs fsl_dcu_drm_plane_helper_funcs = {
  147. .atomic_check = fsl_dcu_drm_plane_atomic_check,
  148. .atomic_disable = fsl_dcu_drm_plane_atomic_disable,
  149. .atomic_update = fsl_dcu_drm_plane_atomic_update,
  150. };
  151. static const struct drm_plane_funcs fsl_dcu_drm_plane_funcs = {
  152. .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
  153. .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
  154. .destroy = drm_plane_helper_destroy,
  155. .disable_plane = drm_atomic_helper_disable_plane,
  156. .reset = drm_atomic_helper_plane_reset,
  157. .update_plane = drm_atomic_helper_update_plane,
  158. };
  159. static const u32 fsl_dcu_drm_plane_formats[] = {
  160. DRM_FORMAT_RGB565,
  161. DRM_FORMAT_RGB888,
  162. DRM_FORMAT_XRGB8888,
  163. DRM_FORMAT_ARGB8888,
  164. DRM_FORMAT_XRGB4444,
  165. DRM_FORMAT_ARGB4444,
  166. DRM_FORMAT_XRGB1555,
  167. DRM_FORMAT_ARGB1555,
  168. DRM_FORMAT_YUV422,
  169. };
  170. void fsl_dcu_drm_init_planes(struct drm_device *dev)
  171. {
  172. struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  173. int i, j;
  174. for (i = 0; i < fsl_dev->soc->total_layer; i++) {
  175. for (j = 1; j <= fsl_dev->soc->layer_regs; j++)
  176. regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
  177. }
  178. }
  179. struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device *dev)
  180. {
  181. struct drm_plane *primary;
  182. int ret;
  183. primary = kzalloc(sizeof(*primary), GFP_KERNEL);
  184. if (!primary) {
  185. DRM_DEBUG_KMS("Failed to allocate primary plane\n");
  186. return NULL;
  187. }
  188. /* possible_crtc's will be filled in later by crtc_init */
  189. ret = drm_universal_plane_init(dev, primary, 0,
  190. &fsl_dcu_drm_plane_funcs,
  191. fsl_dcu_drm_plane_formats,
  192. ARRAY_SIZE(fsl_dcu_drm_plane_formats),
  193. NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
  194. if (ret) {
  195. kfree(primary);
  196. primary = NULL;
  197. }
  198. drm_plane_helper_add(primary, &fsl_dcu_drm_plane_helper_funcs);
  199. return primary;
  200. }