psb_drv.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /**************************************************************************
  3. * Copyright (c) 2007-2011, Intel Corporation.
  4. * All Rights Reserved.
  5. * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
  6. * All Rights Reserved.
  7. *
  8. **************************************************************************/
  9. #include <linux/aperture.h>
  10. #include <linux/cpu.h>
  11. #include <linux/module.h>
  12. #include <linux/notifier.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/delay.h>
  16. #include <asm/set_memory.h>
  17. #include <acpi/video.h>
  18. #include <drm/drm.h>
  19. #include <drm/drm_drv.h>
  20. #include <drm/drm_file.h>
  21. #include <drm/drm_ioctl.h>
  22. #include <drm/drm_pciids.h>
  23. #include <drm/drm_vblank.h>
  24. #include "framebuffer.h"
  25. #include "gem.h"
  26. #include "intel_bios.h"
  27. #include "mid_bios.h"
  28. #include "power.h"
  29. #include "psb_drv.h"
  30. #include "psb_intel_reg.h"
  31. #include "psb_irq.h"
  32. #include "psb_reg.h"
  33. static const struct drm_driver driver;
  34. static int psb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  35. /*
  36. * The table below contains a mapping of the PCI vendor ID and the PCI Device ID
  37. * to the different groups of PowerVR 5-series chip designs
  38. *
  39. * 0x8086 = Intel Corporation
  40. *
  41. * PowerVR SGX535 - Poulsbo - Intel GMA 500, Intel Atom Z5xx
  42. * PowerVR SGX535 - Moorestown - Intel GMA 600
  43. * PowerVR SGX535 - Oaktrail - Intel GMA 600, Intel Atom Z6xx, E6xx
  44. * PowerVR SGX545 - Cedartrail - Intel GMA 3600, Intel Atom D2500, N2600
  45. * PowerVR SGX545 - Cedartrail - Intel GMA 3650, Intel Atom D2550, D2700,
  46. * N2800
  47. */
  48. static const struct pci_device_id pciidlist[] = {
  49. /* Poulsbo */
  50. { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
  51. { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
  52. /* Oak Trail */
  53. { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
  54. { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
  55. { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
  56. { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
  57. { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
  58. { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
  59. { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
  60. { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
  61. { 0x8086, 0x4108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops },
  62. /* Cedar Trail */
  63. { 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  64. { 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  65. { 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  66. { 0x8086, 0x0be3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  67. { 0x8086, 0x0be4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  68. { 0x8086, 0x0be5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  69. { 0x8086, 0x0be6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  70. { 0x8086, 0x0be7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  71. { 0x8086, 0x0be8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  72. { 0x8086, 0x0be9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  73. { 0x8086, 0x0bea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  74. { 0x8086, 0x0beb, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  75. { 0x8086, 0x0bec, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  76. { 0x8086, 0x0bed, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  77. { 0x8086, 0x0bee, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  78. { 0x8086, 0x0bef, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops },
  79. { 0, }
  80. };
  81. MODULE_DEVICE_TABLE(pci, pciidlist);
  82. /*
  83. * Standard IOCTLs.
  84. */
  85. static const struct drm_ioctl_desc psb_ioctls[] = {
  86. };
  87. /**
  88. * psb_spank - reset the 2D engine
  89. * @dev_priv: our PSB DRM device
  90. *
  91. * Soft reset the graphics engine and then reload the necessary registers.
  92. */
  93. static void psb_spank(struct drm_psb_private *dev_priv)
  94. {
  95. PSB_WSGX32(_PSB_CS_RESET_BIF_RESET | _PSB_CS_RESET_DPM_RESET |
  96. _PSB_CS_RESET_TA_RESET | _PSB_CS_RESET_USE_RESET |
  97. _PSB_CS_RESET_ISP_RESET | _PSB_CS_RESET_TSP_RESET |
  98. _PSB_CS_RESET_TWOD_RESET, PSB_CR_SOFT_RESET);
  99. PSB_RSGX32(PSB_CR_SOFT_RESET);
  100. msleep(1);
  101. PSB_WSGX32(0, PSB_CR_SOFT_RESET);
  102. wmb();
  103. PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_CB_CTRL_CLEAR_FAULT,
  104. PSB_CR_BIF_CTRL);
  105. wmb();
  106. (void) PSB_RSGX32(PSB_CR_BIF_CTRL);
  107. msleep(1);
  108. PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) & ~_PSB_CB_CTRL_CLEAR_FAULT,
  109. PSB_CR_BIF_CTRL);
  110. (void) PSB_RSGX32(PSB_CR_BIF_CTRL);
  111. PSB_WSGX32(dev_priv->gtt.gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
  112. }
  113. static int psb_do_init(struct drm_device *dev)
  114. {
  115. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  116. struct psb_gtt *pg = &dev_priv->gtt;
  117. uint32_t stolen_gtt;
  118. if (pg->mmu_gatt_start & 0x0FFFFFFF) {
  119. dev_err(dev->dev, "Gatt must be 256M aligned. This is a bug.\n");
  120. return -EINVAL;
  121. }
  122. stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
  123. stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
  124. stolen_gtt = (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
  125. dev_priv->gatt_free_offset = pg->mmu_gatt_start +
  126. (stolen_gtt << PAGE_SHIFT) * 1024;
  127. spin_lock_init(&dev_priv->irqmask_lock);
  128. PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
  129. PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
  130. PSB_RSGX32(PSB_CR_BIF_BANK1);
  131. /* Do not bypass any MMU access, let them pagefault instead */
  132. PSB_WSGX32((PSB_RSGX32(PSB_CR_BIF_CTRL) & ~_PSB_MMU_ER_MASK),
  133. PSB_CR_BIF_CTRL);
  134. PSB_RSGX32(PSB_CR_BIF_CTRL);
  135. psb_spank(dev_priv);
  136. /* mmu_gatt ?? */
  137. PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
  138. PSB_RSGX32(PSB_CR_BIF_TWOD_REQ_BASE); /* Post */
  139. return 0;
  140. }
  141. static void psb_driver_unload(struct drm_device *dev)
  142. {
  143. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  144. /* TODO: Kill vblank etc here */
  145. gma_backlight_exit(dev);
  146. psb_modeset_cleanup(dev);
  147. gma_irq_uninstall(dev);
  148. if (dev_priv->ops->chip_teardown)
  149. dev_priv->ops->chip_teardown(dev);
  150. psb_intel_opregion_fini(dev);
  151. if (dev_priv->pf_pd) {
  152. psb_mmu_free_pagedir(dev_priv->pf_pd);
  153. dev_priv->pf_pd = NULL;
  154. }
  155. if (dev_priv->mmu) {
  156. struct psb_gtt *pg = &dev_priv->gtt;
  157. psb_mmu_remove_pfn_sequence(
  158. psb_mmu_get_default_pd
  159. (dev_priv->mmu),
  160. pg->mmu_gatt_start,
  161. dev_priv->vram_stolen_size >> PAGE_SHIFT);
  162. psb_mmu_driver_takedown(dev_priv->mmu);
  163. dev_priv->mmu = NULL;
  164. }
  165. psb_gem_mm_fini(dev);
  166. psb_gtt_fini(dev);
  167. if (dev_priv->scratch_page) {
  168. set_pages_wb(dev_priv->scratch_page, 1);
  169. __free_page(dev_priv->scratch_page);
  170. dev_priv->scratch_page = NULL;
  171. }
  172. if (dev_priv->vdc_reg) {
  173. iounmap(dev_priv->vdc_reg);
  174. dev_priv->vdc_reg = NULL;
  175. }
  176. if (dev_priv->sgx_reg) {
  177. iounmap(dev_priv->sgx_reg);
  178. dev_priv->sgx_reg = NULL;
  179. }
  180. if (dev_priv->aux_reg) {
  181. iounmap(dev_priv->aux_reg);
  182. dev_priv->aux_reg = NULL;
  183. }
  184. pci_dev_put(dev_priv->aux_pdev);
  185. pci_dev_put(dev_priv->lpc_pdev);
  186. /* Destroy VBT data */
  187. psb_intel_destroy_bios(dev);
  188. gma_power_uninit(dev);
  189. }
  190. static void psb_device_release(void *data)
  191. {
  192. struct drm_device *dev = data;
  193. psb_driver_unload(dev);
  194. }
  195. static int psb_driver_load(struct drm_device *dev, unsigned long flags)
  196. {
  197. struct pci_dev *pdev = to_pci_dev(dev->dev);
  198. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  199. unsigned long resource_start, resource_len;
  200. unsigned long irqflags;
  201. struct drm_connector_list_iter conn_iter;
  202. struct drm_connector *connector;
  203. struct gma_encoder *gma_encoder;
  204. struct psb_gtt *pg;
  205. int ret = -ENOMEM;
  206. /* initializing driver private data */
  207. dev_priv->ops = (struct psb_ops *)flags;
  208. pg = &dev_priv->gtt;
  209. pci_set_master(pdev);
  210. dev_priv->num_pipe = dev_priv->ops->pipes;
  211. resource_start = pci_resource_start(pdev, PSB_MMIO_RESOURCE);
  212. dev_priv->vdc_reg =
  213. ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
  214. if (!dev_priv->vdc_reg)
  215. goto out_err;
  216. dev_priv->sgx_reg = ioremap(resource_start + dev_priv->ops->sgx_offset,
  217. PSB_SGX_SIZE);
  218. if (!dev_priv->sgx_reg)
  219. goto out_err;
  220. if (IS_MRST(dev)) {
  221. int domain = pci_domain_nr(pdev->bus);
  222. dev_priv->aux_pdev =
  223. pci_get_domain_bus_and_slot(domain, 0,
  224. PCI_DEVFN(3, 0));
  225. if (dev_priv->aux_pdev) {
  226. resource_start = pci_resource_start(dev_priv->aux_pdev,
  227. PSB_AUX_RESOURCE);
  228. resource_len = pci_resource_len(dev_priv->aux_pdev,
  229. PSB_AUX_RESOURCE);
  230. dev_priv->aux_reg = ioremap(resource_start,
  231. resource_len);
  232. if (!dev_priv->aux_reg)
  233. goto out_err;
  234. DRM_DEBUG_KMS("Found aux vdc");
  235. } else {
  236. /* Couldn't find the aux vdc so map to primary vdc */
  237. dev_priv->aux_reg = dev_priv->vdc_reg;
  238. DRM_DEBUG_KMS("Couldn't find aux pci device");
  239. }
  240. dev_priv->gmbus_reg = dev_priv->aux_reg;
  241. dev_priv->lpc_pdev =
  242. pci_get_domain_bus_and_slot(domain, 0,
  243. PCI_DEVFN(31, 0));
  244. if (dev_priv->lpc_pdev) {
  245. pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA,
  246. &dev_priv->lpc_gpio_base);
  247. pci_write_config_dword(dev_priv->lpc_pdev, PSB_LPC_GBA,
  248. (u32)dev_priv->lpc_gpio_base | (1L<<31));
  249. pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA,
  250. &dev_priv->lpc_gpio_base);
  251. dev_priv->lpc_gpio_base &= 0xffc0;
  252. if (dev_priv->lpc_gpio_base)
  253. DRM_DEBUG_KMS("Found LPC GPIO at 0x%04x\n",
  254. dev_priv->lpc_gpio_base);
  255. else {
  256. pci_dev_put(dev_priv->lpc_pdev);
  257. dev_priv->lpc_pdev = NULL;
  258. }
  259. }
  260. } else {
  261. dev_priv->gmbus_reg = dev_priv->vdc_reg;
  262. }
  263. psb_intel_opregion_setup(dev);
  264. ret = dev_priv->ops->chip_setup(dev);
  265. if (ret)
  266. goto out_err;
  267. /* Init OSPM support */
  268. gma_power_init(dev);
  269. ret = -ENOMEM;
  270. dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
  271. if (!dev_priv->scratch_page)
  272. goto out_err;
  273. set_pages_uc(dev_priv->scratch_page, 1);
  274. ret = psb_gtt_init(dev);
  275. if (ret)
  276. goto out_err;
  277. ret = psb_gem_mm_init(dev);
  278. if (ret)
  279. goto out_err;
  280. ret = -ENOMEM;
  281. dev_priv->mmu = psb_mmu_driver_init(dev, 1, 0, NULL);
  282. if (!dev_priv->mmu)
  283. goto out_err;
  284. dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
  285. if (!dev_priv->pf_pd)
  286. goto out_err;
  287. ret = psb_do_init(dev);
  288. if (ret)
  289. return ret;
  290. /* Add stolen memory to SGX MMU */
  291. ret = psb_mmu_insert_pfn_sequence(psb_mmu_get_default_pd(dev_priv->mmu),
  292. dev_priv->stolen_base >> PAGE_SHIFT,
  293. pg->gatt_start,
  294. pg->stolen_size >> PAGE_SHIFT, 0);
  295. psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
  296. psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
  297. PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
  298. PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
  299. acpi_video_register();
  300. /* Setup vertical blanking handling */
  301. ret = drm_vblank_init(dev, dev_priv->num_pipe);
  302. if (ret)
  303. goto out_err;
  304. /*
  305. * Install interrupt handlers prior to powering off SGX or else we will
  306. * crash.
  307. */
  308. dev_priv->vdc_irq_mask = 0;
  309. dev_priv->pipestat[0] = 0;
  310. dev_priv->pipestat[1] = 0;
  311. dev_priv->pipestat[2] = 0;
  312. spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
  313. PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
  314. PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
  315. PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
  316. spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
  317. gma_irq_install(dev);
  318. dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
  319. psb_modeset_init(dev);
  320. drm_kms_helper_poll_init(dev);
  321. /* Only add backlight support if we have LVDS or MIPI output */
  322. drm_connector_list_iter_begin(dev, &conn_iter);
  323. drm_for_each_connector_iter(connector, &conn_iter) {
  324. gma_encoder = gma_attached_encoder(connector);
  325. if (gma_encoder->type == INTEL_OUTPUT_LVDS ||
  326. gma_encoder->type == INTEL_OUTPUT_MIPI) {
  327. ret = gma_backlight_init(dev);
  328. if (ret == 0)
  329. acpi_video_register_backlight();
  330. break;
  331. }
  332. }
  333. drm_connector_list_iter_end(&conn_iter);
  334. if (ret)
  335. return ret;
  336. psb_intel_opregion_enable_asle(dev);
  337. return devm_add_action_or_reset(dev->dev, psb_device_release, dev);
  338. out_err:
  339. psb_driver_unload(dev);
  340. return ret;
  341. }
  342. /*
  343. * Hardware for gma500 is a hybrid device, which both acts as a PCI
  344. * device (for legacy vga functionality) but also more like an
  345. * integrated display on a SoC where the framebuffer simply
  346. * resides in main memory and not in a special PCI bar (that
  347. * internally redirects to a stolen range of main memory) like all
  348. * other integrated PCI display devices implement it.
  349. *
  350. * To catch all cases we need to remove conflicting firmware devices
  351. * for the stolen system memory and for the VGA functionality. As we
  352. * currently cannot easily find the framebuffer's location in stolen
  353. * memory, we remove all framebuffers here.
  354. *
  355. * TODO: Refactor psb_driver_load() to map vdc_reg earlier. Then
  356. * we might be able to read the framebuffer range from the
  357. * device.
  358. */
  359. static int gma_remove_conflicting_framebuffers(struct pci_dev *pdev,
  360. const struct drm_driver *req_driver)
  361. {
  362. resource_size_t base = 0;
  363. resource_size_t size = U32_MAX; /* 4 GiB HW limit */
  364. const char *name = req_driver->name;
  365. int ret;
  366. ret = aperture_remove_conflicting_devices(base, size, name);
  367. if (ret)
  368. return ret;
  369. return __aperture_remove_legacy_vga_devices(pdev);
  370. }
  371. static int psb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  372. {
  373. struct drm_psb_private *dev_priv;
  374. struct drm_device *dev;
  375. int ret;
  376. ret = gma_remove_conflicting_framebuffers(pdev, &driver);
  377. if (ret)
  378. return ret;
  379. ret = pcim_enable_device(pdev);
  380. if (ret)
  381. return ret;
  382. dev_priv = devm_drm_dev_alloc(&pdev->dev, &driver, struct drm_psb_private, dev);
  383. if (IS_ERR(dev_priv))
  384. return PTR_ERR(dev_priv);
  385. dev = &dev_priv->dev;
  386. pci_set_drvdata(pdev, dev);
  387. ret = psb_driver_load(dev, ent->driver_data);
  388. if (ret)
  389. return ret;
  390. ret = drm_dev_register(dev, ent->driver_data);
  391. if (ret)
  392. return ret;
  393. psb_fbdev_setup(dev_priv);
  394. return 0;
  395. }
  396. static void psb_pci_remove(struct pci_dev *pdev)
  397. {
  398. struct drm_device *dev = pci_get_drvdata(pdev);
  399. drm_dev_unregister(dev);
  400. }
  401. static DEFINE_RUNTIME_DEV_PM_OPS(psb_pm_ops, gma_power_suspend, gma_power_resume, NULL);
  402. static const struct file_operations psb_gem_fops = {
  403. .owner = THIS_MODULE,
  404. .open = drm_open,
  405. .release = drm_release,
  406. .unlocked_ioctl = drm_ioctl,
  407. .compat_ioctl = drm_compat_ioctl,
  408. .mmap = drm_gem_mmap,
  409. .poll = drm_poll,
  410. .read = drm_read,
  411. .fop_flags = FOP_UNSIGNED_OFFSET,
  412. };
  413. static const struct drm_driver driver = {
  414. .driver_features = DRIVER_MODESET | DRIVER_GEM,
  415. .num_ioctls = ARRAY_SIZE(psb_ioctls),
  416. .dumb_create = psb_gem_dumb_create,
  417. .ioctls = psb_ioctls,
  418. .fops = &psb_gem_fops,
  419. .name = DRIVER_NAME,
  420. .desc = DRIVER_DESC,
  421. .date = DRIVER_DATE,
  422. .major = DRIVER_MAJOR,
  423. .minor = DRIVER_MINOR,
  424. .patchlevel = DRIVER_PATCHLEVEL
  425. };
  426. static struct pci_driver psb_pci_driver = {
  427. .name = DRIVER_NAME,
  428. .id_table = pciidlist,
  429. .probe = psb_pci_probe,
  430. .remove = psb_pci_remove,
  431. .driver.pm = &psb_pm_ops,
  432. };
  433. static int __init psb_init(void)
  434. {
  435. if (drm_firmware_drivers_only())
  436. return -ENODEV;
  437. return pci_register_driver(&psb_pci_driver);
  438. }
  439. static void __exit psb_exit(void)
  440. {
  441. pci_unregister_driver(&psb_pci_driver);
  442. }
  443. late_initcall(psb_init);
  444. module_exit(psb_exit);
  445. MODULE_AUTHOR(DRIVER_AUTHOR);
  446. MODULE_DESCRIPTION(DRIVER_DESC);
  447. MODULE_LICENSE("GPL");