psb_intel_lvds.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright © 2006-2007 Intel Corporation
  4. *
  5. * Authors:
  6. * Eric Anholt <eric@anholt.net>
  7. * Dave Airlie <airlied@linux.ie>
  8. * Jesse Barnes <jesse.barnes@intel.com>
  9. */
  10. #include <linux/i2c.h>
  11. #include <linux/pm_runtime.h>
  12. #include <drm/drm_crtc_helper.h>
  13. #include <drm/drm_modeset_helper_vtables.h>
  14. #include <drm/drm_simple_kms_helper.h>
  15. #include "intel_bios.h"
  16. #include "power.h"
  17. #include "psb_drv.h"
  18. #include "psb_intel_drv.h"
  19. #include "psb_intel_reg.h"
  20. /*
  21. * LVDS I2C backlight control macros
  22. */
  23. #define BRIGHTNESS_MAX_LEVEL 100
  24. #define BRIGHTNESS_MASK 0xFF
  25. #define BLC_I2C_TYPE 0x01
  26. #define BLC_PWM_TYPT 0x02
  27. #define BLC_POLARITY_NORMAL 0
  28. #define BLC_POLARITY_INVERSE 1
  29. #define PSB_BLC_MAX_PWM_REG_FREQ (0xFFFE)
  30. #define PSB_BLC_MIN_PWM_REG_FREQ (0x2)
  31. #define PSB_BLC_PWM_PRECISION_FACTOR (10)
  32. #define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
  33. #define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
  34. struct psb_intel_lvds_priv {
  35. /*
  36. * Saved LVDO output states
  37. */
  38. uint32_t savePP_ON;
  39. uint32_t savePP_OFF;
  40. uint32_t saveLVDS;
  41. uint32_t savePP_CONTROL;
  42. uint32_t savePP_CYCLE;
  43. uint32_t savePFIT_CONTROL;
  44. uint32_t savePFIT_PGM_RATIOS;
  45. uint32_t saveBLC_PWM_CTL;
  46. struct gma_i2c_chan *i2c_bus;
  47. };
  48. /*
  49. * Returns the maximum level of the backlight duty cycle field.
  50. */
  51. static u32 psb_intel_lvds_get_max_backlight(struct drm_device *dev)
  52. {
  53. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  54. u32 ret;
  55. if (gma_power_begin(dev, false)) {
  56. ret = REG_READ(BLC_PWM_CTL);
  57. gma_power_end(dev);
  58. } else /* Powered off, use the saved value */
  59. ret = dev_priv->regs.saveBLC_PWM_CTL;
  60. /* Top 15bits hold the frequency mask */
  61. ret = (ret & BACKLIGHT_MODULATION_FREQ_MASK) >>
  62. BACKLIGHT_MODULATION_FREQ_SHIFT;
  63. ret *= 2; /* Return a 16bit range as needed for setting */
  64. if (ret == 0)
  65. dev_err(dev->dev, "BL bug: Reg %08x save %08X\n",
  66. REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL);
  67. return ret;
  68. }
  69. /*
  70. * Set LVDS backlight level by I2C command
  71. *
  72. * FIXME: at some point we need to both track this for PM and also
  73. * disable runtime pm on MRST if the brightness is nil (ie blanked)
  74. */
  75. static int psb_lvds_i2c_set_brightness(struct drm_device *dev,
  76. unsigned int level)
  77. {
  78. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  79. struct gma_i2c_chan *lvds_i2c_bus = dev_priv->lvds_i2c_bus;
  80. u8 out_buf[2];
  81. unsigned int blc_i2c_brightness;
  82. struct i2c_msg msgs[] = {
  83. {
  84. .addr = lvds_i2c_bus->target_addr,
  85. .flags = 0,
  86. .len = 2,
  87. .buf = out_buf,
  88. }
  89. };
  90. blc_i2c_brightness = BRIGHTNESS_MASK & ((unsigned int)level *
  91. BRIGHTNESS_MASK /
  92. BRIGHTNESS_MAX_LEVEL);
  93. if (dev_priv->lvds_bl->pol == BLC_POLARITY_INVERSE)
  94. blc_i2c_brightness = BRIGHTNESS_MASK - blc_i2c_brightness;
  95. out_buf[0] = dev_priv->lvds_bl->brightnesscmd;
  96. out_buf[1] = (u8)blc_i2c_brightness;
  97. if (i2c_transfer(&lvds_i2c_bus->base, msgs, 1) == 1) {
  98. dev_dbg(dev->dev, "I2C set brightness.(command, value) (%d, %d)\n",
  99. dev_priv->lvds_bl->brightnesscmd,
  100. blc_i2c_brightness);
  101. return 0;
  102. }
  103. dev_err(dev->dev, "I2C transfer error\n");
  104. return -1;
  105. }
  106. static int psb_lvds_pwm_set_brightness(struct drm_device *dev, int level)
  107. {
  108. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  109. u32 max_pwm_blc;
  110. u32 blc_pwm_duty_cycle;
  111. max_pwm_blc = psb_intel_lvds_get_max_backlight(dev);
  112. /*BLC_PWM_CTL Should be initiated while backlight device init*/
  113. BUG_ON(max_pwm_blc == 0);
  114. blc_pwm_duty_cycle = level * max_pwm_blc / BRIGHTNESS_MAX_LEVEL;
  115. if (dev_priv->lvds_bl->pol == BLC_POLARITY_INVERSE)
  116. blc_pwm_duty_cycle = max_pwm_blc - blc_pwm_duty_cycle;
  117. blc_pwm_duty_cycle &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
  118. REG_WRITE(BLC_PWM_CTL,
  119. (max_pwm_blc << PSB_BACKLIGHT_PWM_CTL_SHIFT) |
  120. (blc_pwm_duty_cycle));
  121. dev_info(dev->dev, "Backlight lvds set brightness %08x\n",
  122. (max_pwm_blc << PSB_BACKLIGHT_PWM_CTL_SHIFT) |
  123. (blc_pwm_duty_cycle));
  124. return 0;
  125. }
  126. /*
  127. * Set LVDS backlight level either by I2C or PWM
  128. */
  129. void psb_intel_lvds_set_brightness(struct drm_device *dev, int level)
  130. {
  131. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  132. dev_dbg(dev->dev, "backlight level is %d\n", level);
  133. if (!dev_priv->lvds_bl) {
  134. dev_err(dev->dev, "NO LVDS backlight info\n");
  135. return;
  136. }
  137. if (dev_priv->lvds_bl->type == BLC_I2C_TYPE)
  138. psb_lvds_i2c_set_brightness(dev, level);
  139. else
  140. psb_lvds_pwm_set_brightness(dev, level);
  141. }
  142. /*
  143. * Sets the backlight level.
  144. *
  145. * level: backlight level, from 0 to psb_intel_lvds_get_max_backlight().
  146. */
  147. static void psb_intel_lvds_set_backlight(struct drm_device *dev, int level)
  148. {
  149. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  150. u32 blc_pwm_ctl;
  151. if (gma_power_begin(dev, false)) {
  152. blc_pwm_ctl = REG_READ(BLC_PWM_CTL);
  153. blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
  154. REG_WRITE(BLC_PWM_CTL,
  155. (blc_pwm_ctl |
  156. (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
  157. dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl |
  158. (level << BACKLIGHT_DUTY_CYCLE_SHIFT));
  159. gma_power_end(dev);
  160. } else {
  161. blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL &
  162. ~BACKLIGHT_DUTY_CYCLE_MASK;
  163. dev_priv->regs.saveBLC_PWM_CTL = (blc_pwm_ctl |
  164. (level << BACKLIGHT_DUTY_CYCLE_SHIFT));
  165. }
  166. }
  167. /*
  168. * Sets the power state for the panel.
  169. */
  170. static void psb_intel_lvds_set_power(struct drm_device *dev, bool on)
  171. {
  172. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  173. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  174. u32 pp_status;
  175. if (!gma_power_begin(dev, true)) {
  176. dev_err(dev->dev, "set power, chip off!\n");
  177. return;
  178. }
  179. if (on) {
  180. REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
  181. POWER_TARGET_ON);
  182. do {
  183. pp_status = REG_READ(PP_STATUS);
  184. } while ((pp_status & PP_ON) == 0);
  185. psb_intel_lvds_set_backlight(dev,
  186. mode_dev->backlight_duty_cycle);
  187. } else {
  188. psb_intel_lvds_set_backlight(dev, 0);
  189. REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
  190. ~POWER_TARGET_ON);
  191. do {
  192. pp_status = REG_READ(PP_STATUS);
  193. } while (pp_status & PP_ON);
  194. }
  195. gma_power_end(dev);
  196. }
  197. static void psb_intel_lvds_encoder_dpms(struct drm_encoder *encoder, int mode)
  198. {
  199. struct drm_device *dev = encoder->dev;
  200. if (mode == DRM_MODE_DPMS_ON)
  201. psb_intel_lvds_set_power(dev, true);
  202. else
  203. psb_intel_lvds_set_power(dev, false);
  204. /* XXX: We never power down the LVDS pairs. */
  205. }
  206. static void psb_intel_lvds_save(struct drm_connector *connector)
  207. {
  208. struct drm_device *dev = connector->dev;
  209. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  210. struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
  211. struct psb_intel_lvds_priv *lvds_priv =
  212. (struct psb_intel_lvds_priv *)gma_encoder->dev_priv;
  213. lvds_priv->savePP_ON = REG_READ(LVDSPP_ON);
  214. lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF);
  215. lvds_priv->saveLVDS = REG_READ(LVDS);
  216. lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL);
  217. lvds_priv->savePP_CYCLE = REG_READ(PP_CYCLE);
  218. /*lvds_priv->savePP_DIVISOR = REG_READ(PP_DIVISOR);*/
  219. lvds_priv->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
  220. lvds_priv->savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
  221. lvds_priv->savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
  222. /*TODO: move backlight_duty_cycle to psb_intel_lvds_priv*/
  223. dev_priv->backlight_duty_cycle = (dev_priv->regs.saveBLC_PWM_CTL &
  224. BACKLIGHT_DUTY_CYCLE_MASK);
  225. /*
  226. * If the light is off at server startup,
  227. * just make it full brightness
  228. */
  229. if (dev_priv->backlight_duty_cycle == 0)
  230. dev_priv->backlight_duty_cycle =
  231. psb_intel_lvds_get_max_backlight(dev);
  232. dev_dbg(dev->dev, "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n",
  233. lvds_priv->savePP_ON,
  234. lvds_priv->savePP_OFF,
  235. lvds_priv->saveLVDS,
  236. lvds_priv->savePP_CONTROL,
  237. lvds_priv->savePP_CYCLE,
  238. lvds_priv->saveBLC_PWM_CTL);
  239. }
  240. static void psb_intel_lvds_restore(struct drm_connector *connector)
  241. {
  242. struct drm_device *dev = connector->dev;
  243. u32 pp_status;
  244. struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
  245. struct psb_intel_lvds_priv *lvds_priv =
  246. (struct psb_intel_lvds_priv *)gma_encoder->dev_priv;
  247. dev_dbg(dev->dev, "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n",
  248. lvds_priv->savePP_ON,
  249. lvds_priv->savePP_OFF,
  250. lvds_priv->saveLVDS,
  251. lvds_priv->savePP_CONTROL,
  252. lvds_priv->savePP_CYCLE,
  253. lvds_priv->saveBLC_PWM_CTL);
  254. REG_WRITE(BLC_PWM_CTL, lvds_priv->saveBLC_PWM_CTL);
  255. REG_WRITE(PFIT_CONTROL, lvds_priv->savePFIT_CONTROL);
  256. REG_WRITE(PFIT_PGM_RATIOS, lvds_priv->savePFIT_PGM_RATIOS);
  257. REG_WRITE(LVDSPP_ON, lvds_priv->savePP_ON);
  258. REG_WRITE(LVDSPP_OFF, lvds_priv->savePP_OFF);
  259. /*REG_WRITE(PP_DIVISOR, lvds_priv->savePP_DIVISOR);*/
  260. REG_WRITE(PP_CYCLE, lvds_priv->savePP_CYCLE);
  261. REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL);
  262. REG_WRITE(LVDS, lvds_priv->saveLVDS);
  263. if (lvds_priv->savePP_CONTROL & POWER_TARGET_ON) {
  264. REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
  265. POWER_TARGET_ON);
  266. do {
  267. pp_status = REG_READ(PP_STATUS);
  268. } while ((pp_status & PP_ON) == 0);
  269. } else {
  270. REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
  271. ~POWER_TARGET_ON);
  272. do {
  273. pp_status = REG_READ(PP_STATUS);
  274. } while (pp_status & PP_ON);
  275. }
  276. }
  277. enum drm_mode_status psb_intel_lvds_mode_valid(struct drm_connector *connector,
  278. struct drm_display_mode *mode)
  279. {
  280. struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev);
  281. struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
  282. struct drm_display_mode *fixed_mode =
  283. dev_priv->mode_dev.panel_fixed_mode;
  284. if (gma_encoder->type == INTEL_OUTPUT_MIPI2)
  285. fixed_mode = dev_priv->mode_dev.panel_fixed_mode2;
  286. /* just in case */
  287. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  288. return MODE_NO_DBLESCAN;
  289. /* just in case */
  290. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  291. return MODE_NO_INTERLACE;
  292. if (fixed_mode) {
  293. if (mode->hdisplay > fixed_mode->hdisplay)
  294. return MODE_PANEL;
  295. if (mode->vdisplay > fixed_mode->vdisplay)
  296. return MODE_PANEL;
  297. }
  298. return MODE_OK;
  299. }
  300. bool psb_intel_lvds_mode_fixup(struct drm_encoder *encoder,
  301. const struct drm_display_mode *mode,
  302. struct drm_display_mode *adjusted_mode)
  303. {
  304. struct drm_device *dev = encoder->dev;
  305. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  306. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  307. struct gma_crtc *gma_crtc = to_gma_crtc(encoder->crtc);
  308. struct drm_encoder *tmp_encoder;
  309. struct drm_display_mode *panel_fixed_mode = mode_dev->panel_fixed_mode;
  310. struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
  311. if (gma_encoder->type == INTEL_OUTPUT_MIPI2)
  312. panel_fixed_mode = mode_dev->panel_fixed_mode2;
  313. /* PSB requires the LVDS is on pipe B, MRST has only one pipe anyway */
  314. if (!IS_MRST(dev) && gma_crtc->pipe == 0) {
  315. pr_err("Can't support LVDS on pipe A\n");
  316. return false;
  317. }
  318. if (IS_MRST(dev) && gma_crtc->pipe != 0) {
  319. pr_err("Must use PIPE A\n");
  320. return false;
  321. }
  322. /* Should never happen!! */
  323. list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list,
  324. head) {
  325. if (tmp_encoder != encoder
  326. && tmp_encoder->crtc == encoder->crtc) {
  327. pr_err("Can't enable LVDS and another encoder on the same pipe\n");
  328. return false;
  329. }
  330. }
  331. /*
  332. * If we have timings from the BIOS for the panel, put them in
  333. * to the adjusted mode. The CRTC will be set up for this mode,
  334. * with the panel scaling set up to source from the H/VDisplay
  335. * of the original mode.
  336. */
  337. if (panel_fixed_mode != NULL) {
  338. adjusted_mode->hdisplay = panel_fixed_mode->hdisplay;
  339. adjusted_mode->hsync_start = panel_fixed_mode->hsync_start;
  340. adjusted_mode->hsync_end = panel_fixed_mode->hsync_end;
  341. adjusted_mode->htotal = panel_fixed_mode->htotal;
  342. adjusted_mode->vdisplay = panel_fixed_mode->vdisplay;
  343. adjusted_mode->vsync_start = panel_fixed_mode->vsync_start;
  344. adjusted_mode->vsync_end = panel_fixed_mode->vsync_end;
  345. adjusted_mode->vtotal = panel_fixed_mode->vtotal;
  346. adjusted_mode->clock = panel_fixed_mode->clock;
  347. drm_mode_set_crtcinfo(adjusted_mode,
  348. CRTC_INTERLACE_HALVE_V);
  349. }
  350. /*
  351. * XXX: It would be nice to support lower refresh rates on the
  352. * panels to reduce power consumption, and perhaps match the
  353. * user's requested refresh rate.
  354. */
  355. return true;
  356. }
  357. static void psb_intel_lvds_prepare(struct drm_encoder *encoder)
  358. {
  359. struct drm_device *dev = encoder->dev;
  360. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  361. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  362. if (!gma_power_begin(dev, true))
  363. return;
  364. mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
  365. mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL &
  366. BACKLIGHT_DUTY_CYCLE_MASK);
  367. psb_intel_lvds_set_power(dev, false);
  368. gma_power_end(dev);
  369. }
  370. static void psb_intel_lvds_commit(struct drm_encoder *encoder)
  371. {
  372. struct drm_device *dev = encoder->dev;
  373. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  374. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  375. if (mode_dev->backlight_duty_cycle == 0)
  376. mode_dev->backlight_duty_cycle =
  377. psb_intel_lvds_get_max_backlight(dev);
  378. psb_intel_lvds_set_power(dev, true);
  379. }
  380. static void psb_intel_lvds_mode_set(struct drm_encoder *encoder,
  381. struct drm_display_mode *mode,
  382. struct drm_display_mode *adjusted_mode)
  383. {
  384. struct drm_device *dev = encoder->dev;
  385. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  386. u32 pfit_control;
  387. /*
  388. * The LVDS pin pair will already have been turned on in the
  389. * psb_intel_crtc_mode_set since it has a large impact on the DPLL
  390. * settings.
  391. */
  392. /*
  393. * Enable automatic panel scaling so that non-native modes fill the
  394. * screen. Should be enabled before the pipe is enabled, according to
  395. * register description and PRM.
  396. */
  397. if (mode->hdisplay != adjusted_mode->hdisplay ||
  398. mode->vdisplay != adjusted_mode->vdisplay)
  399. pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE |
  400. HORIZ_AUTO_SCALE | VERT_INTERP_BILINEAR |
  401. HORIZ_INTERP_BILINEAR);
  402. else
  403. pfit_control = 0;
  404. if (dev_priv->lvds_dither)
  405. pfit_control |= PANEL_8TO6_DITHER_ENABLE;
  406. REG_WRITE(PFIT_CONTROL, pfit_control);
  407. }
  408. /*
  409. * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
  410. */
  411. static int psb_intel_lvds_get_modes(struct drm_connector *connector)
  412. {
  413. struct drm_device *dev = connector->dev;
  414. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  415. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  416. int ret = 0;
  417. if (!IS_MRST(dev))
  418. ret = psb_intel_ddc_get_modes(connector, connector->ddc);
  419. if (ret)
  420. return ret;
  421. if (mode_dev->panel_fixed_mode != NULL) {
  422. struct drm_display_mode *mode =
  423. drm_mode_duplicate(dev, mode_dev->panel_fixed_mode);
  424. if (!mode)
  425. return 0;
  426. drm_mode_probed_add(connector, mode);
  427. return 1;
  428. }
  429. return 0;
  430. }
  431. void psb_intel_lvds_destroy(struct drm_connector *connector)
  432. {
  433. struct gma_connector *gma_connector = to_gma_connector(connector);
  434. struct gma_i2c_chan *ddc_bus = to_gma_i2c_chan(connector->ddc);
  435. gma_i2c_destroy(ddc_bus);
  436. drm_connector_cleanup(connector);
  437. kfree(gma_connector);
  438. }
  439. int psb_intel_lvds_set_property(struct drm_connector *connector,
  440. struct drm_property *property,
  441. uint64_t value)
  442. {
  443. struct drm_encoder *encoder = connector->encoder;
  444. if (!encoder)
  445. return -1;
  446. if (!strcmp(property->name, "scaling mode")) {
  447. struct gma_crtc *crtc = to_gma_crtc(encoder->crtc);
  448. uint64_t curval;
  449. if (!crtc)
  450. goto set_prop_error;
  451. switch (value) {
  452. case DRM_MODE_SCALE_FULLSCREEN:
  453. break;
  454. case DRM_MODE_SCALE_NO_SCALE:
  455. break;
  456. case DRM_MODE_SCALE_ASPECT:
  457. break;
  458. default:
  459. goto set_prop_error;
  460. }
  461. if (drm_object_property_get_value(&connector->base,
  462. property,
  463. &curval))
  464. goto set_prop_error;
  465. if (curval == value)
  466. goto set_prop_done;
  467. if (drm_object_property_set_value(&connector->base,
  468. property,
  469. value))
  470. goto set_prop_error;
  471. if (crtc->saved_mode.hdisplay != 0 &&
  472. crtc->saved_mode.vdisplay != 0) {
  473. if (!drm_crtc_helper_set_mode(encoder->crtc,
  474. &crtc->saved_mode,
  475. encoder->crtc->x,
  476. encoder->crtc->y,
  477. encoder->crtc->primary->fb))
  478. goto set_prop_error;
  479. }
  480. } else if (!strcmp(property->name, "backlight")) {
  481. if (drm_object_property_set_value(&connector->base,
  482. property,
  483. value))
  484. goto set_prop_error;
  485. else
  486. gma_backlight_set(encoder->dev, value);
  487. } else if (!strcmp(property->name, "DPMS")) {
  488. const struct drm_encoder_helper_funcs *hfuncs
  489. = encoder->helper_private;
  490. hfuncs->dpms(encoder, value);
  491. }
  492. set_prop_done:
  493. return 0;
  494. set_prop_error:
  495. return -1;
  496. }
  497. static const struct drm_encoder_helper_funcs psb_intel_lvds_helper_funcs = {
  498. .dpms = psb_intel_lvds_encoder_dpms,
  499. .mode_fixup = psb_intel_lvds_mode_fixup,
  500. .prepare = psb_intel_lvds_prepare,
  501. .mode_set = psb_intel_lvds_mode_set,
  502. .commit = psb_intel_lvds_commit,
  503. };
  504. const struct drm_connector_helper_funcs
  505. psb_intel_lvds_connector_helper_funcs = {
  506. .get_modes = psb_intel_lvds_get_modes,
  507. .mode_valid = psb_intel_lvds_mode_valid,
  508. .best_encoder = gma_best_encoder,
  509. };
  510. const struct drm_connector_funcs psb_intel_lvds_connector_funcs = {
  511. .dpms = drm_helper_connector_dpms,
  512. .fill_modes = drm_helper_probe_single_connector_modes,
  513. .set_property = psb_intel_lvds_set_property,
  514. .destroy = psb_intel_lvds_destroy,
  515. };
  516. /**
  517. * psb_intel_lvds_init - setup LVDS connectors on this device
  518. * @dev: drm device
  519. * @mode_dev: mode device
  520. *
  521. * Create the connector, register the LVDS DDC bus, and try to figure out what
  522. * modes we can display on the LVDS panel (if present).
  523. */
  524. void psb_intel_lvds_init(struct drm_device *dev,
  525. struct psb_intel_mode_device *mode_dev)
  526. {
  527. struct gma_encoder *gma_encoder;
  528. struct gma_connector *gma_connector;
  529. struct psb_intel_lvds_priv *lvds_priv;
  530. struct drm_connector *connector;
  531. struct drm_encoder *encoder;
  532. struct drm_display_mode *scan; /* *modes, *bios_mode; */
  533. struct drm_crtc *crtc;
  534. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  535. struct gma_i2c_chan *ddc_bus;
  536. u32 lvds;
  537. int pipe;
  538. int ret;
  539. gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
  540. if (!gma_encoder) {
  541. dev_err(dev->dev, "gma_encoder allocation error\n");
  542. return;
  543. }
  544. encoder = &gma_encoder->base;
  545. gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
  546. if (!gma_connector) {
  547. dev_err(dev->dev, "gma_connector allocation error\n");
  548. goto err_free_encoder;
  549. }
  550. lvds_priv = kzalloc(sizeof(struct psb_intel_lvds_priv), GFP_KERNEL);
  551. if (!lvds_priv) {
  552. dev_err(dev->dev, "LVDS private allocation error\n");
  553. goto err_free_connector;
  554. }
  555. gma_encoder->dev_priv = lvds_priv;
  556. connector = &gma_connector->base;
  557. gma_connector->save = psb_intel_lvds_save;
  558. gma_connector->restore = psb_intel_lvds_restore;
  559. /* Set up the DDC bus. */
  560. ddc_bus = gma_i2c_create(dev, GPIOC, "LVDSDDC_C");
  561. if (!ddc_bus) {
  562. dev_printk(KERN_ERR, dev->dev,
  563. "DDC bus registration " "failed.\n");
  564. goto err_free_lvds_priv;
  565. }
  566. ret = drm_connector_init_with_ddc(dev, connector,
  567. &psb_intel_lvds_connector_funcs,
  568. DRM_MODE_CONNECTOR_LVDS,
  569. &ddc_bus->base);
  570. if (ret)
  571. goto err_ddc_destroy;
  572. ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_LVDS);
  573. if (ret)
  574. goto err_connector_cleanup;
  575. gma_connector_attach_encoder(gma_connector, gma_encoder);
  576. gma_encoder->type = INTEL_OUTPUT_LVDS;
  577. drm_encoder_helper_add(encoder, &psb_intel_lvds_helper_funcs);
  578. drm_connector_helper_add(connector,
  579. &psb_intel_lvds_connector_helper_funcs);
  580. connector->display_info.subpixel_order = SubPixelHorizontalRGB;
  581. connector->interlace_allowed = false;
  582. connector->doublescan_allowed = false;
  583. /*Attach connector properties*/
  584. drm_object_attach_property(&connector->base,
  585. dev->mode_config.scaling_mode_property,
  586. DRM_MODE_SCALE_FULLSCREEN);
  587. drm_object_attach_property(&connector->base,
  588. dev_priv->backlight_property,
  589. BRIGHTNESS_MAX_LEVEL);
  590. /*
  591. * Set up I2C bus
  592. * FIXME: distroy i2c_bus when exit
  593. */
  594. lvds_priv->i2c_bus = gma_i2c_create(dev, GPIOB, "LVDSBLC_B");
  595. if (!lvds_priv->i2c_bus) {
  596. dev_printk(KERN_ERR,
  597. dev->dev, "I2C bus registration failed.\n");
  598. goto err_encoder_cleanup;
  599. }
  600. lvds_priv->i2c_bus->target_addr = 0x2C;
  601. dev_priv->lvds_i2c_bus = lvds_priv->i2c_bus;
  602. /*
  603. * LVDS discovery:
  604. * 1) check for EDID on DDC
  605. * 2) check for VBT data
  606. * 3) check to see if LVDS is already on
  607. * if none of the above, no panel
  608. * 4) make sure lid is open
  609. * if closed, act like it's not there for now
  610. */
  611. /*
  612. * Attempt to get the fixed panel mode from DDC. Assume that the
  613. * preferred mode is the right one.
  614. */
  615. mutex_lock(&dev->mode_config.mutex);
  616. psb_intel_ddc_get_modes(connector, &ddc_bus->base);
  617. list_for_each_entry(scan, &connector->probed_modes, head) {
  618. if (scan->type & DRM_MODE_TYPE_PREFERRED) {
  619. mode_dev->panel_fixed_mode =
  620. drm_mode_duplicate(dev, scan);
  621. DRM_DEBUG_KMS("Using mode from DDC\n");
  622. goto out; /* FIXME: check for quirks */
  623. }
  624. }
  625. /* Failed to get EDID, what about VBT? do we need this? */
  626. if (dev_priv->lfp_lvds_vbt_mode) {
  627. mode_dev->panel_fixed_mode =
  628. drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
  629. if (mode_dev->panel_fixed_mode) {
  630. mode_dev->panel_fixed_mode->type |=
  631. DRM_MODE_TYPE_PREFERRED;
  632. DRM_DEBUG_KMS("Using mode from VBT\n");
  633. goto out;
  634. }
  635. }
  636. /*
  637. * If we didn't get EDID, try checking if the panel is already turned
  638. * on. If so, assume that whatever is currently programmed is the
  639. * correct mode.
  640. */
  641. lvds = REG_READ(LVDS);
  642. pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
  643. crtc = psb_intel_get_crtc_from_pipe(dev, pipe);
  644. if (crtc && (lvds & LVDS_PORT_EN)) {
  645. mode_dev->panel_fixed_mode =
  646. psb_intel_crtc_mode_get(dev, crtc);
  647. if (mode_dev->panel_fixed_mode) {
  648. mode_dev->panel_fixed_mode->type |=
  649. DRM_MODE_TYPE_PREFERRED;
  650. DRM_DEBUG_KMS("Using pre-programmed mode\n");
  651. goto out; /* FIXME: check for quirks */
  652. }
  653. }
  654. /* If we still don't have a mode after all that, give up. */
  655. if (!mode_dev->panel_fixed_mode) {
  656. dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n");
  657. goto err_unlock;
  658. }
  659. /*
  660. * Blacklist machines with BIOSes that list an LVDS panel without
  661. * actually having one.
  662. */
  663. out:
  664. mutex_unlock(&dev->mode_config.mutex);
  665. return;
  666. err_unlock:
  667. mutex_unlock(&dev->mode_config.mutex);
  668. gma_i2c_destroy(lvds_priv->i2c_bus);
  669. err_encoder_cleanup:
  670. drm_encoder_cleanup(encoder);
  671. err_connector_cleanup:
  672. drm_connector_cleanup(connector);
  673. err_ddc_destroy:
  674. gma_i2c_destroy(ddc_bus);
  675. err_free_lvds_priv:
  676. kfree(lvds_priv);
  677. err_free_connector:
  678. kfree(gma_connector);
  679. err_free_encoder:
  680. kfree(gma_encoder);
  681. }