msm_ringbuffer.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <robdclark@gmail.com>
  5. */
  6. #ifndef __MSM_RINGBUFFER_H__
  7. #define __MSM_RINGBUFFER_H__
  8. #include "drm/gpu_scheduler.h"
  9. #include "msm_drv.h"
  10. #define rbmemptr(ring, member) \
  11. ((ring)->memptrs_iova + offsetof(struct msm_rbmemptrs, member))
  12. #define rbmemptr_stats(ring, index, member) \
  13. (rbmemptr((ring), stats) + \
  14. ((index) * sizeof(struct msm_gpu_submit_stats)) + \
  15. offsetof(struct msm_gpu_submit_stats, member))
  16. struct msm_gpu_submit_stats {
  17. u64 cpcycles_start;
  18. u64 cpcycles_end;
  19. u64 alwayson_start;
  20. u64 alwayson_end;
  21. };
  22. #define MSM_GPU_SUBMIT_STATS_COUNT 64
  23. struct msm_rbmemptrs {
  24. volatile uint32_t rptr;
  25. volatile uint32_t fence;
  26. /* Introduced on A7xx */
  27. volatile uint32_t bv_fence;
  28. volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT];
  29. volatile u64 ttbr0;
  30. };
  31. struct msm_cp_state {
  32. uint64_t ib1_base, ib2_base;
  33. uint32_t ib1_rem, ib2_rem;
  34. };
  35. struct msm_ringbuffer {
  36. struct msm_gpu *gpu;
  37. int id;
  38. struct drm_gem_object *bo;
  39. uint32_t *start, *end, *cur, *next;
  40. /*
  41. * The job scheduler for this ring.
  42. */
  43. struct drm_gpu_scheduler sched;
  44. /*
  45. * List of in-flight submits on this ring. Protected by submit_lock.
  46. *
  47. * Currently just submits that are already written into the ring, not
  48. * submits that are still in drm_gpu_scheduler's queues. At a later
  49. * step we could probably move to letting drm_gpu_scheduler manage
  50. * hangcheck detection and keep track of submit jobs that are in-
  51. * flight.
  52. */
  53. struct list_head submits;
  54. spinlock_t submit_lock;
  55. uint64_t iova;
  56. uint32_t hangcheck_fence;
  57. struct msm_rbmemptrs *memptrs;
  58. uint64_t memptrs_iova;
  59. struct msm_fence_context *fctx;
  60. /**
  61. * hangcheck_progress_retries:
  62. *
  63. * The number of extra hangcheck duration cycles that we have given
  64. * due to it appearing that the GPU is making forward progress.
  65. *
  66. * For GPU generations which support progress detection (see.
  67. * msm_gpu_funcs::progress()), if the GPU appears to be making progress
  68. * (ie. the CP has advanced in the command stream, we'll allow up to
  69. * DRM_MSM_HANGCHECK_PROGRESS_RETRIES expirations of the hangcheck timer
  70. * before killing the job. But to detect progress we need two sample
  71. * points, so the duration of the hangcheck timer is halved. In other
  72. * words we'll let the submit run for up to:
  73. *
  74. * (DRM_MSM_HANGCHECK_DEFAULT_PERIOD / 2) * (DRM_MSM_HANGCHECK_PROGRESS_RETRIES + 1)
  75. */
  76. int hangcheck_progress_retries;
  77. /**
  78. * last_cp_state: The state of the CP at the last call to gpu->progress()
  79. */
  80. struct msm_cp_state last_cp_state;
  81. /*
  82. * preempt_lock protects preemption and serializes wptr updates against
  83. * preemption. Can be aquired from irq context.
  84. */
  85. spinlock_t preempt_lock;
  86. };
  87. struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
  88. void *memptrs, uint64_t memptrs_iova);
  89. void msm_ringbuffer_destroy(struct msm_ringbuffer *ring);
  90. /* ringbuffer helpers (the parts that are same for a3xx/a2xx/z180..) */
  91. static inline void
  92. OUT_RING(struct msm_ringbuffer *ring, uint32_t data)
  93. {
  94. /*
  95. * ring->next points to the current command being written - it won't be
  96. * committed as ring->cur until the flush
  97. */
  98. if (ring->next == ring->end)
  99. ring->next = ring->start;
  100. *(ring->next++) = data;
  101. }
  102. #endif /* __MSM_RINGBUFFER_H__ */