uapi.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2020 NVIDIA Corporation */
  3. #include <linux/host1x.h>
  4. #include <linux/iommu.h>
  5. #include <linux/list.h>
  6. #include <drm/drm_drv.h>
  7. #include <drm/drm_file.h>
  8. #include <drm/drm_utils.h>
  9. #include "drm.h"
  10. #include "uapi.h"
  11. static void tegra_drm_mapping_release(struct kref *ref)
  12. {
  13. struct tegra_drm_mapping *mapping =
  14. container_of(ref, struct tegra_drm_mapping, ref);
  15. host1x_bo_unpin(mapping->map);
  16. host1x_bo_put(mapping->bo);
  17. kfree(mapping);
  18. }
  19. void tegra_drm_mapping_put(struct tegra_drm_mapping *mapping)
  20. {
  21. kref_put(&mapping->ref, tegra_drm_mapping_release);
  22. }
  23. static void tegra_drm_channel_context_close(struct tegra_drm_context *context)
  24. {
  25. struct tegra_drm_mapping *mapping;
  26. unsigned long id;
  27. if (context->memory_context)
  28. host1x_memory_context_put(context->memory_context);
  29. xa_for_each(&context->mappings, id, mapping)
  30. tegra_drm_mapping_put(mapping);
  31. xa_destroy(&context->mappings);
  32. host1x_channel_put(context->channel);
  33. kfree(context);
  34. }
  35. void tegra_drm_uapi_close_file(struct tegra_drm_file *file)
  36. {
  37. struct tegra_drm_context *context;
  38. struct host1x_syncpt *sp;
  39. unsigned long id;
  40. xa_for_each(&file->contexts, id, context)
  41. tegra_drm_channel_context_close(context);
  42. xa_for_each(&file->syncpoints, id, sp)
  43. host1x_syncpt_put(sp);
  44. xa_destroy(&file->contexts);
  45. xa_destroy(&file->syncpoints);
  46. }
  47. static struct tegra_drm_client *tegra_drm_find_client(struct tegra_drm *tegra, u32 class)
  48. {
  49. struct tegra_drm_client *client;
  50. list_for_each_entry(client, &tegra->clients, list)
  51. if (client->base.class == class)
  52. return client;
  53. return NULL;
  54. }
  55. int tegra_drm_ioctl_channel_open(struct drm_device *drm, void *data, struct drm_file *file)
  56. {
  57. struct host1x *host = tegra_drm_to_host1x(drm->dev_private);
  58. struct tegra_drm_file *fpriv = file->driver_priv;
  59. struct tegra_drm *tegra = drm->dev_private;
  60. struct drm_tegra_channel_open *args = data;
  61. struct tegra_drm_client *client = NULL;
  62. struct tegra_drm_context *context;
  63. int err;
  64. if (args->flags)
  65. return -EINVAL;
  66. context = kzalloc(sizeof(*context), GFP_KERNEL);
  67. if (!context)
  68. return -ENOMEM;
  69. client = tegra_drm_find_client(tegra, args->host1x_class);
  70. if (!client) {
  71. err = -ENODEV;
  72. goto free;
  73. }
  74. if (client->shared_channel) {
  75. context->channel = host1x_channel_get(client->shared_channel);
  76. } else {
  77. context->channel = host1x_channel_request(&client->base);
  78. if (!context->channel) {
  79. err = -EBUSY;
  80. goto free;
  81. }
  82. }
  83. /* Only allocate context if the engine supports context isolation. */
  84. if (device_iommu_mapped(client->base.dev) && client->ops->can_use_memory_ctx) {
  85. bool supported;
  86. err = client->ops->can_use_memory_ctx(client, &supported);
  87. if (err)
  88. goto put_channel;
  89. if (supported)
  90. context->memory_context = host1x_memory_context_alloc(
  91. host, client->base.dev, get_task_pid(current, PIDTYPE_TGID));
  92. if (IS_ERR(context->memory_context)) {
  93. if (PTR_ERR(context->memory_context) != -EOPNOTSUPP) {
  94. err = PTR_ERR(context->memory_context);
  95. goto put_channel;
  96. } else {
  97. /*
  98. * OK, HW does not support contexts or contexts
  99. * are disabled.
  100. */
  101. context->memory_context = NULL;
  102. }
  103. }
  104. }
  105. err = xa_alloc(&fpriv->contexts, &args->context, context, XA_LIMIT(1, U32_MAX),
  106. GFP_KERNEL);
  107. if (err < 0)
  108. goto put_memctx;
  109. context->client = client;
  110. xa_init_flags(&context->mappings, XA_FLAGS_ALLOC1);
  111. args->version = client->version;
  112. args->capabilities = 0;
  113. if (device_get_dma_attr(client->base.dev) == DEV_DMA_COHERENT)
  114. args->capabilities |= DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT;
  115. return 0;
  116. put_memctx:
  117. if (context->memory_context)
  118. host1x_memory_context_put(context->memory_context);
  119. put_channel:
  120. host1x_channel_put(context->channel);
  121. free:
  122. kfree(context);
  123. return err;
  124. }
  125. int tegra_drm_ioctl_channel_close(struct drm_device *drm, void *data, struct drm_file *file)
  126. {
  127. struct tegra_drm_file *fpriv = file->driver_priv;
  128. struct drm_tegra_channel_close *args = data;
  129. struct tegra_drm_context *context;
  130. mutex_lock(&fpriv->lock);
  131. context = xa_load(&fpriv->contexts, args->context);
  132. if (!context) {
  133. mutex_unlock(&fpriv->lock);
  134. return -EINVAL;
  135. }
  136. xa_erase(&fpriv->contexts, args->context);
  137. mutex_unlock(&fpriv->lock);
  138. tegra_drm_channel_context_close(context);
  139. return 0;
  140. }
  141. int tegra_drm_ioctl_channel_map(struct drm_device *drm, void *data, struct drm_file *file)
  142. {
  143. struct tegra_drm_file *fpriv = file->driver_priv;
  144. struct drm_tegra_channel_map *args = data;
  145. struct tegra_drm_mapping *mapping;
  146. struct tegra_drm_context *context;
  147. enum dma_data_direction direction;
  148. struct device *mapping_dev;
  149. int err = 0;
  150. if (args->flags & ~DRM_TEGRA_CHANNEL_MAP_READ_WRITE)
  151. return -EINVAL;
  152. mutex_lock(&fpriv->lock);
  153. context = xa_load(&fpriv->contexts, args->context);
  154. if (!context) {
  155. mutex_unlock(&fpriv->lock);
  156. return -EINVAL;
  157. }
  158. mapping = kzalloc(sizeof(*mapping), GFP_KERNEL);
  159. if (!mapping) {
  160. err = -ENOMEM;
  161. goto unlock;
  162. }
  163. kref_init(&mapping->ref);
  164. if (context->memory_context)
  165. mapping_dev = &context->memory_context->dev;
  166. else
  167. mapping_dev = context->client->base.dev;
  168. mapping->bo = tegra_gem_lookup(file, args->handle);
  169. if (!mapping->bo) {
  170. err = -EINVAL;
  171. goto free;
  172. }
  173. switch (args->flags & DRM_TEGRA_CHANNEL_MAP_READ_WRITE) {
  174. case DRM_TEGRA_CHANNEL_MAP_READ_WRITE:
  175. direction = DMA_BIDIRECTIONAL;
  176. break;
  177. case DRM_TEGRA_CHANNEL_MAP_WRITE:
  178. direction = DMA_FROM_DEVICE;
  179. break;
  180. case DRM_TEGRA_CHANNEL_MAP_READ:
  181. direction = DMA_TO_DEVICE;
  182. break;
  183. default:
  184. err = -EINVAL;
  185. goto put_gem;
  186. }
  187. mapping->map = host1x_bo_pin(mapping_dev, mapping->bo, direction, NULL);
  188. if (IS_ERR(mapping->map)) {
  189. err = PTR_ERR(mapping->map);
  190. goto put_gem;
  191. }
  192. mapping->iova = mapping->map->phys;
  193. mapping->iova_end = mapping->iova + host1x_to_tegra_bo(mapping->bo)->gem.size;
  194. err = xa_alloc(&context->mappings, &args->mapping, mapping, XA_LIMIT(1, U32_MAX),
  195. GFP_KERNEL);
  196. if (err < 0)
  197. goto unpin;
  198. mutex_unlock(&fpriv->lock);
  199. return 0;
  200. unpin:
  201. host1x_bo_unpin(mapping->map);
  202. put_gem:
  203. host1x_bo_put(mapping->bo);
  204. free:
  205. kfree(mapping);
  206. unlock:
  207. mutex_unlock(&fpriv->lock);
  208. return err;
  209. }
  210. int tegra_drm_ioctl_channel_unmap(struct drm_device *drm, void *data, struct drm_file *file)
  211. {
  212. struct tegra_drm_file *fpriv = file->driver_priv;
  213. struct drm_tegra_channel_unmap *args = data;
  214. struct tegra_drm_mapping *mapping;
  215. struct tegra_drm_context *context;
  216. mutex_lock(&fpriv->lock);
  217. context = xa_load(&fpriv->contexts, args->context);
  218. if (!context) {
  219. mutex_unlock(&fpriv->lock);
  220. return -EINVAL;
  221. }
  222. mapping = xa_erase(&context->mappings, args->mapping);
  223. mutex_unlock(&fpriv->lock);
  224. if (!mapping)
  225. return -EINVAL;
  226. tegra_drm_mapping_put(mapping);
  227. return 0;
  228. }
  229. int tegra_drm_ioctl_syncpoint_allocate(struct drm_device *drm, void *data, struct drm_file *file)
  230. {
  231. struct host1x *host1x = tegra_drm_to_host1x(drm->dev_private);
  232. struct tegra_drm_file *fpriv = file->driver_priv;
  233. struct drm_tegra_syncpoint_allocate *args = data;
  234. struct host1x_syncpt *sp;
  235. int err;
  236. if (args->id)
  237. return -EINVAL;
  238. sp = host1x_syncpt_alloc(host1x, HOST1X_SYNCPT_CLIENT_MANAGED, current->comm);
  239. if (!sp)
  240. return -EBUSY;
  241. args->id = host1x_syncpt_id(sp);
  242. err = xa_insert(&fpriv->syncpoints, args->id, sp, GFP_KERNEL);
  243. if (err) {
  244. host1x_syncpt_put(sp);
  245. return err;
  246. }
  247. return 0;
  248. }
  249. int tegra_drm_ioctl_syncpoint_free(struct drm_device *drm, void *data, struct drm_file *file)
  250. {
  251. struct tegra_drm_file *fpriv = file->driver_priv;
  252. struct drm_tegra_syncpoint_allocate *args = data;
  253. struct host1x_syncpt *sp;
  254. mutex_lock(&fpriv->lock);
  255. sp = xa_erase(&fpriv->syncpoints, args->id);
  256. mutex_unlock(&fpriv->lock);
  257. if (!sp)
  258. return -EINVAL;
  259. host1x_syncpt_put(sp);
  260. return 0;
  261. }
  262. int tegra_drm_ioctl_syncpoint_wait(struct drm_device *drm, void *data, struct drm_file *file)
  263. {
  264. struct host1x *host1x = tegra_drm_to_host1x(drm->dev_private);
  265. struct drm_tegra_syncpoint_wait *args = data;
  266. signed long timeout_jiffies;
  267. struct host1x_syncpt *sp;
  268. if (args->padding != 0)
  269. return -EINVAL;
  270. sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
  271. if (!sp)
  272. return -EINVAL;
  273. timeout_jiffies = drm_timeout_abs_to_jiffies(args->timeout_ns);
  274. return host1x_syncpt_wait(sp, args->threshold, timeout_jiffies, &args->value);
  275. }