tilcdc_drv.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2012 Texas Instruments
  4. * Author: Rob Clark <robdclark@gmail.com>
  5. */
  6. /* LCDC DRM driver, based on da8xx-fb */
  7. #include <linux/component.h>
  8. #include <linux/mod_devicetable.h>
  9. #include <linux/module.h>
  10. #include <linux/pinctrl/consumer.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pm_runtime.h>
  13. #include <drm/drm_atomic_helper.h>
  14. #include <drm/drm_debugfs.h>
  15. #include <drm/drm_drv.h>
  16. #include <drm/drm_fbdev_dma.h>
  17. #include <drm/drm_fourcc.h>
  18. #include <drm/drm_gem_dma_helper.h>
  19. #include <drm/drm_gem_framebuffer_helper.h>
  20. #include <drm/drm_mm.h>
  21. #include <drm/drm_probe_helper.h>
  22. #include <drm/drm_vblank.h>
  23. #include "tilcdc_drv.h"
  24. #include "tilcdc_external.h"
  25. #include "tilcdc_panel.h"
  26. #include "tilcdc_regs.h"
  27. static LIST_HEAD(module_list);
  28. static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
  29. static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
  30. DRM_FORMAT_BGR888,
  31. DRM_FORMAT_XBGR8888 };
  32. static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
  33. DRM_FORMAT_RGB888,
  34. DRM_FORMAT_XRGB8888 };
  35. static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
  36. DRM_FORMAT_RGB888,
  37. DRM_FORMAT_XRGB8888 };
  38. void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  39. const struct tilcdc_module_ops *funcs)
  40. {
  41. mod->name = name;
  42. mod->funcs = funcs;
  43. INIT_LIST_HEAD(&mod->list);
  44. list_add(&mod->list, &module_list);
  45. }
  46. void tilcdc_module_cleanup(struct tilcdc_module *mod)
  47. {
  48. list_del(&mod->list);
  49. }
  50. static int tilcdc_atomic_check(struct drm_device *dev,
  51. struct drm_atomic_state *state)
  52. {
  53. int ret;
  54. ret = drm_atomic_helper_check_modeset(dev, state);
  55. if (ret)
  56. return ret;
  57. ret = drm_atomic_helper_check_planes(dev, state);
  58. if (ret)
  59. return ret;
  60. /*
  61. * tilcdc ->atomic_check can update ->mode_changed if pixel format
  62. * changes, hence will we check modeset changes again.
  63. */
  64. ret = drm_atomic_helper_check_modeset(dev, state);
  65. if (ret)
  66. return ret;
  67. return ret;
  68. }
  69. static const struct drm_mode_config_funcs mode_config_funcs = {
  70. .fb_create = drm_gem_fb_create,
  71. .atomic_check = tilcdc_atomic_check,
  72. .atomic_commit = drm_atomic_helper_commit,
  73. };
  74. static void modeset_init(struct drm_device *dev)
  75. {
  76. struct tilcdc_drm_private *priv = dev->dev_private;
  77. struct tilcdc_module *mod;
  78. list_for_each_entry(mod, &module_list, list) {
  79. DBG("loading module: %s", mod->name);
  80. mod->funcs->modeset_init(mod, dev);
  81. }
  82. dev->mode_config.min_width = 0;
  83. dev->mode_config.min_height = 0;
  84. dev->mode_config.max_width = priv->max_width;
  85. dev->mode_config.max_height = 2048;
  86. dev->mode_config.funcs = &mode_config_funcs;
  87. }
  88. #ifdef CONFIG_CPU_FREQ
  89. static int cpufreq_transition(struct notifier_block *nb,
  90. unsigned long val, void *data)
  91. {
  92. struct tilcdc_drm_private *priv = container_of(nb,
  93. struct tilcdc_drm_private, freq_transition);
  94. if (val == CPUFREQ_POSTCHANGE)
  95. tilcdc_crtc_update_clk(priv->crtc);
  96. return 0;
  97. }
  98. #endif
  99. static irqreturn_t tilcdc_irq(int irq, void *arg)
  100. {
  101. struct drm_device *dev = arg;
  102. struct tilcdc_drm_private *priv = dev->dev_private;
  103. return tilcdc_crtc_irq(priv->crtc);
  104. }
  105. static int tilcdc_irq_install(struct drm_device *dev, unsigned int irq)
  106. {
  107. struct tilcdc_drm_private *priv = dev->dev_private;
  108. int ret;
  109. ret = request_irq(irq, tilcdc_irq, 0, dev->driver->name, dev);
  110. if (ret)
  111. return ret;
  112. priv->irq_enabled = true;
  113. return 0;
  114. }
  115. static void tilcdc_irq_uninstall(struct drm_device *dev)
  116. {
  117. struct tilcdc_drm_private *priv = dev->dev_private;
  118. if (!priv->irq_enabled)
  119. return;
  120. free_irq(priv->irq, dev);
  121. priv->irq_enabled = false;
  122. }
  123. /*
  124. * DRM operations:
  125. */
  126. static void tilcdc_fini(struct drm_device *dev)
  127. {
  128. struct tilcdc_drm_private *priv = dev->dev_private;
  129. #ifdef CONFIG_CPU_FREQ
  130. if (priv->freq_transition.notifier_call)
  131. cpufreq_unregister_notifier(&priv->freq_transition,
  132. CPUFREQ_TRANSITION_NOTIFIER);
  133. #endif
  134. if (priv->crtc)
  135. tilcdc_crtc_shutdown(priv->crtc);
  136. if (priv->is_registered)
  137. drm_dev_unregister(dev);
  138. drm_kms_helper_poll_fini(dev);
  139. drm_atomic_helper_shutdown(dev);
  140. tilcdc_irq_uninstall(dev);
  141. drm_mode_config_cleanup(dev);
  142. if (priv->clk)
  143. clk_put(priv->clk);
  144. if (priv->wq)
  145. destroy_workqueue(priv->wq);
  146. dev->dev_private = NULL;
  147. pm_runtime_disable(dev->dev);
  148. drm_dev_put(dev);
  149. }
  150. static int tilcdc_init(const struct drm_driver *ddrv, struct device *dev)
  151. {
  152. struct drm_device *ddev;
  153. struct platform_device *pdev = to_platform_device(dev);
  154. struct device_node *node = dev->of_node;
  155. struct tilcdc_drm_private *priv;
  156. u32 bpp = 0;
  157. int ret;
  158. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  159. if (!priv)
  160. return -ENOMEM;
  161. ddev = drm_dev_alloc(ddrv, dev);
  162. if (IS_ERR(ddev))
  163. return PTR_ERR(ddev);
  164. ddev->dev_private = priv;
  165. platform_set_drvdata(pdev, ddev);
  166. drm_mode_config_init(ddev);
  167. priv->is_componentized =
  168. tilcdc_get_external_components(dev, NULL) > 0;
  169. priv->wq = alloc_ordered_workqueue("tilcdc", 0);
  170. if (!priv->wq) {
  171. ret = -ENOMEM;
  172. goto init_failed;
  173. }
  174. priv->mmio = devm_platform_ioremap_resource(pdev, 0);
  175. if (IS_ERR(priv->mmio)) {
  176. dev_err(dev, "failed to request / ioremap\n");
  177. ret = PTR_ERR(priv->mmio);
  178. goto init_failed;
  179. }
  180. priv->clk = clk_get(dev, "fck");
  181. if (IS_ERR(priv->clk)) {
  182. dev_err(dev, "failed to get functional clock\n");
  183. ret = -ENODEV;
  184. goto init_failed;
  185. }
  186. pm_runtime_enable(dev);
  187. /* Determine LCD IP Version */
  188. pm_runtime_get_sync(dev);
  189. switch (tilcdc_read(ddev, LCDC_PID_REG)) {
  190. case 0x4c100102:
  191. priv->rev = 1;
  192. break;
  193. case 0x4f200800:
  194. case 0x4f201000:
  195. priv->rev = 2;
  196. break;
  197. default:
  198. dev_warn(dev, "Unknown PID Reg value 0x%08x, "
  199. "defaulting to LCD revision 1\n",
  200. tilcdc_read(ddev, LCDC_PID_REG));
  201. priv->rev = 1;
  202. break;
  203. }
  204. pm_runtime_put_sync(dev);
  205. if (priv->rev == 1) {
  206. DBG("Revision 1 LCDC supports only RGB565 format");
  207. priv->pixelformats = tilcdc_rev1_formats;
  208. priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
  209. bpp = 16;
  210. } else {
  211. const char *str = "\0";
  212. of_property_read_string(node, "blue-and-red-wiring", &str);
  213. if (0 == strcmp(str, "crossed")) {
  214. DBG("Configured for crossed blue and red wires");
  215. priv->pixelformats = tilcdc_crossed_formats;
  216. priv->num_pixelformats =
  217. ARRAY_SIZE(tilcdc_crossed_formats);
  218. bpp = 32; /* Choose bpp with RGB support for fbdef */
  219. } else if (0 == strcmp(str, "straight")) {
  220. DBG("Configured for straight blue and red wires");
  221. priv->pixelformats = tilcdc_straight_formats;
  222. priv->num_pixelformats =
  223. ARRAY_SIZE(tilcdc_straight_formats);
  224. bpp = 16; /* Choose bpp with RGB support for fbdef */
  225. } else {
  226. DBG("Blue and red wiring '%s' unknown, use legacy mode",
  227. str);
  228. priv->pixelformats = tilcdc_legacy_formats;
  229. priv->num_pixelformats =
  230. ARRAY_SIZE(tilcdc_legacy_formats);
  231. bpp = 16; /* This is just a guess */
  232. }
  233. }
  234. if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
  235. priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
  236. DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
  237. if (of_property_read_u32(node, "max-width", &priv->max_width)) {
  238. if (priv->rev == 1)
  239. priv->max_width = TILCDC_DEFAULT_MAX_WIDTH_V1;
  240. else
  241. priv->max_width = TILCDC_DEFAULT_MAX_WIDTH_V2;
  242. }
  243. DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
  244. if (of_property_read_u32(node, "max-pixelclock",
  245. &priv->max_pixelclock))
  246. priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
  247. DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
  248. ret = tilcdc_crtc_create(ddev);
  249. if (ret < 0) {
  250. dev_err(dev, "failed to create crtc\n");
  251. goto init_failed;
  252. }
  253. modeset_init(ddev);
  254. #ifdef CONFIG_CPU_FREQ
  255. priv->freq_transition.notifier_call = cpufreq_transition;
  256. ret = cpufreq_register_notifier(&priv->freq_transition,
  257. CPUFREQ_TRANSITION_NOTIFIER);
  258. if (ret) {
  259. dev_err(dev, "failed to register cpufreq notifier\n");
  260. priv->freq_transition.notifier_call = NULL;
  261. goto init_failed;
  262. }
  263. #endif
  264. if (priv->is_componentized) {
  265. ret = component_bind_all(dev, ddev);
  266. if (ret < 0)
  267. goto init_failed;
  268. ret = tilcdc_add_component_encoder(ddev);
  269. if (ret < 0)
  270. goto init_failed;
  271. } else {
  272. ret = tilcdc_attach_external_device(ddev);
  273. if (ret)
  274. goto init_failed;
  275. }
  276. if (!priv->external_connector &&
  277. ((priv->num_encoders == 0) || (priv->num_connectors == 0))) {
  278. dev_err(dev, "no encoders/connectors found\n");
  279. ret = -EPROBE_DEFER;
  280. goto init_failed;
  281. }
  282. ret = drm_vblank_init(ddev, 1);
  283. if (ret < 0) {
  284. dev_err(dev, "failed to initialize vblank\n");
  285. goto init_failed;
  286. }
  287. ret = platform_get_irq(pdev, 0);
  288. if (ret < 0)
  289. goto init_failed;
  290. priv->irq = ret;
  291. ret = tilcdc_irq_install(ddev, priv->irq);
  292. if (ret < 0) {
  293. dev_err(dev, "failed to install IRQ handler\n");
  294. goto init_failed;
  295. }
  296. drm_mode_config_reset(ddev);
  297. drm_kms_helper_poll_init(ddev);
  298. ret = drm_dev_register(ddev, 0);
  299. if (ret)
  300. goto init_failed;
  301. priv->is_registered = true;
  302. drm_fbdev_dma_setup(ddev, bpp);
  303. return 0;
  304. init_failed:
  305. tilcdc_fini(ddev);
  306. platform_set_drvdata(pdev, NULL);
  307. return ret;
  308. }
  309. #if defined(CONFIG_DEBUG_FS)
  310. static const struct {
  311. const char *name;
  312. uint8_t rev;
  313. uint8_t save;
  314. uint32_t reg;
  315. } registers[] = {
  316. #define REG(rev, save, reg) { #reg, rev, save, reg }
  317. /* exists in revision 1: */
  318. REG(1, false, LCDC_PID_REG),
  319. REG(1, true, LCDC_CTRL_REG),
  320. REG(1, false, LCDC_STAT_REG),
  321. REG(1, true, LCDC_RASTER_CTRL_REG),
  322. REG(1, true, LCDC_RASTER_TIMING_0_REG),
  323. REG(1, true, LCDC_RASTER_TIMING_1_REG),
  324. REG(1, true, LCDC_RASTER_TIMING_2_REG),
  325. REG(1, true, LCDC_DMA_CTRL_REG),
  326. REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
  327. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
  328. REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
  329. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
  330. /* new in revision 2: */
  331. REG(2, false, LCDC_RAW_STAT_REG),
  332. REG(2, false, LCDC_MASKED_STAT_REG),
  333. REG(2, true, LCDC_INT_ENABLE_SET_REG),
  334. REG(2, false, LCDC_INT_ENABLE_CLR_REG),
  335. REG(2, false, LCDC_END_OF_INT_IND_REG),
  336. REG(2, true, LCDC_CLK_ENABLE_REG),
  337. #undef REG
  338. };
  339. #endif
  340. #ifdef CONFIG_DEBUG_FS
  341. static int tilcdc_regs_show(struct seq_file *m, void *arg)
  342. {
  343. struct drm_info_node *node = (struct drm_info_node *) m->private;
  344. struct drm_device *dev = node->minor->dev;
  345. struct tilcdc_drm_private *priv = dev->dev_private;
  346. unsigned i;
  347. pm_runtime_get_sync(dev->dev);
  348. seq_printf(m, "revision: %d\n", priv->rev);
  349. for (i = 0; i < ARRAY_SIZE(registers); i++)
  350. if (priv->rev >= registers[i].rev)
  351. seq_printf(m, "%s:\t %08x\n", registers[i].name,
  352. tilcdc_read(dev, registers[i].reg));
  353. pm_runtime_put_sync(dev->dev);
  354. return 0;
  355. }
  356. static int tilcdc_mm_show(struct seq_file *m, void *arg)
  357. {
  358. struct drm_info_node *node = (struct drm_info_node *) m->private;
  359. struct drm_device *dev = node->minor->dev;
  360. struct drm_printer p = drm_seq_file_printer(m);
  361. drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
  362. return 0;
  363. }
  364. static struct drm_info_list tilcdc_debugfs_list[] = {
  365. { "regs", tilcdc_regs_show, 0, NULL },
  366. { "mm", tilcdc_mm_show, 0, NULL },
  367. };
  368. static void tilcdc_debugfs_init(struct drm_minor *minor)
  369. {
  370. struct tilcdc_module *mod;
  371. drm_debugfs_create_files(tilcdc_debugfs_list,
  372. ARRAY_SIZE(tilcdc_debugfs_list),
  373. minor->debugfs_root, minor);
  374. list_for_each_entry(mod, &module_list, list)
  375. if (mod->funcs->debugfs_init)
  376. mod->funcs->debugfs_init(mod, minor);
  377. }
  378. #endif
  379. DEFINE_DRM_GEM_DMA_FOPS(fops);
  380. static const struct drm_driver tilcdc_driver = {
  381. .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
  382. DRM_GEM_DMA_DRIVER_OPS,
  383. #ifdef CONFIG_DEBUG_FS
  384. .debugfs_init = tilcdc_debugfs_init,
  385. #endif
  386. .fops = &fops,
  387. .name = "tilcdc",
  388. .desc = "TI LCD Controller DRM",
  389. .date = "20121205",
  390. .major = 1,
  391. .minor = 0,
  392. };
  393. /*
  394. * Power management:
  395. */
  396. static int tilcdc_pm_suspend(struct device *dev)
  397. {
  398. struct drm_device *ddev = dev_get_drvdata(dev);
  399. int ret = 0;
  400. ret = drm_mode_config_helper_suspend(ddev);
  401. /* Select sleep pin state */
  402. pinctrl_pm_select_sleep_state(dev);
  403. return ret;
  404. }
  405. static int tilcdc_pm_resume(struct device *dev)
  406. {
  407. struct drm_device *ddev = dev_get_drvdata(dev);
  408. /* Select default pin state */
  409. pinctrl_pm_select_default_state(dev);
  410. return drm_mode_config_helper_resume(ddev);
  411. }
  412. static DEFINE_SIMPLE_DEV_PM_OPS(tilcdc_pm_ops,
  413. tilcdc_pm_suspend, tilcdc_pm_resume);
  414. /*
  415. * Platform driver:
  416. */
  417. static int tilcdc_bind(struct device *dev)
  418. {
  419. return tilcdc_init(&tilcdc_driver, dev);
  420. }
  421. static void tilcdc_unbind(struct device *dev)
  422. {
  423. struct drm_device *ddev = dev_get_drvdata(dev);
  424. /* Check if a subcomponent has already triggered the unloading. */
  425. if (!ddev->dev_private)
  426. return;
  427. tilcdc_fini(ddev);
  428. dev_set_drvdata(dev, NULL);
  429. }
  430. static const struct component_master_ops tilcdc_comp_ops = {
  431. .bind = tilcdc_bind,
  432. .unbind = tilcdc_unbind,
  433. };
  434. static int tilcdc_pdev_probe(struct platform_device *pdev)
  435. {
  436. struct component_match *match = NULL;
  437. int ret;
  438. /* bail out early if no DT data: */
  439. if (!pdev->dev.of_node) {
  440. dev_err(&pdev->dev, "device-tree data is missing\n");
  441. return -ENXIO;
  442. }
  443. ret = tilcdc_get_external_components(&pdev->dev, &match);
  444. if (ret < 0)
  445. return ret;
  446. else if (ret == 0)
  447. return tilcdc_init(&tilcdc_driver, &pdev->dev);
  448. else
  449. return component_master_add_with_match(&pdev->dev,
  450. &tilcdc_comp_ops,
  451. match);
  452. }
  453. static void tilcdc_pdev_remove(struct platform_device *pdev)
  454. {
  455. int ret;
  456. ret = tilcdc_get_external_components(&pdev->dev, NULL);
  457. if (ret < 0)
  458. dev_err(&pdev->dev, "tilcdc_get_external_components() failed (%pe)\n",
  459. ERR_PTR(ret));
  460. else if (ret == 0)
  461. tilcdc_fini(platform_get_drvdata(pdev));
  462. else
  463. component_master_del(&pdev->dev, &tilcdc_comp_ops);
  464. }
  465. static void tilcdc_pdev_shutdown(struct platform_device *pdev)
  466. {
  467. drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
  468. }
  469. static const struct of_device_id tilcdc_of_match[] = {
  470. { .compatible = "ti,am33xx-tilcdc", },
  471. { .compatible = "ti,da850-tilcdc", },
  472. { },
  473. };
  474. MODULE_DEVICE_TABLE(of, tilcdc_of_match);
  475. static struct platform_driver tilcdc_platform_driver = {
  476. .probe = tilcdc_pdev_probe,
  477. .remove_new = tilcdc_pdev_remove,
  478. .shutdown = tilcdc_pdev_shutdown,
  479. .driver = {
  480. .name = "tilcdc",
  481. .pm = pm_sleep_ptr(&tilcdc_pm_ops),
  482. .of_match_table = tilcdc_of_match,
  483. },
  484. };
  485. static int __init tilcdc_drm_init(void)
  486. {
  487. if (drm_firmware_drivers_only())
  488. return -ENODEV;
  489. DBG("init");
  490. tilcdc_panel_init();
  491. return platform_driver_register(&tilcdc_platform_driver);
  492. }
  493. static void __exit tilcdc_drm_fini(void)
  494. {
  495. DBG("fini");
  496. platform_driver_unregister(&tilcdc_platform_driver);
  497. tilcdc_panel_fini();
  498. }
  499. module_init(tilcdc_drm_init);
  500. module_exit(tilcdc_drm_fini);
  501. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  502. MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
  503. MODULE_LICENSE("GPL");