virtgpu_drv.h 15 KB

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  1. /*
  2. * Copyright (C) 2015 Red Hat, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining
  6. * a copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sublicense, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial
  15. * portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20. * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21. * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22. * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23. * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. */
  25. #ifndef VIRTIO_DRV_H
  26. #define VIRTIO_DRV_H
  27. #include <linux/dma-direction.h>
  28. #include <linux/virtio.h>
  29. #include <linux/virtio_ids.h>
  30. #include <linux/virtio_config.h>
  31. #include <linux/virtio_gpu.h>
  32. #include <drm/drm_atomic.h>
  33. #include <drm/drm_drv.h>
  34. #include <drm/drm_encoder.h>
  35. #include <drm/drm_fourcc.h>
  36. #include <drm/drm_framebuffer.h>
  37. #include <drm/drm_gem.h>
  38. #include <drm/drm_gem_shmem_helper.h>
  39. #include <drm/drm_ioctl.h>
  40. #include <drm/drm_probe_helper.h>
  41. #include <drm/virtgpu_drm.h>
  42. #define DRIVER_NAME "virtio_gpu"
  43. #define DRIVER_DESC "virtio GPU"
  44. #define DRIVER_DATE "0"
  45. #define DRIVER_MAJOR 0
  46. #define DRIVER_MINOR 1
  47. #define DRIVER_PATCHLEVEL 0
  48. #define STATE_INITIALIZING 0
  49. #define STATE_OK 1
  50. #define STATE_ERR 2
  51. #define MAX_CAPSET_ID 63
  52. #define MAX_RINGS 64
  53. /* See virtio_gpu_ctx_create. One additional character for NULL terminator. */
  54. #define DEBUG_NAME_MAX_LEN 65
  55. struct virtio_gpu_object_params {
  56. unsigned long size;
  57. bool dumb;
  58. /* 3d */
  59. bool virgl;
  60. bool blob;
  61. /* classic resources only */
  62. uint32_t format;
  63. uint32_t width;
  64. uint32_t height;
  65. uint32_t target;
  66. uint32_t bind;
  67. uint32_t depth;
  68. uint32_t array_size;
  69. uint32_t last_level;
  70. uint32_t nr_samples;
  71. uint32_t flags;
  72. /* blob resources only */
  73. uint32_t ctx_id;
  74. uint32_t blob_mem;
  75. uint32_t blob_flags;
  76. uint64_t blob_id;
  77. };
  78. struct virtio_gpu_object {
  79. struct drm_gem_shmem_object base;
  80. uint32_t hw_res_handle;
  81. bool dumb;
  82. bool created;
  83. bool host3d_blob, guest_blob;
  84. uint32_t blob_mem, blob_flags;
  85. int uuid_state;
  86. uuid_t uuid;
  87. };
  88. #define gem_to_virtio_gpu_obj(gobj) \
  89. container_of((gobj), struct virtio_gpu_object, base.base)
  90. struct virtio_gpu_object_shmem {
  91. struct virtio_gpu_object base;
  92. };
  93. struct virtio_gpu_object_vram {
  94. struct virtio_gpu_object base;
  95. uint32_t map_state;
  96. uint32_t map_info;
  97. struct drm_mm_node vram_node;
  98. };
  99. #define to_virtio_gpu_shmem(virtio_gpu_object) \
  100. container_of((virtio_gpu_object), struct virtio_gpu_object_shmem, base)
  101. #define to_virtio_gpu_vram(virtio_gpu_object) \
  102. container_of((virtio_gpu_object), struct virtio_gpu_object_vram, base)
  103. struct virtio_gpu_object_array {
  104. struct ww_acquire_ctx ticket;
  105. struct list_head next;
  106. u32 nents, total;
  107. struct drm_gem_object *objs[] __counted_by(total);
  108. };
  109. struct virtio_gpu_vbuffer;
  110. struct virtio_gpu_device;
  111. typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev,
  112. struct virtio_gpu_vbuffer *vbuf);
  113. struct virtio_gpu_fence_driver {
  114. atomic64_t last_fence_id;
  115. uint64_t current_fence_id;
  116. uint64_t context;
  117. struct list_head fences;
  118. spinlock_t lock;
  119. };
  120. struct virtio_gpu_fence_event {
  121. struct drm_pending_event base;
  122. struct drm_event event;
  123. };
  124. struct virtio_gpu_fence {
  125. struct dma_fence f;
  126. uint32_t ring_idx;
  127. uint64_t fence_id;
  128. bool emit_fence_info;
  129. struct virtio_gpu_fence_event *e;
  130. struct virtio_gpu_fence_driver *drv;
  131. struct list_head node;
  132. };
  133. struct virtio_gpu_vbuffer {
  134. char *buf;
  135. int size;
  136. void *data_buf;
  137. uint32_t data_size;
  138. char *resp_buf;
  139. int resp_size;
  140. virtio_gpu_resp_cb resp_cb;
  141. void *resp_cb_data;
  142. struct virtio_gpu_object_array *objs;
  143. struct list_head list;
  144. uint32_t seqno;
  145. };
  146. struct virtio_gpu_output {
  147. int index;
  148. struct drm_crtc crtc;
  149. struct drm_connector conn;
  150. struct drm_encoder enc;
  151. struct virtio_gpu_display_one info;
  152. struct virtio_gpu_update_cursor cursor;
  153. const struct drm_edid *drm_edid;
  154. int cur_x;
  155. int cur_y;
  156. bool needs_modeset;
  157. };
  158. #define drm_crtc_to_virtio_gpu_output(x) \
  159. container_of(x, struct virtio_gpu_output, crtc)
  160. struct virtio_gpu_framebuffer {
  161. struct drm_framebuffer base;
  162. struct virtio_gpu_fence *fence;
  163. };
  164. #define to_virtio_gpu_framebuffer(x) \
  165. container_of(x, struct virtio_gpu_framebuffer, base)
  166. struct virtio_gpu_plane_state {
  167. struct drm_plane_state base;
  168. struct virtio_gpu_fence *fence;
  169. };
  170. #define to_virtio_gpu_plane_state(x) \
  171. container_of(x, struct virtio_gpu_plane_state, base)
  172. struct virtio_gpu_queue {
  173. struct virtqueue *vq;
  174. spinlock_t qlock;
  175. wait_queue_head_t ack_queue;
  176. struct work_struct dequeue_work;
  177. uint32_t seqno;
  178. };
  179. struct virtio_gpu_drv_capset {
  180. uint32_t id;
  181. uint32_t max_version;
  182. uint32_t max_size;
  183. };
  184. struct virtio_gpu_drv_cap_cache {
  185. struct list_head head;
  186. void *caps_cache;
  187. uint32_t id;
  188. uint32_t version;
  189. uint32_t size;
  190. atomic_t is_valid;
  191. };
  192. struct virtio_gpu_device {
  193. struct drm_device *ddev;
  194. struct virtio_device *vdev;
  195. struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS];
  196. uint32_t num_scanouts;
  197. struct virtio_gpu_queue ctrlq;
  198. struct virtio_gpu_queue cursorq;
  199. struct kmem_cache *vbufs;
  200. atomic_t pending_commands;
  201. struct ida resource_ida;
  202. wait_queue_head_t resp_wq;
  203. /* current display info */
  204. spinlock_t display_info_lock;
  205. bool display_info_pending;
  206. struct virtio_gpu_fence_driver fence_drv;
  207. struct ida ctx_id_ida;
  208. bool has_virgl_3d;
  209. bool has_edid;
  210. bool has_indirect;
  211. bool has_resource_assign_uuid;
  212. bool has_resource_blob;
  213. bool has_host_visible;
  214. bool has_context_init;
  215. struct virtio_shm_region host_visible_region;
  216. struct drm_mm host_visible_mm;
  217. struct work_struct config_changed_work;
  218. struct work_struct obj_free_work;
  219. spinlock_t obj_free_lock;
  220. struct list_head obj_free_list;
  221. struct virtio_gpu_drv_capset *capsets;
  222. uint32_t num_capsets;
  223. uint64_t capset_id_mask;
  224. struct list_head cap_cache;
  225. /* protects uuid state when exporting */
  226. spinlock_t resource_export_lock;
  227. /* protects map state and host_visible_mm */
  228. spinlock_t host_visible_lock;
  229. };
  230. struct virtio_gpu_fpriv {
  231. uint32_t ctx_id;
  232. uint32_t context_init;
  233. bool context_created;
  234. uint32_t num_rings;
  235. uint64_t base_fence_ctx;
  236. uint64_t ring_idx_mask;
  237. struct mutex context_lock;
  238. char debug_name[DEBUG_NAME_MAX_LEN];
  239. bool explicit_debug_name;
  240. };
  241. /* virtgpu_ioctl.c */
  242. #define DRM_VIRTIO_NUM_IOCTLS 12
  243. extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];
  244. void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file);
  245. /* virtgpu_kms.c */
  246. int virtio_gpu_init(struct virtio_device *vdev, struct drm_device *dev);
  247. void virtio_gpu_deinit(struct drm_device *dev);
  248. void virtio_gpu_release(struct drm_device *dev);
  249. int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file);
  250. void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file);
  251. /* virtgpu_gem.c */
  252. int virtio_gpu_gem_object_open(struct drm_gem_object *obj,
  253. struct drm_file *file);
  254. void virtio_gpu_gem_object_close(struct drm_gem_object *obj,
  255. struct drm_file *file);
  256. int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
  257. struct drm_device *dev,
  258. struct drm_mode_create_dumb *args);
  259. int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv,
  260. struct drm_device *dev,
  261. uint32_t handle, uint64_t *offset_p);
  262. struct virtio_gpu_object_array *virtio_gpu_array_alloc(u32 nents);
  263. struct virtio_gpu_object_array*
  264. virtio_gpu_array_from_handles(struct drm_file *drm_file, u32 *handles, u32 nents);
  265. void virtio_gpu_array_add_obj(struct virtio_gpu_object_array *objs,
  266. struct drm_gem_object *obj);
  267. int virtio_gpu_array_lock_resv(struct virtio_gpu_object_array *objs);
  268. void virtio_gpu_array_unlock_resv(struct virtio_gpu_object_array *objs);
  269. void virtio_gpu_array_add_fence(struct virtio_gpu_object_array *objs,
  270. struct dma_fence *fence);
  271. void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs);
  272. void virtio_gpu_array_put_free_delayed(struct virtio_gpu_device *vgdev,
  273. struct virtio_gpu_object_array *objs);
  274. void virtio_gpu_array_put_free_work(struct work_struct *work);
  275. /* virtgpu_vq.c */
  276. int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev);
  277. void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev);
  278. void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
  279. struct virtio_gpu_object *bo,
  280. struct virtio_gpu_object_params *params,
  281. struct virtio_gpu_object_array *objs,
  282. struct virtio_gpu_fence *fence);
  283. void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
  284. struct virtio_gpu_object *bo);
  285. void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
  286. uint64_t offset,
  287. uint32_t width, uint32_t height,
  288. uint32_t x, uint32_t y,
  289. struct virtio_gpu_object_array *objs,
  290. struct virtio_gpu_fence *fence);
  291. void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
  292. uint32_t resource_id,
  293. uint32_t x, uint32_t y,
  294. uint32_t width, uint32_t height,
  295. struct virtio_gpu_object_array *objs,
  296. struct virtio_gpu_fence *fence);
  297. void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
  298. uint32_t scanout_id, uint32_t resource_id,
  299. uint32_t width, uint32_t height,
  300. uint32_t x, uint32_t y);
  301. void virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
  302. struct virtio_gpu_object *obj,
  303. struct virtio_gpu_mem_entry *ents,
  304. unsigned int nents);
  305. void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
  306. struct virtio_gpu_output *output);
  307. int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev);
  308. int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx);
  309. int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
  310. int idx, int version,
  311. struct virtio_gpu_drv_cap_cache **cache_p);
  312. int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev);
  313. void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
  314. uint32_t context_init, uint32_t nlen,
  315. const char *name);
  316. void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
  317. uint32_t id);
  318. void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
  319. uint32_t ctx_id,
  320. struct virtio_gpu_object_array *objs);
  321. void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
  322. uint32_t ctx_id,
  323. struct virtio_gpu_object_array *objs);
  324. void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
  325. void *data, uint32_t data_size,
  326. uint32_t ctx_id,
  327. struct virtio_gpu_object_array *objs,
  328. struct virtio_gpu_fence *fence);
  329. void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
  330. uint32_t ctx_id,
  331. uint64_t offset, uint32_t level,
  332. uint32_t stride,
  333. uint32_t layer_stride,
  334. struct drm_virtgpu_3d_box *box,
  335. struct virtio_gpu_object_array *objs,
  336. struct virtio_gpu_fence *fence);
  337. void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
  338. uint32_t ctx_id,
  339. uint64_t offset, uint32_t level,
  340. uint32_t stride,
  341. uint32_t layer_stride,
  342. struct drm_virtgpu_3d_box *box,
  343. struct virtio_gpu_object_array *objs,
  344. struct virtio_gpu_fence *fence);
  345. void
  346. virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
  347. struct virtio_gpu_object *bo,
  348. struct virtio_gpu_object_params *params,
  349. struct virtio_gpu_object_array *objs,
  350. struct virtio_gpu_fence *fence);
  351. void virtio_gpu_ctrl_ack(struct virtqueue *vq);
  352. void virtio_gpu_cursor_ack(struct virtqueue *vq);
  353. void virtio_gpu_dequeue_ctrl_func(struct work_struct *work);
  354. void virtio_gpu_dequeue_cursor_func(struct work_struct *work);
  355. void virtio_gpu_notify(struct virtio_gpu_device *vgdev);
  356. int
  357. virtio_gpu_cmd_resource_assign_uuid(struct virtio_gpu_device *vgdev,
  358. struct virtio_gpu_object_array *objs);
  359. int virtio_gpu_cmd_map(struct virtio_gpu_device *vgdev,
  360. struct virtio_gpu_object_array *objs, uint64_t offset);
  361. void virtio_gpu_cmd_unmap(struct virtio_gpu_device *vgdev,
  362. struct virtio_gpu_object *bo);
  363. void
  364. virtio_gpu_cmd_resource_create_blob(struct virtio_gpu_device *vgdev,
  365. struct virtio_gpu_object *bo,
  366. struct virtio_gpu_object_params *params,
  367. struct virtio_gpu_mem_entry *ents,
  368. uint32_t nents);
  369. void
  370. virtio_gpu_cmd_set_scanout_blob(struct virtio_gpu_device *vgdev,
  371. uint32_t scanout_id,
  372. struct virtio_gpu_object *bo,
  373. struct drm_framebuffer *fb,
  374. uint32_t width, uint32_t height,
  375. uint32_t x, uint32_t y);
  376. /* virtgpu_display.c */
  377. int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev);
  378. void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev);
  379. /* virtgpu_plane.c */
  380. uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc);
  381. struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
  382. enum drm_plane_type type,
  383. int index);
  384. /* virtgpu_fence.c */
  385. struct virtio_gpu_fence *virtio_gpu_fence_alloc(struct virtio_gpu_device *vgdev,
  386. uint64_t base_fence_ctx,
  387. uint32_t ring_idx);
  388. void virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev,
  389. struct virtio_gpu_ctrl_hdr *cmd_hdr,
  390. struct virtio_gpu_fence *fence);
  391. void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev,
  392. u64 fence_id);
  393. /* virtgpu_object.c */
  394. void virtio_gpu_cleanup_object(struct virtio_gpu_object *bo);
  395. struct drm_gem_object *virtio_gpu_create_object(struct drm_device *dev,
  396. size_t size);
  397. int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,
  398. struct virtio_gpu_object_params *params,
  399. struct virtio_gpu_object **bo_ptr,
  400. struct virtio_gpu_fence *fence);
  401. bool virtio_gpu_is_shmem(struct virtio_gpu_object *bo);
  402. int virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev,
  403. uint32_t *resid);
  404. /* virtgpu_prime.c */
  405. int virtio_gpu_resource_assign_uuid(struct virtio_gpu_device *vgdev,
  406. struct virtio_gpu_object *bo);
  407. struct dma_buf *virtgpu_gem_prime_export(struct drm_gem_object *obj,
  408. int flags);
  409. struct drm_gem_object *virtgpu_gem_prime_import(struct drm_device *dev,
  410. struct dma_buf *buf);
  411. struct drm_gem_object *virtgpu_gem_prime_import_sg_table(
  412. struct drm_device *dev, struct dma_buf_attachment *attach,
  413. struct sg_table *sgt);
  414. /* virtgpu_debugfs.c */
  415. void virtio_gpu_debugfs_init(struct drm_minor *minor);
  416. /* virtgpu_vram.c */
  417. bool virtio_gpu_is_vram(struct virtio_gpu_object *bo);
  418. int virtio_gpu_vram_create(struct virtio_gpu_device *vgdev,
  419. struct virtio_gpu_object_params *params,
  420. struct virtio_gpu_object **bo_ptr);
  421. struct sg_table *virtio_gpu_vram_map_dma_buf(struct virtio_gpu_object *bo,
  422. struct device *dev,
  423. enum dma_data_direction dir);
  424. void virtio_gpu_vram_unmap_dma_buf(struct device *dev,
  425. struct sg_table *sgt,
  426. enum dma_data_direction dir);
  427. /* virtgpu_submit.c */
  428. int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
  429. struct drm_file *file);
  430. #endif