virtgpu_ioctl.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735
  1. /*
  2. * Copyright (C) 2015 Red Hat, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Authors:
  6. * Dave Airlie
  7. * Alon Levy
  8. *
  9. * Permission is hereby granted, free of charge, to any person obtaining a
  10. * copy of this software and associated documentation files (the "Software"),
  11. * to deal in the Software without restriction, including without limitation
  12. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13. * and/or sell copies of the Software, and to permit persons to whom the
  14. * Software is furnished to do so, subject to the following conditions:
  15. *
  16. * The above copyright notice and this permission notice shall be included in
  17. * all copies or substantial portions of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25. * OTHER DEALINGS IN THE SOFTWARE.
  26. */
  27. #include <linux/file.h>
  28. #include <linux/sync_file.h>
  29. #include <linux/uaccess.h>
  30. #include <drm/drm_file.h>
  31. #include <drm/virtgpu_drm.h>
  32. #include "virtgpu_drv.h"
  33. #define VIRTGPU_BLOB_FLAG_USE_MASK (VIRTGPU_BLOB_FLAG_USE_MAPPABLE | \
  34. VIRTGPU_BLOB_FLAG_USE_SHAREABLE | \
  35. VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE)
  36. /* Must be called with &virtio_gpu_fpriv.struct_mutex held. */
  37. static void virtio_gpu_create_context_locked(struct virtio_gpu_device *vgdev,
  38. struct virtio_gpu_fpriv *vfpriv)
  39. {
  40. if (vfpriv->explicit_debug_name) {
  41. virtio_gpu_cmd_context_create(vgdev, vfpriv->ctx_id,
  42. vfpriv->context_init,
  43. strlen(vfpriv->debug_name),
  44. vfpriv->debug_name);
  45. } else {
  46. char dbgname[TASK_COMM_LEN];
  47. get_task_comm(dbgname, current);
  48. virtio_gpu_cmd_context_create(vgdev, vfpriv->ctx_id,
  49. vfpriv->context_init, strlen(dbgname),
  50. dbgname);
  51. }
  52. vfpriv->context_created = true;
  53. }
  54. void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file)
  55. {
  56. struct virtio_gpu_device *vgdev = dev->dev_private;
  57. struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
  58. mutex_lock(&vfpriv->context_lock);
  59. if (vfpriv->context_created)
  60. goto out_unlock;
  61. virtio_gpu_create_context_locked(vgdev, vfpriv);
  62. out_unlock:
  63. mutex_unlock(&vfpriv->context_lock);
  64. }
  65. static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
  66. struct drm_file *file)
  67. {
  68. struct virtio_gpu_device *vgdev = dev->dev_private;
  69. struct drm_virtgpu_map *virtio_gpu_map = data;
  70. return virtio_gpu_mode_dumb_mmap(file, vgdev->ddev,
  71. virtio_gpu_map->handle,
  72. &virtio_gpu_map->offset);
  73. }
  74. static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
  75. struct drm_file *file)
  76. {
  77. struct virtio_gpu_device *vgdev = dev->dev_private;
  78. struct drm_virtgpu_getparam *param = data;
  79. int value;
  80. switch (param->param) {
  81. case VIRTGPU_PARAM_3D_FEATURES:
  82. value = vgdev->has_virgl_3d ? 1 : 0;
  83. break;
  84. case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
  85. value = 1;
  86. break;
  87. case VIRTGPU_PARAM_RESOURCE_BLOB:
  88. value = vgdev->has_resource_blob ? 1 : 0;
  89. break;
  90. case VIRTGPU_PARAM_HOST_VISIBLE:
  91. value = vgdev->has_host_visible ? 1 : 0;
  92. break;
  93. case VIRTGPU_PARAM_CROSS_DEVICE:
  94. value = vgdev->has_resource_assign_uuid ? 1 : 0;
  95. break;
  96. case VIRTGPU_PARAM_CONTEXT_INIT:
  97. value = vgdev->has_context_init ? 1 : 0;
  98. break;
  99. case VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs:
  100. value = vgdev->capset_id_mask;
  101. break;
  102. case VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME:
  103. value = vgdev->has_context_init ? 1 : 0;
  104. break;
  105. default:
  106. return -EINVAL;
  107. }
  108. if (copy_to_user(u64_to_user_ptr(param->value), &value, sizeof(int)))
  109. return -EFAULT;
  110. return 0;
  111. }
  112. static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
  113. struct drm_file *file)
  114. {
  115. struct virtio_gpu_device *vgdev = dev->dev_private;
  116. struct drm_virtgpu_resource_create *rc = data;
  117. struct virtio_gpu_fence *fence;
  118. int ret;
  119. struct virtio_gpu_object *qobj;
  120. struct drm_gem_object *obj;
  121. uint32_t handle = 0;
  122. struct virtio_gpu_object_params params = { 0 };
  123. if (vgdev->has_virgl_3d) {
  124. virtio_gpu_create_context(dev, file);
  125. params.virgl = true;
  126. params.target = rc->target;
  127. params.bind = rc->bind;
  128. params.depth = rc->depth;
  129. params.array_size = rc->array_size;
  130. params.last_level = rc->last_level;
  131. params.nr_samples = rc->nr_samples;
  132. params.flags = rc->flags;
  133. } else {
  134. if (rc->depth > 1)
  135. return -EINVAL;
  136. if (rc->nr_samples > 1)
  137. return -EINVAL;
  138. if (rc->last_level > 1)
  139. return -EINVAL;
  140. if (rc->target != 2)
  141. return -EINVAL;
  142. if (rc->array_size > 1)
  143. return -EINVAL;
  144. }
  145. params.format = rc->format;
  146. params.width = rc->width;
  147. params.height = rc->height;
  148. params.size = rc->size;
  149. /* allocate a single page size object */
  150. if (params.size == 0)
  151. params.size = PAGE_SIZE;
  152. fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context, 0);
  153. if (!fence)
  154. return -ENOMEM;
  155. ret = virtio_gpu_object_create(vgdev, &params, &qobj, fence);
  156. dma_fence_put(&fence->f);
  157. if (ret < 0)
  158. return ret;
  159. obj = &qobj->base.base;
  160. ret = drm_gem_handle_create(file, obj, &handle);
  161. if (ret) {
  162. drm_gem_object_release(obj);
  163. return ret;
  164. }
  165. rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */
  166. rc->bo_handle = handle;
  167. /*
  168. * The handle owns the reference now. But we must drop our
  169. * remaining reference *after* we no longer need to dereference
  170. * the obj. Otherwise userspace could guess the handle and
  171. * race closing it from another thread.
  172. */
  173. drm_gem_object_put(obj);
  174. return 0;
  175. }
  176. static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
  177. struct drm_file *file)
  178. {
  179. struct drm_virtgpu_resource_info *ri = data;
  180. struct drm_gem_object *gobj = NULL;
  181. struct virtio_gpu_object *qobj = NULL;
  182. gobj = drm_gem_object_lookup(file, ri->bo_handle);
  183. if (gobj == NULL)
  184. return -ENOENT;
  185. qobj = gem_to_virtio_gpu_obj(gobj);
  186. ri->size = qobj->base.base.size;
  187. ri->res_handle = qobj->hw_res_handle;
  188. if (qobj->host3d_blob || qobj->guest_blob)
  189. ri->blob_mem = qobj->blob_mem;
  190. drm_gem_object_put(gobj);
  191. return 0;
  192. }
  193. static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
  194. void *data,
  195. struct drm_file *file)
  196. {
  197. struct virtio_gpu_device *vgdev = dev->dev_private;
  198. struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
  199. struct drm_virtgpu_3d_transfer_from_host *args = data;
  200. struct virtio_gpu_object *bo;
  201. struct virtio_gpu_object_array *objs;
  202. struct virtio_gpu_fence *fence;
  203. int ret;
  204. u32 offset = args->offset;
  205. if (vgdev->has_virgl_3d == false)
  206. return -ENOSYS;
  207. virtio_gpu_create_context(dev, file);
  208. objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
  209. if (objs == NULL)
  210. return -ENOENT;
  211. bo = gem_to_virtio_gpu_obj(objs->objs[0]);
  212. if (bo->guest_blob && !bo->host3d_blob) {
  213. ret = -EINVAL;
  214. goto err_put_free;
  215. }
  216. if (!bo->host3d_blob && (args->stride || args->layer_stride)) {
  217. ret = -EINVAL;
  218. goto err_put_free;
  219. }
  220. ret = virtio_gpu_array_lock_resv(objs);
  221. if (ret != 0)
  222. goto err_put_free;
  223. fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context, 0);
  224. if (!fence) {
  225. ret = -ENOMEM;
  226. goto err_unlock;
  227. }
  228. virtio_gpu_cmd_transfer_from_host_3d
  229. (vgdev, vfpriv->ctx_id, offset, args->level, args->stride,
  230. args->layer_stride, &args->box, objs, fence);
  231. dma_fence_put(&fence->f);
  232. virtio_gpu_notify(vgdev);
  233. return 0;
  234. err_unlock:
  235. virtio_gpu_array_unlock_resv(objs);
  236. err_put_free:
  237. virtio_gpu_array_put_free(objs);
  238. return ret;
  239. }
  240. static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
  241. struct drm_file *file)
  242. {
  243. struct virtio_gpu_device *vgdev = dev->dev_private;
  244. struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
  245. struct drm_virtgpu_3d_transfer_to_host *args = data;
  246. struct virtio_gpu_object *bo;
  247. struct virtio_gpu_object_array *objs;
  248. struct virtio_gpu_fence *fence;
  249. int ret;
  250. u32 offset = args->offset;
  251. objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
  252. if (objs == NULL)
  253. return -ENOENT;
  254. bo = gem_to_virtio_gpu_obj(objs->objs[0]);
  255. if (bo->guest_blob && !bo->host3d_blob) {
  256. ret = -EINVAL;
  257. goto err_put_free;
  258. }
  259. if (!vgdev->has_virgl_3d) {
  260. virtio_gpu_cmd_transfer_to_host_2d
  261. (vgdev, offset,
  262. args->box.w, args->box.h, args->box.x, args->box.y,
  263. objs, NULL);
  264. } else {
  265. virtio_gpu_create_context(dev, file);
  266. if (!bo->host3d_blob && (args->stride || args->layer_stride)) {
  267. ret = -EINVAL;
  268. goto err_put_free;
  269. }
  270. ret = virtio_gpu_array_lock_resv(objs);
  271. if (ret != 0)
  272. goto err_put_free;
  273. ret = -ENOMEM;
  274. fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context,
  275. 0);
  276. if (!fence)
  277. goto err_unlock;
  278. virtio_gpu_cmd_transfer_to_host_3d
  279. (vgdev,
  280. vfpriv ? vfpriv->ctx_id : 0, offset, args->level,
  281. args->stride, args->layer_stride, &args->box, objs,
  282. fence);
  283. dma_fence_put(&fence->f);
  284. }
  285. virtio_gpu_notify(vgdev);
  286. return 0;
  287. err_unlock:
  288. virtio_gpu_array_unlock_resv(objs);
  289. err_put_free:
  290. virtio_gpu_array_put_free(objs);
  291. return ret;
  292. }
  293. static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
  294. struct drm_file *file)
  295. {
  296. struct drm_virtgpu_3d_wait *args = data;
  297. struct drm_gem_object *obj;
  298. long timeout = 15 * HZ;
  299. int ret;
  300. obj = drm_gem_object_lookup(file, args->handle);
  301. if (obj == NULL)
  302. return -ENOENT;
  303. if (args->flags & VIRTGPU_WAIT_NOWAIT) {
  304. ret = dma_resv_test_signaled(obj->resv, DMA_RESV_USAGE_READ);
  305. } else {
  306. ret = dma_resv_wait_timeout(obj->resv, DMA_RESV_USAGE_READ,
  307. true, timeout);
  308. }
  309. if (ret == 0)
  310. ret = -EBUSY;
  311. else if (ret > 0)
  312. ret = 0;
  313. drm_gem_object_put(obj);
  314. return ret;
  315. }
  316. static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
  317. void *data, struct drm_file *file)
  318. {
  319. struct virtio_gpu_device *vgdev = dev->dev_private;
  320. struct drm_virtgpu_get_caps *args = data;
  321. unsigned size, host_caps_size;
  322. int i;
  323. int found_valid = -1;
  324. int ret;
  325. struct virtio_gpu_drv_cap_cache *cache_ent;
  326. void *ptr;
  327. if (vgdev->num_capsets == 0)
  328. return -ENOSYS;
  329. /* don't allow userspace to pass 0 */
  330. if (args->size == 0)
  331. return -EINVAL;
  332. spin_lock(&vgdev->display_info_lock);
  333. for (i = 0; i < vgdev->num_capsets; i++) {
  334. if (vgdev->capsets[i].id == args->cap_set_id) {
  335. if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
  336. found_valid = i;
  337. break;
  338. }
  339. }
  340. }
  341. if (found_valid == -1) {
  342. spin_unlock(&vgdev->display_info_lock);
  343. return -EINVAL;
  344. }
  345. host_caps_size = vgdev->capsets[found_valid].max_size;
  346. /* only copy to user the minimum of the host caps size or the guest caps size */
  347. size = min(args->size, host_caps_size);
  348. list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
  349. if (cache_ent->id == args->cap_set_id &&
  350. cache_ent->version == args->cap_set_ver) {
  351. spin_unlock(&vgdev->display_info_lock);
  352. goto copy_exit;
  353. }
  354. }
  355. spin_unlock(&vgdev->display_info_lock);
  356. /* not in cache - need to talk to hw */
  357. ret = virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
  358. &cache_ent);
  359. if (ret)
  360. return ret;
  361. virtio_gpu_notify(vgdev);
  362. copy_exit:
  363. ret = wait_event_timeout(vgdev->resp_wq,
  364. atomic_read(&cache_ent->is_valid), 5 * HZ);
  365. if (!ret)
  366. return -EBUSY;
  367. /* is_valid check must proceed before copy of the cache entry. */
  368. smp_rmb();
  369. ptr = cache_ent->caps_cache;
  370. if (copy_to_user(u64_to_user_ptr(args->addr), ptr, size))
  371. return -EFAULT;
  372. return 0;
  373. }
  374. static int verify_blob(struct virtio_gpu_device *vgdev,
  375. struct virtio_gpu_fpriv *vfpriv,
  376. struct virtio_gpu_object_params *params,
  377. struct drm_virtgpu_resource_create_blob *rc_blob,
  378. bool *guest_blob, bool *host3d_blob)
  379. {
  380. if (!vgdev->has_resource_blob)
  381. return -EINVAL;
  382. if (rc_blob->blob_flags & ~VIRTGPU_BLOB_FLAG_USE_MASK)
  383. return -EINVAL;
  384. if (rc_blob->blob_flags & VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE) {
  385. if (!vgdev->has_resource_assign_uuid)
  386. return -EINVAL;
  387. }
  388. switch (rc_blob->blob_mem) {
  389. case VIRTGPU_BLOB_MEM_GUEST:
  390. *guest_blob = true;
  391. break;
  392. case VIRTGPU_BLOB_MEM_HOST3D_GUEST:
  393. *guest_blob = true;
  394. fallthrough;
  395. case VIRTGPU_BLOB_MEM_HOST3D:
  396. *host3d_blob = true;
  397. break;
  398. default:
  399. return -EINVAL;
  400. }
  401. if (*host3d_blob) {
  402. if (!vgdev->has_virgl_3d)
  403. return -EINVAL;
  404. /* Must be dword aligned. */
  405. if (rc_blob->cmd_size % 4 != 0)
  406. return -EINVAL;
  407. params->ctx_id = vfpriv->ctx_id;
  408. params->blob_id = rc_blob->blob_id;
  409. } else {
  410. if (rc_blob->blob_id != 0)
  411. return -EINVAL;
  412. if (rc_blob->cmd_size != 0)
  413. return -EINVAL;
  414. }
  415. params->blob_mem = rc_blob->blob_mem;
  416. params->size = rc_blob->size;
  417. params->blob = true;
  418. params->blob_flags = rc_blob->blob_flags;
  419. return 0;
  420. }
  421. static int virtio_gpu_resource_create_blob_ioctl(struct drm_device *dev,
  422. void *data,
  423. struct drm_file *file)
  424. {
  425. int ret = 0;
  426. uint32_t handle = 0;
  427. bool guest_blob = false;
  428. bool host3d_blob = false;
  429. struct drm_gem_object *obj;
  430. struct virtio_gpu_object *bo;
  431. struct virtio_gpu_object_params params = { 0 };
  432. struct virtio_gpu_device *vgdev = dev->dev_private;
  433. struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
  434. struct drm_virtgpu_resource_create_blob *rc_blob = data;
  435. if (verify_blob(vgdev, vfpriv, &params, rc_blob,
  436. &guest_blob, &host3d_blob))
  437. return -EINVAL;
  438. if (vgdev->has_virgl_3d)
  439. virtio_gpu_create_context(dev, file);
  440. if (rc_blob->cmd_size) {
  441. void *buf;
  442. buf = memdup_user(u64_to_user_ptr(rc_blob->cmd),
  443. rc_blob->cmd_size);
  444. if (IS_ERR(buf))
  445. return PTR_ERR(buf);
  446. virtio_gpu_cmd_submit(vgdev, buf, rc_blob->cmd_size,
  447. vfpriv->ctx_id, NULL, NULL);
  448. }
  449. if (guest_blob)
  450. ret = virtio_gpu_object_create(vgdev, &params, &bo, NULL);
  451. else if (!guest_blob && host3d_blob)
  452. ret = virtio_gpu_vram_create(vgdev, &params, &bo);
  453. else
  454. return -EINVAL;
  455. if (ret < 0)
  456. return ret;
  457. bo->guest_blob = guest_blob;
  458. bo->host3d_blob = host3d_blob;
  459. bo->blob_mem = rc_blob->blob_mem;
  460. bo->blob_flags = rc_blob->blob_flags;
  461. obj = &bo->base.base;
  462. if (params.blob_flags & VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE) {
  463. ret = virtio_gpu_resource_assign_uuid(vgdev, bo);
  464. if (ret) {
  465. drm_gem_object_release(obj);
  466. return ret;
  467. }
  468. }
  469. ret = drm_gem_handle_create(file, obj, &handle);
  470. if (ret) {
  471. drm_gem_object_release(obj);
  472. return ret;
  473. }
  474. rc_blob->res_handle = bo->hw_res_handle;
  475. rc_blob->bo_handle = handle;
  476. /*
  477. * The handle owns the reference now. But we must drop our
  478. * remaining reference *after* we no longer need to dereference
  479. * the obj. Otherwise userspace could guess the handle and
  480. * race closing it from another thread.
  481. */
  482. drm_gem_object_put(obj);
  483. return 0;
  484. }
  485. static int virtio_gpu_context_init_ioctl(struct drm_device *dev,
  486. void *data, struct drm_file *file)
  487. {
  488. int ret = 0;
  489. uint32_t num_params, i;
  490. uint64_t valid_ring_mask, param, value;
  491. size_t len;
  492. struct drm_virtgpu_context_set_param *ctx_set_params = NULL;
  493. struct virtio_gpu_device *vgdev = dev->dev_private;
  494. struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
  495. struct drm_virtgpu_context_init *args = data;
  496. num_params = args->num_params;
  497. len = num_params * sizeof(struct drm_virtgpu_context_set_param);
  498. if (!vgdev->has_context_init || !vgdev->has_virgl_3d)
  499. return -EINVAL;
  500. /* Number of unique parameters supported at this time. */
  501. if (num_params > 4)
  502. return -EINVAL;
  503. ctx_set_params = memdup_user(u64_to_user_ptr(args->ctx_set_params),
  504. len);
  505. if (IS_ERR(ctx_set_params))
  506. return PTR_ERR(ctx_set_params);
  507. mutex_lock(&vfpriv->context_lock);
  508. if (vfpriv->context_created) {
  509. ret = -EEXIST;
  510. goto out_unlock;
  511. }
  512. for (i = 0; i < num_params; i++) {
  513. param = ctx_set_params[i].param;
  514. value = ctx_set_params[i].value;
  515. switch (param) {
  516. case VIRTGPU_CONTEXT_PARAM_CAPSET_ID:
  517. if (value > MAX_CAPSET_ID) {
  518. ret = -EINVAL;
  519. goto out_unlock;
  520. }
  521. if ((vgdev->capset_id_mask & (1ULL << value)) == 0) {
  522. ret = -EINVAL;
  523. goto out_unlock;
  524. }
  525. /* Context capset ID already set */
  526. if (vfpriv->context_init &
  527. VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK) {
  528. ret = -EINVAL;
  529. goto out_unlock;
  530. }
  531. vfpriv->context_init |= value;
  532. break;
  533. case VIRTGPU_CONTEXT_PARAM_NUM_RINGS:
  534. if (vfpriv->base_fence_ctx) {
  535. ret = -EINVAL;
  536. goto out_unlock;
  537. }
  538. if (value > MAX_RINGS) {
  539. ret = -EINVAL;
  540. goto out_unlock;
  541. }
  542. vfpriv->base_fence_ctx = dma_fence_context_alloc(value);
  543. vfpriv->num_rings = value;
  544. break;
  545. case VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK:
  546. if (vfpriv->ring_idx_mask) {
  547. ret = -EINVAL;
  548. goto out_unlock;
  549. }
  550. vfpriv->ring_idx_mask = value;
  551. break;
  552. case VIRTGPU_CONTEXT_PARAM_DEBUG_NAME:
  553. if (vfpriv->explicit_debug_name) {
  554. ret = -EINVAL;
  555. goto out_unlock;
  556. }
  557. ret = strncpy_from_user(vfpriv->debug_name,
  558. u64_to_user_ptr(value),
  559. DEBUG_NAME_MAX_LEN - 1);
  560. if (ret < 0)
  561. goto out_unlock;
  562. vfpriv->explicit_debug_name = true;
  563. ret = 0;
  564. break;
  565. default:
  566. ret = -EINVAL;
  567. goto out_unlock;
  568. }
  569. }
  570. if (vfpriv->ring_idx_mask) {
  571. valid_ring_mask = 0;
  572. for (i = 0; i < vfpriv->num_rings; i++)
  573. valid_ring_mask |= 1ULL << i;
  574. if (~valid_ring_mask & vfpriv->ring_idx_mask) {
  575. ret = -EINVAL;
  576. goto out_unlock;
  577. }
  578. }
  579. virtio_gpu_create_context_locked(vgdev, vfpriv);
  580. virtio_gpu_notify(vgdev);
  581. out_unlock:
  582. mutex_unlock(&vfpriv->context_lock);
  583. kfree(ctx_set_params);
  584. return ret;
  585. }
  586. struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
  587. DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
  588. DRM_RENDER_ALLOW),
  589. DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
  590. DRM_RENDER_ALLOW),
  591. DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
  592. DRM_RENDER_ALLOW),
  593. DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
  594. virtio_gpu_resource_create_ioctl,
  595. DRM_RENDER_ALLOW),
  596. DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
  597. DRM_RENDER_ALLOW),
  598. /* make transfer async to the main ring? - no sure, can we
  599. * thread these in the underlying GL
  600. */
  601. DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
  602. virtio_gpu_transfer_from_host_ioctl,
  603. DRM_RENDER_ALLOW),
  604. DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
  605. virtio_gpu_transfer_to_host_ioctl,
  606. DRM_RENDER_ALLOW),
  607. DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
  608. DRM_RENDER_ALLOW),
  609. DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
  610. DRM_RENDER_ALLOW),
  611. DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE_BLOB,
  612. virtio_gpu_resource_create_blob_ioctl,
  613. DRM_RENDER_ALLOW),
  614. DRM_IOCTL_DEF_DRV(VIRTGPU_CONTEXT_INIT, virtio_gpu_context_init_ioctl,
  615. DRM_RENDER_ALLOW),
  616. };