utils.c 66 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
  2. /* Copyright (c) 2015 - 2021 Intel Corporation */
  3. #include "main.h"
  4. /**
  5. * irdma_arp_table -manage arp table
  6. * @rf: RDMA PCI function
  7. * @ip_addr: ip address for device
  8. * @ipv4: IPv4 flag
  9. * @mac_addr: mac address ptr
  10. * @action: modify, delete or add
  11. */
  12. int irdma_arp_table(struct irdma_pci_f *rf, u32 *ip_addr, bool ipv4,
  13. const u8 *mac_addr, u32 action)
  14. {
  15. unsigned long flags;
  16. int arp_index;
  17. u32 ip[4] = {};
  18. if (ipv4)
  19. ip[0] = *ip_addr;
  20. else
  21. memcpy(ip, ip_addr, sizeof(ip));
  22. spin_lock_irqsave(&rf->arp_lock, flags);
  23. for (arp_index = 0; (u32)arp_index < rf->arp_table_size; arp_index++) {
  24. if (!memcmp(rf->arp_table[arp_index].ip_addr, ip, sizeof(ip)))
  25. break;
  26. }
  27. switch (action) {
  28. case IRDMA_ARP_ADD:
  29. if (arp_index != rf->arp_table_size) {
  30. arp_index = -1;
  31. break;
  32. }
  33. arp_index = 0;
  34. if (irdma_alloc_rsrc(rf, rf->allocated_arps, rf->arp_table_size,
  35. (u32 *)&arp_index, &rf->next_arp_index)) {
  36. arp_index = -1;
  37. break;
  38. }
  39. memcpy(rf->arp_table[arp_index].ip_addr, ip,
  40. sizeof(rf->arp_table[arp_index].ip_addr));
  41. ether_addr_copy(rf->arp_table[arp_index].mac_addr, mac_addr);
  42. break;
  43. case IRDMA_ARP_RESOLVE:
  44. if (arp_index == rf->arp_table_size)
  45. arp_index = -1;
  46. break;
  47. case IRDMA_ARP_DELETE:
  48. if (arp_index == rf->arp_table_size) {
  49. arp_index = -1;
  50. break;
  51. }
  52. memset(rf->arp_table[arp_index].ip_addr, 0,
  53. sizeof(rf->arp_table[arp_index].ip_addr));
  54. eth_zero_addr(rf->arp_table[arp_index].mac_addr);
  55. irdma_free_rsrc(rf, rf->allocated_arps, arp_index);
  56. break;
  57. default:
  58. arp_index = -1;
  59. break;
  60. }
  61. spin_unlock_irqrestore(&rf->arp_lock, flags);
  62. return arp_index;
  63. }
  64. /**
  65. * irdma_add_arp - add a new arp entry if needed
  66. * @rf: RDMA function
  67. * @ip: IP address
  68. * @ipv4: IPv4 flag
  69. * @mac: MAC address
  70. */
  71. int irdma_add_arp(struct irdma_pci_f *rf, u32 *ip, bool ipv4, const u8 *mac)
  72. {
  73. int arpidx;
  74. arpidx = irdma_arp_table(rf, &ip[0], ipv4, NULL, IRDMA_ARP_RESOLVE);
  75. if (arpidx >= 0) {
  76. if (ether_addr_equal(rf->arp_table[arpidx].mac_addr, mac))
  77. return arpidx;
  78. irdma_manage_arp_cache(rf, rf->arp_table[arpidx].mac_addr, ip,
  79. ipv4, IRDMA_ARP_DELETE);
  80. }
  81. irdma_manage_arp_cache(rf, mac, ip, ipv4, IRDMA_ARP_ADD);
  82. return irdma_arp_table(rf, ip, ipv4, NULL, IRDMA_ARP_RESOLVE);
  83. }
  84. /**
  85. * wr32 - write 32 bits to hw register
  86. * @hw: hardware information including registers
  87. * @reg: register offset
  88. * @val: value to write to register
  89. */
  90. inline void wr32(struct irdma_hw *hw, u32 reg, u32 val)
  91. {
  92. writel(val, hw->hw_addr + reg);
  93. }
  94. /**
  95. * rd32 - read a 32 bit hw register
  96. * @hw: hardware information including registers
  97. * @reg: register offset
  98. *
  99. * Return value of register content
  100. */
  101. inline u32 rd32(struct irdma_hw *hw, u32 reg)
  102. {
  103. return readl(hw->hw_addr + reg);
  104. }
  105. /**
  106. * rd64 - read a 64 bit hw register
  107. * @hw: hardware information including registers
  108. * @reg: register offset
  109. *
  110. * Return value of register content
  111. */
  112. inline u64 rd64(struct irdma_hw *hw, u32 reg)
  113. {
  114. return readq(hw->hw_addr + reg);
  115. }
  116. static void irdma_gid_change_event(struct ib_device *ibdev)
  117. {
  118. struct ib_event ib_event;
  119. ib_event.event = IB_EVENT_GID_CHANGE;
  120. ib_event.device = ibdev;
  121. ib_event.element.port_num = 1;
  122. ib_dispatch_event(&ib_event);
  123. }
  124. /**
  125. * irdma_inetaddr_event - system notifier for ipv4 addr events
  126. * @notifier: not used
  127. * @event: event for notifier
  128. * @ptr: if address
  129. */
  130. int irdma_inetaddr_event(struct notifier_block *notifier, unsigned long event,
  131. void *ptr)
  132. {
  133. struct in_ifaddr *ifa = ptr;
  134. struct net_device *real_dev, *netdev = ifa->ifa_dev->dev;
  135. struct irdma_device *iwdev;
  136. struct ib_device *ibdev;
  137. u32 local_ipaddr;
  138. real_dev = rdma_vlan_dev_real_dev(netdev);
  139. if (!real_dev)
  140. real_dev = netdev;
  141. ibdev = ib_device_get_by_netdev(real_dev, RDMA_DRIVER_IRDMA);
  142. if (!ibdev)
  143. return NOTIFY_DONE;
  144. iwdev = to_iwdev(ibdev);
  145. local_ipaddr = ntohl(ifa->ifa_address);
  146. ibdev_dbg(&iwdev->ibdev,
  147. "DEV: netdev %p event %lu local_ip=%pI4 MAC=%pM\n", real_dev,
  148. event, &local_ipaddr, real_dev->dev_addr);
  149. switch (event) {
  150. case NETDEV_DOWN:
  151. irdma_manage_arp_cache(iwdev->rf, real_dev->dev_addr,
  152. &local_ipaddr, true, IRDMA_ARP_DELETE);
  153. irdma_if_notify(iwdev, real_dev, &local_ipaddr, true, false);
  154. irdma_gid_change_event(&iwdev->ibdev);
  155. break;
  156. case NETDEV_UP:
  157. case NETDEV_CHANGEADDR:
  158. irdma_add_arp(iwdev->rf, &local_ipaddr, true, real_dev->dev_addr);
  159. irdma_if_notify(iwdev, real_dev, &local_ipaddr, true, true);
  160. irdma_gid_change_event(&iwdev->ibdev);
  161. break;
  162. default:
  163. break;
  164. }
  165. ib_device_put(ibdev);
  166. return NOTIFY_DONE;
  167. }
  168. /**
  169. * irdma_inet6addr_event - system notifier for ipv6 addr events
  170. * @notifier: not used
  171. * @event: event for notifier
  172. * @ptr: if address
  173. */
  174. int irdma_inet6addr_event(struct notifier_block *notifier, unsigned long event,
  175. void *ptr)
  176. {
  177. struct inet6_ifaddr *ifa = ptr;
  178. struct net_device *real_dev, *netdev = ifa->idev->dev;
  179. struct irdma_device *iwdev;
  180. struct ib_device *ibdev;
  181. u32 local_ipaddr6[4];
  182. real_dev = rdma_vlan_dev_real_dev(netdev);
  183. if (!real_dev)
  184. real_dev = netdev;
  185. ibdev = ib_device_get_by_netdev(real_dev, RDMA_DRIVER_IRDMA);
  186. if (!ibdev)
  187. return NOTIFY_DONE;
  188. iwdev = to_iwdev(ibdev);
  189. irdma_copy_ip_ntohl(local_ipaddr6, ifa->addr.in6_u.u6_addr32);
  190. ibdev_dbg(&iwdev->ibdev,
  191. "DEV: netdev %p event %lu local_ip=%pI6 MAC=%pM\n", real_dev,
  192. event, local_ipaddr6, real_dev->dev_addr);
  193. switch (event) {
  194. case NETDEV_DOWN:
  195. irdma_manage_arp_cache(iwdev->rf, real_dev->dev_addr,
  196. local_ipaddr6, false, IRDMA_ARP_DELETE);
  197. irdma_if_notify(iwdev, real_dev, local_ipaddr6, false, false);
  198. irdma_gid_change_event(&iwdev->ibdev);
  199. break;
  200. case NETDEV_UP:
  201. case NETDEV_CHANGEADDR:
  202. irdma_add_arp(iwdev->rf, local_ipaddr6, false,
  203. real_dev->dev_addr);
  204. irdma_if_notify(iwdev, real_dev, local_ipaddr6, false, true);
  205. irdma_gid_change_event(&iwdev->ibdev);
  206. break;
  207. default:
  208. break;
  209. }
  210. ib_device_put(ibdev);
  211. return NOTIFY_DONE;
  212. }
  213. /**
  214. * irdma_net_event - system notifier for net events
  215. * @notifier: not used
  216. * @event: event for notifier
  217. * @ptr: neighbor
  218. */
  219. int irdma_net_event(struct notifier_block *notifier, unsigned long event,
  220. void *ptr)
  221. {
  222. struct neighbour *neigh = ptr;
  223. struct net_device *real_dev, *netdev = (struct net_device *)neigh->dev;
  224. struct irdma_device *iwdev;
  225. struct ib_device *ibdev;
  226. __be32 *p;
  227. u32 local_ipaddr[4] = {};
  228. bool ipv4 = true;
  229. switch (event) {
  230. case NETEVENT_NEIGH_UPDATE:
  231. real_dev = rdma_vlan_dev_real_dev(netdev);
  232. if (!real_dev)
  233. real_dev = netdev;
  234. ibdev = ib_device_get_by_netdev(real_dev, RDMA_DRIVER_IRDMA);
  235. if (!ibdev)
  236. return NOTIFY_DONE;
  237. iwdev = to_iwdev(ibdev);
  238. p = (__be32 *)neigh->primary_key;
  239. if (neigh->tbl->family == AF_INET6) {
  240. ipv4 = false;
  241. irdma_copy_ip_ntohl(local_ipaddr, p);
  242. } else {
  243. local_ipaddr[0] = ntohl(*p);
  244. }
  245. ibdev_dbg(&iwdev->ibdev,
  246. "DEV: netdev %p state %d local_ip=%pI4 MAC=%pM\n",
  247. iwdev->netdev, neigh->nud_state, local_ipaddr,
  248. neigh->ha);
  249. if (neigh->nud_state & NUD_VALID)
  250. irdma_add_arp(iwdev->rf, local_ipaddr, ipv4, neigh->ha);
  251. else
  252. irdma_manage_arp_cache(iwdev->rf, neigh->ha,
  253. local_ipaddr, ipv4,
  254. IRDMA_ARP_DELETE);
  255. ib_device_put(ibdev);
  256. break;
  257. default:
  258. break;
  259. }
  260. return NOTIFY_DONE;
  261. }
  262. /**
  263. * irdma_netdevice_event - system notifier for netdev events
  264. * @notifier: not used
  265. * @event: event for notifier
  266. * @ptr: netdev
  267. */
  268. int irdma_netdevice_event(struct notifier_block *notifier, unsigned long event,
  269. void *ptr)
  270. {
  271. struct irdma_device *iwdev;
  272. struct ib_device *ibdev;
  273. struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
  274. ibdev = ib_device_get_by_netdev(netdev, RDMA_DRIVER_IRDMA);
  275. if (!ibdev)
  276. return NOTIFY_DONE;
  277. iwdev = to_iwdev(ibdev);
  278. iwdev->iw_status = 1;
  279. switch (event) {
  280. case NETDEV_DOWN:
  281. iwdev->iw_status = 0;
  282. fallthrough;
  283. case NETDEV_UP:
  284. irdma_port_ibevent(iwdev);
  285. break;
  286. default:
  287. break;
  288. }
  289. ib_device_put(ibdev);
  290. return NOTIFY_DONE;
  291. }
  292. /**
  293. * irdma_add_ipv6_addr - add ipv6 address to the hw arp table
  294. * @iwdev: irdma device
  295. */
  296. static void irdma_add_ipv6_addr(struct irdma_device *iwdev)
  297. {
  298. struct net_device *ip_dev;
  299. struct inet6_dev *idev;
  300. struct inet6_ifaddr *ifp, *tmp;
  301. u32 local_ipaddr6[4];
  302. rcu_read_lock();
  303. for_each_netdev_rcu (&init_net, ip_dev) {
  304. if (((rdma_vlan_dev_vlan_id(ip_dev) < 0xFFFF &&
  305. rdma_vlan_dev_real_dev(ip_dev) == iwdev->netdev) ||
  306. ip_dev == iwdev->netdev) &&
  307. (READ_ONCE(ip_dev->flags) & IFF_UP)) {
  308. idev = __in6_dev_get(ip_dev);
  309. if (!idev) {
  310. ibdev_err(&iwdev->ibdev, "ipv6 inet device not found\n");
  311. break;
  312. }
  313. list_for_each_entry_safe (ifp, tmp, &idev->addr_list,
  314. if_list) {
  315. ibdev_dbg(&iwdev->ibdev,
  316. "INIT: IP=%pI6, vlan_id=%d, MAC=%pM\n",
  317. &ifp->addr,
  318. rdma_vlan_dev_vlan_id(ip_dev),
  319. ip_dev->dev_addr);
  320. irdma_copy_ip_ntohl(local_ipaddr6,
  321. ifp->addr.in6_u.u6_addr32);
  322. irdma_manage_arp_cache(iwdev->rf,
  323. ip_dev->dev_addr,
  324. local_ipaddr6, false,
  325. IRDMA_ARP_ADD);
  326. }
  327. }
  328. }
  329. rcu_read_unlock();
  330. }
  331. /**
  332. * irdma_add_ipv4_addr - add ipv4 address to the hw arp table
  333. * @iwdev: irdma device
  334. */
  335. static void irdma_add_ipv4_addr(struct irdma_device *iwdev)
  336. {
  337. struct net_device *dev;
  338. struct in_device *idev;
  339. u32 ip_addr;
  340. rcu_read_lock();
  341. for_each_netdev_rcu (&init_net, dev) {
  342. if (((rdma_vlan_dev_vlan_id(dev) < 0xFFFF &&
  343. rdma_vlan_dev_real_dev(dev) == iwdev->netdev) ||
  344. dev == iwdev->netdev) && (READ_ONCE(dev->flags) & IFF_UP)) {
  345. const struct in_ifaddr *ifa;
  346. idev = __in_dev_get_rcu(dev);
  347. if (!idev)
  348. continue;
  349. in_dev_for_each_ifa_rcu(ifa, idev) {
  350. ibdev_dbg(&iwdev->ibdev, "CM: IP=%pI4, vlan_id=%d, MAC=%pM\n",
  351. &ifa->ifa_address, rdma_vlan_dev_vlan_id(dev),
  352. dev->dev_addr);
  353. ip_addr = ntohl(ifa->ifa_address);
  354. irdma_manage_arp_cache(iwdev->rf, dev->dev_addr,
  355. &ip_addr, true,
  356. IRDMA_ARP_ADD);
  357. }
  358. }
  359. }
  360. rcu_read_unlock();
  361. }
  362. /**
  363. * irdma_add_ip - add ip addresses
  364. * @iwdev: irdma device
  365. *
  366. * Add ipv4/ipv6 addresses to the arp cache
  367. */
  368. void irdma_add_ip(struct irdma_device *iwdev)
  369. {
  370. irdma_add_ipv4_addr(iwdev);
  371. irdma_add_ipv6_addr(iwdev);
  372. }
  373. /**
  374. * irdma_alloc_and_get_cqp_request - get cqp struct
  375. * @cqp: device cqp ptr
  376. * @wait: cqp to be used in wait mode
  377. */
  378. struct irdma_cqp_request *irdma_alloc_and_get_cqp_request(struct irdma_cqp *cqp,
  379. bool wait)
  380. {
  381. struct irdma_cqp_request *cqp_request = NULL;
  382. unsigned long flags;
  383. spin_lock_irqsave(&cqp->req_lock, flags);
  384. if (!list_empty(&cqp->cqp_avail_reqs)) {
  385. cqp_request = list_first_entry(&cqp->cqp_avail_reqs,
  386. struct irdma_cqp_request, list);
  387. list_del_init(&cqp_request->list);
  388. }
  389. spin_unlock_irqrestore(&cqp->req_lock, flags);
  390. if (!cqp_request) {
  391. cqp_request = kzalloc(sizeof(*cqp_request), GFP_ATOMIC);
  392. if (cqp_request) {
  393. cqp_request->dynamic = true;
  394. if (wait)
  395. init_waitqueue_head(&cqp_request->waitq);
  396. }
  397. }
  398. if (!cqp_request) {
  399. ibdev_dbg(to_ibdev(cqp->sc_cqp.dev), "ERR: CQP Request Fail: No Memory");
  400. return NULL;
  401. }
  402. cqp_request->waiting = wait;
  403. refcount_set(&cqp_request->refcnt, 1);
  404. memset(&cqp_request->compl_info, 0, sizeof(cqp_request->compl_info));
  405. return cqp_request;
  406. }
  407. /**
  408. * irdma_get_cqp_request - increase refcount for cqp_request
  409. * @cqp_request: pointer to cqp_request instance
  410. */
  411. static inline void irdma_get_cqp_request(struct irdma_cqp_request *cqp_request)
  412. {
  413. refcount_inc(&cqp_request->refcnt);
  414. }
  415. /**
  416. * irdma_free_cqp_request - free cqp request
  417. * @cqp: cqp ptr
  418. * @cqp_request: to be put back in cqp list
  419. */
  420. void irdma_free_cqp_request(struct irdma_cqp *cqp,
  421. struct irdma_cqp_request *cqp_request)
  422. {
  423. unsigned long flags;
  424. if (cqp_request->dynamic) {
  425. kfree(cqp_request);
  426. } else {
  427. WRITE_ONCE(cqp_request->request_done, false);
  428. cqp_request->callback_fcn = NULL;
  429. cqp_request->waiting = false;
  430. spin_lock_irqsave(&cqp->req_lock, flags);
  431. list_add_tail(&cqp_request->list, &cqp->cqp_avail_reqs);
  432. spin_unlock_irqrestore(&cqp->req_lock, flags);
  433. }
  434. wake_up(&cqp->remove_wq);
  435. }
  436. /**
  437. * irdma_put_cqp_request - dec ref count and free if 0
  438. * @cqp: cqp ptr
  439. * @cqp_request: to be put back in cqp list
  440. */
  441. void irdma_put_cqp_request(struct irdma_cqp *cqp,
  442. struct irdma_cqp_request *cqp_request)
  443. {
  444. if (refcount_dec_and_test(&cqp_request->refcnt))
  445. irdma_free_cqp_request(cqp, cqp_request);
  446. }
  447. /**
  448. * irdma_free_pending_cqp_request -free pending cqp request objs
  449. * @cqp: cqp ptr
  450. * @cqp_request: to be put back in cqp list
  451. */
  452. static void
  453. irdma_free_pending_cqp_request(struct irdma_cqp *cqp,
  454. struct irdma_cqp_request *cqp_request)
  455. {
  456. if (cqp_request->waiting) {
  457. cqp_request->compl_info.error = true;
  458. WRITE_ONCE(cqp_request->request_done, true);
  459. wake_up(&cqp_request->waitq);
  460. }
  461. wait_event_timeout(cqp->remove_wq,
  462. refcount_read(&cqp_request->refcnt) == 1, 1000);
  463. irdma_put_cqp_request(cqp, cqp_request);
  464. }
  465. /**
  466. * irdma_cleanup_pending_cqp_op - clean-up cqp with no
  467. * completions
  468. * @rf: RDMA PCI function
  469. */
  470. void irdma_cleanup_pending_cqp_op(struct irdma_pci_f *rf)
  471. {
  472. struct irdma_sc_dev *dev = &rf->sc_dev;
  473. struct irdma_cqp *cqp = &rf->cqp;
  474. struct irdma_cqp_request *cqp_request = NULL;
  475. struct cqp_cmds_info *pcmdinfo = NULL;
  476. u32 i, pending_work, wqe_idx;
  477. pending_work = IRDMA_RING_USED_QUANTA(cqp->sc_cqp.sq_ring);
  478. wqe_idx = IRDMA_RING_CURRENT_TAIL(cqp->sc_cqp.sq_ring);
  479. for (i = 0; i < pending_work; i++) {
  480. cqp_request = (struct irdma_cqp_request *)(unsigned long)
  481. cqp->scratch_array[wqe_idx];
  482. if (cqp_request)
  483. irdma_free_pending_cqp_request(cqp, cqp_request);
  484. wqe_idx = (wqe_idx + 1) % IRDMA_RING_SIZE(cqp->sc_cqp.sq_ring);
  485. }
  486. while (!list_empty(&dev->cqp_cmd_head)) {
  487. pcmdinfo = irdma_remove_cqp_head(dev);
  488. cqp_request =
  489. container_of(pcmdinfo, struct irdma_cqp_request, info);
  490. if (cqp_request)
  491. irdma_free_pending_cqp_request(cqp, cqp_request);
  492. }
  493. }
  494. /**
  495. * irdma_wait_event - wait for completion
  496. * @rf: RDMA PCI function
  497. * @cqp_request: cqp request to wait
  498. */
  499. static int irdma_wait_event(struct irdma_pci_f *rf,
  500. struct irdma_cqp_request *cqp_request)
  501. {
  502. struct irdma_cqp_timeout cqp_timeout = {};
  503. bool cqp_error = false;
  504. int err_code = 0;
  505. cqp_timeout.compl_cqp_cmds = atomic64_read(&rf->sc_dev.cqp->completed_ops);
  506. do {
  507. irdma_cqp_ce_handler(rf, &rf->ccq.sc_cq);
  508. if (wait_event_timeout(cqp_request->waitq,
  509. READ_ONCE(cqp_request->request_done),
  510. msecs_to_jiffies(CQP_COMPL_WAIT_TIME_MS)))
  511. break;
  512. irdma_check_cqp_progress(&cqp_timeout, &rf->sc_dev);
  513. if (cqp_timeout.count < CQP_TIMEOUT_THRESHOLD)
  514. continue;
  515. if (!rf->reset) {
  516. rf->reset = true;
  517. rf->gen_ops.request_reset(rf);
  518. }
  519. return -ETIMEDOUT;
  520. } while (1);
  521. cqp_error = cqp_request->compl_info.error;
  522. if (cqp_error) {
  523. err_code = -EIO;
  524. if (cqp_request->compl_info.maj_err_code == 0xFFFF) {
  525. if (cqp_request->compl_info.min_err_code == 0x8002)
  526. err_code = -EBUSY;
  527. else if (cqp_request->compl_info.min_err_code == 0x8029) {
  528. if (!rf->reset) {
  529. rf->reset = true;
  530. rf->gen_ops.request_reset(rf);
  531. }
  532. }
  533. }
  534. }
  535. return err_code;
  536. }
  537. static const char *const irdma_cqp_cmd_names[IRDMA_MAX_CQP_OPS] = {
  538. [IRDMA_OP_CEQ_DESTROY] = "Destroy CEQ Cmd",
  539. [IRDMA_OP_AEQ_DESTROY] = "Destroy AEQ Cmd",
  540. [IRDMA_OP_DELETE_ARP_CACHE_ENTRY] = "Delete ARP Cache Cmd",
  541. [IRDMA_OP_MANAGE_APBVT_ENTRY] = "Manage APBV Table Entry Cmd",
  542. [IRDMA_OP_CEQ_CREATE] = "CEQ Create Cmd",
  543. [IRDMA_OP_AEQ_CREATE] = "AEQ Destroy Cmd",
  544. [IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY] = "Manage Quad Hash Table Entry Cmd",
  545. [IRDMA_OP_QP_MODIFY] = "Modify QP Cmd",
  546. [IRDMA_OP_QP_UPLOAD_CONTEXT] = "Upload Context Cmd",
  547. [IRDMA_OP_CQ_CREATE] = "Create CQ Cmd",
  548. [IRDMA_OP_CQ_DESTROY] = "Destroy CQ Cmd",
  549. [IRDMA_OP_QP_CREATE] = "Create QP Cmd",
  550. [IRDMA_OP_QP_DESTROY] = "Destroy QP Cmd",
  551. [IRDMA_OP_ALLOC_STAG] = "Allocate STag Cmd",
  552. [IRDMA_OP_MR_REG_NON_SHARED] = "Register Non-Shared MR Cmd",
  553. [IRDMA_OP_DEALLOC_STAG] = "Deallocate STag Cmd",
  554. [IRDMA_OP_MW_ALLOC] = "Allocate Memory Window Cmd",
  555. [IRDMA_OP_QP_FLUSH_WQES] = "Flush QP Cmd",
  556. [IRDMA_OP_ADD_ARP_CACHE_ENTRY] = "Add ARP Cache Cmd",
  557. [IRDMA_OP_MANAGE_PUSH_PAGE] = "Manage Push Page Cmd",
  558. [IRDMA_OP_UPDATE_PE_SDS] = "Update PE SDs Cmd",
  559. [IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE] = "Manage HMC PM Function Table Cmd",
  560. [IRDMA_OP_SUSPEND] = "Suspend QP Cmd",
  561. [IRDMA_OP_RESUME] = "Resume QP Cmd",
  562. [IRDMA_OP_MANAGE_VF_PBLE_BP] = "Manage VF PBLE Backing Pages Cmd",
  563. [IRDMA_OP_QUERY_FPM_VAL] = "Query FPM Values Cmd",
  564. [IRDMA_OP_COMMIT_FPM_VAL] = "Commit FPM Values Cmd",
  565. [IRDMA_OP_AH_CREATE] = "Create Address Handle Cmd",
  566. [IRDMA_OP_AH_MODIFY] = "Modify Address Handle Cmd",
  567. [IRDMA_OP_AH_DESTROY] = "Destroy Address Handle Cmd",
  568. [IRDMA_OP_MC_CREATE] = "Create Multicast Group Cmd",
  569. [IRDMA_OP_MC_DESTROY] = "Destroy Multicast Group Cmd",
  570. [IRDMA_OP_MC_MODIFY] = "Modify Multicast Group Cmd",
  571. [IRDMA_OP_STATS_ALLOCATE] = "Add Statistics Instance Cmd",
  572. [IRDMA_OP_STATS_FREE] = "Free Statistics Instance Cmd",
  573. [IRDMA_OP_STATS_GATHER] = "Gather Statistics Cmd",
  574. [IRDMA_OP_WS_ADD_NODE] = "Add Work Scheduler Node Cmd",
  575. [IRDMA_OP_WS_MODIFY_NODE] = "Modify Work Scheduler Node Cmd",
  576. [IRDMA_OP_WS_DELETE_NODE] = "Delete Work Scheduler Node Cmd",
  577. [IRDMA_OP_SET_UP_MAP] = "Set UP-UP Mapping Cmd",
  578. [IRDMA_OP_GEN_AE] = "Generate AE Cmd",
  579. [IRDMA_OP_QUERY_RDMA_FEATURES] = "RDMA Get Features Cmd",
  580. [IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY] = "Allocate Local MAC Entry Cmd",
  581. [IRDMA_OP_ADD_LOCAL_MAC_ENTRY] = "Add Local MAC Entry Cmd",
  582. [IRDMA_OP_DELETE_LOCAL_MAC_ENTRY] = "Delete Local MAC Entry Cmd",
  583. [IRDMA_OP_CQ_MODIFY] = "CQ Modify Cmd",
  584. };
  585. static const struct irdma_cqp_err_info irdma_noncrit_err_list[] = {
  586. {0xffff, 0x8002, "Invalid State"},
  587. {0xffff, 0x8006, "Flush No Wqe Pending"},
  588. {0xffff, 0x8007, "Modify QP Bad Close"},
  589. {0xffff, 0x8009, "LLP Closed"},
  590. {0xffff, 0x800a, "Reset Not Sent"}
  591. };
  592. /**
  593. * irdma_cqp_crit_err - check if CQP error is critical
  594. * @dev: pointer to dev structure
  595. * @cqp_cmd: code for last CQP operation
  596. * @maj_err_code: major error code
  597. * @min_err_code: minot error code
  598. */
  599. bool irdma_cqp_crit_err(struct irdma_sc_dev *dev, u8 cqp_cmd,
  600. u16 maj_err_code, u16 min_err_code)
  601. {
  602. int i;
  603. for (i = 0; i < ARRAY_SIZE(irdma_noncrit_err_list); ++i) {
  604. if (maj_err_code == irdma_noncrit_err_list[i].maj &&
  605. min_err_code == irdma_noncrit_err_list[i].min) {
  606. ibdev_dbg(to_ibdev(dev),
  607. "CQP: [%s Error][%s] maj=0x%x min=0x%x\n",
  608. irdma_noncrit_err_list[i].desc,
  609. irdma_cqp_cmd_names[cqp_cmd], maj_err_code,
  610. min_err_code);
  611. return false;
  612. }
  613. }
  614. return true;
  615. }
  616. /**
  617. * irdma_handle_cqp_op - process cqp command
  618. * @rf: RDMA PCI function
  619. * @cqp_request: cqp request to process
  620. */
  621. int irdma_handle_cqp_op(struct irdma_pci_f *rf,
  622. struct irdma_cqp_request *cqp_request)
  623. {
  624. struct irdma_sc_dev *dev = &rf->sc_dev;
  625. struct cqp_cmds_info *info = &cqp_request->info;
  626. int status;
  627. bool put_cqp_request = true;
  628. if (rf->reset)
  629. return -EBUSY;
  630. irdma_get_cqp_request(cqp_request);
  631. status = irdma_process_cqp_cmd(dev, info);
  632. if (status)
  633. goto err;
  634. if (cqp_request->waiting) {
  635. put_cqp_request = false;
  636. status = irdma_wait_event(rf, cqp_request);
  637. if (status)
  638. goto err;
  639. }
  640. return 0;
  641. err:
  642. if (irdma_cqp_crit_err(dev, info->cqp_cmd,
  643. cqp_request->compl_info.maj_err_code,
  644. cqp_request->compl_info.min_err_code))
  645. ibdev_err(&rf->iwdev->ibdev,
  646. "[%s Error][op_code=%d] status=%d waiting=%d completion_err=%d maj=0x%x min=0x%x\n",
  647. irdma_cqp_cmd_names[info->cqp_cmd], info->cqp_cmd, status, cqp_request->waiting,
  648. cqp_request->compl_info.error, cqp_request->compl_info.maj_err_code,
  649. cqp_request->compl_info.min_err_code);
  650. if (put_cqp_request)
  651. irdma_put_cqp_request(&rf->cqp, cqp_request);
  652. return status;
  653. }
  654. void irdma_qp_add_ref(struct ib_qp *ibqp)
  655. {
  656. struct irdma_qp *iwqp = (struct irdma_qp *)ibqp;
  657. refcount_inc(&iwqp->refcnt);
  658. }
  659. void irdma_qp_rem_ref(struct ib_qp *ibqp)
  660. {
  661. struct irdma_qp *iwqp = to_iwqp(ibqp);
  662. struct irdma_device *iwdev = iwqp->iwdev;
  663. u32 qp_num;
  664. unsigned long flags;
  665. spin_lock_irqsave(&iwdev->rf->qptable_lock, flags);
  666. if (!refcount_dec_and_test(&iwqp->refcnt)) {
  667. spin_unlock_irqrestore(&iwdev->rf->qptable_lock, flags);
  668. return;
  669. }
  670. qp_num = iwqp->ibqp.qp_num;
  671. iwdev->rf->qp_table[qp_num] = NULL;
  672. spin_unlock_irqrestore(&iwdev->rf->qptable_lock, flags);
  673. complete(&iwqp->free_qp);
  674. }
  675. void irdma_cq_add_ref(struct ib_cq *ibcq)
  676. {
  677. struct irdma_cq *iwcq = to_iwcq(ibcq);
  678. refcount_inc(&iwcq->refcnt);
  679. }
  680. void irdma_cq_rem_ref(struct ib_cq *ibcq)
  681. {
  682. struct ib_device *ibdev = ibcq->device;
  683. struct irdma_device *iwdev = to_iwdev(ibdev);
  684. struct irdma_cq *iwcq = to_iwcq(ibcq);
  685. unsigned long flags;
  686. spin_lock_irqsave(&iwdev->rf->cqtable_lock, flags);
  687. if (!refcount_dec_and_test(&iwcq->refcnt)) {
  688. spin_unlock_irqrestore(&iwdev->rf->cqtable_lock, flags);
  689. return;
  690. }
  691. iwdev->rf->cq_table[iwcq->cq_num] = NULL;
  692. spin_unlock_irqrestore(&iwdev->rf->cqtable_lock, flags);
  693. complete(&iwcq->free_cq);
  694. }
  695. struct ib_device *to_ibdev(struct irdma_sc_dev *dev)
  696. {
  697. return &(container_of(dev, struct irdma_pci_f, sc_dev))->iwdev->ibdev;
  698. }
  699. /**
  700. * irdma_get_qp - get qp address
  701. * @device: iwarp device
  702. * @qpn: qp number
  703. */
  704. struct ib_qp *irdma_get_qp(struct ib_device *device, int qpn)
  705. {
  706. struct irdma_device *iwdev = to_iwdev(device);
  707. if (qpn < IW_FIRST_QPN || qpn >= iwdev->rf->max_qp)
  708. return NULL;
  709. return &iwdev->rf->qp_table[qpn]->ibqp;
  710. }
  711. /**
  712. * irdma_remove_cqp_head - return head entry and remove
  713. * @dev: device
  714. */
  715. void *irdma_remove_cqp_head(struct irdma_sc_dev *dev)
  716. {
  717. struct list_head *entry;
  718. struct list_head *list = &dev->cqp_cmd_head;
  719. if (list_empty(list))
  720. return NULL;
  721. entry = list->next;
  722. list_del(entry);
  723. return entry;
  724. }
  725. /**
  726. * irdma_cqp_sds_cmd - create cqp command for sd
  727. * @dev: hardware control device structure
  728. * @sdinfo: information for sd cqp
  729. *
  730. */
  731. int irdma_cqp_sds_cmd(struct irdma_sc_dev *dev,
  732. struct irdma_update_sds_info *sdinfo)
  733. {
  734. struct irdma_cqp_request *cqp_request;
  735. struct cqp_cmds_info *cqp_info;
  736. struct irdma_pci_f *rf = dev_to_rf(dev);
  737. int status;
  738. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  739. if (!cqp_request)
  740. return -ENOMEM;
  741. cqp_info = &cqp_request->info;
  742. memcpy(&cqp_info->in.u.update_pe_sds.info, sdinfo,
  743. sizeof(cqp_info->in.u.update_pe_sds.info));
  744. cqp_info->cqp_cmd = IRDMA_OP_UPDATE_PE_SDS;
  745. cqp_info->post_sq = 1;
  746. cqp_info->in.u.update_pe_sds.dev = dev;
  747. cqp_info->in.u.update_pe_sds.scratch = (uintptr_t)cqp_request;
  748. status = irdma_handle_cqp_op(rf, cqp_request);
  749. irdma_put_cqp_request(&rf->cqp, cqp_request);
  750. return status;
  751. }
  752. /**
  753. * irdma_cqp_qp_suspend_resume - cqp command for suspend/resume
  754. * @qp: hardware control qp
  755. * @op: suspend or resume
  756. */
  757. int irdma_cqp_qp_suspend_resume(struct irdma_sc_qp *qp, u8 op)
  758. {
  759. struct irdma_sc_dev *dev = qp->dev;
  760. struct irdma_cqp_request *cqp_request;
  761. struct irdma_sc_cqp *cqp = dev->cqp;
  762. struct cqp_cmds_info *cqp_info;
  763. struct irdma_pci_f *rf = dev_to_rf(dev);
  764. int status;
  765. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false);
  766. if (!cqp_request)
  767. return -ENOMEM;
  768. cqp_info = &cqp_request->info;
  769. cqp_info->cqp_cmd = op;
  770. cqp_info->in.u.suspend_resume.cqp = cqp;
  771. cqp_info->in.u.suspend_resume.qp = qp;
  772. cqp_info->in.u.suspend_resume.scratch = (uintptr_t)cqp_request;
  773. status = irdma_handle_cqp_op(rf, cqp_request);
  774. irdma_put_cqp_request(&rf->cqp, cqp_request);
  775. return status;
  776. }
  777. /**
  778. * irdma_term_modify_qp - modify qp for term message
  779. * @qp: hardware control qp
  780. * @next_state: qp's next state
  781. * @term: terminate code
  782. * @term_len: length
  783. */
  784. void irdma_term_modify_qp(struct irdma_sc_qp *qp, u8 next_state, u8 term,
  785. u8 term_len)
  786. {
  787. struct irdma_qp *iwqp;
  788. iwqp = qp->qp_uk.back_qp;
  789. irdma_next_iw_state(iwqp, next_state, 0, term, term_len);
  790. };
  791. /**
  792. * irdma_terminate_done - after terminate is completed
  793. * @qp: hardware control qp
  794. * @timeout_occurred: indicates if terminate timer expired
  795. */
  796. void irdma_terminate_done(struct irdma_sc_qp *qp, int timeout_occurred)
  797. {
  798. struct irdma_qp *iwqp;
  799. u8 hte = 0;
  800. bool first_time;
  801. unsigned long flags;
  802. iwqp = qp->qp_uk.back_qp;
  803. spin_lock_irqsave(&iwqp->lock, flags);
  804. if (iwqp->hte_added) {
  805. iwqp->hte_added = 0;
  806. hte = 1;
  807. }
  808. first_time = !(qp->term_flags & IRDMA_TERM_DONE);
  809. qp->term_flags |= IRDMA_TERM_DONE;
  810. spin_unlock_irqrestore(&iwqp->lock, flags);
  811. if (first_time) {
  812. if (!timeout_occurred)
  813. irdma_terminate_del_timer(qp);
  814. irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, hte, 0, 0);
  815. irdma_cm_disconn(iwqp);
  816. }
  817. }
  818. static void irdma_terminate_timeout(struct timer_list *t)
  819. {
  820. struct irdma_qp *iwqp = from_timer(iwqp, t, terminate_timer);
  821. struct irdma_sc_qp *qp = &iwqp->sc_qp;
  822. irdma_terminate_done(qp, 1);
  823. irdma_qp_rem_ref(&iwqp->ibqp);
  824. }
  825. /**
  826. * irdma_terminate_start_timer - start terminate timeout
  827. * @qp: hardware control qp
  828. */
  829. void irdma_terminate_start_timer(struct irdma_sc_qp *qp)
  830. {
  831. struct irdma_qp *iwqp;
  832. iwqp = qp->qp_uk.back_qp;
  833. irdma_qp_add_ref(&iwqp->ibqp);
  834. timer_setup(&iwqp->terminate_timer, irdma_terminate_timeout, 0);
  835. iwqp->terminate_timer.expires = jiffies + HZ;
  836. add_timer(&iwqp->terminate_timer);
  837. }
  838. /**
  839. * irdma_terminate_del_timer - delete terminate timeout
  840. * @qp: hardware control qp
  841. */
  842. void irdma_terminate_del_timer(struct irdma_sc_qp *qp)
  843. {
  844. struct irdma_qp *iwqp;
  845. int ret;
  846. iwqp = qp->qp_uk.back_qp;
  847. ret = del_timer(&iwqp->terminate_timer);
  848. if (ret)
  849. irdma_qp_rem_ref(&iwqp->ibqp);
  850. }
  851. /**
  852. * irdma_cqp_query_fpm_val_cmd - send cqp command for fpm
  853. * @dev: function device struct
  854. * @val_mem: buffer for fpm
  855. * @hmc_fn_id: function id for fpm
  856. */
  857. int irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev,
  858. struct irdma_dma_mem *val_mem, u8 hmc_fn_id)
  859. {
  860. struct irdma_cqp_request *cqp_request;
  861. struct cqp_cmds_info *cqp_info;
  862. struct irdma_pci_f *rf = dev_to_rf(dev);
  863. int status;
  864. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  865. if (!cqp_request)
  866. return -ENOMEM;
  867. cqp_info = &cqp_request->info;
  868. cqp_request->param = NULL;
  869. cqp_info->in.u.query_fpm_val.cqp = dev->cqp;
  870. cqp_info->in.u.query_fpm_val.fpm_val_pa = val_mem->pa;
  871. cqp_info->in.u.query_fpm_val.fpm_val_va = val_mem->va;
  872. cqp_info->in.u.query_fpm_val.hmc_fn_id = hmc_fn_id;
  873. cqp_info->cqp_cmd = IRDMA_OP_QUERY_FPM_VAL;
  874. cqp_info->post_sq = 1;
  875. cqp_info->in.u.query_fpm_val.scratch = (uintptr_t)cqp_request;
  876. status = irdma_handle_cqp_op(rf, cqp_request);
  877. irdma_put_cqp_request(&rf->cqp, cqp_request);
  878. return status;
  879. }
  880. /**
  881. * irdma_cqp_commit_fpm_val_cmd - commit fpm values in hw
  882. * @dev: hardware control device structure
  883. * @val_mem: buffer with fpm values
  884. * @hmc_fn_id: function id for fpm
  885. */
  886. int irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev,
  887. struct irdma_dma_mem *val_mem, u8 hmc_fn_id)
  888. {
  889. struct irdma_cqp_request *cqp_request;
  890. struct cqp_cmds_info *cqp_info;
  891. struct irdma_pci_f *rf = dev_to_rf(dev);
  892. int status;
  893. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  894. if (!cqp_request)
  895. return -ENOMEM;
  896. cqp_info = &cqp_request->info;
  897. cqp_request->param = NULL;
  898. cqp_info->in.u.commit_fpm_val.cqp = dev->cqp;
  899. cqp_info->in.u.commit_fpm_val.fpm_val_pa = val_mem->pa;
  900. cqp_info->in.u.commit_fpm_val.fpm_val_va = val_mem->va;
  901. cqp_info->in.u.commit_fpm_val.hmc_fn_id = hmc_fn_id;
  902. cqp_info->cqp_cmd = IRDMA_OP_COMMIT_FPM_VAL;
  903. cqp_info->post_sq = 1;
  904. cqp_info->in.u.commit_fpm_val.scratch = (uintptr_t)cqp_request;
  905. status = irdma_handle_cqp_op(rf, cqp_request);
  906. irdma_put_cqp_request(&rf->cqp, cqp_request);
  907. return status;
  908. }
  909. /**
  910. * irdma_cqp_cq_create_cmd - create a cq for the cqp
  911. * @dev: device pointer
  912. * @cq: pointer to created cq
  913. */
  914. int irdma_cqp_cq_create_cmd(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq)
  915. {
  916. struct irdma_pci_f *rf = dev_to_rf(dev);
  917. struct irdma_cqp *iwcqp = &rf->cqp;
  918. struct irdma_cqp_request *cqp_request;
  919. struct cqp_cmds_info *cqp_info;
  920. int status;
  921. cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
  922. if (!cqp_request)
  923. return -ENOMEM;
  924. cqp_info = &cqp_request->info;
  925. cqp_info->cqp_cmd = IRDMA_OP_CQ_CREATE;
  926. cqp_info->post_sq = 1;
  927. cqp_info->in.u.cq_create.cq = cq;
  928. cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
  929. status = irdma_handle_cqp_op(rf, cqp_request);
  930. irdma_put_cqp_request(iwcqp, cqp_request);
  931. return status;
  932. }
  933. /**
  934. * irdma_cqp_qp_create_cmd - create a qp for the cqp
  935. * @dev: device pointer
  936. * @qp: pointer to created qp
  937. */
  938. int irdma_cqp_qp_create_cmd(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp)
  939. {
  940. struct irdma_pci_f *rf = dev_to_rf(dev);
  941. struct irdma_cqp *iwcqp = &rf->cqp;
  942. struct irdma_cqp_request *cqp_request;
  943. struct cqp_cmds_info *cqp_info;
  944. struct irdma_create_qp_info *qp_info;
  945. int status;
  946. cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
  947. if (!cqp_request)
  948. return -ENOMEM;
  949. cqp_info = &cqp_request->info;
  950. qp_info = &cqp_request->info.in.u.qp_create.info;
  951. memset(qp_info, 0, sizeof(*qp_info));
  952. qp_info->cq_num_valid = true;
  953. qp_info->next_iwarp_state = IRDMA_QP_STATE_RTS;
  954. cqp_info->cqp_cmd = IRDMA_OP_QP_CREATE;
  955. cqp_info->post_sq = 1;
  956. cqp_info->in.u.qp_create.qp = qp;
  957. cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
  958. status = irdma_handle_cqp_op(rf, cqp_request);
  959. irdma_put_cqp_request(iwcqp, cqp_request);
  960. return status;
  961. }
  962. /**
  963. * irdma_dealloc_push_page - free a push page for qp
  964. * @rf: RDMA PCI function
  965. * @qp: hardware control qp
  966. */
  967. static void irdma_dealloc_push_page(struct irdma_pci_f *rf,
  968. struct irdma_sc_qp *qp)
  969. {
  970. struct irdma_cqp_request *cqp_request;
  971. struct cqp_cmds_info *cqp_info;
  972. int status;
  973. if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX)
  974. return;
  975. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false);
  976. if (!cqp_request)
  977. return;
  978. cqp_info = &cqp_request->info;
  979. cqp_info->cqp_cmd = IRDMA_OP_MANAGE_PUSH_PAGE;
  980. cqp_info->post_sq = 1;
  981. cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx;
  982. cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
  983. cqp_info->in.u.manage_push_page.info.free_page = 1;
  984. cqp_info->in.u.manage_push_page.info.push_page_type = 0;
  985. cqp_info->in.u.manage_push_page.cqp = &rf->cqp.sc_cqp;
  986. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  987. status = irdma_handle_cqp_op(rf, cqp_request);
  988. if (!status)
  989. qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX;
  990. irdma_put_cqp_request(&rf->cqp, cqp_request);
  991. }
  992. /**
  993. * irdma_free_qp_rsrc - free up memory resources for qp
  994. * @iwqp: qp ptr (user or kernel)
  995. */
  996. void irdma_free_qp_rsrc(struct irdma_qp *iwqp)
  997. {
  998. struct irdma_device *iwdev = iwqp->iwdev;
  999. struct irdma_pci_f *rf = iwdev->rf;
  1000. u32 qp_num = iwqp->ibqp.qp_num;
  1001. irdma_ieq_cleanup_qp(iwdev->vsi.ieq, &iwqp->sc_qp);
  1002. irdma_dealloc_push_page(rf, &iwqp->sc_qp);
  1003. if (iwqp->sc_qp.vsi) {
  1004. irdma_qp_rem_qos(&iwqp->sc_qp);
  1005. iwqp->sc_qp.dev->ws_remove(iwqp->sc_qp.vsi,
  1006. iwqp->sc_qp.user_pri);
  1007. }
  1008. if (qp_num > 2)
  1009. irdma_free_rsrc(rf, rf->allocated_qps, qp_num);
  1010. dma_free_coherent(rf->sc_dev.hw->device, iwqp->q2_ctx_mem.size,
  1011. iwqp->q2_ctx_mem.va, iwqp->q2_ctx_mem.pa);
  1012. iwqp->q2_ctx_mem.va = NULL;
  1013. dma_free_coherent(rf->sc_dev.hw->device, iwqp->kqp.dma_mem.size,
  1014. iwqp->kqp.dma_mem.va, iwqp->kqp.dma_mem.pa);
  1015. iwqp->kqp.dma_mem.va = NULL;
  1016. kfree(iwqp->kqp.sq_wrid_mem);
  1017. kfree(iwqp->kqp.rq_wrid_mem);
  1018. }
  1019. /**
  1020. * irdma_cq_wq_destroy - send cq destroy cqp
  1021. * @rf: RDMA PCI function
  1022. * @cq: hardware control cq
  1023. */
  1024. void irdma_cq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_cq *cq)
  1025. {
  1026. struct irdma_cqp_request *cqp_request;
  1027. struct cqp_cmds_info *cqp_info;
  1028. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  1029. if (!cqp_request)
  1030. return;
  1031. cqp_info = &cqp_request->info;
  1032. cqp_info->cqp_cmd = IRDMA_OP_CQ_DESTROY;
  1033. cqp_info->post_sq = 1;
  1034. cqp_info->in.u.cq_destroy.cq = cq;
  1035. cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;
  1036. irdma_handle_cqp_op(rf, cqp_request);
  1037. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1038. }
  1039. /**
  1040. * irdma_hw_modify_qp_callback - handle state for modifyQPs that don't wait
  1041. * @cqp_request: modify QP completion
  1042. */
  1043. static void irdma_hw_modify_qp_callback(struct irdma_cqp_request *cqp_request)
  1044. {
  1045. struct cqp_cmds_info *cqp_info;
  1046. struct irdma_qp *iwqp;
  1047. cqp_info = &cqp_request->info;
  1048. iwqp = cqp_info->in.u.qp_modify.qp->qp_uk.back_qp;
  1049. atomic_dec(&iwqp->hw_mod_qp_pend);
  1050. wake_up(&iwqp->mod_qp_waitq);
  1051. }
  1052. /**
  1053. * irdma_hw_modify_qp - setup cqp for modify qp
  1054. * @iwdev: RDMA device
  1055. * @iwqp: qp ptr (user or kernel)
  1056. * @info: info for modify qp
  1057. * @wait: flag to wait or not for modify qp completion
  1058. */
  1059. int irdma_hw_modify_qp(struct irdma_device *iwdev, struct irdma_qp *iwqp,
  1060. struct irdma_modify_qp_info *info, bool wait)
  1061. {
  1062. int status;
  1063. struct irdma_pci_f *rf = iwdev->rf;
  1064. struct irdma_cqp_request *cqp_request;
  1065. struct cqp_cmds_info *cqp_info;
  1066. struct irdma_modify_qp_info *m_info;
  1067. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
  1068. if (!cqp_request)
  1069. return -ENOMEM;
  1070. if (!wait) {
  1071. cqp_request->callback_fcn = irdma_hw_modify_qp_callback;
  1072. atomic_inc(&iwqp->hw_mod_qp_pend);
  1073. }
  1074. cqp_info = &cqp_request->info;
  1075. m_info = &cqp_info->in.u.qp_modify.info;
  1076. memcpy(m_info, info, sizeof(*m_info));
  1077. cqp_info->cqp_cmd = IRDMA_OP_QP_MODIFY;
  1078. cqp_info->post_sq = 1;
  1079. cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
  1080. cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
  1081. status = irdma_handle_cqp_op(rf, cqp_request);
  1082. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1083. if (status) {
  1084. if (rdma_protocol_roce(&iwdev->ibdev, 1))
  1085. return status;
  1086. switch (m_info->next_iwarp_state) {
  1087. struct irdma_gen_ae_info ae_info;
  1088. case IRDMA_QP_STATE_RTS:
  1089. case IRDMA_QP_STATE_IDLE:
  1090. case IRDMA_QP_STATE_TERMINATE:
  1091. case IRDMA_QP_STATE_CLOSING:
  1092. if (info->curr_iwarp_state == IRDMA_QP_STATE_IDLE)
  1093. irdma_send_reset(iwqp->cm_node);
  1094. else
  1095. iwqp->sc_qp.term_flags = IRDMA_TERM_DONE;
  1096. if (!wait) {
  1097. ae_info.ae_code = IRDMA_AE_BAD_CLOSE;
  1098. ae_info.ae_src = 0;
  1099. irdma_gen_ae(rf, &iwqp->sc_qp, &ae_info, false);
  1100. } else {
  1101. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp,
  1102. wait);
  1103. if (!cqp_request)
  1104. return -ENOMEM;
  1105. cqp_info = &cqp_request->info;
  1106. m_info = &cqp_info->in.u.qp_modify.info;
  1107. memcpy(m_info, info, sizeof(*m_info));
  1108. cqp_info->cqp_cmd = IRDMA_OP_QP_MODIFY;
  1109. cqp_info->post_sq = 1;
  1110. cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;
  1111. cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;
  1112. m_info->next_iwarp_state = IRDMA_QP_STATE_ERROR;
  1113. m_info->reset_tcp_conn = true;
  1114. irdma_handle_cqp_op(rf, cqp_request);
  1115. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1116. }
  1117. break;
  1118. case IRDMA_QP_STATE_ERROR:
  1119. default:
  1120. break;
  1121. }
  1122. }
  1123. return status;
  1124. }
  1125. /**
  1126. * irdma_cqp_cq_destroy_cmd - destroy the cqp cq
  1127. * @dev: device pointer
  1128. * @cq: pointer to cq
  1129. */
  1130. void irdma_cqp_cq_destroy_cmd(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq)
  1131. {
  1132. struct irdma_pci_f *rf = dev_to_rf(dev);
  1133. irdma_cq_wq_destroy(rf, cq);
  1134. }
  1135. /**
  1136. * irdma_cqp_qp_destroy_cmd - destroy the cqp
  1137. * @dev: device pointer
  1138. * @qp: pointer to qp
  1139. */
  1140. int irdma_cqp_qp_destroy_cmd(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp)
  1141. {
  1142. struct irdma_pci_f *rf = dev_to_rf(dev);
  1143. struct irdma_cqp *iwcqp = &rf->cqp;
  1144. struct irdma_cqp_request *cqp_request;
  1145. struct cqp_cmds_info *cqp_info;
  1146. int status;
  1147. cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
  1148. if (!cqp_request)
  1149. return -ENOMEM;
  1150. cqp_info = &cqp_request->info;
  1151. memset(cqp_info, 0, sizeof(*cqp_info));
  1152. cqp_info->cqp_cmd = IRDMA_OP_QP_DESTROY;
  1153. cqp_info->post_sq = 1;
  1154. cqp_info->in.u.qp_destroy.qp = qp;
  1155. cqp_info->in.u.qp_destroy.scratch = (uintptr_t)cqp_request;
  1156. cqp_info->in.u.qp_destroy.remove_hash_idx = true;
  1157. status = irdma_handle_cqp_op(rf, cqp_request);
  1158. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1159. return status;
  1160. }
  1161. /**
  1162. * irdma_ieq_mpa_crc_ae - generate AE for crc error
  1163. * @dev: hardware control device structure
  1164. * @qp: hardware control qp
  1165. */
  1166. void irdma_ieq_mpa_crc_ae(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp)
  1167. {
  1168. struct irdma_gen_ae_info info = {};
  1169. struct irdma_pci_f *rf = dev_to_rf(dev);
  1170. ibdev_dbg(&rf->iwdev->ibdev, "AEQ: Generate MPA CRC AE\n");
  1171. info.ae_code = IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR;
  1172. info.ae_src = IRDMA_AE_SOURCE_RQ;
  1173. irdma_gen_ae(rf, qp, &info, false);
  1174. }
  1175. /**
  1176. * irdma_init_hash_desc - initialize hash for crc calculation
  1177. * @desc: cryption type
  1178. */
  1179. int irdma_init_hash_desc(struct shash_desc **desc)
  1180. {
  1181. struct crypto_shash *tfm;
  1182. struct shash_desc *tdesc;
  1183. tfm = crypto_alloc_shash("crc32c", 0, 0);
  1184. if (IS_ERR(tfm))
  1185. return -EINVAL;
  1186. tdesc = kzalloc(sizeof(*tdesc) + crypto_shash_descsize(tfm),
  1187. GFP_KERNEL);
  1188. if (!tdesc) {
  1189. crypto_free_shash(tfm);
  1190. return -EINVAL;
  1191. }
  1192. tdesc->tfm = tfm;
  1193. *desc = tdesc;
  1194. return 0;
  1195. }
  1196. /**
  1197. * irdma_free_hash_desc - free hash desc
  1198. * @desc: to be freed
  1199. */
  1200. void irdma_free_hash_desc(struct shash_desc *desc)
  1201. {
  1202. if (desc) {
  1203. crypto_free_shash(desc->tfm);
  1204. kfree(desc);
  1205. }
  1206. }
  1207. /**
  1208. * irdma_ieq_check_mpacrc - check if mpa crc is OK
  1209. * @desc: desc for hash
  1210. * @addr: address of buffer for crc
  1211. * @len: length of buffer
  1212. * @val: value to be compared
  1213. */
  1214. int irdma_ieq_check_mpacrc(struct shash_desc *desc, void *addr, u32 len,
  1215. u32 val)
  1216. {
  1217. u32 crc = 0;
  1218. crypto_shash_digest(desc, addr, len, (u8 *)&crc);
  1219. if (crc != val)
  1220. return -EINVAL;
  1221. return 0;
  1222. }
  1223. /**
  1224. * irdma_ieq_get_qp - get qp based on quad in puda buffer
  1225. * @dev: hardware control device structure
  1226. * @buf: receive puda buffer on exception q
  1227. */
  1228. struct irdma_sc_qp *irdma_ieq_get_qp(struct irdma_sc_dev *dev,
  1229. struct irdma_puda_buf *buf)
  1230. {
  1231. struct irdma_qp *iwqp;
  1232. struct irdma_cm_node *cm_node;
  1233. struct irdma_device *iwdev = buf->vsi->back_vsi;
  1234. u32 loc_addr[4] = {};
  1235. u32 rem_addr[4] = {};
  1236. u16 loc_port, rem_port;
  1237. struct ipv6hdr *ip6h;
  1238. struct iphdr *iph = (struct iphdr *)buf->iph;
  1239. struct tcphdr *tcph = (struct tcphdr *)buf->tcph;
  1240. if (iph->version == 4) {
  1241. loc_addr[0] = ntohl(iph->daddr);
  1242. rem_addr[0] = ntohl(iph->saddr);
  1243. } else {
  1244. ip6h = (struct ipv6hdr *)buf->iph;
  1245. irdma_copy_ip_ntohl(loc_addr, ip6h->daddr.in6_u.u6_addr32);
  1246. irdma_copy_ip_ntohl(rem_addr, ip6h->saddr.in6_u.u6_addr32);
  1247. }
  1248. loc_port = ntohs(tcph->dest);
  1249. rem_port = ntohs(tcph->source);
  1250. cm_node = irdma_find_node(&iwdev->cm_core, rem_port, rem_addr, loc_port,
  1251. loc_addr, buf->vlan_valid ? buf->vlan_id : 0xFFFF);
  1252. if (!cm_node)
  1253. return NULL;
  1254. iwqp = cm_node->iwqp;
  1255. irdma_rem_ref_cm_node(cm_node);
  1256. return &iwqp->sc_qp;
  1257. }
  1258. /**
  1259. * irdma_send_ieq_ack - ACKs for duplicate or OOO partials FPDUs
  1260. * @qp: qp ptr
  1261. */
  1262. void irdma_send_ieq_ack(struct irdma_sc_qp *qp)
  1263. {
  1264. struct irdma_cm_node *cm_node = ((struct irdma_qp *)qp->qp_uk.back_qp)->cm_node;
  1265. struct irdma_puda_buf *buf = qp->pfpdu.lastrcv_buf;
  1266. struct tcphdr *tcph = (struct tcphdr *)buf->tcph;
  1267. cm_node->tcp_cntxt.rcv_nxt = qp->pfpdu.nextseqnum;
  1268. cm_node->tcp_cntxt.loc_seq_num = ntohl(tcph->ack_seq);
  1269. irdma_send_ack(cm_node);
  1270. }
  1271. /**
  1272. * irdma_puda_ieq_get_ah_info - get AH info from IEQ buffer
  1273. * @qp: qp pointer
  1274. * @ah_info: AH info pointer
  1275. */
  1276. void irdma_puda_ieq_get_ah_info(struct irdma_sc_qp *qp,
  1277. struct irdma_ah_info *ah_info)
  1278. {
  1279. struct irdma_puda_buf *buf = qp->pfpdu.ah_buf;
  1280. struct iphdr *iph;
  1281. struct ipv6hdr *ip6h;
  1282. memset(ah_info, 0, sizeof(*ah_info));
  1283. ah_info->do_lpbk = true;
  1284. ah_info->vlan_tag = buf->vlan_id;
  1285. ah_info->insert_vlan_tag = buf->vlan_valid;
  1286. ah_info->ipv4_valid = buf->ipv4;
  1287. ah_info->vsi = qp->vsi;
  1288. if (buf->smac_valid)
  1289. ether_addr_copy(ah_info->mac_addr, buf->smac);
  1290. if (buf->ipv4) {
  1291. ah_info->ipv4_valid = true;
  1292. iph = (struct iphdr *)buf->iph;
  1293. ah_info->hop_ttl = iph->ttl;
  1294. ah_info->tc_tos = iph->tos;
  1295. ah_info->dest_ip_addr[0] = ntohl(iph->daddr);
  1296. ah_info->src_ip_addr[0] = ntohl(iph->saddr);
  1297. } else {
  1298. ip6h = (struct ipv6hdr *)buf->iph;
  1299. ah_info->hop_ttl = ip6h->hop_limit;
  1300. ah_info->tc_tos = ip6h->priority;
  1301. irdma_copy_ip_ntohl(ah_info->dest_ip_addr,
  1302. ip6h->daddr.in6_u.u6_addr32);
  1303. irdma_copy_ip_ntohl(ah_info->src_ip_addr,
  1304. ip6h->saddr.in6_u.u6_addr32);
  1305. }
  1306. ah_info->dst_arpindex = irdma_arp_table(dev_to_rf(qp->dev),
  1307. ah_info->dest_ip_addr,
  1308. ah_info->ipv4_valid,
  1309. NULL, IRDMA_ARP_RESOLVE);
  1310. }
  1311. /**
  1312. * irdma_gen1_ieq_update_tcpip_info - update tcpip in the buffer
  1313. * @buf: puda to update
  1314. * @len: length of buffer
  1315. * @seqnum: seq number for tcp
  1316. */
  1317. static void irdma_gen1_ieq_update_tcpip_info(struct irdma_puda_buf *buf,
  1318. u16 len, u32 seqnum)
  1319. {
  1320. struct tcphdr *tcph;
  1321. struct iphdr *iph;
  1322. u16 iphlen;
  1323. u16 pktsize;
  1324. u8 *addr = buf->mem.va;
  1325. iphlen = (buf->ipv4) ? 20 : 40;
  1326. iph = (struct iphdr *)(addr + buf->maclen);
  1327. tcph = (struct tcphdr *)(addr + buf->maclen + iphlen);
  1328. pktsize = len + buf->tcphlen + iphlen;
  1329. iph->tot_len = htons(pktsize);
  1330. tcph->seq = htonl(seqnum);
  1331. }
  1332. /**
  1333. * irdma_ieq_update_tcpip_info - update tcpip in the buffer
  1334. * @buf: puda to update
  1335. * @len: length of buffer
  1336. * @seqnum: seq number for tcp
  1337. */
  1338. void irdma_ieq_update_tcpip_info(struct irdma_puda_buf *buf, u16 len,
  1339. u32 seqnum)
  1340. {
  1341. struct tcphdr *tcph;
  1342. u8 *addr;
  1343. if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
  1344. return irdma_gen1_ieq_update_tcpip_info(buf, len, seqnum);
  1345. addr = buf->mem.va;
  1346. tcph = (struct tcphdr *)addr;
  1347. tcph->seq = htonl(seqnum);
  1348. }
  1349. /**
  1350. * irdma_gen1_puda_get_tcpip_info - get tcpip info from puda
  1351. * buffer
  1352. * @info: to get information
  1353. * @buf: puda buffer
  1354. */
  1355. static int irdma_gen1_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,
  1356. struct irdma_puda_buf *buf)
  1357. {
  1358. struct iphdr *iph;
  1359. struct ipv6hdr *ip6h;
  1360. struct tcphdr *tcph;
  1361. u16 iphlen;
  1362. u16 pkt_len;
  1363. u8 *mem = buf->mem.va;
  1364. struct ethhdr *ethh = buf->mem.va;
  1365. if (ethh->h_proto == htons(0x8100)) {
  1366. info->vlan_valid = true;
  1367. buf->vlan_id = ntohs(((struct vlan_ethhdr *)ethh)->h_vlan_TCI) &
  1368. VLAN_VID_MASK;
  1369. }
  1370. buf->maclen = (info->vlan_valid) ? 18 : 14;
  1371. iphlen = (info->l3proto) ? 40 : 20;
  1372. buf->ipv4 = (info->l3proto) ? false : true;
  1373. buf->iph = mem + buf->maclen;
  1374. iph = (struct iphdr *)buf->iph;
  1375. buf->tcph = buf->iph + iphlen;
  1376. tcph = (struct tcphdr *)buf->tcph;
  1377. if (buf->ipv4) {
  1378. pkt_len = ntohs(iph->tot_len);
  1379. } else {
  1380. ip6h = (struct ipv6hdr *)buf->iph;
  1381. pkt_len = ntohs(ip6h->payload_len) + iphlen;
  1382. }
  1383. buf->totallen = pkt_len + buf->maclen;
  1384. if (info->payload_len < buf->totallen) {
  1385. ibdev_dbg(to_ibdev(buf->vsi->dev),
  1386. "ERR: payload_len = 0x%x totallen expected0x%x\n",
  1387. info->payload_len, buf->totallen);
  1388. return -EINVAL;
  1389. }
  1390. buf->tcphlen = tcph->doff << 2;
  1391. buf->datalen = pkt_len - iphlen - buf->tcphlen;
  1392. buf->data = buf->datalen ? buf->tcph + buf->tcphlen : NULL;
  1393. buf->hdrlen = buf->maclen + iphlen + buf->tcphlen;
  1394. buf->seqnum = ntohl(tcph->seq);
  1395. return 0;
  1396. }
  1397. /**
  1398. * irdma_puda_get_tcpip_info - get tcpip info from puda buffer
  1399. * @info: to get information
  1400. * @buf: puda buffer
  1401. */
  1402. int irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,
  1403. struct irdma_puda_buf *buf)
  1404. {
  1405. struct tcphdr *tcph;
  1406. u32 pkt_len;
  1407. u8 *mem;
  1408. if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
  1409. return irdma_gen1_puda_get_tcpip_info(info, buf);
  1410. mem = buf->mem.va;
  1411. buf->vlan_valid = info->vlan_valid;
  1412. if (info->vlan_valid)
  1413. buf->vlan_id = info->vlan;
  1414. buf->ipv4 = info->ipv4;
  1415. if (buf->ipv4)
  1416. buf->iph = mem + IRDMA_IPV4_PAD;
  1417. else
  1418. buf->iph = mem;
  1419. buf->tcph = mem + IRDMA_TCP_OFFSET;
  1420. tcph = (struct tcphdr *)buf->tcph;
  1421. pkt_len = info->payload_len;
  1422. buf->totallen = pkt_len;
  1423. buf->tcphlen = tcph->doff << 2;
  1424. buf->datalen = pkt_len - IRDMA_TCP_OFFSET - buf->tcphlen;
  1425. buf->data = buf->datalen ? buf->tcph + buf->tcphlen : NULL;
  1426. buf->hdrlen = IRDMA_TCP_OFFSET + buf->tcphlen;
  1427. buf->seqnum = ntohl(tcph->seq);
  1428. if (info->smac_valid) {
  1429. ether_addr_copy(buf->smac, info->smac);
  1430. buf->smac_valid = true;
  1431. }
  1432. return 0;
  1433. }
  1434. /**
  1435. * irdma_hw_stats_timeout - Stats timer-handler which updates all HW stats
  1436. * @t: timer_list pointer
  1437. */
  1438. static void irdma_hw_stats_timeout(struct timer_list *t)
  1439. {
  1440. struct irdma_vsi_pestat *pf_devstat =
  1441. from_timer(pf_devstat, t, stats_timer);
  1442. struct irdma_sc_vsi *sc_vsi = pf_devstat->vsi;
  1443. if (sc_vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
  1444. irdma_cqp_gather_stats_cmd(sc_vsi->dev, sc_vsi->pestat, false);
  1445. else
  1446. irdma_cqp_gather_stats_gen1(sc_vsi->dev, sc_vsi->pestat);
  1447. mod_timer(&pf_devstat->stats_timer,
  1448. jiffies + msecs_to_jiffies(STATS_TIMER_DELAY));
  1449. }
  1450. /**
  1451. * irdma_hw_stats_start_timer - Start periodic stats timer
  1452. * @vsi: vsi structure pointer
  1453. */
  1454. void irdma_hw_stats_start_timer(struct irdma_sc_vsi *vsi)
  1455. {
  1456. struct irdma_vsi_pestat *devstat = vsi->pestat;
  1457. timer_setup(&devstat->stats_timer, irdma_hw_stats_timeout, 0);
  1458. mod_timer(&devstat->stats_timer,
  1459. jiffies + msecs_to_jiffies(STATS_TIMER_DELAY));
  1460. }
  1461. /**
  1462. * irdma_hw_stats_stop_timer - Delete periodic stats timer
  1463. * @vsi: pointer to vsi structure
  1464. */
  1465. void irdma_hw_stats_stop_timer(struct irdma_sc_vsi *vsi)
  1466. {
  1467. struct irdma_vsi_pestat *devstat = vsi->pestat;
  1468. del_timer_sync(&devstat->stats_timer);
  1469. }
  1470. /**
  1471. * irdma_process_stats - Checking for wrap and update stats
  1472. * @pestat: stats structure pointer
  1473. */
  1474. static inline void irdma_process_stats(struct irdma_vsi_pestat *pestat)
  1475. {
  1476. sc_vsi_update_stats(pestat->vsi);
  1477. }
  1478. /**
  1479. * irdma_cqp_gather_stats_gen1 - Gather stats
  1480. * @dev: pointer to device structure
  1481. * @pestat: statistics structure
  1482. */
  1483. void irdma_cqp_gather_stats_gen1(struct irdma_sc_dev *dev,
  1484. struct irdma_vsi_pestat *pestat)
  1485. {
  1486. struct irdma_gather_stats *gather_stats =
  1487. pestat->gather_info.gather_stats_va;
  1488. const struct irdma_hw_stat_map *map = dev->hw_stats_map;
  1489. u16 max_stats_idx = dev->hw_attrs.max_stat_idx;
  1490. u32 stats_inst_offset_32;
  1491. u32 stats_inst_offset_64;
  1492. u64 new_val;
  1493. u16 i;
  1494. stats_inst_offset_32 = (pestat->gather_info.use_stats_inst) ?
  1495. pestat->gather_info.stats_inst_index :
  1496. pestat->hw->hmc.hmc_fn_id;
  1497. stats_inst_offset_32 *= 4;
  1498. stats_inst_offset_64 = stats_inst_offset_32 * 2;
  1499. for (i = 0; i < max_stats_idx; i++) {
  1500. if (map[i].bitmask <= IRDMA_MAX_STATS_32)
  1501. new_val = rd32(dev->hw,
  1502. dev->hw_stats_regs[i] + stats_inst_offset_32);
  1503. else
  1504. new_val = rd64(dev->hw,
  1505. dev->hw_stats_regs[i] + stats_inst_offset_64);
  1506. gather_stats->val[map[i].byteoff / sizeof(u64)] = new_val;
  1507. }
  1508. irdma_process_stats(pestat);
  1509. }
  1510. /**
  1511. * irdma_process_cqp_stats - Checking for wrap and update stats
  1512. * @cqp_request: cqp_request structure pointer
  1513. */
  1514. static void irdma_process_cqp_stats(struct irdma_cqp_request *cqp_request)
  1515. {
  1516. struct irdma_vsi_pestat *pestat = cqp_request->param;
  1517. irdma_process_stats(pestat);
  1518. }
  1519. /**
  1520. * irdma_cqp_gather_stats_cmd - Gather stats
  1521. * @dev: pointer to device structure
  1522. * @pestat: pointer to stats info
  1523. * @wait: flag to wait or not wait for stats
  1524. */
  1525. int irdma_cqp_gather_stats_cmd(struct irdma_sc_dev *dev,
  1526. struct irdma_vsi_pestat *pestat, bool wait)
  1527. {
  1528. struct irdma_pci_f *rf = dev_to_rf(dev);
  1529. struct irdma_cqp *iwcqp = &rf->cqp;
  1530. struct irdma_cqp_request *cqp_request;
  1531. struct cqp_cmds_info *cqp_info;
  1532. int status;
  1533. cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait);
  1534. if (!cqp_request)
  1535. return -ENOMEM;
  1536. cqp_info = &cqp_request->info;
  1537. memset(cqp_info, 0, sizeof(*cqp_info));
  1538. cqp_info->cqp_cmd = IRDMA_OP_STATS_GATHER;
  1539. cqp_info->post_sq = 1;
  1540. cqp_info->in.u.stats_gather.info = pestat->gather_info;
  1541. cqp_info->in.u.stats_gather.scratch = (uintptr_t)cqp_request;
  1542. cqp_info->in.u.stats_gather.cqp = &rf->cqp.sc_cqp;
  1543. cqp_request->param = pestat;
  1544. if (!wait)
  1545. cqp_request->callback_fcn = irdma_process_cqp_stats;
  1546. status = irdma_handle_cqp_op(rf, cqp_request);
  1547. if (wait)
  1548. irdma_process_stats(pestat);
  1549. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1550. return status;
  1551. }
  1552. /**
  1553. * irdma_cqp_stats_inst_cmd - Allocate/free stats instance
  1554. * @vsi: pointer to vsi structure
  1555. * @cmd: command to allocate or free
  1556. * @stats_info: pointer to allocate stats info
  1557. */
  1558. int irdma_cqp_stats_inst_cmd(struct irdma_sc_vsi *vsi, u8 cmd,
  1559. struct irdma_stats_inst_info *stats_info)
  1560. {
  1561. struct irdma_pci_f *rf = dev_to_rf(vsi->dev);
  1562. struct irdma_cqp *iwcqp = &rf->cqp;
  1563. struct irdma_cqp_request *cqp_request;
  1564. struct cqp_cmds_info *cqp_info;
  1565. int status;
  1566. bool wait = false;
  1567. if (cmd == IRDMA_OP_STATS_ALLOCATE)
  1568. wait = true;
  1569. cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait);
  1570. if (!cqp_request)
  1571. return -ENOMEM;
  1572. cqp_info = &cqp_request->info;
  1573. memset(cqp_info, 0, sizeof(*cqp_info));
  1574. cqp_info->cqp_cmd = cmd;
  1575. cqp_info->post_sq = 1;
  1576. cqp_info->in.u.stats_manage.info = *stats_info;
  1577. cqp_info->in.u.stats_manage.scratch = (uintptr_t)cqp_request;
  1578. cqp_info->in.u.stats_manage.cqp = &rf->cqp.sc_cqp;
  1579. status = irdma_handle_cqp_op(rf, cqp_request);
  1580. if (wait)
  1581. stats_info->stats_idx = cqp_request->compl_info.op_ret_val;
  1582. irdma_put_cqp_request(iwcqp, cqp_request);
  1583. return status;
  1584. }
  1585. /**
  1586. * irdma_cqp_ceq_cmd - Create/Destroy CEQ's after CEQ 0
  1587. * @dev: pointer to device info
  1588. * @sc_ceq: pointer to ceq structure
  1589. * @op: Create or Destroy
  1590. */
  1591. int irdma_cqp_ceq_cmd(struct irdma_sc_dev *dev, struct irdma_sc_ceq *sc_ceq,
  1592. u8 op)
  1593. {
  1594. struct irdma_cqp_request *cqp_request;
  1595. struct cqp_cmds_info *cqp_info;
  1596. struct irdma_pci_f *rf = dev_to_rf(dev);
  1597. int status;
  1598. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  1599. if (!cqp_request)
  1600. return -ENOMEM;
  1601. cqp_info = &cqp_request->info;
  1602. cqp_info->post_sq = 1;
  1603. cqp_info->cqp_cmd = op;
  1604. cqp_info->in.u.ceq_create.ceq = sc_ceq;
  1605. cqp_info->in.u.ceq_create.scratch = (uintptr_t)cqp_request;
  1606. status = irdma_handle_cqp_op(rf, cqp_request);
  1607. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1608. return status;
  1609. }
  1610. /**
  1611. * irdma_cqp_aeq_cmd - Create/Destroy AEQ
  1612. * @dev: pointer to device info
  1613. * @sc_aeq: pointer to aeq structure
  1614. * @op: Create or Destroy
  1615. */
  1616. int irdma_cqp_aeq_cmd(struct irdma_sc_dev *dev, struct irdma_sc_aeq *sc_aeq,
  1617. u8 op)
  1618. {
  1619. struct irdma_cqp_request *cqp_request;
  1620. struct cqp_cmds_info *cqp_info;
  1621. struct irdma_pci_f *rf = dev_to_rf(dev);
  1622. int status;
  1623. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  1624. if (!cqp_request)
  1625. return -ENOMEM;
  1626. cqp_info = &cqp_request->info;
  1627. cqp_info->post_sq = 1;
  1628. cqp_info->cqp_cmd = op;
  1629. cqp_info->in.u.aeq_create.aeq = sc_aeq;
  1630. cqp_info->in.u.aeq_create.scratch = (uintptr_t)cqp_request;
  1631. status = irdma_handle_cqp_op(rf, cqp_request);
  1632. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1633. return status;
  1634. }
  1635. /**
  1636. * irdma_cqp_ws_node_cmd - Add/modify/delete ws node
  1637. * @dev: pointer to device structure
  1638. * @cmd: Add, modify or delete
  1639. * @node_info: pointer to ws node info
  1640. */
  1641. int irdma_cqp_ws_node_cmd(struct irdma_sc_dev *dev, u8 cmd,
  1642. struct irdma_ws_node_info *node_info)
  1643. {
  1644. struct irdma_pci_f *rf = dev_to_rf(dev);
  1645. struct irdma_cqp *iwcqp = &rf->cqp;
  1646. struct irdma_sc_cqp *cqp = &iwcqp->sc_cqp;
  1647. struct irdma_cqp_request *cqp_request;
  1648. struct cqp_cmds_info *cqp_info;
  1649. int status;
  1650. bool poll;
  1651. if (!rf->sc_dev.ceq_valid)
  1652. poll = true;
  1653. else
  1654. poll = false;
  1655. cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, !poll);
  1656. if (!cqp_request)
  1657. return -ENOMEM;
  1658. cqp_info = &cqp_request->info;
  1659. memset(cqp_info, 0, sizeof(*cqp_info));
  1660. cqp_info->cqp_cmd = cmd;
  1661. cqp_info->post_sq = 1;
  1662. cqp_info->in.u.ws_node.info = *node_info;
  1663. cqp_info->in.u.ws_node.cqp = cqp;
  1664. cqp_info->in.u.ws_node.scratch = (uintptr_t)cqp_request;
  1665. status = irdma_handle_cqp_op(rf, cqp_request);
  1666. if (status)
  1667. goto exit;
  1668. if (poll) {
  1669. struct irdma_ccq_cqe_info compl_info;
  1670. status = irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_WORK_SCHED_NODE,
  1671. &compl_info);
  1672. node_info->qs_handle = compl_info.op_ret_val;
  1673. ibdev_dbg(&rf->iwdev->ibdev, "DCB: opcode=%d, compl_info.retval=%d\n",
  1674. compl_info.op_code, compl_info.op_ret_val);
  1675. } else {
  1676. node_info->qs_handle = cqp_request->compl_info.op_ret_val;
  1677. }
  1678. exit:
  1679. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1680. return status;
  1681. }
  1682. /**
  1683. * irdma_ah_cqp_op - perform an AH cqp operation
  1684. * @rf: RDMA PCI function
  1685. * @sc_ah: address handle
  1686. * @cmd: AH operation
  1687. * @wait: wait if true
  1688. * @callback_fcn: Callback function on CQP op completion
  1689. * @cb_param: parameter for callback function
  1690. *
  1691. * returns errno
  1692. */
  1693. int irdma_ah_cqp_op(struct irdma_pci_f *rf, struct irdma_sc_ah *sc_ah, u8 cmd,
  1694. bool wait,
  1695. void (*callback_fcn)(struct irdma_cqp_request *),
  1696. void *cb_param)
  1697. {
  1698. struct irdma_cqp_request *cqp_request;
  1699. struct cqp_cmds_info *cqp_info;
  1700. int status;
  1701. if (cmd != IRDMA_OP_AH_CREATE && cmd != IRDMA_OP_AH_DESTROY)
  1702. return -EINVAL;
  1703. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
  1704. if (!cqp_request)
  1705. return -ENOMEM;
  1706. cqp_info = &cqp_request->info;
  1707. cqp_info->cqp_cmd = cmd;
  1708. cqp_info->post_sq = 1;
  1709. if (cmd == IRDMA_OP_AH_CREATE) {
  1710. cqp_info->in.u.ah_create.info = sc_ah->ah_info;
  1711. cqp_info->in.u.ah_create.scratch = (uintptr_t)cqp_request;
  1712. cqp_info->in.u.ah_create.cqp = &rf->cqp.sc_cqp;
  1713. } else if (cmd == IRDMA_OP_AH_DESTROY) {
  1714. cqp_info->in.u.ah_destroy.info = sc_ah->ah_info;
  1715. cqp_info->in.u.ah_destroy.scratch = (uintptr_t)cqp_request;
  1716. cqp_info->in.u.ah_destroy.cqp = &rf->cqp.sc_cqp;
  1717. }
  1718. if (!wait) {
  1719. cqp_request->callback_fcn = callback_fcn;
  1720. cqp_request->param = cb_param;
  1721. }
  1722. status = irdma_handle_cqp_op(rf, cqp_request);
  1723. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1724. if (status)
  1725. return -ENOMEM;
  1726. if (wait)
  1727. sc_ah->ah_info.ah_valid = (cmd == IRDMA_OP_AH_CREATE);
  1728. return 0;
  1729. }
  1730. /**
  1731. * irdma_ieq_ah_cb - callback after creation of AH for IEQ
  1732. * @cqp_request: pointer to cqp_request of create AH
  1733. */
  1734. static void irdma_ieq_ah_cb(struct irdma_cqp_request *cqp_request)
  1735. {
  1736. struct irdma_sc_qp *qp = cqp_request->param;
  1737. struct irdma_sc_ah *sc_ah = qp->pfpdu.ah;
  1738. unsigned long flags;
  1739. spin_lock_irqsave(&qp->pfpdu.lock, flags);
  1740. if (!cqp_request->compl_info.op_ret_val) {
  1741. sc_ah->ah_info.ah_valid = true;
  1742. irdma_ieq_process_fpdus(qp, qp->vsi->ieq);
  1743. } else {
  1744. sc_ah->ah_info.ah_valid = false;
  1745. irdma_ieq_cleanup_qp(qp->vsi->ieq, qp);
  1746. }
  1747. spin_unlock_irqrestore(&qp->pfpdu.lock, flags);
  1748. }
  1749. /**
  1750. * irdma_ilq_ah_cb - callback after creation of AH for ILQ
  1751. * @cqp_request: pointer to cqp_request of create AH
  1752. */
  1753. static void irdma_ilq_ah_cb(struct irdma_cqp_request *cqp_request)
  1754. {
  1755. struct irdma_cm_node *cm_node = cqp_request->param;
  1756. struct irdma_sc_ah *sc_ah = cm_node->ah;
  1757. sc_ah->ah_info.ah_valid = !cqp_request->compl_info.op_ret_val;
  1758. irdma_add_conn_est_qh(cm_node);
  1759. }
  1760. /**
  1761. * irdma_puda_create_ah - create AH for ILQ/IEQ qp's
  1762. * @dev: device pointer
  1763. * @ah_info: Address handle info
  1764. * @wait: When true will wait for operation to complete
  1765. * @type: ILQ/IEQ
  1766. * @cb_param: Callback param when not waiting
  1767. * @ah_ret: Returned pointer to address handle if created
  1768. *
  1769. */
  1770. int irdma_puda_create_ah(struct irdma_sc_dev *dev,
  1771. struct irdma_ah_info *ah_info, bool wait,
  1772. enum puda_rsrc_type type, void *cb_param,
  1773. struct irdma_sc_ah **ah_ret)
  1774. {
  1775. struct irdma_sc_ah *ah;
  1776. struct irdma_pci_f *rf = dev_to_rf(dev);
  1777. int err;
  1778. ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
  1779. *ah_ret = ah;
  1780. if (!ah)
  1781. return -ENOMEM;
  1782. err = irdma_alloc_rsrc(rf, rf->allocated_ahs, rf->max_ah,
  1783. &ah_info->ah_idx, &rf->next_ah);
  1784. if (err)
  1785. goto err_free;
  1786. ah->dev = dev;
  1787. ah->ah_info = *ah_info;
  1788. if (type == IRDMA_PUDA_RSRC_TYPE_ILQ)
  1789. err = irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_CREATE, wait,
  1790. irdma_ilq_ah_cb, cb_param);
  1791. else
  1792. err = irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_CREATE, wait,
  1793. irdma_ieq_ah_cb, cb_param);
  1794. if (err)
  1795. goto error;
  1796. return 0;
  1797. error:
  1798. irdma_free_rsrc(rf, rf->allocated_ahs, ah->ah_info.ah_idx);
  1799. err_free:
  1800. kfree(ah);
  1801. *ah_ret = NULL;
  1802. return -ENOMEM;
  1803. }
  1804. /**
  1805. * irdma_puda_free_ah - free a puda address handle
  1806. * @dev: device pointer
  1807. * @ah: The address handle to free
  1808. */
  1809. void irdma_puda_free_ah(struct irdma_sc_dev *dev, struct irdma_sc_ah *ah)
  1810. {
  1811. struct irdma_pci_f *rf = dev_to_rf(dev);
  1812. if (!ah)
  1813. return;
  1814. if (ah->ah_info.ah_valid) {
  1815. irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_DESTROY, false, NULL, NULL);
  1816. irdma_free_rsrc(rf, rf->allocated_ahs, ah->ah_info.ah_idx);
  1817. }
  1818. kfree(ah);
  1819. }
  1820. /**
  1821. * irdma_gsi_ud_qp_ah_cb - callback after creation of AH for GSI/ID QP
  1822. * @cqp_request: pointer to cqp_request of create AH
  1823. */
  1824. void irdma_gsi_ud_qp_ah_cb(struct irdma_cqp_request *cqp_request)
  1825. {
  1826. struct irdma_sc_ah *sc_ah = cqp_request->param;
  1827. if (!cqp_request->compl_info.op_ret_val)
  1828. sc_ah->ah_info.ah_valid = true;
  1829. else
  1830. sc_ah->ah_info.ah_valid = false;
  1831. }
  1832. /**
  1833. * irdma_prm_add_pble_mem - add moemory to pble resources
  1834. * @pprm: pble resource manager
  1835. * @pchunk: chunk of memory to add
  1836. */
  1837. int irdma_prm_add_pble_mem(struct irdma_pble_prm *pprm,
  1838. struct irdma_chunk *pchunk)
  1839. {
  1840. u64 sizeofbitmap;
  1841. if (pchunk->size & 0xfff)
  1842. return -EINVAL;
  1843. sizeofbitmap = (u64)pchunk->size >> pprm->pble_shift;
  1844. pchunk->bitmapbuf = bitmap_zalloc(sizeofbitmap, GFP_KERNEL);
  1845. if (!pchunk->bitmapbuf)
  1846. return -ENOMEM;
  1847. pchunk->sizeofbitmap = sizeofbitmap;
  1848. /* each pble is 8 bytes hence shift by 3 */
  1849. pprm->total_pble_alloc += pchunk->size >> 3;
  1850. pprm->free_pble_cnt += pchunk->size >> 3;
  1851. return 0;
  1852. }
  1853. /**
  1854. * irdma_prm_get_pbles - get pble's from prm
  1855. * @pprm: pble resource manager
  1856. * @chunkinfo: nformation about chunk where pble's were acquired
  1857. * @mem_size: size of pble memory needed
  1858. * @vaddr: returns virtual address of pble memory
  1859. * @fpm_addr: returns fpm address of pble memory
  1860. */
  1861. int irdma_prm_get_pbles(struct irdma_pble_prm *pprm,
  1862. struct irdma_pble_chunkinfo *chunkinfo, u64 mem_size,
  1863. u64 **vaddr, u64 *fpm_addr)
  1864. {
  1865. u64 bits_needed;
  1866. u64 bit_idx = PBLE_INVALID_IDX;
  1867. struct irdma_chunk *pchunk = NULL;
  1868. struct list_head *chunk_entry = pprm->clist.next;
  1869. u32 offset;
  1870. unsigned long flags;
  1871. *vaddr = NULL;
  1872. *fpm_addr = 0;
  1873. bits_needed = DIV_ROUND_UP_ULL(mem_size, BIT_ULL(pprm->pble_shift));
  1874. spin_lock_irqsave(&pprm->prm_lock, flags);
  1875. while (chunk_entry != &pprm->clist) {
  1876. pchunk = (struct irdma_chunk *)chunk_entry;
  1877. bit_idx = bitmap_find_next_zero_area(pchunk->bitmapbuf,
  1878. pchunk->sizeofbitmap, 0,
  1879. bits_needed, 0);
  1880. if (bit_idx < pchunk->sizeofbitmap)
  1881. break;
  1882. /* list.next used macro */
  1883. chunk_entry = pchunk->list.next;
  1884. }
  1885. if (!pchunk || bit_idx >= pchunk->sizeofbitmap) {
  1886. spin_unlock_irqrestore(&pprm->prm_lock, flags);
  1887. return -ENOMEM;
  1888. }
  1889. bitmap_set(pchunk->bitmapbuf, bit_idx, bits_needed);
  1890. offset = bit_idx << pprm->pble_shift;
  1891. *vaddr = pchunk->vaddr + offset;
  1892. *fpm_addr = pchunk->fpm_addr + offset;
  1893. chunkinfo->pchunk = pchunk;
  1894. chunkinfo->bit_idx = bit_idx;
  1895. chunkinfo->bits_used = bits_needed;
  1896. /* 3 is sizeof pble divide */
  1897. pprm->free_pble_cnt -= chunkinfo->bits_used << (pprm->pble_shift - 3);
  1898. spin_unlock_irqrestore(&pprm->prm_lock, flags);
  1899. return 0;
  1900. }
  1901. /**
  1902. * irdma_prm_return_pbles - return pbles back to prm
  1903. * @pprm: pble resource manager
  1904. * @chunkinfo: chunk where pble's were acquired and to be freed
  1905. */
  1906. void irdma_prm_return_pbles(struct irdma_pble_prm *pprm,
  1907. struct irdma_pble_chunkinfo *chunkinfo)
  1908. {
  1909. unsigned long flags;
  1910. spin_lock_irqsave(&pprm->prm_lock, flags);
  1911. pprm->free_pble_cnt += chunkinfo->bits_used << (pprm->pble_shift - 3);
  1912. bitmap_clear(chunkinfo->pchunk->bitmapbuf, chunkinfo->bit_idx,
  1913. chunkinfo->bits_used);
  1914. spin_unlock_irqrestore(&pprm->prm_lock, flags);
  1915. }
  1916. int irdma_map_vm_page_list(struct irdma_hw *hw, void *va, dma_addr_t *pg_dma,
  1917. u32 pg_cnt)
  1918. {
  1919. struct page *vm_page;
  1920. int i;
  1921. u8 *addr;
  1922. addr = (u8 *)(uintptr_t)va;
  1923. for (i = 0; i < pg_cnt; i++) {
  1924. vm_page = vmalloc_to_page(addr);
  1925. if (!vm_page)
  1926. goto err;
  1927. pg_dma[i] = dma_map_page(hw->device, vm_page, 0, PAGE_SIZE,
  1928. DMA_BIDIRECTIONAL);
  1929. if (dma_mapping_error(hw->device, pg_dma[i]))
  1930. goto err;
  1931. addr += PAGE_SIZE;
  1932. }
  1933. return 0;
  1934. err:
  1935. irdma_unmap_vm_page_list(hw, pg_dma, i);
  1936. return -ENOMEM;
  1937. }
  1938. void irdma_unmap_vm_page_list(struct irdma_hw *hw, dma_addr_t *pg_dma, u32 pg_cnt)
  1939. {
  1940. int i;
  1941. for (i = 0; i < pg_cnt; i++)
  1942. dma_unmap_page(hw->device, pg_dma[i], PAGE_SIZE, DMA_BIDIRECTIONAL);
  1943. }
  1944. /**
  1945. * irdma_pble_free_paged_mem - free virtual paged memory
  1946. * @chunk: chunk to free with paged memory
  1947. */
  1948. void irdma_pble_free_paged_mem(struct irdma_chunk *chunk)
  1949. {
  1950. if (!chunk->pg_cnt)
  1951. goto done;
  1952. irdma_unmap_vm_page_list(chunk->dev->hw, chunk->dmainfo.dmaaddrs,
  1953. chunk->pg_cnt);
  1954. done:
  1955. kfree(chunk->dmainfo.dmaaddrs);
  1956. chunk->dmainfo.dmaaddrs = NULL;
  1957. vfree(chunk->vaddr);
  1958. chunk->vaddr = NULL;
  1959. chunk->type = 0;
  1960. }
  1961. /**
  1962. * irdma_pble_get_paged_mem -allocate paged memory for pbles
  1963. * @chunk: chunk to add for paged memory
  1964. * @pg_cnt: number of pages needed
  1965. */
  1966. int irdma_pble_get_paged_mem(struct irdma_chunk *chunk, u32 pg_cnt)
  1967. {
  1968. u32 size;
  1969. void *va;
  1970. chunk->dmainfo.dmaaddrs = kzalloc(pg_cnt << 3, GFP_KERNEL);
  1971. if (!chunk->dmainfo.dmaaddrs)
  1972. return -ENOMEM;
  1973. size = PAGE_SIZE * pg_cnt;
  1974. va = vmalloc(size);
  1975. if (!va)
  1976. goto err;
  1977. if (irdma_map_vm_page_list(chunk->dev->hw, va, chunk->dmainfo.dmaaddrs,
  1978. pg_cnt)) {
  1979. vfree(va);
  1980. goto err;
  1981. }
  1982. chunk->vaddr = va;
  1983. chunk->size = size;
  1984. chunk->pg_cnt = pg_cnt;
  1985. chunk->type = PBLE_SD_PAGED;
  1986. return 0;
  1987. err:
  1988. kfree(chunk->dmainfo.dmaaddrs);
  1989. chunk->dmainfo.dmaaddrs = NULL;
  1990. return -ENOMEM;
  1991. }
  1992. /**
  1993. * irdma_alloc_ws_node_id - Allocate a tx scheduler node ID
  1994. * @dev: device pointer
  1995. */
  1996. u16 irdma_alloc_ws_node_id(struct irdma_sc_dev *dev)
  1997. {
  1998. struct irdma_pci_f *rf = dev_to_rf(dev);
  1999. u32 next = 1;
  2000. u32 node_id;
  2001. if (irdma_alloc_rsrc(rf, rf->allocated_ws_nodes, rf->max_ws_node_id,
  2002. &node_id, &next))
  2003. return IRDMA_WS_NODE_INVALID;
  2004. return (u16)node_id;
  2005. }
  2006. /**
  2007. * irdma_free_ws_node_id - Free a tx scheduler node ID
  2008. * @dev: device pointer
  2009. * @node_id: Work scheduler node ID
  2010. */
  2011. void irdma_free_ws_node_id(struct irdma_sc_dev *dev, u16 node_id)
  2012. {
  2013. struct irdma_pci_f *rf = dev_to_rf(dev);
  2014. irdma_free_rsrc(rf, rf->allocated_ws_nodes, (u32)node_id);
  2015. }
  2016. /**
  2017. * irdma_modify_qp_to_err - Modify a QP to error
  2018. * @sc_qp: qp structure
  2019. */
  2020. void irdma_modify_qp_to_err(struct irdma_sc_qp *sc_qp)
  2021. {
  2022. struct irdma_qp *qp = sc_qp->qp_uk.back_qp;
  2023. struct ib_qp_attr attr;
  2024. if (qp->iwdev->rf->reset)
  2025. return;
  2026. attr.qp_state = IB_QPS_ERR;
  2027. if (rdma_protocol_roce(qp->ibqp.device, 1))
  2028. irdma_modify_qp_roce(&qp->ibqp, &attr, IB_QP_STATE, NULL);
  2029. else
  2030. irdma_modify_qp(&qp->ibqp, &attr, IB_QP_STATE, NULL);
  2031. }
  2032. void irdma_ib_qp_event(struct irdma_qp *iwqp, enum irdma_qp_event_type event)
  2033. {
  2034. struct ib_event ibevent;
  2035. if (!iwqp->ibqp.event_handler)
  2036. return;
  2037. switch (event) {
  2038. case IRDMA_QP_EVENT_CATASTROPHIC:
  2039. ibevent.event = IB_EVENT_QP_FATAL;
  2040. break;
  2041. case IRDMA_QP_EVENT_ACCESS_ERR:
  2042. ibevent.event = IB_EVENT_QP_ACCESS_ERR;
  2043. break;
  2044. case IRDMA_QP_EVENT_REQ_ERR:
  2045. ibevent.event = IB_EVENT_QP_REQ_ERR;
  2046. break;
  2047. }
  2048. ibevent.device = iwqp->ibqp.device;
  2049. ibevent.element.qp = &iwqp->ibqp;
  2050. iwqp->ibqp.event_handler(&ibevent, iwqp->ibqp.qp_context);
  2051. }
  2052. bool irdma_cq_empty(struct irdma_cq *iwcq)
  2053. {
  2054. struct irdma_cq_uk *ukcq;
  2055. u64 qword3;
  2056. __le64 *cqe;
  2057. u8 polarity;
  2058. ukcq = &iwcq->sc_cq.cq_uk;
  2059. cqe = IRDMA_GET_CURRENT_CQ_ELEM(ukcq);
  2060. get_64bit_val(cqe, 24, &qword3);
  2061. polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3);
  2062. return polarity != ukcq->polarity;
  2063. }
  2064. void irdma_remove_cmpls_list(struct irdma_cq *iwcq)
  2065. {
  2066. struct irdma_cmpl_gen *cmpl_node;
  2067. struct list_head *tmp_node, *list_node;
  2068. list_for_each_safe (list_node, tmp_node, &iwcq->cmpl_generated) {
  2069. cmpl_node = list_entry(list_node, struct irdma_cmpl_gen, list);
  2070. list_del(&cmpl_node->list);
  2071. kfree(cmpl_node);
  2072. }
  2073. }
  2074. int irdma_generated_cmpls(struct irdma_cq *iwcq, struct irdma_cq_poll_info *cq_poll_info)
  2075. {
  2076. struct irdma_cmpl_gen *cmpl;
  2077. if (list_empty(&iwcq->cmpl_generated))
  2078. return -ENOENT;
  2079. cmpl = list_first_entry_or_null(&iwcq->cmpl_generated, struct irdma_cmpl_gen, list);
  2080. list_del(&cmpl->list);
  2081. memcpy(cq_poll_info, &cmpl->cpi, sizeof(*cq_poll_info));
  2082. kfree(cmpl);
  2083. ibdev_dbg(iwcq->ibcq.device,
  2084. "VERBS: %s: Poll artificially generated completion for QP 0x%X, op %u, wr_id=0x%llx\n",
  2085. __func__, cq_poll_info->qp_id, cq_poll_info->op_type,
  2086. cq_poll_info->wr_id);
  2087. return 0;
  2088. }
  2089. /**
  2090. * irdma_set_cpi_common_values - fill in values for polling info struct
  2091. * @cpi: resulting structure of cq_poll_info type
  2092. * @qp: QPair
  2093. * @qp_num: id of the QP
  2094. */
  2095. static void irdma_set_cpi_common_values(struct irdma_cq_poll_info *cpi,
  2096. struct irdma_qp_uk *qp, u32 qp_num)
  2097. {
  2098. cpi->comp_status = IRDMA_COMPL_STATUS_FLUSHED;
  2099. cpi->error = true;
  2100. cpi->major_err = IRDMA_FLUSH_MAJOR_ERR;
  2101. cpi->minor_err = FLUSH_GENERAL_ERR;
  2102. cpi->qp_handle = (irdma_qp_handle)(uintptr_t)qp;
  2103. cpi->qp_id = qp_num;
  2104. }
  2105. static inline void irdma_comp_handler(struct irdma_cq *cq)
  2106. {
  2107. if (!cq->ibcq.comp_handler)
  2108. return;
  2109. if (atomic_cmpxchg(&cq->armed, 1, 0))
  2110. cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
  2111. }
  2112. void irdma_generate_flush_completions(struct irdma_qp *iwqp)
  2113. {
  2114. struct irdma_qp_uk *qp = &iwqp->sc_qp.qp_uk;
  2115. struct irdma_ring *sq_ring = &qp->sq_ring;
  2116. struct irdma_ring *rq_ring = &qp->rq_ring;
  2117. struct irdma_cmpl_gen *cmpl;
  2118. __le64 *sw_wqe;
  2119. u64 wqe_qword;
  2120. u32 wqe_idx;
  2121. bool compl_generated = false;
  2122. unsigned long flags1;
  2123. spin_lock_irqsave(&iwqp->iwscq->lock, flags1);
  2124. if (irdma_cq_empty(iwqp->iwscq)) {
  2125. unsigned long flags2;
  2126. spin_lock_irqsave(&iwqp->lock, flags2);
  2127. while (IRDMA_RING_MORE_WORK(*sq_ring)) {
  2128. cmpl = kzalloc(sizeof(*cmpl), GFP_ATOMIC);
  2129. if (!cmpl) {
  2130. spin_unlock_irqrestore(&iwqp->lock, flags2);
  2131. spin_unlock_irqrestore(&iwqp->iwscq->lock, flags1);
  2132. return;
  2133. }
  2134. wqe_idx = sq_ring->tail;
  2135. irdma_set_cpi_common_values(&cmpl->cpi, qp, qp->qp_id);
  2136. cmpl->cpi.wr_id = qp->sq_wrtrk_array[wqe_idx].wrid;
  2137. sw_wqe = qp->sq_base[wqe_idx].elem;
  2138. get_64bit_val(sw_wqe, 24, &wqe_qword);
  2139. cmpl->cpi.op_type = (u8)FIELD_GET(IRDMAQPSQ_OPCODE, IRDMAQPSQ_OPCODE);
  2140. cmpl->cpi.q_type = IRDMA_CQE_QTYPE_SQ;
  2141. /* remove the SQ WR by moving SQ tail*/
  2142. IRDMA_RING_SET_TAIL(*sq_ring,
  2143. sq_ring->tail + qp->sq_wrtrk_array[sq_ring->tail].quanta);
  2144. if (cmpl->cpi.op_type == IRDMAQP_OP_NOP) {
  2145. kfree(cmpl);
  2146. continue;
  2147. }
  2148. ibdev_dbg(iwqp->iwscq->ibcq.device,
  2149. "DEV: %s: adding wr_id = 0x%llx SQ Completion to list qp_id=%d\n",
  2150. __func__, cmpl->cpi.wr_id, qp->qp_id);
  2151. list_add_tail(&cmpl->list, &iwqp->iwscq->cmpl_generated);
  2152. compl_generated = true;
  2153. }
  2154. spin_unlock_irqrestore(&iwqp->lock, flags2);
  2155. spin_unlock_irqrestore(&iwqp->iwscq->lock, flags1);
  2156. if (compl_generated)
  2157. irdma_comp_handler(iwqp->iwscq);
  2158. } else {
  2159. spin_unlock_irqrestore(&iwqp->iwscq->lock, flags1);
  2160. mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush,
  2161. msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
  2162. }
  2163. spin_lock_irqsave(&iwqp->iwrcq->lock, flags1);
  2164. if (irdma_cq_empty(iwqp->iwrcq)) {
  2165. unsigned long flags2;
  2166. spin_lock_irqsave(&iwqp->lock, flags2);
  2167. while (IRDMA_RING_MORE_WORK(*rq_ring)) {
  2168. cmpl = kzalloc(sizeof(*cmpl), GFP_ATOMIC);
  2169. if (!cmpl) {
  2170. spin_unlock_irqrestore(&iwqp->lock, flags2);
  2171. spin_unlock_irqrestore(&iwqp->iwrcq->lock, flags1);
  2172. return;
  2173. }
  2174. wqe_idx = rq_ring->tail;
  2175. irdma_set_cpi_common_values(&cmpl->cpi, qp, qp->qp_id);
  2176. cmpl->cpi.wr_id = qp->rq_wrid_array[wqe_idx];
  2177. cmpl->cpi.op_type = IRDMA_OP_TYPE_REC;
  2178. cmpl->cpi.q_type = IRDMA_CQE_QTYPE_RQ;
  2179. /* remove the RQ WR by moving RQ tail */
  2180. IRDMA_RING_SET_TAIL(*rq_ring, rq_ring->tail + 1);
  2181. ibdev_dbg(iwqp->iwrcq->ibcq.device,
  2182. "DEV: %s: adding wr_id = 0x%llx RQ Completion to list qp_id=%d, wqe_idx=%d\n",
  2183. __func__, cmpl->cpi.wr_id, qp->qp_id,
  2184. wqe_idx);
  2185. list_add_tail(&cmpl->list, &iwqp->iwrcq->cmpl_generated);
  2186. compl_generated = true;
  2187. }
  2188. spin_unlock_irqrestore(&iwqp->lock, flags2);
  2189. spin_unlock_irqrestore(&iwqp->iwrcq->lock, flags1);
  2190. if (compl_generated)
  2191. irdma_comp_handler(iwqp->iwrcq);
  2192. } else {
  2193. spin_unlock_irqrestore(&iwqp->iwrcq->lock, flags1);
  2194. mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush,
  2195. msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
  2196. }
  2197. }