verbs.c 133 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
  2. /* Copyright (c) 2015 - 2021 Intel Corporation */
  3. #include "main.h"
  4. /**
  5. * irdma_query_device - get device attributes
  6. * @ibdev: device pointer from stack
  7. * @props: returning device attributes
  8. * @udata: user data
  9. */
  10. static int irdma_query_device(struct ib_device *ibdev,
  11. struct ib_device_attr *props,
  12. struct ib_udata *udata)
  13. {
  14. struct irdma_device *iwdev = to_iwdev(ibdev);
  15. struct irdma_pci_f *rf = iwdev->rf;
  16. struct pci_dev *pcidev = iwdev->rf->pcidev;
  17. struct irdma_hw_attrs *hw_attrs = &rf->sc_dev.hw_attrs;
  18. if (udata->inlen || udata->outlen)
  19. return -EINVAL;
  20. memset(props, 0, sizeof(*props));
  21. addrconf_addr_eui48((u8 *)&props->sys_image_guid,
  22. iwdev->netdev->dev_addr);
  23. props->fw_ver = (u64)irdma_fw_major_ver(&rf->sc_dev) << 32 |
  24. irdma_fw_minor_ver(&rf->sc_dev);
  25. props->device_cap_flags = IB_DEVICE_MEM_WINDOW |
  26. IB_DEVICE_MEM_MGT_EXTENSIONS;
  27. props->kernel_cap_flags = IBK_LOCAL_DMA_LKEY;
  28. props->vendor_id = pcidev->vendor;
  29. props->vendor_part_id = pcidev->device;
  30. props->hw_ver = rf->pcidev->revision;
  31. props->page_size_cap = hw_attrs->page_size_cap;
  32. props->max_mr_size = hw_attrs->max_mr_size;
  33. props->max_qp = rf->max_qp - rf->used_qps;
  34. props->max_qp_wr = hw_attrs->max_qp_wr;
  35. props->max_send_sge = hw_attrs->uk_attrs.max_hw_wq_frags;
  36. props->max_recv_sge = hw_attrs->uk_attrs.max_hw_wq_frags;
  37. props->max_cq = rf->max_cq - rf->used_cqs;
  38. props->max_cqe = rf->max_cqe - 1;
  39. props->max_mr = rf->max_mr - rf->used_mrs;
  40. props->max_mw = props->max_mr;
  41. props->max_pd = rf->max_pd - rf->used_pds;
  42. props->max_sge_rd = hw_attrs->uk_attrs.max_hw_read_sges;
  43. props->max_qp_rd_atom = hw_attrs->max_hw_ird;
  44. props->max_qp_init_rd_atom = hw_attrs->max_hw_ord;
  45. if (rdma_protocol_roce(ibdev, 1)) {
  46. props->device_cap_flags |= IB_DEVICE_RC_RNR_NAK_GEN;
  47. props->max_pkeys = IRDMA_PKEY_TBL_SZ;
  48. }
  49. props->max_ah = rf->max_ah;
  50. props->max_mcast_grp = rf->max_mcg;
  51. props->max_mcast_qp_attach = IRDMA_MAX_MGS_PER_CTX;
  52. props->max_total_mcast_qp_attach = rf->max_qp * IRDMA_MAX_MGS_PER_CTX;
  53. props->max_fast_reg_page_list_len = IRDMA_MAX_PAGES_PER_FMR;
  54. #define HCA_CLOCK_TIMESTAMP_MASK 0x1ffff
  55. if (hw_attrs->uk_attrs.hw_rev >= IRDMA_GEN_2)
  56. props->timestamp_mask = HCA_CLOCK_TIMESTAMP_MASK;
  57. return 0;
  58. }
  59. /**
  60. * irdma_query_port - get port attributes
  61. * @ibdev: device pointer from stack
  62. * @port: port number for query
  63. * @props: returning device attributes
  64. */
  65. static int irdma_query_port(struct ib_device *ibdev, u32 port,
  66. struct ib_port_attr *props)
  67. {
  68. struct irdma_device *iwdev = to_iwdev(ibdev);
  69. struct net_device *netdev = iwdev->netdev;
  70. /* no need to zero out pros here. done by caller */
  71. props->max_mtu = IB_MTU_4096;
  72. props->active_mtu = ib_mtu_int_to_enum(netdev->mtu);
  73. props->lid = 1;
  74. props->lmc = 0;
  75. props->sm_lid = 0;
  76. props->sm_sl = 0;
  77. if (netif_carrier_ok(netdev) && netif_running(netdev)) {
  78. props->state = IB_PORT_ACTIVE;
  79. props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
  80. } else {
  81. props->state = IB_PORT_DOWN;
  82. props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
  83. }
  84. ib_get_eth_speed(ibdev, port, &props->active_speed,
  85. &props->active_width);
  86. if (rdma_protocol_roce(ibdev, 1)) {
  87. props->gid_tbl_len = 32;
  88. props->ip_gids = true;
  89. props->pkey_tbl_len = IRDMA_PKEY_TBL_SZ;
  90. } else {
  91. props->gid_tbl_len = 1;
  92. }
  93. props->qkey_viol_cntr = 0;
  94. props->port_cap_flags |= IB_PORT_CM_SUP | IB_PORT_REINIT_SUP;
  95. props->max_msg_sz = iwdev->rf->sc_dev.hw_attrs.max_hw_outbound_msg_size;
  96. return 0;
  97. }
  98. /**
  99. * irdma_disassociate_ucontext - Disassociate user context
  100. * @context: ib user context
  101. */
  102. static void irdma_disassociate_ucontext(struct ib_ucontext *context)
  103. {
  104. }
  105. static int irdma_mmap_legacy(struct irdma_ucontext *ucontext,
  106. struct vm_area_struct *vma)
  107. {
  108. u64 pfn;
  109. if (vma->vm_pgoff || vma->vm_end - vma->vm_start != PAGE_SIZE)
  110. return -EINVAL;
  111. vma->vm_private_data = ucontext;
  112. pfn = ((uintptr_t)ucontext->iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET] +
  113. pci_resource_start(ucontext->iwdev->rf->pcidev, 0)) >> PAGE_SHIFT;
  114. return rdma_user_mmap_io(&ucontext->ibucontext, vma, pfn, PAGE_SIZE,
  115. pgprot_noncached(vma->vm_page_prot), NULL);
  116. }
  117. static void irdma_mmap_free(struct rdma_user_mmap_entry *rdma_entry)
  118. {
  119. struct irdma_user_mmap_entry *entry = to_irdma_mmap_entry(rdma_entry);
  120. kfree(entry);
  121. }
  122. static struct rdma_user_mmap_entry*
  123. irdma_user_mmap_entry_insert(struct irdma_ucontext *ucontext, u64 bar_offset,
  124. enum irdma_mmap_flag mmap_flag, u64 *mmap_offset)
  125. {
  126. struct irdma_user_mmap_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL);
  127. int ret;
  128. if (!entry)
  129. return NULL;
  130. entry->bar_offset = bar_offset;
  131. entry->mmap_flag = mmap_flag;
  132. ret = rdma_user_mmap_entry_insert(&ucontext->ibucontext,
  133. &entry->rdma_entry, PAGE_SIZE);
  134. if (ret) {
  135. kfree(entry);
  136. return NULL;
  137. }
  138. *mmap_offset = rdma_user_mmap_get_offset(&entry->rdma_entry);
  139. return &entry->rdma_entry;
  140. }
  141. /**
  142. * irdma_mmap - user memory map
  143. * @context: context created during alloc
  144. * @vma: kernel info for user memory map
  145. */
  146. static int irdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  147. {
  148. struct rdma_user_mmap_entry *rdma_entry;
  149. struct irdma_user_mmap_entry *entry;
  150. struct irdma_ucontext *ucontext;
  151. u64 pfn;
  152. int ret;
  153. ucontext = to_ucontext(context);
  154. /* Legacy support for libi40iw with hard-coded mmap key */
  155. if (ucontext->legacy_mode)
  156. return irdma_mmap_legacy(ucontext, vma);
  157. rdma_entry = rdma_user_mmap_entry_get(&ucontext->ibucontext, vma);
  158. if (!rdma_entry) {
  159. ibdev_dbg(&ucontext->iwdev->ibdev,
  160. "VERBS: pgoff[0x%lx] does not have valid entry\n",
  161. vma->vm_pgoff);
  162. return -EINVAL;
  163. }
  164. entry = to_irdma_mmap_entry(rdma_entry);
  165. ibdev_dbg(&ucontext->iwdev->ibdev,
  166. "VERBS: bar_offset [0x%llx] mmap_flag [%d]\n",
  167. entry->bar_offset, entry->mmap_flag);
  168. pfn = (entry->bar_offset +
  169. pci_resource_start(ucontext->iwdev->rf->pcidev, 0)) >> PAGE_SHIFT;
  170. switch (entry->mmap_flag) {
  171. case IRDMA_MMAP_IO_NC:
  172. ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE,
  173. pgprot_noncached(vma->vm_page_prot),
  174. rdma_entry);
  175. break;
  176. case IRDMA_MMAP_IO_WC:
  177. ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE,
  178. pgprot_writecombine(vma->vm_page_prot),
  179. rdma_entry);
  180. break;
  181. default:
  182. ret = -EINVAL;
  183. }
  184. if (ret)
  185. ibdev_dbg(&ucontext->iwdev->ibdev,
  186. "VERBS: bar_offset [0x%llx] mmap_flag[%d] err[%d]\n",
  187. entry->bar_offset, entry->mmap_flag, ret);
  188. rdma_user_mmap_entry_put(rdma_entry);
  189. return ret;
  190. }
  191. /**
  192. * irdma_alloc_push_page - allocate a push page for qp
  193. * @iwqp: qp pointer
  194. */
  195. static void irdma_alloc_push_page(struct irdma_qp *iwqp)
  196. {
  197. struct irdma_cqp_request *cqp_request;
  198. struct cqp_cmds_info *cqp_info;
  199. struct irdma_device *iwdev = iwqp->iwdev;
  200. struct irdma_sc_qp *qp = &iwqp->sc_qp;
  201. int status;
  202. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  203. if (!cqp_request)
  204. return;
  205. cqp_info = &cqp_request->info;
  206. cqp_info->cqp_cmd = IRDMA_OP_MANAGE_PUSH_PAGE;
  207. cqp_info->post_sq = 1;
  208. cqp_info->in.u.manage_push_page.info.push_idx = 0;
  209. cqp_info->in.u.manage_push_page.info.qs_handle =
  210. qp->vsi->qos[qp->user_pri].qs_handle;
  211. cqp_info->in.u.manage_push_page.info.free_page = 0;
  212. cqp_info->in.u.manage_push_page.info.push_page_type = 0;
  213. cqp_info->in.u.manage_push_page.cqp = &iwdev->rf->cqp.sc_cqp;
  214. cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
  215. status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
  216. if (!status && cqp_request->compl_info.op_ret_val <
  217. iwdev->rf->sc_dev.hw_attrs.max_hw_device_pages) {
  218. qp->push_idx = cqp_request->compl_info.op_ret_val;
  219. qp->push_offset = 0;
  220. }
  221. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  222. }
  223. /**
  224. * irdma_alloc_ucontext - Allocate the user context data structure
  225. * @uctx: uverbs context pointer
  226. * @udata: user data
  227. *
  228. * This keeps track of all objects associated with a particular
  229. * user-mode client.
  230. */
  231. static int irdma_alloc_ucontext(struct ib_ucontext *uctx,
  232. struct ib_udata *udata)
  233. {
  234. #define IRDMA_ALLOC_UCTX_MIN_REQ_LEN offsetofend(struct irdma_alloc_ucontext_req, rsvd8)
  235. #define IRDMA_ALLOC_UCTX_MIN_RESP_LEN offsetofend(struct irdma_alloc_ucontext_resp, rsvd)
  236. struct ib_device *ibdev = uctx->device;
  237. struct irdma_device *iwdev = to_iwdev(ibdev);
  238. struct irdma_alloc_ucontext_req req = {};
  239. struct irdma_alloc_ucontext_resp uresp = {};
  240. struct irdma_ucontext *ucontext = to_ucontext(uctx);
  241. struct irdma_uk_attrs *uk_attrs = &iwdev->rf->sc_dev.hw_attrs.uk_attrs;
  242. if (udata->inlen < IRDMA_ALLOC_UCTX_MIN_REQ_LEN ||
  243. udata->outlen < IRDMA_ALLOC_UCTX_MIN_RESP_LEN)
  244. return -EINVAL;
  245. if (ib_copy_from_udata(&req, udata, min(sizeof(req), udata->inlen)))
  246. return -EINVAL;
  247. if (req.userspace_ver < 4 || req.userspace_ver > IRDMA_ABI_VER)
  248. goto ver_error;
  249. ucontext->iwdev = iwdev;
  250. ucontext->abi_ver = req.userspace_ver;
  251. if (req.comp_mask & IRDMA_ALLOC_UCTX_USE_RAW_ATTR)
  252. ucontext->use_raw_attrs = true;
  253. /* GEN_1 legacy support with libi40iw */
  254. if (udata->outlen == IRDMA_ALLOC_UCTX_MIN_RESP_LEN) {
  255. if (uk_attrs->hw_rev != IRDMA_GEN_1)
  256. return -EOPNOTSUPP;
  257. ucontext->legacy_mode = true;
  258. uresp.max_qps = iwdev->rf->max_qp;
  259. uresp.max_pds = iwdev->rf->sc_dev.hw_attrs.max_hw_pds;
  260. uresp.wq_size = iwdev->rf->sc_dev.hw_attrs.max_qp_wr * 2;
  261. uresp.kernel_ver = req.userspace_ver;
  262. if (ib_copy_to_udata(udata, &uresp,
  263. min(sizeof(uresp), udata->outlen)))
  264. return -EFAULT;
  265. } else {
  266. u64 bar_off = (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET];
  267. ucontext->db_mmap_entry =
  268. irdma_user_mmap_entry_insert(ucontext, bar_off,
  269. IRDMA_MMAP_IO_NC,
  270. &uresp.db_mmap_key);
  271. if (!ucontext->db_mmap_entry)
  272. return -ENOMEM;
  273. uresp.kernel_ver = IRDMA_ABI_VER;
  274. uresp.feature_flags = uk_attrs->feature_flags;
  275. uresp.max_hw_wq_frags = uk_attrs->max_hw_wq_frags;
  276. uresp.max_hw_read_sges = uk_attrs->max_hw_read_sges;
  277. uresp.max_hw_inline = uk_attrs->max_hw_inline;
  278. uresp.max_hw_rq_quanta = uk_attrs->max_hw_rq_quanta;
  279. uresp.max_hw_wq_quanta = uk_attrs->max_hw_wq_quanta;
  280. uresp.max_hw_sq_chunk = uk_attrs->max_hw_sq_chunk;
  281. uresp.max_hw_cq_size = uk_attrs->max_hw_cq_size;
  282. uresp.min_hw_cq_size = uk_attrs->min_hw_cq_size;
  283. uresp.hw_rev = uk_attrs->hw_rev;
  284. uresp.comp_mask |= IRDMA_ALLOC_UCTX_USE_RAW_ATTR;
  285. uresp.min_hw_wq_size = uk_attrs->min_hw_wq_size;
  286. uresp.comp_mask |= IRDMA_ALLOC_UCTX_MIN_HW_WQ_SIZE;
  287. if (ib_copy_to_udata(udata, &uresp,
  288. min(sizeof(uresp), udata->outlen))) {
  289. rdma_user_mmap_entry_remove(ucontext->db_mmap_entry);
  290. return -EFAULT;
  291. }
  292. }
  293. INIT_LIST_HEAD(&ucontext->cq_reg_mem_list);
  294. spin_lock_init(&ucontext->cq_reg_mem_list_lock);
  295. INIT_LIST_HEAD(&ucontext->qp_reg_mem_list);
  296. spin_lock_init(&ucontext->qp_reg_mem_list_lock);
  297. return 0;
  298. ver_error:
  299. ibdev_err(&iwdev->ibdev,
  300. "Invalid userspace driver version detected. Detected version %d, should be %d\n",
  301. req.userspace_ver, IRDMA_ABI_VER);
  302. return -EINVAL;
  303. }
  304. /**
  305. * irdma_dealloc_ucontext - deallocate the user context data structure
  306. * @context: user context created during alloc
  307. */
  308. static void irdma_dealloc_ucontext(struct ib_ucontext *context)
  309. {
  310. struct irdma_ucontext *ucontext = to_ucontext(context);
  311. rdma_user_mmap_entry_remove(ucontext->db_mmap_entry);
  312. }
  313. /**
  314. * irdma_alloc_pd - allocate protection domain
  315. * @pd: PD pointer
  316. * @udata: user data
  317. */
  318. static int irdma_alloc_pd(struct ib_pd *pd, struct ib_udata *udata)
  319. {
  320. #define IRDMA_ALLOC_PD_MIN_RESP_LEN offsetofend(struct irdma_alloc_pd_resp, rsvd)
  321. struct irdma_pd *iwpd = to_iwpd(pd);
  322. struct irdma_device *iwdev = to_iwdev(pd->device);
  323. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  324. struct irdma_pci_f *rf = iwdev->rf;
  325. struct irdma_alloc_pd_resp uresp = {};
  326. struct irdma_sc_pd *sc_pd;
  327. u32 pd_id = 0;
  328. int err;
  329. if (udata && udata->outlen < IRDMA_ALLOC_PD_MIN_RESP_LEN)
  330. return -EINVAL;
  331. err = irdma_alloc_rsrc(rf, rf->allocated_pds, rf->max_pd, &pd_id,
  332. &rf->next_pd);
  333. if (err)
  334. return err;
  335. sc_pd = &iwpd->sc_pd;
  336. if (udata) {
  337. struct irdma_ucontext *ucontext =
  338. rdma_udata_to_drv_context(udata, struct irdma_ucontext,
  339. ibucontext);
  340. irdma_sc_pd_init(dev, sc_pd, pd_id, ucontext->abi_ver);
  341. uresp.pd_id = pd_id;
  342. if (ib_copy_to_udata(udata, &uresp,
  343. min(sizeof(uresp), udata->outlen))) {
  344. err = -EFAULT;
  345. goto error;
  346. }
  347. } else {
  348. irdma_sc_pd_init(dev, sc_pd, pd_id, IRDMA_ABI_VER);
  349. }
  350. return 0;
  351. error:
  352. irdma_free_rsrc(rf, rf->allocated_pds, pd_id);
  353. return err;
  354. }
  355. /**
  356. * irdma_dealloc_pd - deallocate pd
  357. * @ibpd: ptr of pd to be deallocated
  358. * @udata: user data
  359. */
  360. static int irdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
  361. {
  362. struct irdma_pd *iwpd = to_iwpd(ibpd);
  363. struct irdma_device *iwdev = to_iwdev(ibpd->device);
  364. irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_pds, iwpd->sc_pd.pd_id);
  365. return 0;
  366. }
  367. /**
  368. * irdma_get_pbl - Retrieve pbl from a list given a virtual
  369. * address
  370. * @va: user virtual address
  371. * @pbl_list: pbl list to search in (QP's or CQ's)
  372. */
  373. static struct irdma_pbl *irdma_get_pbl(unsigned long va,
  374. struct list_head *pbl_list)
  375. {
  376. struct irdma_pbl *iwpbl;
  377. list_for_each_entry (iwpbl, pbl_list, list) {
  378. if (iwpbl->user_base == va) {
  379. list_del(&iwpbl->list);
  380. iwpbl->on_list = false;
  381. return iwpbl;
  382. }
  383. }
  384. return NULL;
  385. }
  386. /**
  387. * irdma_clean_cqes - clean cq entries for qp
  388. * @iwqp: qp ptr (user or kernel)
  389. * @iwcq: cq ptr
  390. */
  391. static void irdma_clean_cqes(struct irdma_qp *iwqp, struct irdma_cq *iwcq)
  392. {
  393. struct irdma_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
  394. unsigned long flags;
  395. spin_lock_irqsave(&iwcq->lock, flags);
  396. irdma_uk_clean_cq(&iwqp->sc_qp.qp_uk, ukcq);
  397. spin_unlock_irqrestore(&iwcq->lock, flags);
  398. }
  399. static void irdma_remove_push_mmap_entries(struct irdma_qp *iwqp)
  400. {
  401. if (iwqp->push_db_mmap_entry) {
  402. rdma_user_mmap_entry_remove(iwqp->push_db_mmap_entry);
  403. iwqp->push_db_mmap_entry = NULL;
  404. }
  405. if (iwqp->push_wqe_mmap_entry) {
  406. rdma_user_mmap_entry_remove(iwqp->push_wqe_mmap_entry);
  407. iwqp->push_wqe_mmap_entry = NULL;
  408. }
  409. }
  410. static int irdma_setup_push_mmap_entries(struct irdma_ucontext *ucontext,
  411. struct irdma_qp *iwqp,
  412. u64 *push_wqe_mmap_key,
  413. u64 *push_db_mmap_key)
  414. {
  415. struct irdma_device *iwdev = ucontext->iwdev;
  416. u64 rsvd, bar_off;
  417. rsvd = IRDMA_PF_BAR_RSVD;
  418. bar_off = (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET];
  419. /* skip over db page */
  420. bar_off += IRDMA_HW_PAGE_SIZE;
  421. /* push wqe page */
  422. bar_off += rsvd + iwqp->sc_qp.push_idx * IRDMA_HW_PAGE_SIZE;
  423. iwqp->push_wqe_mmap_entry = irdma_user_mmap_entry_insert(ucontext,
  424. bar_off, IRDMA_MMAP_IO_WC,
  425. push_wqe_mmap_key);
  426. if (!iwqp->push_wqe_mmap_entry)
  427. return -ENOMEM;
  428. /* push doorbell page */
  429. bar_off += IRDMA_HW_PAGE_SIZE;
  430. iwqp->push_db_mmap_entry = irdma_user_mmap_entry_insert(ucontext,
  431. bar_off, IRDMA_MMAP_IO_NC,
  432. push_db_mmap_key);
  433. if (!iwqp->push_db_mmap_entry) {
  434. rdma_user_mmap_entry_remove(iwqp->push_wqe_mmap_entry);
  435. return -ENOMEM;
  436. }
  437. return 0;
  438. }
  439. /**
  440. * irdma_destroy_qp - destroy qp
  441. * @ibqp: qp's ib pointer also to get to device's qp address
  442. * @udata: user data
  443. */
  444. static int irdma_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
  445. {
  446. struct irdma_qp *iwqp = to_iwqp(ibqp);
  447. struct irdma_device *iwdev = iwqp->iwdev;
  448. iwqp->sc_qp.qp_uk.destroy_pending = true;
  449. if (iwqp->iwarp_state == IRDMA_QP_STATE_RTS)
  450. irdma_modify_qp_to_err(&iwqp->sc_qp);
  451. if (!iwqp->user_mode)
  452. cancel_delayed_work_sync(&iwqp->dwork_flush);
  453. if (!iwqp->user_mode) {
  454. if (iwqp->iwscq) {
  455. irdma_clean_cqes(iwqp, iwqp->iwscq);
  456. if (iwqp->iwrcq != iwqp->iwscq)
  457. irdma_clean_cqes(iwqp, iwqp->iwrcq);
  458. }
  459. }
  460. irdma_qp_rem_ref(&iwqp->ibqp);
  461. wait_for_completion(&iwqp->free_qp);
  462. irdma_free_lsmm_rsrc(iwqp);
  463. irdma_cqp_qp_destroy_cmd(&iwdev->rf->sc_dev, &iwqp->sc_qp);
  464. irdma_remove_push_mmap_entries(iwqp);
  465. irdma_free_qp_rsrc(iwqp);
  466. return 0;
  467. }
  468. /**
  469. * irdma_setup_virt_qp - setup for allocation of virtual qp
  470. * @iwdev: irdma device
  471. * @iwqp: qp ptr
  472. * @init_info: initialize info to return
  473. */
  474. static void irdma_setup_virt_qp(struct irdma_device *iwdev,
  475. struct irdma_qp *iwqp,
  476. struct irdma_qp_init_info *init_info)
  477. {
  478. struct irdma_pbl *iwpbl = iwqp->iwpbl;
  479. struct irdma_qp_mr *qpmr = &iwpbl->qp_mr;
  480. iwqp->page = qpmr->sq_page;
  481. init_info->shadow_area_pa = qpmr->shadow;
  482. if (iwpbl->pbl_allocated) {
  483. init_info->virtual_map = true;
  484. init_info->sq_pa = qpmr->sq_pbl.idx;
  485. init_info->rq_pa = qpmr->rq_pbl.idx;
  486. } else {
  487. init_info->sq_pa = qpmr->sq_pbl.addr;
  488. init_info->rq_pa = qpmr->rq_pbl.addr;
  489. }
  490. }
  491. /**
  492. * irdma_setup_umode_qp - setup sq and rq size in user mode qp
  493. * @udata: udata
  494. * @iwdev: iwarp device
  495. * @iwqp: qp ptr (user or kernel)
  496. * @info: initialize info to return
  497. * @init_attr: Initial QP create attributes
  498. */
  499. static int irdma_setup_umode_qp(struct ib_udata *udata,
  500. struct irdma_device *iwdev,
  501. struct irdma_qp *iwqp,
  502. struct irdma_qp_init_info *info,
  503. struct ib_qp_init_attr *init_attr)
  504. {
  505. struct irdma_ucontext *ucontext = rdma_udata_to_drv_context(udata,
  506. struct irdma_ucontext, ibucontext);
  507. struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
  508. struct irdma_create_qp_req req;
  509. unsigned long flags;
  510. int ret;
  511. ret = ib_copy_from_udata(&req, udata,
  512. min(sizeof(req), udata->inlen));
  513. if (ret) {
  514. ibdev_dbg(&iwdev->ibdev, "VERBS: ib_copy_from_data fail\n");
  515. return ret;
  516. }
  517. iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx;
  518. iwqp->user_mode = 1;
  519. if (req.user_wqe_bufs) {
  520. info->qp_uk_init_info.legacy_mode = ucontext->legacy_mode;
  521. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  522. iwqp->iwpbl = irdma_get_pbl((unsigned long)req.user_wqe_bufs,
  523. &ucontext->qp_reg_mem_list);
  524. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  525. if (!iwqp->iwpbl) {
  526. ret = -ENODATA;
  527. ibdev_dbg(&iwdev->ibdev, "VERBS: no pbl info\n");
  528. return ret;
  529. }
  530. }
  531. if (!ucontext->use_raw_attrs) {
  532. /**
  533. * Maintain backward compat with older ABI which passes sq and
  534. * rq depth in quanta in cap.max_send_wr and cap.max_recv_wr.
  535. * There is no way to compute the correct value of
  536. * iwqp->max_send_wr/max_recv_wr in the kernel.
  537. */
  538. iwqp->max_send_wr = init_attr->cap.max_send_wr;
  539. iwqp->max_recv_wr = init_attr->cap.max_recv_wr;
  540. ukinfo->sq_size = init_attr->cap.max_send_wr;
  541. ukinfo->rq_size = init_attr->cap.max_recv_wr;
  542. irdma_uk_calc_shift_wq(ukinfo, &ukinfo->sq_shift,
  543. &ukinfo->rq_shift);
  544. } else {
  545. ret = irdma_uk_calc_depth_shift_sq(ukinfo, &ukinfo->sq_depth,
  546. &ukinfo->sq_shift);
  547. if (ret)
  548. return ret;
  549. ret = irdma_uk_calc_depth_shift_rq(ukinfo, &ukinfo->rq_depth,
  550. &ukinfo->rq_shift);
  551. if (ret)
  552. return ret;
  553. iwqp->max_send_wr =
  554. (ukinfo->sq_depth - IRDMA_SQ_RSVD) >> ukinfo->sq_shift;
  555. iwqp->max_recv_wr =
  556. (ukinfo->rq_depth - IRDMA_RQ_RSVD) >> ukinfo->rq_shift;
  557. ukinfo->sq_size = ukinfo->sq_depth >> ukinfo->sq_shift;
  558. ukinfo->rq_size = ukinfo->rq_depth >> ukinfo->rq_shift;
  559. }
  560. irdma_setup_virt_qp(iwdev, iwqp, info);
  561. return 0;
  562. }
  563. /**
  564. * irdma_setup_kmode_qp - setup initialization for kernel mode qp
  565. * @iwdev: iwarp device
  566. * @iwqp: qp ptr (user or kernel)
  567. * @info: initialize info to return
  568. * @init_attr: Initial QP create attributes
  569. */
  570. static int irdma_setup_kmode_qp(struct irdma_device *iwdev,
  571. struct irdma_qp *iwqp,
  572. struct irdma_qp_init_info *info,
  573. struct ib_qp_init_attr *init_attr)
  574. {
  575. struct irdma_dma_mem *mem = &iwqp->kqp.dma_mem;
  576. u32 size;
  577. int status;
  578. struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
  579. status = irdma_uk_calc_depth_shift_sq(ukinfo, &ukinfo->sq_depth,
  580. &ukinfo->sq_shift);
  581. if (status)
  582. return status;
  583. status = irdma_uk_calc_depth_shift_rq(ukinfo, &ukinfo->rq_depth,
  584. &ukinfo->rq_shift);
  585. if (status)
  586. return status;
  587. iwqp->kqp.sq_wrid_mem =
  588. kcalloc(ukinfo->sq_depth, sizeof(*iwqp->kqp.sq_wrid_mem), GFP_KERNEL);
  589. if (!iwqp->kqp.sq_wrid_mem)
  590. return -ENOMEM;
  591. iwqp->kqp.rq_wrid_mem =
  592. kcalloc(ukinfo->rq_depth, sizeof(*iwqp->kqp.rq_wrid_mem), GFP_KERNEL);
  593. if (!iwqp->kqp.rq_wrid_mem) {
  594. kfree(iwqp->kqp.sq_wrid_mem);
  595. iwqp->kqp.sq_wrid_mem = NULL;
  596. return -ENOMEM;
  597. }
  598. ukinfo->sq_wrtrk_array = iwqp->kqp.sq_wrid_mem;
  599. ukinfo->rq_wrid_array = iwqp->kqp.rq_wrid_mem;
  600. size = (ukinfo->sq_depth + ukinfo->rq_depth) * IRDMA_QP_WQE_MIN_SIZE;
  601. size += (IRDMA_SHADOW_AREA_SIZE << 3);
  602. mem->size = ALIGN(size, 256);
  603. mem->va = dma_alloc_coherent(iwdev->rf->hw.device, mem->size,
  604. &mem->pa, GFP_KERNEL);
  605. if (!mem->va) {
  606. kfree(iwqp->kqp.sq_wrid_mem);
  607. iwqp->kqp.sq_wrid_mem = NULL;
  608. kfree(iwqp->kqp.rq_wrid_mem);
  609. iwqp->kqp.rq_wrid_mem = NULL;
  610. return -ENOMEM;
  611. }
  612. ukinfo->sq = mem->va;
  613. info->sq_pa = mem->pa;
  614. ukinfo->rq = &ukinfo->sq[ukinfo->sq_depth];
  615. info->rq_pa = info->sq_pa + (ukinfo->sq_depth * IRDMA_QP_WQE_MIN_SIZE);
  616. ukinfo->shadow_area = ukinfo->rq[ukinfo->rq_depth].elem;
  617. info->shadow_area_pa =
  618. info->rq_pa + (ukinfo->rq_depth * IRDMA_QP_WQE_MIN_SIZE);
  619. ukinfo->sq_size = ukinfo->sq_depth >> ukinfo->sq_shift;
  620. ukinfo->rq_size = ukinfo->rq_depth >> ukinfo->rq_shift;
  621. iwqp->max_send_wr = (ukinfo->sq_depth - IRDMA_SQ_RSVD) >> ukinfo->sq_shift;
  622. iwqp->max_recv_wr = (ukinfo->rq_depth - IRDMA_RQ_RSVD) >> ukinfo->rq_shift;
  623. init_attr->cap.max_send_wr = iwqp->max_send_wr;
  624. init_attr->cap.max_recv_wr = iwqp->max_recv_wr;
  625. return 0;
  626. }
  627. static int irdma_cqp_create_qp_cmd(struct irdma_qp *iwqp)
  628. {
  629. struct irdma_pci_f *rf = iwqp->iwdev->rf;
  630. struct irdma_cqp_request *cqp_request;
  631. struct cqp_cmds_info *cqp_info;
  632. struct irdma_create_qp_info *qp_info;
  633. int status;
  634. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  635. if (!cqp_request)
  636. return -ENOMEM;
  637. cqp_info = &cqp_request->info;
  638. qp_info = &cqp_request->info.in.u.qp_create.info;
  639. memset(qp_info, 0, sizeof(*qp_info));
  640. qp_info->mac_valid = true;
  641. qp_info->cq_num_valid = true;
  642. qp_info->next_iwarp_state = IRDMA_QP_STATE_IDLE;
  643. cqp_info->cqp_cmd = IRDMA_OP_QP_CREATE;
  644. cqp_info->post_sq = 1;
  645. cqp_info->in.u.qp_create.qp = &iwqp->sc_qp;
  646. cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
  647. status = irdma_handle_cqp_op(rf, cqp_request);
  648. irdma_put_cqp_request(&rf->cqp, cqp_request);
  649. return status;
  650. }
  651. static void irdma_roce_fill_and_set_qpctx_info(struct irdma_qp *iwqp,
  652. struct irdma_qp_host_ctx_info *ctx_info)
  653. {
  654. struct irdma_device *iwdev = iwqp->iwdev;
  655. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  656. struct irdma_roce_offload_info *roce_info;
  657. struct irdma_udp_offload_info *udp_info;
  658. udp_info = &iwqp->udp_info;
  659. udp_info->snd_mss = ib_mtu_enum_to_int(ib_mtu_int_to_enum(iwdev->vsi.mtu));
  660. udp_info->cwnd = iwdev->roce_cwnd;
  661. udp_info->rexmit_thresh = 2;
  662. udp_info->rnr_nak_thresh = 2;
  663. udp_info->src_port = 0xc000;
  664. udp_info->dst_port = ROCE_V2_UDP_DPORT;
  665. roce_info = &iwqp->roce_info;
  666. ether_addr_copy(roce_info->mac_addr, iwdev->netdev->dev_addr);
  667. roce_info->rd_en = true;
  668. roce_info->wr_rdresp_en = true;
  669. roce_info->bind_en = true;
  670. roce_info->dcqcn_en = false;
  671. roce_info->rtomin = 5;
  672. roce_info->ack_credits = iwdev->roce_ackcreds;
  673. roce_info->ird_size = dev->hw_attrs.max_hw_ird;
  674. roce_info->ord_size = dev->hw_attrs.max_hw_ord;
  675. if (!iwqp->user_mode) {
  676. roce_info->priv_mode_en = true;
  677. roce_info->fast_reg_en = true;
  678. roce_info->udprivcq_en = true;
  679. }
  680. roce_info->roce_tver = 0;
  681. ctx_info->roce_info = &iwqp->roce_info;
  682. ctx_info->udp_info = &iwqp->udp_info;
  683. irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
  684. }
  685. static void irdma_iw_fill_and_set_qpctx_info(struct irdma_qp *iwqp,
  686. struct irdma_qp_host_ctx_info *ctx_info)
  687. {
  688. struct irdma_device *iwdev = iwqp->iwdev;
  689. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  690. struct irdma_iwarp_offload_info *iwarp_info;
  691. iwarp_info = &iwqp->iwarp_info;
  692. ether_addr_copy(iwarp_info->mac_addr, iwdev->netdev->dev_addr);
  693. iwarp_info->rd_en = true;
  694. iwarp_info->wr_rdresp_en = true;
  695. iwarp_info->bind_en = true;
  696. iwarp_info->ecn_en = true;
  697. iwarp_info->rtomin = 5;
  698. if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
  699. iwarp_info->ib_rd_en = true;
  700. if (!iwqp->user_mode) {
  701. iwarp_info->priv_mode_en = true;
  702. iwarp_info->fast_reg_en = true;
  703. }
  704. iwarp_info->ddp_ver = 1;
  705. iwarp_info->rdmap_ver = 1;
  706. ctx_info->iwarp_info = &iwqp->iwarp_info;
  707. ctx_info->iwarp_info_valid = true;
  708. irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
  709. ctx_info->iwarp_info_valid = false;
  710. }
  711. static int irdma_validate_qp_attrs(struct ib_qp_init_attr *init_attr,
  712. struct irdma_device *iwdev)
  713. {
  714. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  715. struct irdma_uk_attrs *uk_attrs = &dev->hw_attrs.uk_attrs;
  716. if (init_attr->create_flags)
  717. return -EOPNOTSUPP;
  718. if (init_attr->cap.max_inline_data > uk_attrs->max_hw_inline ||
  719. init_attr->cap.max_send_sge > uk_attrs->max_hw_wq_frags ||
  720. init_attr->cap.max_recv_sge > uk_attrs->max_hw_wq_frags ||
  721. init_attr->cap.max_send_wr > uk_attrs->max_hw_wq_quanta ||
  722. init_attr->cap.max_recv_wr > uk_attrs->max_hw_rq_quanta)
  723. return -EINVAL;
  724. if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
  725. if (init_attr->qp_type != IB_QPT_RC &&
  726. init_attr->qp_type != IB_QPT_UD &&
  727. init_attr->qp_type != IB_QPT_GSI)
  728. return -EOPNOTSUPP;
  729. } else {
  730. if (init_attr->qp_type != IB_QPT_RC)
  731. return -EOPNOTSUPP;
  732. }
  733. return 0;
  734. }
  735. static void irdma_flush_worker(struct work_struct *work)
  736. {
  737. struct delayed_work *dwork = to_delayed_work(work);
  738. struct irdma_qp *iwqp = container_of(dwork, struct irdma_qp, dwork_flush);
  739. irdma_generate_flush_completions(iwqp);
  740. }
  741. /**
  742. * irdma_create_qp - create qp
  743. * @ibqp: ptr of qp
  744. * @init_attr: attributes for qp
  745. * @udata: user data for create qp
  746. */
  747. static int irdma_create_qp(struct ib_qp *ibqp,
  748. struct ib_qp_init_attr *init_attr,
  749. struct ib_udata *udata)
  750. {
  751. #define IRDMA_CREATE_QP_MIN_REQ_LEN offsetofend(struct irdma_create_qp_req, user_compl_ctx)
  752. #define IRDMA_CREATE_QP_MIN_RESP_LEN offsetofend(struct irdma_create_qp_resp, rsvd)
  753. struct ib_pd *ibpd = ibqp->pd;
  754. struct irdma_pd *iwpd = to_iwpd(ibpd);
  755. struct irdma_device *iwdev = to_iwdev(ibpd->device);
  756. struct irdma_pci_f *rf = iwdev->rf;
  757. struct irdma_qp *iwqp = to_iwqp(ibqp);
  758. struct irdma_create_qp_resp uresp = {};
  759. u32 qp_num = 0;
  760. int err_code;
  761. struct irdma_sc_qp *qp;
  762. struct irdma_sc_dev *dev = &rf->sc_dev;
  763. struct irdma_uk_attrs *uk_attrs = &dev->hw_attrs.uk_attrs;
  764. struct irdma_qp_init_info init_info = {};
  765. struct irdma_qp_host_ctx_info *ctx_info;
  766. err_code = irdma_validate_qp_attrs(init_attr, iwdev);
  767. if (err_code)
  768. return err_code;
  769. if (udata && (udata->inlen < IRDMA_CREATE_QP_MIN_REQ_LEN ||
  770. udata->outlen < IRDMA_CREATE_QP_MIN_RESP_LEN))
  771. return -EINVAL;
  772. init_info.vsi = &iwdev->vsi;
  773. init_info.qp_uk_init_info.uk_attrs = uk_attrs;
  774. init_info.qp_uk_init_info.sq_size = init_attr->cap.max_send_wr;
  775. init_info.qp_uk_init_info.rq_size = init_attr->cap.max_recv_wr;
  776. init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
  777. init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge;
  778. init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data;
  779. qp = &iwqp->sc_qp;
  780. qp->qp_uk.back_qp = iwqp;
  781. qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX;
  782. iwqp->iwdev = iwdev;
  783. iwqp->q2_ctx_mem.size = ALIGN(IRDMA_Q2_BUF_SIZE + IRDMA_QP_CTX_SIZE,
  784. 256);
  785. iwqp->q2_ctx_mem.va = dma_alloc_coherent(dev->hw->device,
  786. iwqp->q2_ctx_mem.size,
  787. &iwqp->q2_ctx_mem.pa,
  788. GFP_KERNEL);
  789. if (!iwqp->q2_ctx_mem.va)
  790. return -ENOMEM;
  791. init_info.q2 = iwqp->q2_ctx_mem.va;
  792. init_info.q2_pa = iwqp->q2_ctx_mem.pa;
  793. init_info.host_ctx = (__le64 *)(init_info.q2 + IRDMA_Q2_BUF_SIZE);
  794. init_info.host_ctx_pa = init_info.q2_pa + IRDMA_Q2_BUF_SIZE;
  795. if (init_attr->qp_type == IB_QPT_GSI)
  796. qp_num = 1;
  797. else
  798. err_code = irdma_alloc_rsrc(rf, rf->allocated_qps, rf->max_qp,
  799. &qp_num, &rf->next_qp);
  800. if (err_code)
  801. goto error;
  802. iwqp->iwpd = iwpd;
  803. iwqp->ibqp.qp_num = qp_num;
  804. qp = &iwqp->sc_qp;
  805. iwqp->iwscq = to_iwcq(init_attr->send_cq);
  806. iwqp->iwrcq = to_iwcq(init_attr->recv_cq);
  807. iwqp->host_ctx.va = init_info.host_ctx;
  808. iwqp->host_ctx.pa = init_info.host_ctx_pa;
  809. iwqp->host_ctx.size = IRDMA_QP_CTX_SIZE;
  810. init_info.pd = &iwpd->sc_pd;
  811. init_info.qp_uk_init_info.qp_id = qp_num;
  812. if (!rdma_protocol_roce(&iwdev->ibdev, 1))
  813. init_info.qp_uk_init_info.first_sq_wq = 1;
  814. iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp;
  815. init_waitqueue_head(&iwqp->waitq);
  816. init_waitqueue_head(&iwqp->mod_qp_waitq);
  817. if (udata) {
  818. init_info.qp_uk_init_info.abi_ver = iwpd->sc_pd.abi_ver;
  819. err_code = irdma_setup_umode_qp(udata, iwdev, iwqp, &init_info,
  820. init_attr);
  821. } else {
  822. INIT_DELAYED_WORK(&iwqp->dwork_flush, irdma_flush_worker);
  823. init_info.qp_uk_init_info.abi_ver = IRDMA_ABI_VER;
  824. err_code = irdma_setup_kmode_qp(iwdev, iwqp, &init_info, init_attr);
  825. }
  826. if (err_code) {
  827. ibdev_dbg(&iwdev->ibdev, "VERBS: setup qp failed\n");
  828. goto error;
  829. }
  830. if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
  831. if (init_attr->qp_type == IB_QPT_RC) {
  832. init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_ROCE_RC;
  833. init_info.qp_uk_init_info.qp_caps = IRDMA_SEND_WITH_IMM |
  834. IRDMA_WRITE_WITH_IMM |
  835. IRDMA_ROCE;
  836. } else {
  837. init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_ROCE_UD;
  838. init_info.qp_uk_init_info.qp_caps = IRDMA_SEND_WITH_IMM |
  839. IRDMA_ROCE;
  840. }
  841. } else {
  842. init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_IWARP;
  843. init_info.qp_uk_init_info.qp_caps = IRDMA_WRITE_WITH_IMM;
  844. }
  845. if (dev->hw_attrs.uk_attrs.hw_rev > IRDMA_GEN_1)
  846. init_info.qp_uk_init_info.qp_caps |= IRDMA_PUSH_MODE;
  847. err_code = irdma_sc_qp_init(qp, &init_info);
  848. if (err_code) {
  849. ibdev_dbg(&iwdev->ibdev, "VERBS: qp_init fail\n");
  850. goto error;
  851. }
  852. ctx_info = &iwqp->ctx_info;
  853. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  854. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  855. if (rdma_protocol_roce(&iwdev->ibdev, 1))
  856. irdma_roce_fill_and_set_qpctx_info(iwqp, ctx_info);
  857. else
  858. irdma_iw_fill_and_set_qpctx_info(iwqp, ctx_info);
  859. err_code = irdma_cqp_create_qp_cmd(iwqp);
  860. if (err_code)
  861. goto error;
  862. refcount_set(&iwqp->refcnt, 1);
  863. spin_lock_init(&iwqp->lock);
  864. spin_lock_init(&iwqp->sc_qp.pfpdu.lock);
  865. iwqp->sig_all = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR;
  866. rf->qp_table[qp_num] = iwqp;
  867. if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
  868. if (dev->ws_add(&iwdev->vsi, 0)) {
  869. irdma_cqp_qp_destroy_cmd(&rf->sc_dev, &iwqp->sc_qp);
  870. err_code = -EINVAL;
  871. goto error;
  872. }
  873. irdma_qp_add_qos(&iwqp->sc_qp);
  874. }
  875. if (udata) {
  876. /* GEN_1 legacy support with libi40iw does not have expanded uresp struct */
  877. if (udata->outlen < sizeof(uresp)) {
  878. uresp.lsmm = 1;
  879. uresp.push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1;
  880. } else {
  881. if (rdma_protocol_iwarp(&iwdev->ibdev, 1))
  882. uresp.lsmm = 1;
  883. }
  884. uresp.actual_sq_size = init_info.qp_uk_init_info.sq_size;
  885. uresp.actual_rq_size = init_info.qp_uk_init_info.rq_size;
  886. uresp.qp_id = qp_num;
  887. uresp.qp_caps = qp->qp_uk.qp_caps;
  888. err_code = ib_copy_to_udata(udata, &uresp,
  889. min(sizeof(uresp), udata->outlen));
  890. if (err_code) {
  891. ibdev_dbg(&iwdev->ibdev, "VERBS: copy_to_udata failed\n");
  892. irdma_destroy_qp(&iwqp->ibqp, udata);
  893. return err_code;
  894. }
  895. }
  896. init_completion(&iwqp->free_qp);
  897. return 0;
  898. error:
  899. irdma_free_qp_rsrc(iwqp);
  900. return err_code;
  901. }
  902. static int irdma_get_ib_acc_flags(struct irdma_qp *iwqp)
  903. {
  904. int acc_flags = 0;
  905. if (rdma_protocol_roce(iwqp->ibqp.device, 1)) {
  906. if (iwqp->roce_info.wr_rdresp_en) {
  907. acc_flags |= IB_ACCESS_LOCAL_WRITE;
  908. acc_flags |= IB_ACCESS_REMOTE_WRITE;
  909. }
  910. if (iwqp->roce_info.rd_en)
  911. acc_flags |= IB_ACCESS_REMOTE_READ;
  912. if (iwqp->roce_info.bind_en)
  913. acc_flags |= IB_ACCESS_MW_BIND;
  914. } else {
  915. if (iwqp->iwarp_info.wr_rdresp_en) {
  916. acc_flags |= IB_ACCESS_LOCAL_WRITE;
  917. acc_flags |= IB_ACCESS_REMOTE_WRITE;
  918. }
  919. if (iwqp->iwarp_info.rd_en)
  920. acc_flags |= IB_ACCESS_REMOTE_READ;
  921. if (iwqp->iwarp_info.bind_en)
  922. acc_flags |= IB_ACCESS_MW_BIND;
  923. }
  924. return acc_flags;
  925. }
  926. /**
  927. * irdma_query_qp - query qp attributes
  928. * @ibqp: qp pointer
  929. * @attr: attributes pointer
  930. * @attr_mask: Not used
  931. * @init_attr: qp attributes to return
  932. */
  933. static int irdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  934. int attr_mask, struct ib_qp_init_attr *init_attr)
  935. {
  936. struct irdma_qp *iwqp = to_iwqp(ibqp);
  937. struct irdma_sc_qp *qp = &iwqp->sc_qp;
  938. memset(attr, 0, sizeof(*attr));
  939. memset(init_attr, 0, sizeof(*init_attr));
  940. attr->qp_state = iwqp->ibqp_state;
  941. attr->cur_qp_state = iwqp->ibqp_state;
  942. attr->cap.max_send_wr = iwqp->max_send_wr;
  943. attr->cap.max_recv_wr = iwqp->max_recv_wr;
  944. attr->cap.max_inline_data = qp->qp_uk.max_inline_data;
  945. attr->cap.max_send_sge = qp->qp_uk.max_sq_frag_cnt;
  946. attr->cap.max_recv_sge = qp->qp_uk.max_rq_frag_cnt;
  947. attr->qp_access_flags = irdma_get_ib_acc_flags(iwqp);
  948. attr->port_num = 1;
  949. if (rdma_protocol_roce(ibqp->device, 1)) {
  950. attr->path_mtu = ib_mtu_int_to_enum(iwqp->udp_info.snd_mss);
  951. attr->qkey = iwqp->roce_info.qkey;
  952. attr->rq_psn = iwqp->udp_info.epsn;
  953. attr->sq_psn = iwqp->udp_info.psn_nxt;
  954. attr->dest_qp_num = iwqp->roce_info.dest_qp;
  955. attr->pkey_index = iwqp->roce_info.p_key;
  956. attr->retry_cnt = iwqp->udp_info.rexmit_thresh;
  957. attr->rnr_retry = iwqp->udp_info.rnr_nak_thresh;
  958. attr->max_rd_atomic = iwqp->roce_info.ord_size;
  959. attr->max_dest_rd_atomic = iwqp->roce_info.ird_size;
  960. }
  961. init_attr->event_handler = iwqp->ibqp.event_handler;
  962. init_attr->qp_context = iwqp->ibqp.qp_context;
  963. init_attr->send_cq = iwqp->ibqp.send_cq;
  964. init_attr->recv_cq = iwqp->ibqp.recv_cq;
  965. init_attr->cap = attr->cap;
  966. return 0;
  967. }
  968. /**
  969. * irdma_query_pkey - Query partition key
  970. * @ibdev: device pointer from stack
  971. * @port: port number
  972. * @index: index of pkey
  973. * @pkey: pointer to store the pkey
  974. */
  975. static int irdma_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
  976. u16 *pkey)
  977. {
  978. if (index >= IRDMA_PKEY_TBL_SZ)
  979. return -EINVAL;
  980. *pkey = IRDMA_DEFAULT_PKEY;
  981. return 0;
  982. }
  983. static u8 irdma_roce_get_vlan_prio(const struct ib_gid_attr *attr, u8 prio)
  984. {
  985. struct net_device *ndev;
  986. rcu_read_lock();
  987. ndev = rcu_dereference(attr->ndev);
  988. if (!ndev)
  989. goto exit;
  990. if (is_vlan_dev(ndev)) {
  991. u16 vlan_qos = vlan_dev_get_egress_qos_mask(ndev, prio);
  992. prio = (vlan_qos & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
  993. }
  994. exit:
  995. rcu_read_unlock();
  996. return prio;
  997. }
  998. static int irdma_wait_for_suspend(struct irdma_qp *iwqp)
  999. {
  1000. if (!wait_event_timeout(iwqp->iwdev->suspend_wq,
  1001. !iwqp->suspend_pending,
  1002. msecs_to_jiffies(IRDMA_EVENT_TIMEOUT_MS))) {
  1003. iwqp->suspend_pending = false;
  1004. ibdev_warn(&iwqp->iwdev->ibdev,
  1005. "modify_qp timed out waiting for suspend. qp_id = %d, last_ae = 0x%x\n",
  1006. iwqp->ibqp.qp_num, iwqp->last_aeq);
  1007. return -EBUSY;
  1008. }
  1009. return 0;
  1010. }
  1011. /**
  1012. * irdma_modify_qp_roce - modify qp request
  1013. * @ibqp: qp's pointer for modify
  1014. * @attr: access attributes
  1015. * @attr_mask: state mask
  1016. * @udata: user data
  1017. */
  1018. int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1019. int attr_mask, struct ib_udata *udata)
  1020. {
  1021. #define IRDMA_MODIFY_QP_MIN_REQ_LEN offsetofend(struct irdma_modify_qp_req, rq_flush)
  1022. #define IRDMA_MODIFY_QP_MIN_RESP_LEN offsetofend(struct irdma_modify_qp_resp, push_valid)
  1023. struct irdma_pd *iwpd = to_iwpd(ibqp->pd);
  1024. struct irdma_qp *iwqp = to_iwqp(ibqp);
  1025. struct irdma_device *iwdev = iwqp->iwdev;
  1026. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  1027. struct irdma_qp_host_ctx_info *ctx_info;
  1028. struct irdma_roce_offload_info *roce_info;
  1029. struct irdma_udp_offload_info *udp_info;
  1030. struct irdma_modify_qp_info info = {};
  1031. struct irdma_modify_qp_resp uresp = {};
  1032. struct irdma_modify_qp_req ureq = {};
  1033. unsigned long flags;
  1034. u8 issue_modify_qp = 0;
  1035. int ret = 0;
  1036. ctx_info = &iwqp->ctx_info;
  1037. roce_info = &iwqp->roce_info;
  1038. udp_info = &iwqp->udp_info;
  1039. if (udata) {
  1040. /* udata inlen/outlen can be 0 when supporting legacy libi40iw */
  1041. if ((udata->inlen && udata->inlen < IRDMA_MODIFY_QP_MIN_REQ_LEN) ||
  1042. (udata->outlen && udata->outlen < IRDMA_MODIFY_QP_MIN_RESP_LEN))
  1043. return -EINVAL;
  1044. }
  1045. if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
  1046. return -EOPNOTSUPP;
  1047. if (attr_mask & IB_QP_DEST_QPN)
  1048. roce_info->dest_qp = attr->dest_qp_num;
  1049. if (attr_mask & IB_QP_PKEY_INDEX) {
  1050. ret = irdma_query_pkey(ibqp->device, 0, attr->pkey_index,
  1051. &roce_info->p_key);
  1052. if (ret)
  1053. return ret;
  1054. }
  1055. if (attr_mask & IB_QP_QKEY)
  1056. roce_info->qkey = attr->qkey;
  1057. if (attr_mask & IB_QP_PATH_MTU)
  1058. udp_info->snd_mss = ib_mtu_enum_to_int(attr->path_mtu);
  1059. if (attr_mask & IB_QP_SQ_PSN) {
  1060. udp_info->psn_nxt = attr->sq_psn;
  1061. udp_info->lsn = 0xffff;
  1062. udp_info->psn_una = attr->sq_psn;
  1063. udp_info->psn_max = attr->sq_psn;
  1064. }
  1065. if (attr_mask & IB_QP_RQ_PSN)
  1066. udp_info->epsn = attr->rq_psn;
  1067. if (attr_mask & IB_QP_RNR_RETRY)
  1068. udp_info->rnr_nak_thresh = attr->rnr_retry;
  1069. if (attr_mask & IB_QP_RETRY_CNT)
  1070. udp_info->rexmit_thresh = attr->retry_cnt;
  1071. ctx_info->roce_info->pd_id = iwpd->sc_pd.pd_id;
  1072. if (attr_mask & IB_QP_AV) {
  1073. struct irdma_av *av = &iwqp->roce_ah.av;
  1074. const struct ib_gid_attr *sgid_attr =
  1075. attr->ah_attr.grh.sgid_attr;
  1076. u16 vlan_id = VLAN_N_VID;
  1077. u32 local_ip[4];
  1078. memset(&iwqp->roce_ah, 0, sizeof(iwqp->roce_ah));
  1079. if (attr->ah_attr.ah_flags & IB_AH_GRH) {
  1080. udp_info->ttl = attr->ah_attr.grh.hop_limit;
  1081. udp_info->flow_label = attr->ah_attr.grh.flow_label;
  1082. udp_info->tos = attr->ah_attr.grh.traffic_class;
  1083. udp_info->src_port =
  1084. rdma_get_udp_sport(udp_info->flow_label,
  1085. ibqp->qp_num,
  1086. roce_info->dest_qp);
  1087. irdma_qp_rem_qos(&iwqp->sc_qp);
  1088. dev->ws_remove(iwqp->sc_qp.vsi, ctx_info->user_pri);
  1089. if (iwqp->sc_qp.vsi->dscp_mode)
  1090. ctx_info->user_pri =
  1091. iwqp->sc_qp.vsi->dscp_map[irdma_tos2dscp(udp_info->tos)];
  1092. else
  1093. ctx_info->user_pri = rt_tos2priority(udp_info->tos);
  1094. }
  1095. ret = rdma_read_gid_l2_fields(sgid_attr, &vlan_id,
  1096. ctx_info->roce_info->mac_addr);
  1097. if (ret)
  1098. return ret;
  1099. ctx_info->user_pri = irdma_roce_get_vlan_prio(sgid_attr,
  1100. ctx_info->user_pri);
  1101. if (dev->ws_add(iwqp->sc_qp.vsi, ctx_info->user_pri))
  1102. return -ENOMEM;
  1103. iwqp->sc_qp.user_pri = ctx_info->user_pri;
  1104. irdma_qp_add_qos(&iwqp->sc_qp);
  1105. if (vlan_id >= VLAN_N_VID && iwdev->dcb_vlan_mode)
  1106. vlan_id = 0;
  1107. if (vlan_id < VLAN_N_VID) {
  1108. udp_info->insert_vlan_tag = true;
  1109. udp_info->vlan_tag = vlan_id |
  1110. ctx_info->user_pri << VLAN_PRIO_SHIFT;
  1111. } else {
  1112. udp_info->insert_vlan_tag = false;
  1113. }
  1114. av->attrs = attr->ah_attr;
  1115. rdma_gid2ip((struct sockaddr *)&av->sgid_addr, &sgid_attr->gid);
  1116. rdma_gid2ip((struct sockaddr *)&av->dgid_addr, &attr->ah_attr.grh.dgid);
  1117. av->net_type = rdma_gid_attr_network_type(sgid_attr);
  1118. if (av->net_type == RDMA_NETWORK_IPV6) {
  1119. __be32 *daddr =
  1120. av->dgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32;
  1121. __be32 *saddr =
  1122. av->sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32;
  1123. irdma_copy_ip_ntohl(&udp_info->dest_ip_addr[0], daddr);
  1124. irdma_copy_ip_ntohl(&udp_info->local_ipaddr[0], saddr);
  1125. udp_info->ipv4 = false;
  1126. irdma_copy_ip_ntohl(local_ip, daddr);
  1127. } else if (av->net_type == RDMA_NETWORK_IPV4) {
  1128. __be32 saddr = av->sgid_addr.saddr_in.sin_addr.s_addr;
  1129. __be32 daddr = av->dgid_addr.saddr_in.sin_addr.s_addr;
  1130. local_ip[0] = ntohl(daddr);
  1131. udp_info->ipv4 = true;
  1132. udp_info->dest_ip_addr[0] = 0;
  1133. udp_info->dest_ip_addr[1] = 0;
  1134. udp_info->dest_ip_addr[2] = 0;
  1135. udp_info->dest_ip_addr[3] = local_ip[0];
  1136. udp_info->local_ipaddr[0] = 0;
  1137. udp_info->local_ipaddr[1] = 0;
  1138. udp_info->local_ipaddr[2] = 0;
  1139. udp_info->local_ipaddr[3] = ntohl(saddr);
  1140. }
  1141. udp_info->arp_idx =
  1142. irdma_add_arp(iwdev->rf, local_ip, udp_info->ipv4,
  1143. attr->ah_attr.roce.dmac);
  1144. }
  1145. if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
  1146. if (attr->max_rd_atomic > dev->hw_attrs.max_hw_ord) {
  1147. ibdev_err(&iwdev->ibdev,
  1148. "rd_atomic = %d, above max_hw_ord=%d\n",
  1149. attr->max_rd_atomic,
  1150. dev->hw_attrs.max_hw_ord);
  1151. return -EINVAL;
  1152. }
  1153. if (attr->max_rd_atomic)
  1154. roce_info->ord_size = attr->max_rd_atomic;
  1155. info.ord_valid = true;
  1156. }
  1157. if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
  1158. if (attr->max_dest_rd_atomic > dev->hw_attrs.max_hw_ird) {
  1159. ibdev_err(&iwdev->ibdev,
  1160. "rd_atomic = %d, above max_hw_ird=%d\n",
  1161. attr->max_dest_rd_atomic,
  1162. dev->hw_attrs.max_hw_ird);
  1163. return -EINVAL;
  1164. }
  1165. if (attr->max_dest_rd_atomic)
  1166. roce_info->ird_size = attr->max_dest_rd_atomic;
  1167. }
  1168. if (attr_mask & IB_QP_ACCESS_FLAGS) {
  1169. if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
  1170. roce_info->wr_rdresp_en = true;
  1171. if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
  1172. roce_info->wr_rdresp_en = true;
  1173. if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
  1174. roce_info->rd_en = true;
  1175. }
  1176. wait_event(iwqp->mod_qp_waitq, !atomic_read(&iwqp->hw_mod_qp_pend));
  1177. ibdev_dbg(&iwdev->ibdev,
  1178. "VERBS: caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d attr_mask=0x%x\n",
  1179. __builtin_return_address(0), ibqp->qp_num, attr->qp_state,
  1180. iwqp->ibqp_state, iwqp->iwarp_state, attr_mask);
  1181. spin_lock_irqsave(&iwqp->lock, flags);
  1182. if (attr_mask & IB_QP_STATE) {
  1183. if (!ib_modify_qp_is_ok(iwqp->ibqp_state, attr->qp_state,
  1184. iwqp->ibqp.qp_type, attr_mask)) {
  1185. ibdev_warn(&iwdev->ibdev, "modify_qp invalid for qp_id=%d, old_state=0x%x, new_state=0x%x\n",
  1186. iwqp->ibqp.qp_num, iwqp->ibqp_state,
  1187. attr->qp_state);
  1188. ret = -EINVAL;
  1189. goto exit;
  1190. }
  1191. info.curr_iwarp_state = iwqp->iwarp_state;
  1192. switch (attr->qp_state) {
  1193. case IB_QPS_INIT:
  1194. if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) {
  1195. ret = -EINVAL;
  1196. goto exit;
  1197. }
  1198. if (iwqp->iwarp_state == IRDMA_QP_STATE_INVALID) {
  1199. info.next_iwarp_state = IRDMA_QP_STATE_IDLE;
  1200. issue_modify_qp = 1;
  1201. }
  1202. break;
  1203. case IB_QPS_RTR:
  1204. if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) {
  1205. ret = -EINVAL;
  1206. goto exit;
  1207. }
  1208. info.arp_cache_idx_valid = true;
  1209. info.cq_num_valid = true;
  1210. info.next_iwarp_state = IRDMA_QP_STATE_RTR;
  1211. issue_modify_qp = 1;
  1212. break;
  1213. case IB_QPS_RTS:
  1214. if (iwqp->ibqp_state < IB_QPS_RTR ||
  1215. iwqp->ibqp_state == IB_QPS_ERR) {
  1216. ret = -EINVAL;
  1217. goto exit;
  1218. }
  1219. info.arp_cache_idx_valid = true;
  1220. info.cq_num_valid = true;
  1221. info.ord_valid = true;
  1222. info.next_iwarp_state = IRDMA_QP_STATE_RTS;
  1223. issue_modify_qp = 1;
  1224. if (iwdev->push_mode && udata &&
  1225. iwqp->sc_qp.push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX &&
  1226. dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
  1227. spin_unlock_irqrestore(&iwqp->lock, flags);
  1228. irdma_alloc_push_page(iwqp);
  1229. spin_lock_irqsave(&iwqp->lock, flags);
  1230. }
  1231. break;
  1232. case IB_QPS_SQD:
  1233. if (iwqp->iwarp_state == IRDMA_QP_STATE_SQD)
  1234. goto exit;
  1235. if (iwqp->iwarp_state != IRDMA_QP_STATE_RTS) {
  1236. ret = -EINVAL;
  1237. goto exit;
  1238. }
  1239. info.next_iwarp_state = IRDMA_QP_STATE_SQD;
  1240. issue_modify_qp = 1;
  1241. iwqp->suspend_pending = true;
  1242. break;
  1243. case IB_QPS_SQE:
  1244. case IB_QPS_ERR:
  1245. case IB_QPS_RESET:
  1246. if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) {
  1247. spin_unlock_irqrestore(&iwqp->lock, flags);
  1248. if (udata && udata->inlen) {
  1249. if (ib_copy_from_udata(&ureq, udata,
  1250. min(sizeof(ureq), udata->inlen)))
  1251. return -EINVAL;
  1252. irdma_flush_wqes(iwqp,
  1253. (ureq.sq_flush ? IRDMA_FLUSH_SQ : 0) |
  1254. (ureq.rq_flush ? IRDMA_FLUSH_RQ : 0) |
  1255. IRDMA_REFLUSH);
  1256. }
  1257. return 0;
  1258. }
  1259. info.next_iwarp_state = IRDMA_QP_STATE_ERROR;
  1260. issue_modify_qp = 1;
  1261. break;
  1262. default:
  1263. ret = -EINVAL;
  1264. goto exit;
  1265. }
  1266. iwqp->ibqp_state = attr->qp_state;
  1267. }
  1268. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  1269. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  1270. irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
  1271. spin_unlock_irqrestore(&iwqp->lock, flags);
  1272. if (attr_mask & IB_QP_STATE) {
  1273. if (issue_modify_qp) {
  1274. ctx_info->rem_endpoint_idx = udp_info->arp_idx;
  1275. if (irdma_hw_modify_qp(iwdev, iwqp, &info, true))
  1276. return -EINVAL;
  1277. if (info.next_iwarp_state == IRDMA_QP_STATE_SQD) {
  1278. ret = irdma_wait_for_suspend(iwqp);
  1279. if (ret)
  1280. return ret;
  1281. }
  1282. spin_lock_irqsave(&iwqp->lock, flags);
  1283. if (iwqp->iwarp_state == info.curr_iwarp_state) {
  1284. iwqp->iwarp_state = info.next_iwarp_state;
  1285. iwqp->ibqp_state = attr->qp_state;
  1286. }
  1287. if (iwqp->ibqp_state > IB_QPS_RTS &&
  1288. !iwqp->flush_issued) {
  1289. spin_unlock_irqrestore(&iwqp->lock, flags);
  1290. irdma_flush_wqes(iwqp, IRDMA_FLUSH_SQ |
  1291. IRDMA_FLUSH_RQ |
  1292. IRDMA_FLUSH_WAIT);
  1293. iwqp->flush_issued = 1;
  1294. } else {
  1295. spin_unlock_irqrestore(&iwqp->lock, flags);
  1296. }
  1297. } else {
  1298. iwqp->ibqp_state = attr->qp_state;
  1299. }
  1300. if (udata && udata->outlen && dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
  1301. struct irdma_ucontext *ucontext;
  1302. ucontext = rdma_udata_to_drv_context(udata,
  1303. struct irdma_ucontext, ibucontext);
  1304. if (iwqp->sc_qp.push_idx != IRDMA_INVALID_PUSH_PAGE_INDEX &&
  1305. !iwqp->push_wqe_mmap_entry &&
  1306. !irdma_setup_push_mmap_entries(ucontext, iwqp,
  1307. &uresp.push_wqe_mmap_key, &uresp.push_db_mmap_key)) {
  1308. uresp.push_valid = 1;
  1309. uresp.push_offset = iwqp->sc_qp.push_offset;
  1310. }
  1311. ret = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp),
  1312. udata->outlen));
  1313. if (ret) {
  1314. irdma_remove_push_mmap_entries(iwqp);
  1315. ibdev_dbg(&iwdev->ibdev,
  1316. "VERBS: copy_to_udata failed\n");
  1317. return ret;
  1318. }
  1319. }
  1320. }
  1321. return 0;
  1322. exit:
  1323. spin_unlock_irqrestore(&iwqp->lock, flags);
  1324. return ret;
  1325. }
  1326. /**
  1327. * irdma_modify_qp - modify qp request
  1328. * @ibqp: qp's pointer for modify
  1329. * @attr: access attributes
  1330. * @attr_mask: state mask
  1331. * @udata: user data
  1332. */
  1333. int irdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
  1334. struct ib_udata *udata)
  1335. {
  1336. #define IRDMA_MODIFY_QP_MIN_REQ_LEN offsetofend(struct irdma_modify_qp_req, rq_flush)
  1337. #define IRDMA_MODIFY_QP_MIN_RESP_LEN offsetofend(struct irdma_modify_qp_resp, push_valid)
  1338. struct irdma_qp *iwqp = to_iwqp(ibqp);
  1339. struct irdma_device *iwdev = iwqp->iwdev;
  1340. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  1341. struct irdma_qp_host_ctx_info *ctx_info;
  1342. struct irdma_tcp_offload_info *tcp_info;
  1343. struct irdma_iwarp_offload_info *offload_info;
  1344. struct irdma_modify_qp_info info = {};
  1345. struct irdma_modify_qp_resp uresp = {};
  1346. struct irdma_modify_qp_req ureq = {};
  1347. u8 issue_modify_qp = 0;
  1348. u8 dont_wait = 0;
  1349. int err;
  1350. unsigned long flags;
  1351. if (udata) {
  1352. /* udata inlen/outlen can be 0 when supporting legacy libi40iw */
  1353. if ((udata->inlen && udata->inlen < IRDMA_MODIFY_QP_MIN_REQ_LEN) ||
  1354. (udata->outlen && udata->outlen < IRDMA_MODIFY_QP_MIN_RESP_LEN))
  1355. return -EINVAL;
  1356. }
  1357. if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
  1358. return -EOPNOTSUPP;
  1359. ctx_info = &iwqp->ctx_info;
  1360. offload_info = &iwqp->iwarp_info;
  1361. tcp_info = &iwqp->tcp_info;
  1362. wait_event(iwqp->mod_qp_waitq, !atomic_read(&iwqp->hw_mod_qp_pend));
  1363. ibdev_dbg(&iwdev->ibdev,
  1364. "VERBS: caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d last_aeq=%d hw_tcp_state=%d hw_iwarp_state=%d attr_mask=0x%x\n",
  1365. __builtin_return_address(0), ibqp->qp_num, attr->qp_state,
  1366. iwqp->ibqp_state, iwqp->iwarp_state, iwqp->last_aeq,
  1367. iwqp->hw_tcp_state, iwqp->hw_iwarp_state, attr_mask);
  1368. spin_lock_irqsave(&iwqp->lock, flags);
  1369. if (attr_mask & IB_QP_STATE) {
  1370. info.curr_iwarp_state = iwqp->iwarp_state;
  1371. switch (attr->qp_state) {
  1372. case IB_QPS_INIT:
  1373. case IB_QPS_RTR:
  1374. if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) {
  1375. err = -EINVAL;
  1376. goto exit;
  1377. }
  1378. if (iwqp->iwarp_state == IRDMA_QP_STATE_INVALID) {
  1379. info.next_iwarp_state = IRDMA_QP_STATE_IDLE;
  1380. issue_modify_qp = 1;
  1381. }
  1382. if (iwdev->push_mode && udata &&
  1383. iwqp->sc_qp.push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX &&
  1384. dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
  1385. spin_unlock_irqrestore(&iwqp->lock, flags);
  1386. irdma_alloc_push_page(iwqp);
  1387. spin_lock_irqsave(&iwqp->lock, flags);
  1388. }
  1389. break;
  1390. case IB_QPS_RTS:
  1391. if (iwqp->iwarp_state > IRDMA_QP_STATE_RTS ||
  1392. !iwqp->cm_id) {
  1393. err = -EINVAL;
  1394. goto exit;
  1395. }
  1396. issue_modify_qp = 1;
  1397. iwqp->hw_tcp_state = IRDMA_TCP_STATE_ESTABLISHED;
  1398. iwqp->hte_added = 1;
  1399. info.next_iwarp_state = IRDMA_QP_STATE_RTS;
  1400. info.tcp_ctx_valid = true;
  1401. info.ord_valid = true;
  1402. info.arp_cache_idx_valid = true;
  1403. info.cq_num_valid = true;
  1404. break;
  1405. case IB_QPS_SQD:
  1406. if (iwqp->hw_iwarp_state > IRDMA_QP_STATE_RTS) {
  1407. err = 0;
  1408. goto exit;
  1409. }
  1410. if (iwqp->iwarp_state == IRDMA_QP_STATE_CLOSING ||
  1411. iwqp->iwarp_state < IRDMA_QP_STATE_RTS) {
  1412. err = 0;
  1413. goto exit;
  1414. }
  1415. if (iwqp->iwarp_state > IRDMA_QP_STATE_CLOSING) {
  1416. err = -EINVAL;
  1417. goto exit;
  1418. }
  1419. info.next_iwarp_state = IRDMA_QP_STATE_CLOSING;
  1420. issue_modify_qp = 1;
  1421. break;
  1422. case IB_QPS_SQE:
  1423. if (iwqp->iwarp_state >= IRDMA_QP_STATE_TERMINATE) {
  1424. err = -EINVAL;
  1425. goto exit;
  1426. }
  1427. info.next_iwarp_state = IRDMA_QP_STATE_TERMINATE;
  1428. issue_modify_qp = 1;
  1429. break;
  1430. case IB_QPS_ERR:
  1431. case IB_QPS_RESET:
  1432. if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) {
  1433. spin_unlock_irqrestore(&iwqp->lock, flags);
  1434. if (udata && udata->inlen) {
  1435. if (ib_copy_from_udata(&ureq, udata,
  1436. min(sizeof(ureq), udata->inlen)))
  1437. return -EINVAL;
  1438. irdma_flush_wqes(iwqp,
  1439. (ureq.sq_flush ? IRDMA_FLUSH_SQ : 0) |
  1440. (ureq.rq_flush ? IRDMA_FLUSH_RQ : 0) |
  1441. IRDMA_REFLUSH);
  1442. }
  1443. return 0;
  1444. }
  1445. if (iwqp->sc_qp.term_flags) {
  1446. spin_unlock_irqrestore(&iwqp->lock, flags);
  1447. irdma_terminate_del_timer(&iwqp->sc_qp);
  1448. spin_lock_irqsave(&iwqp->lock, flags);
  1449. }
  1450. info.next_iwarp_state = IRDMA_QP_STATE_ERROR;
  1451. if (iwqp->hw_tcp_state > IRDMA_TCP_STATE_CLOSED &&
  1452. iwdev->iw_status &&
  1453. iwqp->hw_tcp_state != IRDMA_TCP_STATE_TIME_WAIT)
  1454. info.reset_tcp_conn = true;
  1455. else
  1456. dont_wait = 1;
  1457. issue_modify_qp = 1;
  1458. info.next_iwarp_state = IRDMA_QP_STATE_ERROR;
  1459. break;
  1460. default:
  1461. err = -EINVAL;
  1462. goto exit;
  1463. }
  1464. iwqp->ibqp_state = attr->qp_state;
  1465. }
  1466. if (attr_mask & IB_QP_ACCESS_FLAGS) {
  1467. ctx_info->iwarp_info_valid = true;
  1468. if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
  1469. offload_info->wr_rdresp_en = true;
  1470. if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
  1471. offload_info->wr_rdresp_en = true;
  1472. if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
  1473. offload_info->rd_en = true;
  1474. }
  1475. if (ctx_info->iwarp_info_valid) {
  1476. ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
  1477. ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
  1478. irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
  1479. }
  1480. spin_unlock_irqrestore(&iwqp->lock, flags);
  1481. if (attr_mask & IB_QP_STATE) {
  1482. if (issue_modify_qp) {
  1483. ctx_info->rem_endpoint_idx = tcp_info->arp_idx;
  1484. if (irdma_hw_modify_qp(iwdev, iwqp, &info, true))
  1485. return -EINVAL;
  1486. }
  1487. spin_lock_irqsave(&iwqp->lock, flags);
  1488. if (iwqp->iwarp_state == info.curr_iwarp_state) {
  1489. iwqp->iwarp_state = info.next_iwarp_state;
  1490. iwqp->ibqp_state = attr->qp_state;
  1491. }
  1492. spin_unlock_irqrestore(&iwqp->lock, flags);
  1493. }
  1494. if (issue_modify_qp && iwqp->ibqp_state > IB_QPS_RTS) {
  1495. if (dont_wait) {
  1496. if (iwqp->hw_tcp_state) {
  1497. spin_lock_irqsave(&iwqp->lock, flags);
  1498. iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSED;
  1499. iwqp->last_aeq = IRDMA_AE_RESET_SENT;
  1500. spin_unlock_irqrestore(&iwqp->lock, flags);
  1501. }
  1502. irdma_cm_disconn(iwqp);
  1503. } else {
  1504. int close_timer_started;
  1505. spin_lock_irqsave(&iwdev->cm_core.ht_lock, flags);
  1506. if (iwqp->cm_node) {
  1507. refcount_inc(&iwqp->cm_node->refcnt);
  1508. spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags);
  1509. close_timer_started = atomic_inc_return(&iwqp->close_timer_started);
  1510. if (iwqp->cm_id && close_timer_started == 1)
  1511. irdma_schedule_cm_timer(iwqp->cm_node,
  1512. (struct irdma_puda_buf *)iwqp,
  1513. IRDMA_TIMER_TYPE_CLOSE, 1, 0);
  1514. irdma_rem_ref_cm_node(iwqp->cm_node);
  1515. } else {
  1516. spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags);
  1517. }
  1518. }
  1519. }
  1520. if (attr_mask & IB_QP_STATE && udata && udata->outlen &&
  1521. dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
  1522. struct irdma_ucontext *ucontext;
  1523. ucontext = rdma_udata_to_drv_context(udata,
  1524. struct irdma_ucontext, ibucontext);
  1525. if (iwqp->sc_qp.push_idx != IRDMA_INVALID_PUSH_PAGE_INDEX &&
  1526. !iwqp->push_wqe_mmap_entry &&
  1527. !irdma_setup_push_mmap_entries(ucontext, iwqp,
  1528. &uresp.push_wqe_mmap_key, &uresp.push_db_mmap_key)) {
  1529. uresp.push_valid = 1;
  1530. uresp.push_offset = iwqp->sc_qp.push_offset;
  1531. }
  1532. err = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp),
  1533. udata->outlen));
  1534. if (err) {
  1535. irdma_remove_push_mmap_entries(iwqp);
  1536. ibdev_dbg(&iwdev->ibdev,
  1537. "VERBS: copy_to_udata failed\n");
  1538. return err;
  1539. }
  1540. }
  1541. return 0;
  1542. exit:
  1543. spin_unlock_irqrestore(&iwqp->lock, flags);
  1544. return err;
  1545. }
  1546. /**
  1547. * irdma_cq_free_rsrc - free up resources for cq
  1548. * @rf: RDMA PCI function
  1549. * @iwcq: cq ptr
  1550. */
  1551. static void irdma_cq_free_rsrc(struct irdma_pci_f *rf, struct irdma_cq *iwcq)
  1552. {
  1553. struct irdma_sc_cq *cq = &iwcq->sc_cq;
  1554. if (!iwcq->user_mode) {
  1555. dma_free_coherent(rf->sc_dev.hw->device, iwcq->kmem.size,
  1556. iwcq->kmem.va, iwcq->kmem.pa);
  1557. iwcq->kmem.va = NULL;
  1558. dma_free_coherent(rf->sc_dev.hw->device,
  1559. iwcq->kmem_shadow.size,
  1560. iwcq->kmem_shadow.va, iwcq->kmem_shadow.pa);
  1561. iwcq->kmem_shadow.va = NULL;
  1562. }
  1563. irdma_free_rsrc(rf, rf->allocated_cqs, cq->cq_uk.cq_id);
  1564. }
  1565. /**
  1566. * irdma_free_cqbuf - worker to free a cq buffer
  1567. * @work: provides access to the cq buffer to free
  1568. */
  1569. static void irdma_free_cqbuf(struct work_struct *work)
  1570. {
  1571. struct irdma_cq_buf *cq_buf = container_of(work, struct irdma_cq_buf, work);
  1572. dma_free_coherent(cq_buf->hw->device, cq_buf->kmem_buf.size,
  1573. cq_buf->kmem_buf.va, cq_buf->kmem_buf.pa);
  1574. cq_buf->kmem_buf.va = NULL;
  1575. kfree(cq_buf);
  1576. }
  1577. /**
  1578. * irdma_process_resize_list - remove resized cq buffers from the resize_list
  1579. * @iwcq: cq which owns the resize_list
  1580. * @iwdev: irdma device
  1581. * @lcqe_buf: the buffer where the last cqe is received
  1582. */
  1583. static int irdma_process_resize_list(struct irdma_cq *iwcq,
  1584. struct irdma_device *iwdev,
  1585. struct irdma_cq_buf *lcqe_buf)
  1586. {
  1587. struct list_head *tmp_node, *list_node;
  1588. struct irdma_cq_buf *cq_buf;
  1589. int cnt = 0;
  1590. list_for_each_safe(list_node, tmp_node, &iwcq->resize_list) {
  1591. cq_buf = list_entry(list_node, struct irdma_cq_buf, list);
  1592. if (cq_buf == lcqe_buf)
  1593. return cnt;
  1594. list_del(&cq_buf->list);
  1595. queue_work(iwdev->cleanup_wq, &cq_buf->work);
  1596. cnt++;
  1597. }
  1598. return cnt;
  1599. }
  1600. /**
  1601. * irdma_destroy_cq - destroy cq
  1602. * @ib_cq: cq pointer
  1603. * @udata: user data
  1604. */
  1605. static int irdma_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
  1606. {
  1607. struct irdma_device *iwdev = to_iwdev(ib_cq->device);
  1608. struct irdma_cq *iwcq = to_iwcq(ib_cq);
  1609. struct irdma_sc_cq *cq = &iwcq->sc_cq;
  1610. struct irdma_sc_dev *dev = cq->dev;
  1611. struct irdma_sc_ceq *ceq = dev->ceq[cq->ceq_id];
  1612. struct irdma_ceq *iwceq = container_of(ceq, struct irdma_ceq, sc_ceq);
  1613. unsigned long flags;
  1614. spin_lock_irqsave(&iwcq->lock, flags);
  1615. if (!list_empty(&iwcq->cmpl_generated))
  1616. irdma_remove_cmpls_list(iwcq);
  1617. if (!list_empty(&iwcq->resize_list))
  1618. irdma_process_resize_list(iwcq, iwdev, NULL);
  1619. spin_unlock_irqrestore(&iwcq->lock, flags);
  1620. irdma_cq_rem_ref(ib_cq);
  1621. wait_for_completion(&iwcq->free_cq);
  1622. irdma_cq_wq_destroy(iwdev->rf, cq);
  1623. spin_lock_irqsave(&iwceq->ce_lock, flags);
  1624. irdma_sc_cleanup_ceqes(cq, ceq);
  1625. spin_unlock_irqrestore(&iwceq->ce_lock, flags);
  1626. irdma_cq_free_rsrc(iwdev->rf, iwcq);
  1627. return 0;
  1628. }
  1629. /**
  1630. * irdma_resize_cq - resize cq
  1631. * @ibcq: cq to be resized
  1632. * @entries: desired cq size
  1633. * @udata: user data
  1634. */
  1635. static int irdma_resize_cq(struct ib_cq *ibcq, int entries,
  1636. struct ib_udata *udata)
  1637. {
  1638. #define IRDMA_RESIZE_CQ_MIN_REQ_LEN offsetofend(struct irdma_resize_cq_req, user_cq_buffer)
  1639. struct irdma_cq *iwcq = to_iwcq(ibcq);
  1640. struct irdma_sc_dev *dev = iwcq->sc_cq.dev;
  1641. struct irdma_cqp_request *cqp_request;
  1642. struct cqp_cmds_info *cqp_info;
  1643. struct irdma_modify_cq_info *m_info;
  1644. struct irdma_modify_cq_info info = {};
  1645. struct irdma_dma_mem kmem_buf;
  1646. struct irdma_cq_mr *cqmr_buf;
  1647. struct irdma_pbl *iwpbl_buf;
  1648. struct irdma_device *iwdev;
  1649. struct irdma_pci_f *rf;
  1650. struct irdma_cq_buf *cq_buf = NULL;
  1651. unsigned long flags;
  1652. int ret;
  1653. iwdev = to_iwdev(ibcq->device);
  1654. rf = iwdev->rf;
  1655. if (!(rf->sc_dev.hw_attrs.uk_attrs.feature_flags &
  1656. IRDMA_FEATURE_CQ_RESIZE))
  1657. return -EOPNOTSUPP;
  1658. if (udata && udata->inlen < IRDMA_RESIZE_CQ_MIN_REQ_LEN)
  1659. return -EINVAL;
  1660. if (entries > rf->max_cqe)
  1661. return -EINVAL;
  1662. if (!iwcq->user_mode) {
  1663. entries++;
  1664. if (rf->sc_dev.hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
  1665. entries *= 2;
  1666. }
  1667. info.cq_size = max(entries, 4);
  1668. if (info.cq_size == iwcq->sc_cq.cq_uk.cq_size - 1)
  1669. return 0;
  1670. if (udata) {
  1671. struct irdma_resize_cq_req req = {};
  1672. struct irdma_ucontext *ucontext =
  1673. rdma_udata_to_drv_context(udata, struct irdma_ucontext,
  1674. ibucontext);
  1675. /* CQ resize not supported with legacy GEN_1 libi40iw */
  1676. if (ucontext->legacy_mode)
  1677. return -EOPNOTSUPP;
  1678. if (ib_copy_from_udata(&req, udata,
  1679. min(sizeof(req), udata->inlen)))
  1680. return -EINVAL;
  1681. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1682. iwpbl_buf = irdma_get_pbl((unsigned long)req.user_cq_buffer,
  1683. &ucontext->cq_reg_mem_list);
  1684. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1685. if (!iwpbl_buf)
  1686. return -ENOMEM;
  1687. cqmr_buf = &iwpbl_buf->cq_mr;
  1688. if (iwpbl_buf->pbl_allocated) {
  1689. info.virtual_map = true;
  1690. info.pbl_chunk_size = 1;
  1691. info.first_pm_pbl_idx = cqmr_buf->cq_pbl.idx;
  1692. } else {
  1693. info.cq_pa = cqmr_buf->cq_pbl.addr;
  1694. }
  1695. } else {
  1696. /* Kmode CQ resize */
  1697. int rsize;
  1698. rsize = info.cq_size * sizeof(struct irdma_cqe);
  1699. kmem_buf.size = ALIGN(round_up(rsize, 256), 256);
  1700. kmem_buf.va = dma_alloc_coherent(dev->hw->device,
  1701. kmem_buf.size, &kmem_buf.pa,
  1702. GFP_KERNEL);
  1703. if (!kmem_buf.va)
  1704. return -ENOMEM;
  1705. info.cq_base = kmem_buf.va;
  1706. info.cq_pa = kmem_buf.pa;
  1707. cq_buf = kzalloc(sizeof(*cq_buf), GFP_KERNEL);
  1708. if (!cq_buf) {
  1709. ret = -ENOMEM;
  1710. goto error;
  1711. }
  1712. }
  1713. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  1714. if (!cqp_request) {
  1715. ret = -ENOMEM;
  1716. goto error;
  1717. }
  1718. info.shadow_read_threshold = iwcq->sc_cq.shadow_read_threshold;
  1719. info.cq_resize = true;
  1720. cqp_info = &cqp_request->info;
  1721. m_info = &cqp_info->in.u.cq_modify.info;
  1722. memcpy(m_info, &info, sizeof(*m_info));
  1723. cqp_info->cqp_cmd = IRDMA_OP_CQ_MODIFY;
  1724. cqp_info->in.u.cq_modify.cq = &iwcq->sc_cq;
  1725. cqp_info->in.u.cq_modify.scratch = (uintptr_t)cqp_request;
  1726. cqp_info->post_sq = 1;
  1727. ret = irdma_handle_cqp_op(rf, cqp_request);
  1728. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1729. if (ret)
  1730. goto error;
  1731. spin_lock_irqsave(&iwcq->lock, flags);
  1732. if (cq_buf) {
  1733. cq_buf->kmem_buf = iwcq->kmem;
  1734. cq_buf->hw = dev->hw;
  1735. memcpy(&cq_buf->cq_uk, &iwcq->sc_cq.cq_uk, sizeof(cq_buf->cq_uk));
  1736. INIT_WORK(&cq_buf->work, irdma_free_cqbuf);
  1737. list_add_tail(&cq_buf->list, &iwcq->resize_list);
  1738. iwcq->kmem = kmem_buf;
  1739. }
  1740. irdma_sc_cq_resize(&iwcq->sc_cq, &info);
  1741. ibcq->cqe = info.cq_size - 1;
  1742. spin_unlock_irqrestore(&iwcq->lock, flags);
  1743. return 0;
  1744. error:
  1745. if (!udata) {
  1746. dma_free_coherent(dev->hw->device, kmem_buf.size, kmem_buf.va,
  1747. kmem_buf.pa);
  1748. kmem_buf.va = NULL;
  1749. }
  1750. kfree(cq_buf);
  1751. return ret;
  1752. }
  1753. static inline int cq_validate_flags(u32 flags, u8 hw_rev)
  1754. {
  1755. /* GEN1 does not support CQ create flags */
  1756. if (hw_rev == IRDMA_GEN_1)
  1757. return flags ? -EOPNOTSUPP : 0;
  1758. return flags & ~IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION ? -EOPNOTSUPP : 0;
  1759. }
  1760. /**
  1761. * irdma_create_cq - create cq
  1762. * @ibcq: CQ allocated
  1763. * @attr: attributes for cq
  1764. * @attrs: uverbs attribute bundle
  1765. */
  1766. static int irdma_create_cq(struct ib_cq *ibcq,
  1767. const struct ib_cq_init_attr *attr,
  1768. struct uverbs_attr_bundle *attrs)
  1769. {
  1770. #define IRDMA_CREATE_CQ_MIN_REQ_LEN offsetofend(struct irdma_create_cq_req, user_cq_buf)
  1771. #define IRDMA_CREATE_CQ_MIN_RESP_LEN offsetofend(struct irdma_create_cq_resp, cq_size)
  1772. struct ib_udata *udata = &attrs->driver_udata;
  1773. struct ib_device *ibdev = ibcq->device;
  1774. struct irdma_device *iwdev = to_iwdev(ibdev);
  1775. struct irdma_pci_f *rf = iwdev->rf;
  1776. struct irdma_cq *iwcq = to_iwcq(ibcq);
  1777. u32 cq_num = 0;
  1778. struct irdma_sc_cq *cq;
  1779. struct irdma_sc_dev *dev = &rf->sc_dev;
  1780. struct irdma_cq_init_info info = {};
  1781. struct irdma_cqp_request *cqp_request;
  1782. struct cqp_cmds_info *cqp_info;
  1783. struct irdma_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
  1784. unsigned long flags;
  1785. int err_code;
  1786. int entries = attr->cqe;
  1787. err_code = cq_validate_flags(attr->flags, dev->hw_attrs.uk_attrs.hw_rev);
  1788. if (err_code)
  1789. return err_code;
  1790. if (udata && (udata->inlen < IRDMA_CREATE_CQ_MIN_REQ_LEN ||
  1791. udata->outlen < IRDMA_CREATE_CQ_MIN_RESP_LEN))
  1792. return -EINVAL;
  1793. err_code = irdma_alloc_rsrc(rf, rf->allocated_cqs, rf->max_cq, &cq_num,
  1794. &rf->next_cq);
  1795. if (err_code)
  1796. return err_code;
  1797. cq = &iwcq->sc_cq;
  1798. cq->back_cq = iwcq;
  1799. refcount_set(&iwcq->refcnt, 1);
  1800. spin_lock_init(&iwcq->lock);
  1801. INIT_LIST_HEAD(&iwcq->resize_list);
  1802. INIT_LIST_HEAD(&iwcq->cmpl_generated);
  1803. info.dev = dev;
  1804. ukinfo->cq_size = max(entries, 4);
  1805. ukinfo->cq_id = cq_num;
  1806. iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
  1807. if (attr->comp_vector < rf->ceqs_count)
  1808. info.ceq_id = attr->comp_vector;
  1809. info.ceq_id_valid = true;
  1810. info.ceqe_mask = 1;
  1811. info.type = IRDMA_CQ_TYPE_IWARP;
  1812. info.vsi = &iwdev->vsi;
  1813. if (udata) {
  1814. struct irdma_ucontext *ucontext;
  1815. struct irdma_create_cq_req req = {};
  1816. struct irdma_cq_mr *cqmr;
  1817. struct irdma_pbl *iwpbl;
  1818. struct irdma_pbl *iwpbl_shadow;
  1819. struct irdma_cq_mr *cqmr_shadow;
  1820. iwcq->user_mode = true;
  1821. ucontext =
  1822. rdma_udata_to_drv_context(udata, struct irdma_ucontext,
  1823. ibucontext);
  1824. if (ib_copy_from_udata(&req, udata,
  1825. min(sizeof(req), udata->inlen))) {
  1826. err_code = -EFAULT;
  1827. goto cq_free_rsrc;
  1828. }
  1829. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1830. iwpbl = irdma_get_pbl((unsigned long)req.user_cq_buf,
  1831. &ucontext->cq_reg_mem_list);
  1832. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1833. if (!iwpbl) {
  1834. err_code = -EPROTO;
  1835. goto cq_free_rsrc;
  1836. }
  1837. iwcq->iwpbl = iwpbl;
  1838. iwcq->cq_mem_size = 0;
  1839. cqmr = &iwpbl->cq_mr;
  1840. if (rf->sc_dev.hw_attrs.uk_attrs.feature_flags &
  1841. IRDMA_FEATURE_CQ_RESIZE && !ucontext->legacy_mode) {
  1842. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  1843. iwpbl_shadow = irdma_get_pbl(
  1844. (unsigned long)req.user_shadow_area,
  1845. &ucontext->cq_reg_mem_list);
  1846. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  1847. if (!iwpbl_shadow) {
  1848. err_code = -EPROTO;
  1849. goto cq_free_rsrc;
  1850. }
  1851. iwcq->iwpbl_shadow = iwpbl_shadow;
  1852. cqmr_shadow = &iwpbl_shadow->cq_mr;
  1853. info.shadow_area_pa = cqmr_shadow->cq_pbl.addr;
  1854. cqmr->split = true;
  1855. } else {
  1856. info.shadow_area_pa = cqmr->shadow;
  1857. }
  1858. if (iwpbl->pbl_allocated) {
  1859. info.virtual_map = true;
  1860. info.pbl_chunk_size = 1;
  1861. info.first_pm_pbl_idx = cqmr->cq_pbl.idx;
  1862. } else {
  1863. info.cq_base_pa = cqmr->cq_pbl.addr;
  1864. }
  1865. } else {
  1866. /* Kmode allocations */
  1867. int rsize;
  1868. if (entries < 1 || entries > rf->max_cqe) {
  1869. err_code = -EINVAL;
  1870. goto cq_free_rsrc;
  1871. }
  1872. entries++;
  1873. if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
  1874. entries *= 2;
  1875. ukinfo->cq_size = entries;
  1876. rsize = info.cq_uk_init_info.cq_size * sizeof(struct irdma_cqe);
  1877. iwcq->kmem.size = ALIGN(round_up(rsize, 256), 256);
  1878. iwcq->kmem.va = dma_alloc_coherent(dev->hw->device,
  1879. iwcq->kmem.size,
  1880. &iwcq->kmem.pa, GFP_KERNEL);
  1881. if (!iwcq->kmem.va) {
  1882. err_code = -ENOMEM;
  1883. goto cq_free_rsrc;
  1884. }
  1885. iwcq->kmem_shadow.size = ALIGN(IRDMA_SHADOW_AREA_SIZE << 3,
  1886. 64);
  1887. iwcq->kmem_shadow.va = dma_alloc_coherent(dev->hw->device,
  1888. iwcq->kmem_shadow.size,
  1889. &iwcq->kmem_shadow.pa,
  1890. GFP_KERNEL);
  1891. if (!iwcq->kmem_shadow.va) {
  1892. err_code = -ENOMEM;
  1893. goto cq_free_rsrc;
  1894. }
  1895. info.shadow_area_pa = iwcq->kmem_shadow.pa;
  1896. ukinfo->shadow_area = iwcq->kmem_shadow.va;
  1897. ukinfo->cq_base = iwcq->kmem.va;
  1898. info.cq_base_pa = iwcq->kmem.pa;
  1899. }
  1900. info.shadow_read_threshold = min(info.cq_uk_init_info.cq_size / 2,
  1901. (u32)IRDMA_MAX_CQ_READ_THRESH);
  1902. if (irdma_sc_cq_init(cq, &info)) {
  1903. ibdev_dbg(&iwdev->ibdev, "VERBS: init cq fail\n");
  1904. err_code = -EPROTO;
  1905. goto cq_free_rsrc;
  1906. }
  1907. cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
  1908. if (!cqp_request) {
  1909. err_code = -ENOMEM;
  1910. goto cq_free_rsrc;
  1911. }
  1912. cqp_info = &cqp_request->info;
  1913. cqp_info->cqp_cmd = IRDMA_OP_CQ_CREATE;
  1914. cqp_info->post_sq = 1;
  1915. cqp_info->in.u.cq_create.cq = cq;
  1916. cqp_info->in.u.cq_create.check_overflow = true;
  1917. cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
  1918. err_code = irdma_handle_cqp_op(rf, cqp_request);
  1919. irdma_put_cqp_request(&rf->cqp, cqp_request);
  1920. if (err_code)
  1921. goto cq_free_rsrc;
  1922. if (udata) {
  1923. struct irdma_create_cq_resp resp = {};
  1924. resp.cq_id = info.cq_uk_init_info.cq_id;
  1925. resp.cq_size = info.cq_uk_init_info.cq_size;
  1926. if (ib_copy_to_udata(udata, &resp,
  1927. min(sizeof(resp), udata->outlen))) {
  1928. ibdev_dbg(&iwdev->ibdev,
  1929. "VERBS: copy to user data\n");
  1930. err_code = -EPROTO;
  1931. goto cq_destroy;
  1932. }
  1933. }
  1934. rf->cq_table[cq_num] = iwcq;
  1935. init_completion(&iwcq->free_cq);
  1936. return 0;
  1937. cq_destroy:
  1938. irdma_cq_wq_destroy(rf, cq);
  1939. cq_free_rsrc:
  1940. irdma_cq_free_rsrc(rf, iwcq);
  1941. return err_code;
  1942. }
  1943. /**
  1944. * irdma_get_mr_access - get hw MR access permissions from IB access flags
  1945. * @access: IB access flags
  1946. */
  1947. static inline u16 irdma_get_mr_access(int access)
  1948. {
  1949. u16 hw_access = 0;
  1950. hw_access |= (access & IB_ACCESS_LOCAL_WRITE) ?
  1951. IRDMA_ACCESS_FLAGS_LOCALWRITE : 0;
  1952. hw_access |= (access & IB_ACCESS_REMOTE_WRITE) ?
  1953. IRDMA_ACCESS_FLAGS_REMOTEWRITE : 0;
  1954. hw_access |= (access & IB_ACCESS_REMOTE_READ) ?
  1955. IRDMA_ACCESS_FLAGS_REMOTEREAD : 0;
  1956. hw_access |= (access & IB_ACCESS_MW_BIND) ?
  1957. IRDMA_ACCESS_FLAGS_BIND_WINDOW : 0;
  1958. hw_access |= (access & IB_ZERO_BASED) ?
  1959. IRDMA_ACCESS_FLAGS_ZERO_BASED : 0;
  1960. hw_access |= IRDMA_ACCESS_FLAGS_LOCALREAD;
  1961. return hw_access;
  1962. }
  1963. /**
  1964. * irdma_free_stag - free stag resource
  1965. * @iwdev: irdma device
  1966. * @stag: stag to free
  1967. */
  1968. static void irdma_free_stag(struct irdma_device *iwdev, u32 stag)
  1969. {
  1970. u32 stag_idx;
  1971. stag_idx = (stag & iwdev->rf->mr_stagmask) >> IRDMA_CQPSQ_STAG_IDX_S;
  1972. irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_mrs, stag_idx);
  1973. }
  1974. /**
  1975. * irdma_create_stag - create random stag
  1976. * @iwdev: irdma device
  1977. */
  1978. static u32 irdma_create_stag(struct irdma_device *iwdev)
  1979. {
  1980. u32 stag = 0;
  1981. u32 stag_index = 0;
  1982. u32 next_stag_index;
  1983. u32 driver_key;
  1984. u32 random;
  1985. u8 consumer_key;
  1986. int ret;
  1987. get_random_bytes(&random, sizeof(random));
  1988. consumer_key = (u8)random;
  1989. driver_key = random & ~iwdev->rf->mr_stagmask;
  1990. next_stag_index = (random & iwdev->rf->mr_stagmask) >> 8;
  1991. next_stag_index %= iwdev->rf->max_mr;
  1992. ret = irdma_alloc_rsrc(iwdev->rf, iwdev->rf->allocated_mrs,
  1993. iwdev->rf->max_mr, &stag_index,
  1994. &next_stag_index);
  1995. if (ret)
  1996. return stag;
  1997. stag = stag_index << IRDMA_CQPSQ_STAG_IDX_S;
  1998. stag |= driver_key;
  1999. stag += (u32)consumer_key;
  2000. return stag;
  2001. }
  2002. /**
  2003. * irdma_next_pbl_addr - Get next pbl address
  2004. * @pbl: pointer to a pble
  2005. * @pinfo: info pointer
  2006. * @idx: index
  2007. */
  2008. static inline u64 *irdma_next_pbl_addr(u64 *pbl, struct irdma_pble_info **pinfo,
  2009. u32 *idx)
  2010. {
  2011. *idx += 1;
  2012. if (!(*pinfo) || *idx != (*pinfo)->cnt)
  2013. return ++pbl;
  2014. *idx = 0;
  2015. (*pinfo)++;
  2016. return (*pinfo)->addr;
  2017. }
  2018. /**
  2019. * irdma_copy_user_pgaddrs - copy user page address to pble's os locally
  2020. * @iwmr: iwmr for IB's user page addresses
  2021. * @pbl: ple pointer to save 1 level or 0 level pble
  2022. * @level: indicated level 0, 1 or 2
  2023. */
  2024. static void irdma_copy_user_pgaddrs(struct irdma_mr *iwmr, u64 *pbl,
  2025. enum irdma_pble_level level)
  2026. {
  2027. struct ib_umem *region = iwmr->region;
  2028. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2029. struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
  2030. struct irdma_pble_info *pinfo;
  2031. struct ib_block_iter biter;
  2032. u32 idx = 0;
  2033. u32 pbl_cnt = 0;
  2034. pinfo = (level == PBLE_LEVEL_1) ? NULL : palloc->level2.leaf;
  2035. if (iwmr->type == IRDMA_MEMREG_TYPE_QP)
  2036. iwpbl->qp_mr.sq_page = sg_page(region->sgt_append.sgt.sgl);
  2037. rdma_umem_for_each_dma_block(region, &biter, iwmr->page_size) {
  2038. *pbl = rdma_block_iter_dma_address(&biter);
  2039. if (++pbl_cnt == palloc->total_cnt)
  2040. break;
  2041. pbl = irdma_next_pbl_addr(pbl, &pinfo, &idx);
  2042. }
  2043. }
  2044. /**
  2045. * irdma_check_mem_contiguous - check if pbls stored in arr are contiguous
  2046. * @arr: lvl1 pbl array
  2047. * @npages: page count
  2048. * @pg_size: page size
  2049. *
  2050. */
  2051. static bool irdma_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size)
  2052. {
  2053. u32 pg_idx;
  2054. for (pg_idx = 0; pg_idx < npages; pg_idx++) {
  2055. if ((*arr + (pg_size * pg_idx)) != arr[pg_idx])
  2056. return false;
  2057. }
  2058. return true;
  2059. }
  2060. /**
  2061. * irdma_check_mr_contiguous - check if MR is physically contiguous
  2062. * @palloc: pbl allocation struct
  2063. * @pg_size: page size
  2064. */
  2065. static bool irdma_check_mr_contiguous(struct irdma_pble_alloc *palloc,
  2066. u32 pg_size)
  2067. {
  2068. struct irdma_pble_level2 *lvl2 = &palloc->level2;
  2069. struct irdma_pble_info *leaf = lvl2->leaf;
  2070. u64 *arr = NULL;
  2071. u64 *start_addr = NULL;
  2072. int i;
  2073. bool ret;
  2074. if (palloc->level == PBLE_LEVEL_1) {
  2075. arr = palloc->level1.addr;
  2076. ret = irdma_check_mem_contiguous(arr, palloc->total_cnt,
  2077. pg_size);
  2078. return ret;
  2079. }
  2080. start_addr = leaf->addr;
  2081. for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) {
  2082. arr = leaf->addr;
  2083. if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr)
  2084. return false;
  2085. ret = irdma_check_mem_contiguous(arr, leaf->cnt, pg_size);
  2086. if (!ret)
  2087. return false;
  2088. }
  2089. return true;
  2090. }
  2091. /**
  2092. * irdma_setup_pbles - copy user pg address to pble's
  2093. * @rf: RDMA PCI function
  2094. * @iwmr: mr pointer for this memory registration
  2095. * @lvl: requested pble levels
  2096. */
  2097. static int irdma_setup_pbles(struct irdma_pci_f *rf, struct irdma_mr *iwmr,
  2098. u8 lvl)
  2099. {
  2100. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2101. struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
  2102. struct irdma_pble_info *pinfo;
  2103. u64 *pbl;
  2104. int status;
  2105. enum irdma_pble_level level = PBLE_LEVEL_1;
  2106. if (lvl) {
  2107. status = irdma_get_pble(rf->pble_rsrc, palloc, iwmr->page_cnt,
  2108. lvl);
  2109. if (status)
  2110. return status;
  2111. iwpbl->pbl_allocated = true;
  2112. level = palloc->level;
  2113. pinfo = (level == PBLE_LEVEL_1) ? &palloc->level1 :
  2114. palloc->level2.leaf;
  2115. pbl = pinfo->addr;
  2116. } else {
  2117. pbl = iwmr->pgaddrmem;
  2118. }
  2119. irdma_copy_user_pgaddrs(iwmr, pbl, level);
  2120. if (lvl)
  2121. iwmr->pgaddrmem[0] = *pbl;
  2122. return 0;
  2123. }
  2124. /**
  2125. * irdma_handle_q_mem - handle memory for qp and cq
  2126. * @iwdev: irdma device
  2127. * @req: information for q memory management
  2128. * @iwpbl: pble struct
  2129. * @lvl: pble level mask
  2130. */
  2131. static int irdma_handle_q_mem(struct irdma_device *iwdev,
  2132. struct irdma_mem_reg_req *req,
  2133. struct irdma_pbl *iwpbl, u8 lvl)
  2134. {
  2135. struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
  2136. struct irdma_mr *iwmr = iwpbl->iwmr;
  2137. struct irdma_qp_mr *qpmr = &iwpbl->qp_mr;
  2138. struct irdma_cq_mr *cqmr = &iwpbl->cq_mr;
  2139. struct irdma_hmc_pble *hmc_p;
  2140. u64 *arr = iwmr->pgaddrmem;
  2141. u32 pg_size, total;
  2142. int err = 0;
  2143. bool ret = true;
  2144. pg_size = iwmr->page_size;
  2145. err = irdma_setup_pbles(iwdev->rf, iwmr, lvl);
  2146. if (err)
  2147. return err;
  2148. if (lvl)
  2149. arr = palloc->level1.addr;
  2150. switch (iwmr->type) {
  2151. case IRDMA_MEMREG_TYPE_QP:
  2152. total = req->sq_pages + req->rq_pages;
  2153. hmc_p = &qpmr->sq_pbl;
  2154. qpmr->shadow = (dma_addr_t)arr[total];
  2155. if (lvl) {
  2156. ret = irdma_check_mem_contiguous(arr, req->sq_pages,
  2157. pg_size);
  2158. if (ret)
  2159. ret = irdma_check_mem_contiguous(&arr[req->sq_pages],
  2160. req->rq_pages,
  2161. pg_size);
  2162. }
  2163. if (!ret) {
  2164. hmc_p->idx = palloc->level1.idx;
  2165. hmc_p = &qpmr->rq_pbl;
  2166. hmc_p->idx = palloc->level1.idx + req->sq_pages;
  2167. } else {
  2168. hmc_p->addr = arr[0];
  2169. hmc_p = &qpmr->rq_pbl;
  2170. hmc_p->addr = arr[req->sq_pages];
  2171. }
  2172. break;
  2173. case IRDMA_MEMREG_TYPE_CQ:
  2174. hmc_p = &cqmr->cq_pbl;
  2175. if (!cqmr->split)
  2176. cqmr->shadow = (dma_addr_t)arr[req->cq_pages];
  2177. if (lvl)
  2178. ret = irdma_check_mem_contiguous(arr, req->cq_pages,
  2179. pg_size);
  2180. if (!ret)
  2181. hmc_p->idx = palloc->level1.idx;
  2182. else
  2183. hmc_p->addr = arr[0];
  2184. break;
  2185. default:
  2186. ibdev_dbg(&iwdev->ibdev, "VERBS: MR type error\n");
  2187. err = -EINVAL;
  2188. }
  2189. if (lvl && ret) {
  2190. irdma_free_pble(iwdev->rf->pble_rsrc, palloc);
  2191. iwpbl->pbl_allocated = false;
  2192. }
  2193. return err;
  2194. }
  2195. /**
  2196. * irdma_hw_alloc_mw - create the hw memory window
  2197. * @iwdev: irdma device
  2198. * @iwmr: pointer to memory window info
  2199. */
  2200. static int irdma_hw_alloc_mw(struct irdma_device *iwdev, struct irdma_mr *iwmr)
  2201. {
  2202. struct irdma_mw_alloc_info *info;
  2203. struct irdma_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
  2204. struct irdma_cqp_request *cqp_request;
  2205. struct cqp_cmds_info *cqp_info;
  2206. int status;
  2207. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  2208. if (!cqp_request)
  2209. return -ENOMEM;
  2210. cqp_info = &cqp_request->info;
  2211. info = &cqp_info->in.u.mw_alloc.info;
  2212. memset(info, 0, sizeof(*info));
  2213. if (iwmr->ibmw.type == IB_MW_TYPE_1)
  2214. info->mw_wide = true;
  2215. info->page_size = PAGE_SIZE;
  2216. info->mw_stag_index = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S;
  2217. info->pd_id = iwpd->sc_pd.pd_id;
  2218. info->remote_access = true;
  2219. cqp_info->cqp_cmd = IRDMA_OP_MW_ALLOC;
  2220. cqp_info->post_sq = 1;
  2221. cqp_info->in.u.mw_alloc.dev = &iwdev->rf->sc_dev;
  2222. cqp_info->in.u.mw_alloc.scratch = (uintptr_t)cqp_request;
  2223. status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
  2224. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  2225. return status;
  2226. }
  2227. /**
  2228. * irdma_alloc_mw - Allocate memory window
  2229. * @ibmw: Memory Window
  2230. * @udata: user data pointer
  2231. */
  2232. static int irdma_alloc_mw(struct ib_mw *ibmw, struct ib_udata *udata)
  2233. {
  2234. struct irdma_device *iwdev = to_iwdev(ibmw->device);
  2235. struct irdma_mr *iwmr = to_iwmw(ibmw);
  2236. int err_code;
  2237. u32 stag;
  2238. stag = irdma_create_stag(iwdev);
  2239. if (!stag)
  2240. return -ENOMEM;
  2241. iwmr->stag = stag;
  2242. ibmw->rkey = stag;
  2243. err_code = irdma_hw_alloc_mw(iwdev, iwmr);
  2244. if (err_code) {
  2245. irdma_free_stag(iwdev, stag);
  2246. return err_code;
  2247. }
  2248. return 0;
  2249. }
  2250. /**
  2251. * irdma_dealloc_mw - Dealloc memory window
  2252. * @ibmw: memory window structure.
  2253. */
  2254. static int irdma_dealloc_mw(struct ib_mw *ibmw)
  2255. {
  2256. struct ib_pd *ibpd = ibmw->pd;
  2257. struct irdma_pd *iwpd = to_iwpd(ibpd);
  2258. struct irdma_mr *iwmr = to_iwmr((struct ib_mr *)ibmw);
  2259. struct irdma_device *iwdev = to_iwdev(ibmw->device);
  2260. struct irdma_cqp_request *cqp_request;
  2261. struct cqp_cmds_info *cqp_info;
  2262. struct irdma_dealloc_stag_info *info;
  2263. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  2264. if (!cqp_request)
  2265. return -ENOMEM;
  2266. cqp_info = &cqp_request->info;
  2267. info = &cqp_info->in.u.dealloc_stag.info;
  2268. memset(info, 0, sizeof(*info));
  2269. info->pd_id = iwpd->sc_pd.pd_id;
  2270. info->stag_idx = ibmw->rkey >> IRDMA_CQPSQ_STAG_IDX_S;
  2271. info->mr = false;
  2272. cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG;
  2273. cqp_info->post_sq = 1;
  2274. cqp_info->in.u.dealloc_stag.dev = &iwdev->rf->sc_dev;
  2275. cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
  2276. irdma_handle_cqp_op(iwdev->rf, cqp_request);
  2277. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  2278. irdma_free_stag(iwdev, iwmr->stag);
  2279. return 0;
  2280. }
  2281. /**
  2282. * irdma_hw_alloc_stag - cqp command to allocate stag
  2283. * @iwdev: irdma device
  2284. * @iwmr: irdma mr pointer
  2285. */
  2286. static int irdma_hw_alloc_stag(struct irdma_device *iwdev,
  2287. struct irdma_mr *iwmr)
  2288. {
  2289. struct irdma_allocate_stag_info *info;
  2290. struct ib_pd *pd = iwmr->ibmr.pd;
  2291. struct irdma_pd *iwpd = to_iwpd(pd);
  2292. int status;
  2293. struct irdma_cqp_request *cqp_request;
  2294. struct cqp_cmds_info *cqp_info;
  2295. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  2296. if (!cqp_request)
  2297. return -ENOMEM;
  2298. cqp_info = &cqp_request->info;
  2299. info = &cqp_info->in.u.alloc_stag.info;
  2300. memset(info, 0, sizeof(*info));
  2301. info->page_size = PAGE_SIZE;
  2302. info->stag_idx = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S;
  2303. info->pd_id = iwpd->sc_pd.pd_id;
  2304. info->total_len = iwmr->len;
  2305. info->all_memory = pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY;
  2306. info->remote_access = true;
  2307. cqp_info->cqp_cmd = IRDMA_OP_ALLOC_STAG;
  2308. cqp_info->post_sq = 1;
  2309. cqp_info->in.u.alloc_stag.dev = &iwdev->rf->sc_dev;
  2310. cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
  2311. status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
  2312. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  2313. if (status)
  2314. return status;
  2315. iwmr->is_hwreg = 1;
  2316. return 0;
  2317. }
  2318. /**
  2319. * irdma_alloc_mr - register stag for fast memory registration
  2320. * @pd: ibpd pointer
  2321. * @mr_type: memory for stag registrion
  2322. * @max_num_sg: man number of pages
  2323. */
  2324. static struct ib_mr *irdma_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
  2325. u32 max_num_sg)
  2326. {
  2327. struct irdma_device *iwdev = to_iwdev(pd->device);
  2328. struct irdma_pble_alloc *palloc;
  2329. struct irdma_pbl *iwpbl;
  2330. struct irdma_mr *iwmr;
  2331. u32 stag;
  2332. int err_code;
  2333. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  2334. if (!iwmr)
  2335. return ERR_PTR(-ENOMEM);
  2336. stag = irdma_create_stag(iwdev);
  2337. if (!stag) {
  2338. err_code = -ENOMEM;
  2339. goto err;
  2340. }
  2341. iwmr->stag = stag;
  2342. iwmr->ibmr.rkey = stag;
  2343. iwmr->ibmr.lkey = stag;
  2344. iwmr->ibmr.pd = pd;
  2345. iwmr->ibmr.device = pd->device;
  2346. iwpbl = &iwmr->iwpbl;
  2347. iwpbl->iwmr = iwmr;
  2348. iwmr->type = IRDMA_MEMREG_TYPE_MEM;
  2349. palloc = &iwpbl->pble_alloc;
  2350. iwmr->page_cnt = max_num_sg;
  2351. /* Use system PAGE_SIZE as the sg page sizes are unknown at this point */
  2352. iwmr->len = max_num_sg * PAGE_SIZE;
  2353. err_code = irdma_get_pble(iwdev->rf->pble_rsrc, palloc, iwmr->page_cnt,
  2354. false);
  2355. if (err_code)
  2356. goto err_get_pble;
  2357. err_code = irdma_hw_alloc_stag(iwdev, iwmr);
  2358. if (err_code)
  2359. goto err_alloc_stag;
  2360. iwpbl->pbl_allocated = true;
  2361. return &iwmr->ibmr;
  2362. err_alloc_stag:
  2363. irdma_free_pble(iwdev->rf->pble_rsrc, palloc);
  2364. err_get_pble:
  2365. irdma_free_stag(iwdev, stag);
  2366. err:
  2367. kfree(iwmr);
  2368. return ERR_PTR(err_code);
  2369. }
  2370. /**
  2371. * irdma_set_page - populate pbl list for fmr
  2372. * @ibmr: ib mem to access iwarp mr pointer
  2373. * @addr: page dma address fro pbl list
  2374. */
  2375. static int irdma_set_page(struct ib_mr *ibmr, u64 addr)
  2376. {
  2377. struct irdma_mr *iwmr = to_iwmr(ibmr);
  2378. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2379. struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
  2380. u64 *pbl;
  2381. if (unlikely(iwmr->npages == iwmr->page_cnt))
  2382. return -ENOMEM;
  2383. if (palloc->level == PBLE_LEVEL_2) {
  2384. struct irdma_pble_info *palloc_info =
  2385. palloc->level2.leaf + (iwmr->npages >> PBLE_512_SHIFT);
  2386. palloc_info->addr[iwmr->npages & (PBLE_PER_PAGE - 1)] = addr;
  2387. } else {
  2388. pbl = palloc->level1.addr;
  2389. pbl[iwmr->npages] = addr;
  2390. }
  2391. iwmr->npages++;
  2392. return 0;
  2393. }
  2394. /**
  2395. * irdma_map_mr_sg - map of sg list for fmr
  2396. * @ibmr: ib mem to access iwarp mr pointer
  2397. * @sg: scatter gather list
  2398. * @sg_nents: number of sg pages
  2399. * @sg_offset: scatter gather list for fmr
  2400. */
  2401. static int irdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
  2402. int sg_nents, unsigned int *sg_offset)
  2403. {
  2404. struct irdma_mr *iwmr = to_iwmr(ibmr);
  2405. iwmr->npages = 0;
  2406. return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, irdma_set_page);
  2407. }
  2408. /**
  2409. * irdma_hwreg_mr - send cqp command for memory registration
  2410. * @iwdev: irdma device
  2411. * @iwmr: irdma mr pointer
  2412. * @access: access for MR
  2413. */
  2414. static int irdma_hwreg_mr(struct irdma_device *iwdev, struct irdma_mr *iwmr,
  2415. u16 access)
  2416. {
  2417. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2418. struct irdma_reg_ns_stag_info *stag_info;
  2419. struct ib_pd *pd = iwmr->ibmr.pd;
  2420. struct irdma_pd *iwpd = to_iwpd(pd);
  2421. struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
  2422. struct irdma_cqp_request *cqp_request;
  2423. struct cqp_cmds_info *cqp_info;
  2424. int ret;
  2425. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  2426. if (!cqp_request)
  2427. return -ENOMEM;
  2428. cqp_info = &cqp_request->info;
  2429. stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
  2430. memset(stag_info, 0, sizeof(*stag_info));
  2431. stag_info->va = iwpbl->user_base;
  2432. stag_info->stag_idx = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S;
  2433. stag_info->stag_key = (u8)iwmr->stag;
  2434. stag_info->total_len = iwmr->len;
  2435. stag_info->access_rights = irdma_get_mr_access(access);
  2436. stag_info->pd_id = iwpd->sc_pd.pd_id;
  2437. stag_info->all_memory = pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY;
  2438. if (stag_info->access_rights & IRDMA_ACCESS_FLAGS_ZERO_BASED)
  2439. stag_info->addr_type = IRDMA_ADDR_TYPE_ZERO_BASED;
  2440. else
  2441. stag_info->addr_type = IRDMA_ADDR_TYPE_VA_BASED;
  2442. stag_info->page_size = iwmr->page_size;
  2443. if (iwpbl->pbl_allocated) {
  2444. if (palloc->level == PBLE_LEVEL_1) {
  2445. stag_info->first_pm_pbl_index = palloc->level1.idx;
  2446. stag_info->chunk_size = 1;
  2447. } else {
  2448. stag_info->first_pm_pbl_index = palloc->level2.root.idx;
  2449. stag_info->chunk_size = 3;
  2450. }
  2451. } else {
  2452. stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
  2453. }
  2454. cqp_info->cqp_cmd = IRDMA_OP_MR_REG_NON_SHARED;
  2455. cqp_info->post_sq = 1;
  2456. cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->rf->sc_dev;
  2457. cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
  2458. ret = irdma_handle_cqp_op(iwdev->rf, cqp_request);
  2459. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  2460. if (!ret)
  2461. iwmr->is_hwreg = 1;
  2462. return ret;
  2463. }
  2464. static int irdma_reg_user_mr_type_mem(struct irdma_mr *iwmr, int access,
  2465. bool create_stag)
  2466. {
  2467. struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
  2468. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2469. u32 stag = 0;
  2470. u8 lvl;
  2471. int err;
  2472. lvl = iwmr->page_cnt != 1 ? PBLE_LEVEL_1 | PBLE_LEVEL_2 : PBLE_LEVEL_0;
  2473. err = irdma_setup_pbles(iwdev->rf, iwmr, lvl);
  2474. if (err)
  2475. return err;
  2476. if (lvl) {
  2477. err = irdma_check_mr_contiguous(&iwpbl->pble_alloc,
  2478. iwmr->page_size);
  2479. if (err) {
  2480. irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc);
  2481. iwpbl->pbl_allocated = false;
  2482. }
  2483. }
  2484. if (create_stag) {
  2485. stag = irdma_create_stag(iwdev);
  2486. if (!stag) {
  2487. err = -ENOMEM;
  2488. goto free_pble;
  2489. }
  2490. iwmr->stag = stag;
  2491. iwmr->ibmr.rkey = stag;
  2492. iwmr->ibmr.lkey = stag;
  2493. }
  2494. err = irdma_hwreg_mr(iwdev, iwmr, access);
  2495. if (err)
  2496. goto err_hwreg;
  2497. return 0;
  2498. err_hwreg:
  2499. if (stag)
  2500. irdma_free_stag(iwdev, stag);
  2501. free_pble:
  2502. if (iwpbl->pble_alloc.level != PBLE_LEVEL_0 && iwpbl->pbl_allocated)
  2503. irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc);
  2504. return err;
  2505. }
  2506. static struct irdma_mr *irdma_alloc_iwmr(struct ib_umem *region,
  2507. struct ib_pd *pd, u64 virt,
  2508. enum irdma_memreg_type reg_type)
  2509. {
  2510. struct irdma_device *iwdev = to_iwdev(pd->device);
  2511. struct irdma_pbl *iwpbl;
  2512. struct irdma_mr *iwmr;
  2513. unsigned long pgsz_bitmap;
  2514. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  2515. if (!iwmr)
  2516. return ERR_PTR(-ENOMEM);
  2517. iwpbl = &iwmr->iwpbl;
  2518. iwpbl->iwmr = iwmr;
  2519. iwmr->region = region;
  2520. iwmr->ibmr.pd = pd;
  2521. iwmr->ibmr.device = pd->device;
  2522. iwmr->ibmr.iova = virt;
  2523. iwmr->type = reg_type;
  2524. pgsz_bitmap = (reg_type == IRDMA_MEMREG_TYPE_MEM) ?
  2525. iwdev->rf->sc_dev.hw_attrs.page_size_cap : SZ_4K;
  2526. iwmr->page_size = ib_umem_find_best_pgsz(region, pgsz_bitmap, virt);
  2527. if (unlikely(!iwmr->page_size)) {
  2528. kfree(iwmr);
  2529. return ERR_PTR(-EOPNOTSUPP);
  2530. }
  2531. iwmr->len = region->length;
  2532. iwpbl->user_base = virt;
  2533. iwmr->page_cnt = ib_umem_num_dma_blocks(region, iwmr->page_size);
  2534. return iwmr;
  2535. }
  2536. static void irdma_free_iwmr(struct irdma_mr *iwmr)
  2537. {
  2538. kfree(iwmr);
  2539. }
  2540. static int irdma_reg_user_mr_type_qp(struct irdma_mem_reg_req req,
  2541. struct ib_udata *udata,
  2542. struct irdma_mr *iwmr)
  2543. {
  2544. struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
  2545. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2546. struct irdma_ucontext *ucontext = NULL;
  2547. unsigned long flags;
  2548. u32 total;
  2549. int err;
  2550. u8 lvl;
  2551. /* iWarp: Catch page not starting on OS page boundary */
  2552. if (!rdma_protocol_roce(&iwdev->ibdev, 1) &&
  2553. ib_umem_offset(iwmr->region))
  2554. return -EINVAL;
  2555. total = req.sq_pages + req.rq_pages + 1;
  2556. if (total > iwmr->page_cnt)
  2557. return -EINVAL;
  2558. total = req.sq_pages + req.rq_pages;
  2559. lvl = total > 2 ? PBLE_LEVEL_1 : PBLE_LEVEL_0;
  2560. err = irdma_handle_q_mem(iwdev, &req, iwpbl, lvl);
  2561. if (err)
  2562. return err;
  2563. ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext,
  2564. ibucontext);
  2565. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  2566. list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
  2567. iwpbl->on_list = true;
  2568. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  2569. return 0;
  2570. }
  2571. static int irdma_reg_user_mr_type_cq(struct irdma_mem_reg_req req,
  2572. struct ib_udata *udata,
  2573. struct irdma_mr *iwmr)
  2574. {
  2575. struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
  2576. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2577. struct irdma_ucontext *ucontext = NULL;
  2578. u8 shadow_pgcnt = 1;
  2579. unsigned long flags;
  2580. u32 total;
  2581. int err;
  2582. u8 lvl;
  2583. if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_CQ_RESIZE)
  2584. shadow_pgcnt = 0;
  2585. total = req.cq_pages + shadow_pgcnt;
  2586. if (total > iwmr->page_cnt)
  2587. return -EINVAL;
  2588. lvl = req.cq_pages > 1 ? PBLE_LEVEL_1 : PBLE_LEVEL_0;
  2589. err = irdma_handle_q_mem(iwdev, &req, iwpbl, lvl);
  2590. if (err)
  2591. return err;
  2592. ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext,
  2593. ibucontext);
  2594. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  2595. list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
  2596. iwpbl->on_list = true;
  2597. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  2598. return 0;
  2599. }
  2600. /**
  2601. * irdma_reg_user_mr - Register a user memory region
  2602. * @pd: ptr of pd
  2603. * @start: virtual start address
  2604. * @len: length of mr
  2605. * @virt: virtual address
  2606. * @access: access of mr
  2607. * @udata: user data
  2608. */
  2609. static struct ib_mr *irdma_reg_user_mr(struct ib_pd *pd, u64 start, u64 len,
  2610. u64 virt, int access,
  2611. struct ib_udata *udata)
  2612. {
  2613. #define IRDMA_MEM_REG_MIN_REQ_LEN offsetofend(struct irdma_mem_reg_req, sq_pages)
  2614. struct irdma_device *iwdev = to_iwdev(pd->device);
  2615. struct irdma_mem_reg_req req = {};
  2616. struct ib_umem *region = NULL;
  2617. struct irdma_mr *iwmr = NULL;
  2618. int err;
  2619. if (len > iwdev->rf->sc_dev.hw_attrs.max_mr_size)
  2620. return ERR_PTR(-EINVAL);
  2621. if (udata->inlen < IRDMA_MEM_REG_MIN_REQ_LEN)
  2622. return ERR_PTR(-EINVAL);
  2623. region = ib_umem_get(pd->device, start, len, access);
  2624. if (IS_ERR(region)) {
  2625. ibdev_dbg(&iwdev->ibdev,
  2626. "VERBS: Failed to create ib_umem region\n");
  2627. return (struct ib_mr *)region;
  2628. }
  2629. if (ib_copy_from_udata(&req, udata, min(sizeof(req), udata->inlen))) {
  2630. ib_umem_release(region);
  2631. return ERR_PTR(-EFAULT);
  2632. }
  2633. iwmr = irdma_alloc_iwmr(region, pd, virt, req.reg_type);
  2634. if (IS_ERR(iwmr)) {
  2635. ib_umem_release(region);
  2636. return (struct ib_mr *)iwmr;
  2637. }
  2638. switch (req.reg_type) {
  2639. case IRDMA_MEMREG_TYPE_QP:
  2640. err = irdma_reg_user_mr_type_qp(req, udata, iwmr);
  2641. if (err)
  2642. goto error;
  2643. break;
  2644. case IRDMA_MEMREG_TYPE_CQ:
  2645. err = irdma_reg_user_mr_type_cq(req, udata, iwmr);
  2646. if (err)
  2647. goto error;
  2648. break;
  2649. case IRDMA_MEMREG_TYPE_MEM:
  2650. err = irdma_reg_user_mr_type_mem(iwmr, access, true);
  2651. if (err)
  2652. goto error;
  2653. break;
  2654. default:
  2655. err = -EINVAL;
  2656. goto error;
  2657. }
  2658. return &iwmr->ibmr;
  2659. error:
  2660. ib_umem_release(region);
  2661. irdma_free_iwmr(iwmr);
  2662. return ERR_PTR(err);
  2663. }
  2664. static struct ib_mr *irdma_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start,
  2665. u64 len, u64 virt,
  2666. int fd, int access,
  2667. struct uverbs_attr_bundle *attrs)
  2668. {
  2669. struct irdma_device *iwdev = to_iwdev(pd->device);
  2670. struct ib_umem_dmabuf *umem_dmabuf;
  2671. struct irdma_mr *iwmr;
  2672. int err;
  2673. if (len > iwdev->rf->sc_dev.hw_attrs.max_mr_size)
  2674. return ERR_PTR(-EINVAL);
  2675. umem_dmabuf = ib_umem_dmabuf_get_pinned(pd->device, start, len, fd, access);
  2676. if (IS_ERR(umem_dmabuf)) {
  2677. err = PTR_ERR(umem_dmabuf);
  2678. ibdev_dbg(&iwdev->ibdev, "Failed to get dmabuf umem[%d]\n", err);
  2679. return ERR_PTR(err);
  2680. }
  2681. iwmr = irdma_alloc_iwmr(&umem_dmabuf->umem, pd, virt, IRDMA_MEMREG_TYPE_MEM);
  2682. if (IS_ERR(iwmr)) {
  2683. err = PTR_ERR(iwmr);
  2684. goto err_release;
  2685. }
  2686. err = irdma_reg_user_mr_type_mem(iwmr, access, true);
  2687. if (err)
  2688. goto err_iwmr;
  2689. return &iwmr->ibmr;
  2690. err_iwmr:
  2691. irdma_free_iwmr(iwmr);
  2692. err_release:
  2693. ib_umem_release(&umem_dmabuf->umem);
  2694. return ERR_PTR(err);
  2695. }
  2696. static int irdma_hwdereg_mr(struct ib_mr *ib_mr)
  2697. {
  2698. struct irdma_device *iwdev = to_iwdev(ib_mr->device);
  2699. struct irdma_mr *iwmr = to_iwmr(ib_mr);
  2700. struct irdma_pd *iwpd = to_iwpd(ib_mr->pd);
  2701. struct irdma_dealloc_stag_info *info;
  2702. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2703. struct irdma_cqp_request *cqp_request;
  2704. struct cqp_cmds_info *cqp_info;
  2705. int status;
  2706. /* Skip HW MR de-register when it is already de-registered
  2707. * during an MR re-reregister and the re-registration fails
  2708. */
  2709. if (!iwmr->is_hwreg)
  2710. return 0;
  2711. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  2712. if (!cqp_request)
  2713. return -ENOMEM;
  2714. cqp_info = &cqp_request->info;
  2715. info = &cqp_info->in.u.dealloc_stag.info;
  2716. memset(info, 0, sizeof(*info));
  2717. info->pd_id = iwpd->sc_pd.pd_id;
  2718. info->stag_idx = ib_mr->rkey >> IRDMA_CQPSQ_STAG_IDX_S;
  2719. info->mr = true;
  2720. if (iwpbl->pbl_allocated)
  2721. info->dealloc_pbl = true;
  2722. cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG;
  2723. cqp_info->post_sq = 1;
  2724. cqp_info->in.u.dealloc_stag.dev = &iwdev->rf->sc_dev;
  2725. cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
  2726. status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
  2727. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  2728. if (status)
  2729. return status;
  2730. iwmr->is_hwreg = 0;
  2731. return 0;
  2732. }
  2733. /*
  2734. * irdma_rereg_mr_trans - Re-register a user MR for a change translation.
  2735. * @iwmr: ptr of iwmr
  2736. * @start: virtual start address
  2737. * @len: length of mr
  2738. * @virt: virtual address
  2739. *
  2740. * Re-register a user memory region when a change translation is requested.
  2741. * Re-register a new region while reusing the stag from the original registration.
  2742. */
  2743. static int irdma_rereg_mr_trans(struct irdma_mr *iwmr, u64 start, u64 len,
  2744. u64 virt)
  2745. {
  2746. struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
  2747. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2748. struct ib_pd *pd = iwmr->ibmr.pd;
  2749. struct ib_umem *region;
  2750. int err;
  2751. region = ib_umem_get(pd->device, start, len, iwmr->access);
  2752. if (IS_ERR(region))
  2753. return PTR_ERR(region);
  2754. iwmr->region = region;
  2755. iwmr->ibmr.iova = virt;
  2756. iwmr->ibmr.pd = pd;
  2757. iwmr->page_size = ib_umem_find_best_pgsz(region,
  2758. iwdev->rf->sc_dev.hw_attrs.page_size_cap,
  2759. virt);
  2760. if (unlikely(!iwmr->page_size)) {
  2761. err = -EOPNOTSUPP;
  2762. goto err;
  2763. }
  2764. iwmr->len = region->length;
  2765. iwpbl->user_base = virt;
  2766. iwmr->page_cnt = ib_umem_num_dma_blocks(region, iwmr->page_size);
  2767. err = irdma_reg_user_mr_type_mem(iwmr, iwmr->access, false);
  2768. if (err)
  2769. goto err;
  2770. return 0;
  2771. err:
  2772. ib_umem_release(region);
  2773. return err;
  2774. }
  2775. /*
  2776. * irdma_rereg_user_mr - Re-Register a user memory region(MR)
  2777. * @ibmr: ib mem to access iwarp mr pointer
  2778. * @flags: bit mask to indicate which of the attr's of MR modified
  2779. * @start: virtual start address
  2780. * @len: length of mr
  2781. * @virt: virtual address
  2782. * @new_access: bit mask of access flags
  2783. * @new_pd: ptr of pd
  2784. * @udata: user data
  2785. *
  2786. * Return:
  2787. * NULL - Success, existing MR updated
  2788. * ERR_PTR - error occurred
  2789. */
  2790. static struct ib_mr *irdma_rereg_user_mr(struct ib_mr *ib_mr, int flags,
  2791. u64 start, u64 len, u64 virt,
  2792. int new_access, struct ib_pd *new_pd,
  2793. struct ib_udata *udata)
  2794. {
  2795. struct irdma_device *iwdev = to_iwdev(ib_mr->device);
  2796. struct irdma_mr *iwmr = to_iwmr(ib_mr);
  2797. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2798. int ret;
  2799. if (len > iwdev->rf->sc_dev.hw_attrs.max_mr_size)
  2800. return ERR_PTR(-EINVAL);
  2801. if (flags & ~(IB_MR_REREG_TRANS | IB_MR_REREG_PD | IB_MR_REREG_ACCESS))
  2802. return ERR_PTR(-EOPNOTSUPP);
  2803. ret = irdma_hwdereg_mr(ib_mr);
  2804. if (ret)
  2805. return ERR_PTR(ret);
  2806. if (flags & IB_MR_REREG_ACCESS)
  2807. iwmr->access = new_access;
  2808. if (flags & IB_MR_REREG_PD) {
  2809. iwmr->ibmr.pd = new_pd;
  2810. iwmr->ibmr.device = new_pd->device;
  2811. }
  2812. if (flags & IB_MR_REREG_TRANS) {
  2813. if (iwpbl->pbl_allocated) {
  2814. irdma_free_pble(iwdev->rf->pble_rsrc,
  2815. &iwpbl->pble_alloc);
  2816. iwpbl->pbl_allocated = false;
  2817. }
  2818. if (iwmr->region) {
  2819. ib_umem_release(iwmr->region);
  2820. iwmr->region = NULL;
  2821. }
  2822. ret = irdma_rereg_mr_trans(iwmr, start, len, virt);
  2823. } else
  2824. ret = irdma_hwreg_mr(iwdev, iwmr, iwmr->access);
  2825. if (ret)
  2826. return ERR_PTR(ret);
  2827. return NULL;
  2828. }
  2829. /**
  2830. * irdma_reg_phys_mr - register kernel physical memory
  2831. * @pd: ibpd pointer
  2832. * @addr: physical address of memory to register
  2833. * @size: size of memory to register
  2834. * @access: Access rights
  2835. * @iova_start: start of virtual address for physical buffers
  2836. */
  2837. struct ib_mr *irdma_reg_phys_mr(struct ib_pd *pd, u64 addr, u64 size, int access,
  2838. u64 *iova_start)
  2839. {
  2840. struct irdma_device *iwdev = to_iwdev(pd->device);
  2841. struct irdma_pbl *iwpbl;
  2842. struct irdma_mr *iwmr;
  2843. u32 stag;
  2844. int ret;
  2845. iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL);
  2846. if (!iwmr)
  2847. return ERR_PTR(-ENOMEM);
  2848. iwmr->ibmr.pd = pd;
  2849. iwmr->ibmr.device = pd->device;
  2850. iwpbl = &iwmr->iwpbl;
  2851. iwpbl->iwmr = iwmr;
  2852. iwmr->type = IRDMA_MEMREG_TYPE_MEM;
  2853. iwpbl->user_base = *iova_start;
  2854. stag = irdma_create_stag(iwdev);
  2855. if (!stag) {
  2856. ret = -ENOMEM;
  2857. goto err;
  2858. }
  2859. iwmr->stag = stag;
  2860. iwmr->ibmr.iova = *iova_start;
  2861. iwmr->ibmr.rkey = stag;
  2862. iwmr->ibmr.lkey = stag;
  2863. iwmr->page_cnt = 1;
  2864. iwmr->pgaddrmem[0] = addr;
  2865. iwmr->len = size;
  2866. iwmr->page_size = SZ_4K;
  2867. ret = irdma_hwreg_mr(iwdev, iwmr, access);
  2868. if (ret) {
  2869. irdma_free_stag(iwdev, stag);
  2870. goto err;
  2871. }
  2872. return &iwmr->ibmr;
  2873. err:
  2874. kfree(iwmr);
  2875. return ERR_PTR(ret);
  2876. }
  2877. /**
  2878. * irdma_get_dma_mr - register physical mem
  2879. * @pd: ptr of pd
  2880. * @acc: access for memory
  2881. */
  2882. static struct ib_mr *irdma_get_dma_mr(struct ib_pd *pd, int acc)
  2883. {
  2884. u64 kva = 0;
  2885. return irdma_reg_phys_mr(pd, 0, 0, acc, &kva);
  2886. }
  2887. /**
  2888. * irdma_del_memlist - Deleting pbl list entries for CQ/QP
  2889. * @iwmr: iwmr for IB's user page addresses
  2890. * @ucontext: ptr to user context
  2891. */
  2892. static void irdma_del_memlist(struct irdma_mr *iwmr,
  2893. struct irdma_ucontext *ucontext)
  2894. {
  2895. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2896. unsigned long flags;
  2897. switch (iwmr->type) {
  2898. case IRDMA_MEMREG_TYPE_CQ:
  2899. spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
  2900. if (iwpbl->on_list) {
  2901. iwpbl->on_list = false;
  2902. list_del(&iwpbl->list);
  2903. }
  2904. spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
  2905. break;
  2906. case IRDMA_MEMREG_TYPE_QP:
  2907. spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
  2908. if (iwpbl->on_list) {
  2909. iwpbl->on_list = false;
  2910. list_del(&iwpbl->list);
  2911. }
  2912. spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
  2913. break;
  2914. default:
  2915. break;
  2916. }
  2917. }
  2918. /**
  2919. * irdma_dereg_mr - deregister mr
  2920. * @ib_mr: mr ptr for dereg
  2921. * @udata: user data
  2922. */
  2923. static int irdma_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
  2924. {
  2925. struct irdma_mr *iwmr = to_iwmr(ib_mr);
  2926. struct irdma_device *iwdev = to_iwdev(ib_mr->device);
  2927. struct irdma_pbl *iwpbl = &iwmr->iwpbl;
  2928. int ret;
  2929. if (iwmr->type != IRDMA_MEMREG_TYPE_MEM) {
  2930. if (iwmr->region) {
  2931. struct irdma_ucontext *ucontext;
  2932. ucontext = rdma_udata_to_drv_context(udata,
  2933. struct irdma_ucontext,
  2934. ibucontext);
  2935. irdma_del_memlist(iwmr, ucontext);
  2936. }
  2937. goto done;
  2938. }
  2939. ret = irdma_hwdereg_mr(ib_mr);
  2940. if (ret)
  2941. return ret;
  2942. irdma_free_stag(iwdev, iwmr->stag);
  2943. done:
  2944. if (iwpbl->pbl_allocated)
  2945. irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc);
  2946. if (iwmr->region)
  2947. ib_umem_release(iwmr->region);
  2948. kfree(iwmr);
  2949. return 0;
  2950. }
  2951. /**
  2952. * irdma_post_send - kernel application wr
  2953. * @ibqp: qp ptr for wr
  2954. * @ib_wr: work request ptr
  2955. * @bad_wr: return of bad wr if err
  2956. */
  2957. static int irdma_post_send(struct ib_qp *ibqp,
  2958. const struct ib_send_wr *ib_wr,
  2959. const struct ib_send_wr **bad_wr)
  2960. {
  2961. struct irdma_qp *iwqp;
  2962. struct irdma_qp_uk *ukqp;
  2963. struct irdma_sc_dev *dev;
  2964. struct irdma_post_sq_info info;
  2965. int err = 0;
  2966. unsigned long flags;
  2967. bool inv_stag;
  2968. struct irdma_ah *ah;
  2969. iwqp = to_iwqp(ibqp);
  2970. ukqp = &iwqp->sc_qp.qp_uk;
  2971. dev = &iwqp->iwdev->rf->sc_dev;
  2972. spin_lock_irqsave(&iwqp->lock, flags);
  2973. while (ib_wr) {
  2974. memset(&info, 0, sizeof(info));
  2975. inv_stag = false;
  2976. info.wr_id = (ib_wr->wr_id);
  2977. if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
  2978. info.signaled = true;
  2979. if (ib_wr->send_flags & IB_SEND_FENCE)
  2980. info.read_fence = true;
  2981. switch (ib_wr->opcode) {
  2982. case IB_WR_SEND_WITH_IMM:
  2983. if (ukqp->qp_caps & IRDMA_SEND_WITH_IMM) {
  2984. info.imm_data_valid = true;
  2985. info.imm_data = ntohl(ib_wr->ex.imm_data);
  2986. } else {
  2987. err = -EINVAL;
  2988. break;
  2989. }
  2990. fallthrough;
  2991. case IB_WR_SEND:
  2992. case IB_WR_SEND_WITH_INV:
  2993. if (ib_wr->opcode == IB_WR_SEND ||
  2994. ib_wr->opcode == IB_WR_SEND_WITH_IMM) {
  2995. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  2996. info.op_type = IRDMA_OP_TYPE_SEND_SOL;
  2997. else
  2998. info.op_type = IRDMA_OP_TYPE_SEND;
  2999. } else {
  3000. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  3001. info.op_type = IRDMA_OP_TYPE_SEND_SOL_INV;
  3002. else
  3003. info.op_type = IRDMA_OP_TYPE_SEND_INV;
  3004. info.stag_to_inv = ib_wr->ex.invalidate_rkey;
  3005. }
  3006. info.op.send.num_sges = ib_wr->num_sge;
  3007. info.op.send.sg_list = ib_wr->sg_list;
  3008. if (iwqp->ibqp.qp_type == IB_QPT_UD ||
  3009. iwqp->ibqp.qp_type == IB_QPT_GSI) {
  3010. ah = to_iwah(ud_wr(ib_wr)->ah);
  3011. info.op.send.ah_id = ah->sc_ah.ah_info.ah_idx;
  3012. info.op.send.qkey = ud_wr(ib_wr)->remote_qkey;
  3013. info.op.send.dest_qp = ud_wr(ib_wr)->remote_qpn;
  3014. }
  3015. if (ib_wr->send_flags & IB_SEND_INLINE)
  3016. err = irdma_uk_inline_send(ukqp, &info, false);
  3017. else
  3018. err = irdma_uk_send(ukqp, &info, false);
  3019. break;
  3020. case IB_WR_RDMA_WRITE_WITH_IMM:
  3021. if (ukqp->qp_caps & IRDMA_WRITE_WITH_IMM) {
  3022. info.imm_data_valid = true;
  3023. info.imm_data = ntohl(ib_wr->ex.imm_data);
  3024. } else {
  3025. err = -EINVAL;
  3026. break;
  3027. }
  3028. fallthrough;
  3029. case IB_WR_RDMA_WRITE:
  3030. if (ib_wr->send_flags & IB_SEND_SOLICITED)
  3031. info.op_type = IRDMA_OP_TYPE_RDMA_WRITE_SOL;
  3032. else
  3033. info.op_type = IRDMA_OP_TYPE_RDMA_WRITE;
  3034. info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
  3035. info.op.rdma_write.lo_sg_list = ib_wr->sg_list;
  3036. info.op.rdma_write.rem_addr.addr =
  3037. rdma_wr(ib_wr)->remote_addr;
  3038. info.op.rdma_write.rem_addr.lkey = rdma_wr(ib_wr)->rkey;
  3039. if (ib_wr->send_flags & IB_SEND_INLINE)
  3040. err = irdma_uk_inline_rdma_write(ukqp, &info, false);
  3041. else
  3042. err = irdma_uk_rdma_write(ukqp, &info, false);
  3043. break;
  3044. case IB_WR_RDMA_READ_WITH_INV:
  3045. inv_stag = true;
  3046. fallthrough;
  3047. case IB_WR_RDMA_READ:
  3048. if (ib_wr->num_sge >
  3049. dev->hw_attrs.uk_attrs.max_hw_read_sges) {
  3050. err = -EINVAL;
  3051. break;
  3052. }
  3053. info.op_type = IRDMA_OP_TYPE_RDMA_READ;
  3054. info.op.rdma_read.rem_addr.addr = rdma_wr(ib_wr)->remote_addr;
  3055. info.op.rdma_read.rem_addr.lkey = rdma_wr(ib_wr)->rkey;
  3056. info.op.rdma_read.lo_sg_list = (void *)ib_wr->sg_list;
  3057. info.op.rdma_read.num_lo_sges = ib_wr->num_sge;
  3058. err = irdma_uk_rdma_read(ukqp, &info, inv_stag, false);
  3059. break;
  3060. case IB_WR_LOCAL_INV:
  3061. info.op_type = IRDMA_OP_TYPE_INV_STAG;
  3062. info.local_fence = info.read_fence;
  3063. info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
  3064. err = irdma_uk_stag_local_invalidate(ukqp, &info, true);
  3065. break;
  3066. case IB_WR_REG_MR: {
  3067. struct irdma_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
  3068. struct irdma_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
  3069. struct irdma_fast_reg_stag_info stag_info = {};
  3070. stag_info.signaled = info.signaled;
  3071. stag_info.read_fence = info.read_fence;
  3072. stag_info.access_rights = irdma_get_mr_access(reg_wr(ib_wr)->access);
  3073. stag_info.stag_key = reg_wr(ib_wr)->key & 0xff;
  3074. stag_info.stag_idx = reg_wr(ib_wr)->key >> 8;
  3075. stag_info.page_size = reg_wr(ib_wr)->mr->page_size;
  3076. stag_info.wr_id = ib_wr->wr_id;
  3077. stag_info.addr_type = IRDMA_ADDR_TYPE_VA_BASED;
  3078. stag_info.va = (void *)(uintptr_t)iwmr->ibmr.iova;
  3079. stag_info.total_len = iwmr->ibmr.length;
  3080. stag_info.reg_addr_pa = *palloc->level1.addr;
  3081. stag_info.first_pm_pbl_index = palloc->level1.idx;
  3082. stag_info.local_fence = ib_wr->send_flags & IB_SEND_FENCE;
  3083. if (iwmr->npages > IRDMA_MIN_PAGES_PER_FMR)
  3084. stag_info.chunk_size = 1;
  3085. err = irdma_sc_mr_fast_register(&iwqp->sc_qp, &stag_info,
  3086. true);
  3087. break;
  3088. }
  3089. default:
  3090. err = -EINVAL;
  3091. ibdev_dbg(&iwqp->iwdev->ibdev,
  3092. "VERBS: upost_send bad opcode = 0x%x\n",
  3093. ib_wr->opcode);
  3094. break;
  3095. }
  3096. if (err)
  3097. break;
  3098. ib_wr = ib_wr->next;
  3099. }
  3100. if (!iwqp->flush_issued) {
  3101. if (iwqp->hw_iwarp_state <= IRDMA_QP_STATE_RTS)
  3102. irdma_uk_qp_post_wr(ukqp);
  3103. spin_unlock_irqrestore(&iwqp->lock, flags);
  3104. } else {
  3105. spin_unlock_irqrestore(&iwqp->lock, flags);
  3106. mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush,
  3107. msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
  3108. }
  3109. if (err)
  3110. *bad_wr = ib_wr;
  3111. return err;
  3112. }
  3113. /**
  3114. * irdma_post_recv - post receive wr for kernel application
  3115. * @ibqp: ib qp pointer
  3116. * @ib_wr: work request for receive
  3117. * @bad_wr: bad wr caused an error
  3118. */
  3119. static int irdma_post_recv(struct ib_qp *ibqp,
  3120. const struct ib_recv_wr *ib_wr,
  3121. const struct ib_recv_wr **bad_wr)
  3122. {
  3123. struct irdma_qp *iwqp;
  3124. struct irdma_qp_uk *ukqp;
  3125. struct irdma_post_rq_info post_recv = {};
  3126. unsigned long flags;
  3127. int err = 0;
  3128. iwqp = to_iwqp(ibqp);
  3129. ukqp = &iwqp->sc_qp.qp_uk;
  3130. spin_lock_irqsave(&iwqp->lock, flags);
  3131. while (ib_wr) {
  3132. post_recv.num_sges = ib_wr->num_sge;
  3133. post_recv.wr_id = ib_wr->wr_id;
  3134. post_recv.sg_list = ib_wr->sg_list;
  3135. err = irdma_uk_post_receive(ukqp, &post_recv);
  3136. if (err) {
  3137. ibdev_dbg(&iwqp->iwdev->ibdev,
  3138. "VERBS: post_recv err %d\n", err);
  3139. goto out;
  3140. }
  3141. ib_wr = ib_wr->next;
  3142. }
  3143. out:
  3144. spin_unlock_irqrestore(&iwqp->lock, flags);
  3145. if (iwqp->flush_issued)
  3146. mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush,
  3147. msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
  3148. if (err)
  3149. *bad_wr = ib_wr;
  3150. return err;
  3151. }
  3152. /**
  3153. * irdma_flush_err_to_ib_wc_status - return change flush error code to IB status
  3154. * @opcode: iwarp flush code
  3155. */
  3156. static enum ib_wc_status irdma_flush_err_to_ib_wc_status(enum irdma_flush_opcode opcode)
  3157. {
  3158. switch (opcode) {
  3159. case FLUSH_PROT_ERR:
  3160. return IB_WC_LOC_PROT_ERR;
  3161. case FLUSH_REM_ACCESS_ERR:
  3162. return IB_WC_REM_ACCESS_ERR;
  3163. case FLUSH_LOC_QP_OP_ERR:
  3164. return IB_WC_LOC_QP_OP_ERR;
  3165. case FLUSH_REM_OP_ERR:
  3166. return IB_WC_REM_OP_ERR;
  3167. case FLUSH_LOC_LEN_ERR:
  3168. return IB_WC_LOC_LEN_ERR;
  3169. case FLUSH_GENERAL_ERR:
  3170. return IB_WC_WR_FLUSH_ERR;
  3171. case FLUSH_RETRY_EXC_ERR:
  3172. return IB_WC_RETRY_EXC_ERR;
  3173. case FLUSH_MW_BIND_ERR:
  3174. return IB_WC_MW_BIND_ERR;
  3175. case FLUSH_REM_INV_REQ_ERR:
  3176. return IB_WC_REM_INV_REQ_ERR;
  3177. case FLUSH_FATAL_ERR:
  3178. default:
  3179. return IB_WC_FATAL_ERR;
  3180. }
  3181. }
  3182. /**
  3183. * irdma_process_cqe - process cqe info
  3184. * @entry: processed cqe
  3185. * @cq_poll_info: cqe info
  3186. */
  3187. static void irdma_process_cqe(struct ib_wc *entry,
  3188. struct irdma_cq_poll_info *cq_poll_info)
  3189. {
  3190. struct irdma_sc_qp *qp;
  3191. entry->wc_flags = 0;
  3192. entry->pkey_index = 0;
  3193. entry->wr_id = cq_poll_info->wr_id;
  3194. qp = cq_poll_info->qp_handle;
  3195. entry->qp = qp->qp_uk.back_qp;
  3196. if (cq_poll_info->error) {
  3197. entry->status = (cq_poll_info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) ?
  3198. irdma_flush_err_to_ib_wc_status(cq_poll_info->minor_err) : IB_WC_GENERAL_ERR;
  3199. entry->vendor_err = cq_poll_info->major_err << 16 |
  3200. cq_poll_info->minor_err;
  3201. } else {
  3202. entry->status = IB_WC_SUCCESS;
  3203. if (cq_poll_info->imm_valid) {
  3204. entry->ex.imm_data = htonl(cq_poll_info->imm_data);
  3205. entry->wc_flags |= IB_WC_WITH_IMM;
  3206. }
  3207. if (cq_poll_info->ud_smac_valid) {
  3208. ether_addr_copy(entry->smac, cq_poll_info->ud_smac);
  3209. entry->wc_flags |= IB_WC_WITH_SMAC;
  3210. }
  3211. if (cq_poll_info->ud_vlan_valid) {
  3212. u16 vlan = cq_poll_info->ud_vlan & VLAN_VID_MASK;
  3213. entry->sl = cq_poll_info->ud_vlan >> VLAN_PRIO_SHIFT;
  3214. if (vlan) {
  3215. entry->vlan_id = vlan;
  3216. entry->wc_flags |= IB_WC_WITH_VLAN;
  3217. }
  3218. } else {
  3219. entry->sl = 0;
  3220. }
  3221. }
  3222. if (cq_poll_info->q_type == IRDMA_CQE_QTYPE_SQ) {
  3223. set_ib_wc_op_sq(cq_poll_info, entry);
  3224. } else {
  3225. set_ib_wc_op_rq(cq_poll_info, entry,
  3226. qp->qp_uk.qp_caps & IRDMA_SEND_WITH_IMM);
  3227. if (qp->qp_uk.qp_type != IRDMA_QP_TYPE_ROCE_UD &&
  3228. cq_poll_info->stag_invalid_set) {
  3229. entry->ex.invalidate_rkey = cq_poll_info->inv_stag;
  3230. entry->wc_flags |= IB_WC_WITH_INVALIDATE;
  3231. }
  3232. }
  3233. if (qp->qp_uk.qp_type == IRDMA_QP_TYPE_ROCE_UD) {
  3234. entry->src_qp = cq_poll_info->ud_src_qpn;
  3235. entry->slid = 0;
  3236. entry->wc_flags |=
  3237. (IB_WC_GRH | IB_WC_WITH_NETWORK_HDR_TYPE);
  3238. entry->network_hdr_type = cq_poll_info->ipv4 ?
  3239. RDMA_NETWORK_IPV4 :
  3240. RDMA_NETWORK_IPV6;
  3241. } else {
  3242. entry->src_qp = cq_poll_info->qp_id;
  3243. }
  3244. entry->byte_len = cq_poll_info->bytes_xfered;
  3245. }
  3246. /**
  3247. * irdma_poll_one - poll one entry of the CQ
  3248. * @ukcq: ukcq to poll
  3249. * @cur_cqe: current CQE info to be filled in
  3250. * @entry: ibv_wc object to be filled for non-extended CQ or NULL for extended CQ
  3251. *
  3252. * Returns the internal irdma device error code or 0 on success
  3253. */
  3254. static inline int irdma_poll_one(struct irdma_cq_uk *ukcq,
  3255. struct irdma_cq_poll_info *cur_cqe,
  3256. struct ib_wc *entry)
  3257. {
  3258. int ret = irdma_uk_cq_poll_cmpl(ukcq, cur_cqe);
  3259. if (ret)
  3260. return ret;
  3261. irdma_process_cqe(entry, cur_cqe);
  3262. return 0;
  3263. }
  3264. /**
  3265. * __irdma_poll_cq - poll cq for completion (kernel apps)
  3266. * @iwcq: cq to poll
  3267. * @num_entries: number of entries to poll
  3268. * @entry: wr of a completed entry
  3269. */
  3270. static int __irdma_poll_cq(struct irdma_cq *iwcq, int num_entries, struct ib_wc *entry)
  3271. {
  3272. struct list_head *tmp_node, *list_node;
  3273. struct irdma_cq_buf *last_buf = NULL;
  3274. struct irdma_cq_poll_info *cur_cqe = &iwcq->cur_cqe;
  3275. struct irdma_cq_buf *cq_buf;
  3276. int ret;
  3277. struct irdma_device *iwdev;
  3278. struct irdma_cq_uk *ukcq;
  3279. bool cq_new_cqe = false;
  3280. int resized_bufs = 0;
  3281. int npolled = 0;
  3282. iwdev = to_iwdev(iwcq->ibcq.device);
  3283. ukcq = &iwcq->sc_cq.cq_uk;
  3284. /* go through the list of previously resized CQ buffers */
  3285. list_for_each_safe(list_node, tmp_node, &iwcq->resize_list) {
  3286. cq_buf = container_of(list_node, struct irdma_cq_buf, list);
  3287. while (npolled < num_entries) {
  3288. ret = irdma_poll_one(&cq_buf->cq_uk, cur_cqe, entry + npolled);
  3289. if (!ret) {
  3290. ++npolled;
  3291. cq_new_cqe = true;
  3292. continue;
  3293. }
  3294. if (ret == -ENOENT)
  3295. break;
  3296. /* QP using the CQ is destroyed. Skip reporting this CQE */
  3297. if (ret == -EFAULT) {
  3298. cq_new_cqe = true;
  3299. continue;
  3300. }
  3301. goto error;
  3302. }
  3303. /* save the resized CQ buffer which received the last cqe */
  3304. if (cq_new_cqe)
  3305. last_buf = cq_buf;
  3306. cq_new_cqe = false;
  3307. }
  3308. /* check the current CQ for new cqes */
  3309. while (npolled < num_entries) {
  3310. ret = irdma_poll_one(ukcq, cur_cqe, entry + npolled);
  3311. if (ret == -ENOENT) {
  3312. ret = irdma_generated_cmpls(iwcq, cur_cqe);
  3313. if (!ret)
  3314. irdma_process_cqe(entry + npolled, cur_cqe);
  3315. }
  3316. if (!ret) {
  3317. ++npolled;
  3318. cq_new_cqe = true;
  3319. continue;
  3320. }
  3321. if (ret == -ENOENT)
  3322. break;
  3323. /* QP using the CQ is destroyed. Skip reporting this CQE */
  3324. if (ret == -EFAULT) {
  3325. cq_new_cqe = true;
  3326. continue;
  3327. }
  3328. goto error;
  3329. }
  3330. if (cq_new_cqe)
  3331. /* all previous CQ resizes are complete */
  3332. resized_bufs = irdma_process_resize_list(iwcq, iwdev, NULL);
  3333. else if (last_buf)
  3334. /* only CQ resizes up to the last_buf are complete */
  3335. resized_bufs = irdma_process_resize_list(iwcq, iwdev, last_buf);
  3336. if (resized_bufs)
  3337. /* report to the HW the number of complete CQ resizes */
  3338. irdma_uk_cq_set_resized_cnt(ukcq, resized_bufs);
  3339. return npolled;
  3340. error:
  3341. ibdev_dbg(&iwdev->ibdev, "%s: Error polling CQ, irdma_err: %d\n",
  3342. __func__, ret);
  3343. return ret;
  3344. }
  3345. /**
  3346. * irdma_poll_cq - poll cq for completion (kernel apps)
  3347. * @ibcq: cq to poll
  3348. * @num_entries: number of entries to poll
  3349. * @entry: wr of a completed entry
  3350. */
  3351. static int irdma_poll_cq(struct ib_cq *ibcq, int num_entries,
  3352. struct ib_wc *entry)
  3353. {
  3354. struct irdma_cq *iwcq;
  3355. unsigned long flags;
  3356. int ret;
  3357. iwcq = to_iwcq(ibcq);
  3358. spin_lock_irqsave(&iwcq->lock, flags);
  3359. ret = __irdma_poll_cq(iwcq, num_entries, entry);
  3360. spin_unlock_irqrestore(&iwcq->lock, flags);
  3361. return ret;
  3362. }
  3363. /**
  3364. * irdma_req_notify_cq - arm cq kernel application
  3365. * @ibcq: cq to arm
  3366. * @notify_flags: notofication flags
  3367. */
  3368. static int irdma_req_notify_cq(struct ib_cq *ibcq,
  3369. enum ib_cq_notify_flags notify_flags)
  3370. {
  3371. struct irdma_cq *iwcq;
  3372. struct irdma_cq_uk *ukcq;
  3373. unsigned long flags;
  3374. enum irdma_cmpl_notify cq_notify;
  3375. bool promo_event = false;
  3376. int ret = 0;
  3377. cq_notify = notify_flags == IB_CQ_SOLICITED ?
  3378. IRDMA_CQ_COMPL_SOLICITED : IRDMA_CQ_COMPL_EVENT;
  3379. iwcq = to_iwcq(ibcq);
  3380. ukcq = &iwcq->sc_cq.cq_uk;
  3381. spin_lock_irqsave(&iwcq->lock, flags);
  3382. /* Only promote to arm the CQ for any event if the last arm event was solicited. */
  3383. if (iwcq->last_notify == IRDMA_CQ_COMPL_SOLICITED && notify_flags != IB_CQ_SOLICITED)
  3384. promo_event = true;
  3385. if (!atomic_cmpxchg(&iwcq->armed, 0, 1) || promo_event) {
  3386. iwcq->last_notify = cq_notify;
  3387. irdma_uk_cq_request_notification(ukcq, cq_notify);
  3388. }
  3389. if ((notify_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
  3390. (!irdma_cq_empty(iwcq) || !list_empty(&iwcq->cmpl_generated)))
  3391. ret = 1;
  3392. spin_unlock_irqrestore(&iwcq->lock, flags);
  3393. return ret;
  3394. }
  3395. static int irdma_roce_port_immutable(struct ib_device *ibdev, u32 port_num,
  3396. struct ib_port_immutable *immutable)
  3397. {
  3398. struct ib_port_attr attr;
  3399. int err;
  3400. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  3401. err = ib_query_port(ibdev, port_num, &attr);
  3402. if (err)
  3403. return err;
  3404. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  3405. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  3406. immutable->gid_tbl_len = attr.gid_tbl_len;
  3407. return 0;
  3408. }
  3409. static int irdma_iw_port_immutable(struct ib_device *ibdev, u32 port_num,
  3410. struct ib_port_immutable *immutable)
  3411. {
  3412. struct ib_port_attr attr;
  3413. int err;
  3414. immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
  3415. err = ib_query_port(ibdev, port_num, &attr);
  3416. if (err)
  3417. return err;
  3418. immutable->gid_tbl_len = attr.gid_tbl_len;
  3419. return 0;
  3420. }
  3421. static const struct rdma_stat_desc irdma_hw_stat_names[] = {
  3422. /* gen1 - 32-bit */
  3423. [IRDMA_HW_STAT_INDEX_IP4RXDISCARD].name = "ip4InDiscards",
  3424. [IRDMA_HW_STAT_INDEX_IP4RXTRUNC].name = "ip4InTruncatedPkts",
  3425. [IRDMA_HW_STAT_INDEX_IP4TXNOROUTE].name = "ip4OutNoRoutes",
  3426. [IRDMA_HW_STAT_INDEX_IP6RXDISCARD].name = "ip6InDiscards",
  3427. [IRDMA_HW_STAT_INDEX_IP6RXTRUNC].name = "ip6InTruncatedPkts",
  3428. [IRDMA_HW_STAT_INDEX_IP6TXNOROUTE].name = "ip6OutNoRoutes",
  3429. [IRDMA_HW_STAT_INDEX_TCPRTXSEG].name = "tcpRetransSegs",
  3430. [IRDMA_HW_STAT_INDEX_TCPRXOPTERR].name = "tcpInOptErrors",
  3431. [IRDMA_HW_STAT_INDEX_TCPRXPROTOERR].name = "tcpInProtoErrors",
  3432. [IRDMA_HW_STAT_INDEX_RXVLANERR].name = "rxVlanErrors",
  3433. /* gen1 - 64-bit */
  3434. [IRDMA_HW_STAT_INDEX_IP4RXOCTS].name = "ip4InOctets",
  3435. [IRDMA_HW_STAT_INDEX_IP4RXPKTS].name = "ip4InPkts",
  3436. [IRDMA_HW_STAT_INDEX_IP4RXFRAGS].name = "ip4InReasmRqd",
  3437. [IRDMA_HW_STAT_INDEX_IP4RXMCPKTS].name = "ip4InMcastPkts",
  3438. [IRDMA_HW_STAT_INDEX_IP4TXOCTS].name = "ip4OutOctets",
  3439. [IRDMA_HW_STAT_INDEX_IP4TXPKTS].name = "ip4OutPkts",
  3440. [IRDMA_HW_STAT_INDEX_IP4TXFRAGS].name = "ip4OutSegRqd",
  3441. [IRDMA_HW_STAT_INDEX_IP4TXMCPKTS].name = "ip4OutMcastPkts",
  3442. [IRDMA_HW_STAT_INDEX_IP6RXOCTS].name = "ip6InOctets",
  3443. [IRDMA_HW_STAT_INDEX_IP6RXPKTS].name = "ip6InPkts",
  3444. [IRDMA_HW_STAT_INDEX_IP6RXFRAGS].name = "ip6InReasmRqd",
  3445. [IRDMA_HW_STAT_INDEX_IP6RXMCPKTS].name = "ip6InMcastPkts",
  3446. [IRDMA_HW_STAT_INDEX_IP6TXOCTS].name = "ip6OutOctets",
  3447. [IRDMA_HW_STAT_INDEX_IP6TXPKTS].name = "ip6OutPkts",
  3448. [IRDMA_HW_STAT_INDEX_IP6TXFRAGS].name = "ip6OutSegRqd",
  3449. [IRDMA_HW_STAT_INDEX_IP6TXMCPKTS].name = "ip6OutMcastPkts",
  3450. [IRDMA_HW_STAT_INDEX_TCPRXSEGS].name = "tcpInSegs",
  3451. [IRDMA_HW_STAT_INDEX_TCPTXSEG].name = "tcpOutSegs",
  3452. [IRDMA_HW_STAT_INDEX_RDMARXRDS].name = "iwInRdmaReads",
  3453. [IRDMA_HW_STAT_INDEX_RDMARXSNDS].name = "iwInRdmaSends",
  3454. [IRDMA_HW_STAT_INDEX_RDMARXWRS].name = "iwInRdmaWrites",
  3455. [IRDMA_HW_STAT_INDEX_RDMATXRDS].name = "iwOutRdmaReads",
  3456. [IRDMA_HW_STAT_INDEX_RDMATXSNDS].name = "iwOutRdmaSends",
  3457. [IRDMA_HW_STAT_INDEX_RDMATXWRS].name = "iwOutRdmaWrites",
  3458. [IRDMA_HW_STAT_INDEX_RDMAVBND].name = "iwRdmaBnd",
  3459. [IRDMA_HW_STAT_INDEX_RDMAVINV].name = "iwRdmaInv",
  3460. /* gen2 - 32-bit */
  3461. [IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED].name = "cnpHandled",
  3462. [IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED].name = "cnpIgnored",
  3463. [IRDMA_HW_STAT_INDEX_TXNPCNPSENT].name = "cnpSent",
  3464. /* gen2 - 64-bit */
  3465. [IRDMA_HW_STAT_INDEX_IP4RXMCOCTS].name = "ip4InMcastOctets",
  3466. [IRDMA_HW_STAT_INDEX_IP4TXMCOCTS].name = "ip4OutMcastOctets",
  3467. [IRDMA_HW_STAT_INDEX_IP6RXMCOCTS].name = "ip6InMcastOctets",
  3468. [IRDMA_HW_STAT_INDEX_IP6TXMCOCTS].name = "ip6OutMcastOctets",
  3469. [IRDMA_HW_STAT_INDEX_UDPRXPKTS].name = "RxUDP",
  3470. [IRDMA_HW_STAT_INDEX_UDPTXPKTS].name = "TxUDP",
  3471. [IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS].name = "RxECNMrkd",
  3472. };
  3473. static void irdma_get_dev_fw_str(struct ib_device *dev, char *str)
  3474. {
  3475. struct irdma_device *iwdev = to_iwdev(dev);
  3476. snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u",
  3477. irdma_fw_major_ver(&iwdev->rf->sc_dev),
  3478. irdma_fw_minor_ver(&iwdev->rf->sc_dev));
  3479. }
  3480. /**
  3481. * irdma_alloc_hw_port_stats - Allocate a hw stats structure
  3482. * @ibdev: device pointer from stack
  3483. * @port_num: port number
  3484. */
  3485. static struct rdma_hw_stats *irdma_alloc_hw_port_stats(struct ib_device *ibdev,
  3486. u32 port_num)
  3487. {
  3488. struct irdma_device *iwdev = to_iwdev(ibdev);
  3489. struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
  3490. int num_counters = dev->hw_attrs.max_stat_idx;
  3491. unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN;
  3492. return rdma_alloc_hw_stats_struct(irdma_hw_stat_names, num_counters,
  3493. lifespan);
  3494. }
  3495. /**
  3496. * irdma_get_hw_stats - Populates the rdma_hw_stats structure
  3497. * @ibdev: device pointer from stack
  3498. * @stats: stats pointer from stack
  3499. * @port_num: port number
  3500. * @index: which hw counter the stack is requesting we update
  3501. */
  3502. static int irdma_get_hw_stats(struct ib_device *ibdev,
  3503. struct rdma_hw_stats *stats, u32 port_num,
  3504. int index)
  3505. {
  3506. struct irdma_device *iwdev = to_iwdev(ibdev);
  3507. struct irdma_dev_hw_stats *hw_stats = &iwdev->vsi.pestat->hw_stats;
  3508. if (iwdev->rf->rdma_ver >= IRDMA_GEN_2)
  3509. irdma_cqp_gather_stats_cmd(&iwdev->rf->sc_dev, iwdev->vsi.pestat, true);
  3510. else
  3511. irdma_cqp_gather_stats_gen1(&iwdev->rf->sc_dev, iwdev->vsi.pestat);
  3512. memcpy(&stats->value[0], hw_stats, sizeof(u64) * stats->num_counters);
  3513. return stats->num_counters;
  3514. }
  3515. /**
  3516. * irdma_query_gid - Query port GID
  3517. * @ibdev: device pointer from stack
  3518. * @port: port number
  3519. * @index: Entry index
  3520. * @gid: Global ID
  3521. */
  3522. static int irdma_query_gid(struct ib_device *ibdev, u32 port, int index,
  3523. union ib_gid *gid)
  3524. {
  3525. struct irdma_device *iwdev = to_iwdev(ibdev);
  3526. memset(gid->raw, 0, sizeof(gid->raw));
  3527. ether_addr_copy(gid->raw, iwdev->netdev->dev_addr);
  3528. return 0;
  3529. }
  3530. /**
  3531. * mcast_list_add - Add a new mcast item to list
  3532. * @rf: RDMA PCI function
  3533. * @new_elem: pointer to element to add
  3534. */
  3535. static void mcast_list_add(struct irdma_pci_f *rf,
  3536. struct mc_table_list *new_elem)
  3537. {
  3538. list_add(&new_elem->list, &rf->mc_qht_list.list);
  3539. }
  3540. /**
  3541. * mcast_list_del - Remove an mcast item from list
  3542. * @mc_qht_elem: pointer to mcast table list element
  3543. */
  3544. static void mcast_list_del(struct mc_table_list *mc_qht_elem)
  3545. {
  3546. if (mc_qht_elem)
  3547. list_del(&mc_qht_elem->list);
  3548. }
  3549. /**
  3550. * mcast_list_lookup_ip - Search mcast list for address
  3551. * @rf: RDMA PCI function
  3552. * @ip_mcast: pointer to mcast IP address
  3553. */
  3554. static struct mc_table_list *mcast_list_lookup_ip(struct irdma_pci_f *rf,
  3555. u32 *ip_mcast)
  3556. {
  3557. struct mc_table_list *mc_qht_el;
  3558. struct list_head *pos, *q;
  3559. list_for_each_safe (pos, q, &rf->mc_qht_list.list) {
  3560. mc_qht_el = list_entry(pos, struct mc_table_list, list);
  3561. if (!memcmp(mc_qht_el->mc_info.dest_ip, ip_mcast,
  3562. sizeof(mc_qht_el->mc_info.dest_ip)))
  3563. return mc_qht_el;
  3564. }
  3565. return NULL;
  3566. }
  3567. /**
  3568. * irdma_mcast_cqp_op - perform a mcast cqp operation
  3569. * @iwdev: irdma device
  3570. * @mc_grp_ctx: mcast group info
  3571. * @op: operation
  3572. *
  3573. * returns error status
  3574. */
  3575. static int irdma_mcast_cqp_op(struct irdma_device *iwdev,
  3576. struct irdma_mcast_grp_info *mc_grp_ctx, u8 op)
  3577. {
  3578. struct cqp_cmds_info *cqp_info;
  3579. struct irdma_cqp_request *cqp_request;
  3580. int status;
  3581. cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
  3582. if (!cqp_request)
  3583. return -ENOMEM;
  3584. cqp_request->info.in.u.mc_create.info = *mc_grp_ctx;
  3585. cqp_info = &cqp_request->info;
  3586. cqp_info->cqp_cmd = op;
  3587. cqp_info->post_sq = 1;
  3588. cqp_info->in.u.mc_create.scratch = (uintptr_t)cqp_request;
  3589. cqp_info->in.u.mc_create.cqp = &iwdev->rf->cqp.sc_cqp;
  3590. status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
  3591. irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
  3592. return status;
  3593. }
  3594. /**
  3595. * irdma_mcast_mac - Get the multicast MAC for an IP address
  3596. * @ip_addr: IPv4 or IPv6 address
  3597. * @mac: pointer to result MAC address
  3598. * @ipv4: flag indicating IPv4 or IPv6
  3599. *
  3600. */
  3601. void irdma_mcast_mac(u32 *ip_addr, u8 *mac, bool ipv4)
  3602. {
  3603. u8 *ip = (u8 *)ip_addr;
  3604. if (ipv4) {
  3605. unsigned char mac4[ETH_ALEN] = {0x01, 0x00, 0x5E, 0x00,
  3606. 0x00, 0x00};
  3607. mac4[3] = ip[2] & 0x7F;
  3608. mac4[4] = ip[1];
  3609. mac4[5] = ip[0];
  3610. ether_addr_copy(mac, mac4);
  3611. } else {
  3612. unsigned char mac6[ETH_ALEN] = {0x33, 0x33, 0x00, 0x00,
  3613. 0x00, 0x00};
  3614. mac6[2] = ip[3];
  3615. mac6[3] = ip[2];
  3616. mac6[4] = ip[1];
  3617. mac6[5] = ip[0];
  3618. ether_addr_copy(mac, mac6);
  3619. }
  3620. }
  3621. /**
  3622. * irdma_attach_mcast - attach a qp to a multicast group
  3623. * @ibqp: ptr to qp
  3624. * @ibgid: pointer to global ID
  3625. * @lid: local ID
  3626. *
  3627. * returns error status
  3628. */
  3629. static int irdma_attach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid)
  3630. {
  3631. struct irdma_qp *iwqp = to_iwqp(ibqp);
  3632. struct irdma_device *iwdev = iwqp->iwdev;
  3633. struct irdma_pci_f *rf = iwdev->rf;
  3634. struct mc_table_list *mc_qht_elem;
  3635. struct irdma_mcast_grp_ctx_entry_info mcg_info = {};
  3636. unsigned long flags;
  3637. u32 ip_addr[4] = {};
  3638. u32 mgn;
  3639. u32 no_mgs;
  3640. int ret = 0;
  3641. bool ipv4;
  3642. u16 vlan_id;
  3643. union irdma_sockaddr sgid_addr;
  3644. unsigned char dmac[ETH_ALEN];
  3645. rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);
  3646. if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid)) {
  3647. irdma_copy_ip_ntohl(ip_addr,
  3648. sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32);
  3649. irdma_get_vlan_mac_ipv6(ip_addr, &vlan_id, NULL);
  3650. ipv4 = false;
  3651. ibdev_dbg(&iwdev->ibdev,
  3652. "VERBS: qp_id=%d, IP6address=%pI6\n", ibqp->qp_num,
  3653. ip_addr);
  3654. irdma_mcast_mac(ip_addr, dmac, false);
  3655. } else {
  3656. ip_addr[0] = ntohl(sgid_addr.saddr_in.sin_addr.s_addr);
  3657. ipv4 = true;
  3658. vlan_id = irdma_get_vlan_ipv4(ip_addr);
  3659. irdma_mcast_mac(ip_addr, dmac, true);
  3660. ibdev_dbg(&iwdev->ibdev,
  3661. "VERBS: qp_id=%d, IP4address=%pI4, MAC=%pM\n",
  3662. ibqp->qp_num, ip_addr, dmac);
  3663. }
  3664. spin_lock_irqsave(&rf->qh_list_lock, flags);
  3665. mc_qht_elem = mcast_list_lookup_ip(rf, ip_addr);
  3666. if (!mc_qht_elem) {
  3667. struct irdma_dma_mem *dma_mem_mc;
  3668. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3669. mc_qht_elem = kzalloc(sizeof(*mc_qht_elem), GFP_KERNEL);
  3670. if (!mc_qht_elem)
  3671. return -ENOMEM;
  3672. mc_qht_elem->mc_info.ipv4_valid = ipv4;
  3673. memcpy(mc_qht_elem->mc_info.dest_ip, ip_addr,
  3674. sizeof(mc_qht_elem->mc_info.dest_ip));
  3675. ret = irdma_alloc_rsrc(rf, rf->allocated_mcgs, rf->max_mcg,
  3676. &mgn, &rf->next_mcg);
  3677. if (ret) {
  3678. kfree(mc_qht_elem);
  3679. return -ENOMEM;
  3680. }
  3681. mc_qht_elem->mc_info.mgn = mgn;
  3682. dma_mem_mc = &mc_qht_elem->mc_grp_ctx.dma_mem_mc;
  3683. dma_mem_mc->size = ALIGN(sizeof(u64) * IRDMA_MAX_MGS_PER_CTX,
  3684. IRDMA_HW_PAGE_SIZE);
  3685. dma_mem_mc->va = dma_alloc_coherent(rf->hw.device,
  3686. dma_mem_mc->size,
  3687. &dma_mem_mc->pa,
  3688. GFP_KERNEL);
  3689. if (!dma_mem_mc->va) {
  3690. irdma_free_rsrc(rf, rf->allocated_mcgs, mgn);
  3691. kfree(mc_qht_elem);
  3692. return -ENOMEM;
  3693. }
  3694. mc_qht_elem->mc_grp_ctx.mg_id = (u16)mgn;
  3695. memcpy(mc_qht_elem->mc_grp_ctx.dest_ip_addr, ip_addr,
  3696. sizeof(mc_qht_elem->mc_grp_ctx.dest_ip_addr));
  3697. mc_qht_elem->mc_grp_ctx.ipv4_valid = ipv4;
  3698. mc_qht_elem->mc_grp_ctx.vlan_id = vlan_id;
  3699. if (vlan_id < VLAN_N_VID)
  3700. mc_qht_elem->mc_grp_ctx.vlan_valid = true;
  3701. mc_qht_elem->mc_grp_ctx.hmc_fcn_id = iwdev->rf->sc_dev.hmc_fn_id;
  3702. mc_qht_elem->mc_grp_ctx.qs_handle =
  3703. iwqp->sc_qp.vsi->qos[iwqp->sc_qp.user_pri].qs_handle;
  3704. ether_addr_copy(mc_qht_elem->mc_grp_ctx.dest_mac_addr, dmac);
  3705. spin_lock_irqsave(&rf->qh_list_lock, flags);
  3706. mcast_list_add(rf, mc_qht_elem);
  3707. } else {
  3708. if (mc_qht_elem->mc_grp_ctx.no_of_mgs ==
  3709. IRDMA_MAX_MGS_PER_CTX) {
  3710. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3711. return -ENOMEM;
  3712. }
  3713. }
  3714. mcg_info.qp_id = iwqp->ibqp.qp_num;
  3715. no_mgs = mc_qht_elem->mc_grp_ctx.no_of_mgs;
  3716. irdma_sc_add_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info);
  3717. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3718. /* Only if there is a change do we need to modify or create */
  3719. if (!no_mgs) {
  3720. ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
  3721. IRDMA_OP_MC_CREATE);
  3722. } else if (no_mgs != mc_qht_elem->mc_grp_ctx.no_of_mgs) {
  3723. ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
  3724. IRDMA_OP_MC_MODIFY);
  3725. } else {
  3726. return 0;
  3727. }
  3728. if (ret)
  3729. goto error;
  3730. return 0;
  3731. error:
  3732. irdma_sc_del_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info);
  3733. if (!mc_qht_elem->mc_grp_ctx.no_of_mgs) {
  3734. mcast_list_del(mc_qht_elem);
  3735. dma_free_coherent(rf->hw.device,
  3736. mc_qht_elem->mc_grp_ctx.dma_mem_mc.size,
  3737. mc_qht_elem->mc_grp_ctx.dma_mem_mc.va,
  3738. mc_qht_elem->mc_grp_ctx.dma_mem_mc.pa);
  3739. mc_qht_elem->mc_grp_ctx.dma_mem_mc.va = NULL;
  3740. irdma_free_rsrc(rf, rf->allocated_mcgs,
  3741. mc_qht_elem->mc_grp_ctx.mg_id);
  3742. kfree(mc_qht_elem);
  3743. }
  3744. return ret;
  3745. }
  3746. /**
  3747. * irdma_detach_mcast - detach a qp from a multicast group
  3748. * @ibqp: ptr to qp
  3749. * @ibgid: pointer to global ID
  3750. * @lid: local ID
  3751. *
  3752. * returns error status
  3753. */
  3754. static int irdma_detach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid)
  3755. {
  3756. struct irdma_qp *iwqp = to_iwqp(ibqp);
  3757. struct irdma_device *iwdev = iwqp->iwdev;
  3758. struct irdma_pci_f *rf = iwdev->rf;
  3759. u32 ip_addr[4] = {};
  3760. struct mc_table_list *mc_qht_elem;
  3761. struct irdma_mcast_grp_ctx_entry_info mcg_info = {};
  3762. int ret;
  3763. unsigned long flags;
  3764. union irdma_sockaddr sgid_addr;
  3765. rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);
  3766. if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid))
  3767. irdma_copy_ip_ntohl(ip_addr,
  3768. sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32);
  3769. else
  3770. ip_addr[0] = ntohl(sgid_addr.saddr_in.sin_addr.s_addr);
  3771. spin_lock_irqsave(&rf->qh_list_lock, flags);
  3772. mc_qht_elem = mcast_list_lookup_ip(rf, ip_addr);
  3773. if (!mc_qht_elem) {
  3774. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3775. ibdev_dbg(&iwdev->ibdev,
  3776. "VERBS: address not found MCG\n");
  3777. return 0;
  3778. }
  3779. mcg_info.qp_id = iwqp->ibqp.qp_num;
  3780. irdma_sc_del_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info);
  3781. if (!mc_qht_elem->mc_grp_ctx.no_of_mgs) {
  3782. mcast_list_del(mc_qht_elem);
  3783. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3784. ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
  3785. IRDMA_OP_MC_DESTROY);
  3786. if (ret) {
  3787. ibdev_dbg(&iwdev->ibdev,
  3788. "VERBS: failed MC_DESTROY MCG\n");
  3789. spin_lock_irqsave(&rf->qh_list_lock, flags);
  3790. mcast_list_add(rf, mc_qht_elem);
  3791. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3792. return -EAGAIN;
  3793. }
  3794. dma_free_coherent(rf->hw.device,
  3795. mc_qht_elem->mc_grp_ctx.dma_mem_mc.size,
  3796. mc_qht_elem->mc_grp_ctx.dma_mem_mc.va,
  3797. mc_qht_elem->mc_grp_ctx.dma_mem_mc.pa);
  3798. mc_qht_elem->mc_grp_ctx.dma_mem_mc.va = NULL;
  3799. irdma_free_rsrc(rf, rf->allocated_mcgs,
  3800. mc_qht_elem->mc_grp_ctx.mg_id);
  3801. kfree(mc_qht_elem);
  3802. } else {
  3803. spin_unlock_irqrestore(&rf->qh_list_lock, flags);
  3804. ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
  3805. IRDMA_OP_MC_MODIFY);
  3806. if (ret) {
  3807. ibdev_dbg(&iwdev->ibdev,
  3808. "VERBS: failed Modify MCG\n");
  3809. return ret;
  3810. }
  3811. }
  3812. return 0;
  3813. }
  3814. static int irdma_create_hw_ah(struct irdma_device *iwdev, struct irdma_ah *ah, bool sleep)
  3815. {
  3816. struct irdma_pci_f *rf = iwdev->rf;
  3817. int err;
  3818. err = irdma_alloc_rsrc(rf, rf->allocated_ahs, rf->max_ah, &ah->sc_ah.ah_info.ah_idx,
  3819. &rf->next_ah);
  3820. if (err)
  3821. return err;
  3822. err = irdma_ah_cqp_op(rf, &ah->sc_ah, IRDMA_OP_AH_CREATE, sleep,
  3823. irdma_gsi_ud_qp_ah_cb, &ah->sc_ah);
  3824. if (err) {
  3825. ibdev_dbg(&iwdev->ibdev, "VERBS: CQP-OP Create AH fail");
  3826. goto err_ah_create;
  3827. }
  3828. if (!sleep) {
  3829. int cnt = CQP_COMPL_WAIT_TIME_MS * CQP_TIMEOUT_THRESHOLD;
  3830. do {
  3831. irdma_cqp_ce_handler(rf, &rf->ccq.sc_cq);
  3832. mdelay(1);
  3833. } while (!ah->sc_ah.ah_info.ah_valid && --cnt);
  3834. if (!cnt) {
  3835. ibdev_dbg(&iwdev->ibdev, "VERBS: CQP create AH timed out");
  3836. err = -ETIMEDOUT;
  3837. goto err_ah_create;
  3838. }
  3839. }
  3840. return 0;
  3841. err_ah_create:
  3842. irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah->sc_ah.ah_info.ah_idx);
  3843. return err;
  3844. }
  3845. static int irdma_setup_ah(struct ib_ah *ibah, struct rdma_ah_init_attr *attr)
  3846. {
  3847. struct irdma_pd *pd = to_iwpd(ibah->pd);
  3848. struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);
  3849. struct rdma_ah_attr *ah_attr = attr->ah_attr;
  3850. const struct ib_gid_attr *sgid_attr;
  3851. struct irdma_device *iwdev = to_iwdev(ibah->pd->device);
  3852. struct irdma_pci_f *rf = iwdev->rf;
  3853. struct irdma_sc_ah *sc_ah;
  3854. struct irdma_ah_info *ah_info;
  3855. union irdma_sockaddr sgid_addr, dgid_addr;
  3856. int err;
  3857. u8 dmac[ETH_ALEN];
  3858. ah->pd = pd;
  3859. sc_ah = &ah->sc_ah;
  3860. sc_ah->ah_info.vsi = &iwdev->vsi;
  3861. irdma_sc_init_ah(&rf->sc_dev, sc_ah);
  3862. ah->sgid_index = ah_attr->grh.sgid_index;
  3863. sgid_attr = ah_attr->grh.sgid_attr;
  3864. memcpy(&ah->dgid, &ah_attr->grh.dgid, sizeof(ah->dgid));
  3865. rdma_gid2ip((struct sockaddr *)&sgid_addr, &sgid_attr->gid);
  3866. rdma_gid2ip((struct sockaddr *)&dgid_addr, &ah_attr->grh.dgid);
  3867. ah->av.attrs = *ah_attr;
  3868. ah->av.net_type = rdma_gid_attr_network_type(sgid_attr);
  3869. ah_info = &sc_ah->ah_info;
  3870. ah_info->pd_idx = pd->sc_pd.pd_id;
  3871. if (ah_attr->ah_flags & IB_AH_GRH) {
  3872. ah_info->flow_label = ah_attr->grh.flow_label;
  3873. ah_info->hop_ttl = ah_attr->grh.hop_limit;
  3874. ah_info->tc_tos = ah_attr->grh.traffic_class;
  3875. }
  3876. ether_addr_copy(dmac, ah_attr->roce.dmac);
  3877. if (ah->av.net_type == RDMA_NETWORK_IPV4) {
  3878. ah_info->ipv4_valid = true;
  3879. ah_info->dest_ip_addr[0] =
  3880. ntohl(dgid_addr.saddr_in.sin_addr.s_addr);
  3881. ah_info->src_ip_addr[0] =
  3882. ntohl(sgid_addr.saddr_in.sin_addr.s_addr);
  3883. ah_info->do_lpbk = irdma_ipv4_is_lpb(ah_info->src_ip_addr[0],
  3884. ah_info->dest_ip_addr[0]);
  3885. if (ipv4_is_multicast(dgid_addr.saddr_in.sin_addr.s_addr)) {
  3886. ah_info->do_lpbk = true;
  3887. irdma_mcast_mac(ah_info->dest_ip_addr, dmac, true);
  3888. }
  3889. } else {
  3890. irdma_copy_ip_ntohl(ah_info->dest_ip_addr,
  3891. dgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32);
  3892. irdma_copy_ip_ntohl(ah_info->src_ip_addr,
  3893. sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32);
  3894. ah_info->do_lpbk = irdma_ipv6_is_lpb(ah_info->src_ip_addr,
  3895. ah_info->dest_ip_addr);
  3896. if (rdma_is_multicast_addr(&dgid_addr.saddr_in6.sin6_addr)) {
  3897. ah_info->do_lpbk = true;
  3898. irdma_mcast_mac(ah_info->dest_ip_addr, dmac, false);
  3899. }
  3900. }
  3901. err = rdma_read_gid_l2_fields(sgid_attr, &ah_info->vlan_tag,
  3902. ah_info->mac_addr);
  3903. if (err)
  3904. return err;
  3905. ah_info->dst_arpindex = irdma_add_arp(iwdev->rf, ah_info->dest_ip_addr,
  3906. ah_info->ipv4_valid, dmac);
  3907. if (ah_info->dst_arpindex == -1)
  3908. return -EINVAL;
  3909. if (ah_info->vlan_tag >= VLAN_N_VID && iwdev->dcb_vlan_mode)
  3910. ah_info->vlan_tag = 0;
  3911. if (ah_info->vlan_tag < VLAN_N_VID) {
  3912. u8 prio = rt_tos2priority(ah_info->tc_tos);
  3913. prio = irdma_roce_get_vlan_prio(sgid_attr, prio);
  3914. ah_info->vlan_tag |= (u16)prio << VLAN_PRIO_SHIFT;
  3915. ah_info->insert_vlan_tag = true;
  3916. }
  3917. return 0;
  3918. }
  3919. /**
  3920. * irdma_ah_exists - Check for existing identical AH
  3921. * @iwdev: irdma device
  3922. * @new_ah: AH to check for
  3923. *
  3924. * returns true if AH is found, false if not found.
  3925. */
  3926. static bool irdma_ah_exists(struct irdma_device *iwdev,
  3927. struct irdma_ah *new_ah)
  3928. {
  3929. struct irdma_ah *ah;
  3930. u32 key = new_ah->sc_ah.ah_info.dest_ip_addr[0] ^
  3931. new_ah->sc_ah.ah_info.dest_ip_addr[1] ^
  3932. new_ah->sc_ah.ah_info.dest_ip_addr[2] ^
  3933. new_ah->sc_ah.ah_info.dest_ip_addr[3];
  3934. hash_for_each_possible(iwdev->ah_hash_tbl, ah, list, key) {
  3935. /* Set ah_valid and ah_id the same so memcmp can work */
  3936. new_ah->sc_ah.ah_info.ah_idx = ah->sc_ah.ah_info.ah_idx;
  3937. new_ah->sc_ah.ah_info.ah_valid = ah->sc_ah.ah_info.ah_valid;
  3938. if (!memcmp(&ah->sc_ah.ah_info, &new_ah->sc_ah.ah_info,
  3939. sizeof(ah->sc_ah.ah_info))) {
  3940. refcount_inc(&ah->refcnt);
  3941. new_ah->parent_ah = ah;
  3942. return true;
  3943. }
  3944. }
  3945. return false;
  3946. }
  3947. /**
  3948. * irdma_destroy_ah - Destroy address handle
  3949. * @ibah: pointer to address handle
  3950. * @ah_flags: flags for sleepable
  3951. */
  3952. static int irdma_destroy_ah(struct ib_ah *ibah, u32 ah_flags)
  3953. {
  3954. struct irdma_device *iwdev = to_iwdev(ibah->device);
  3955. struct irdma_ah *ah = to_iwah(ibah);
  3956. if ((ah_flags & RDMA_DESTROY_AH_SLEEPABLE) && ah->parent_ah) {
  3957. mutex_lock(&iwdev->ah_tbl_lock);
  3958. if (!refcount_dec_and_test(&ah->parent_ah->refcnt)) {
  3959. mutex_unlock(&iwdev->ah_tbl_lock);
  3960. return 0;
  3961. }
  3962. hash_del(&ah->parent_ah->list);
  3963. kfree(ah->parent_ah);
  3964. mutex_unlock(&iwdev->ah_tbl_lock);
  3965. }
  3966. irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, IRDMA_OP_AH_DESTROY,
  3967. false, NULL, ah);
  3968. irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs,
  3969. ah->sc_ah.ah_info.ah_idx);
  3970. return 0;
  3971. }
  3972. /**
  3973. * irdma_create_user_ah - create user address handle
  3974. * @ibah: address handle
  3975. * @attr: address handle attributes
  3976. * @udata: User data
  3977. *
  3978. * returns 0 on success, error otherwise
  3979. */
  3980. static int irdma_create_user_ah(struct ib_ah *ibah,
  3981. struct rdma_ah_init_attr *attr,
  3982. struct ib_udata *udata)
  3983. {
  3984. #define IRDMA_CREATE_AH_MIN_RESP_LEN offsetofend(struct irdma_create_ah_resp, rsvd)
  3985. struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);
  3986. struct irdma_device *iwdev = to_iwdev(ibah->pd->device);
  3987. struct irdma_create_ah_resp uresp;
  3988. struct irdma_ah *parent_ah;
  3989. int err;
  3990. if (udata && udata->outlen < IRDMA_CREATE_AH_MIN_RESP_LEN)
  3991. return -EINVAL;
  3992. err = irdma_setup_ah(ibah, attr);
  3993. if (err)
  3994. return err;
  3995. mutex_lock(&iwdev->ah_tbl_lock);
  3996. if (!irdma_ah_exists(iwdev, ah)) {
  3997. err = irdma_create_hw_ah(iwdev, ah, true);
  3998. if (err) {
  3999. mutex_unlock(&iwdev->ah_tbl_lock);
  4000. return err;
  4001. }
  4002. /* Add new AH to list */
  4003. parent_ah = kmemdup(ah, sizeof(*ah), GFP_KERNEL);
  4004. if (parent_ah) {
  4005. u32 key = parent_ah->sc_ah.ah_info.dest_ip_addr[0] ^
  4006. parent_ah->sc_ah.ah_info.dest_ip_addr[1] ^
  4007. parent_ah->sc_ah.ah_info.dest_ip_addr[2] ^
  4008. parent_ah->sc_ah.ah_info.dest_ip_addr[3];
  4009. ah->parent_ah = parent_ah;
  4010. hash_add(iwdev->ah_hash_tbl, &parent_ah->list, key);
  4011. refcount_set(&parent_ah->refcnt, 1);
  4012. }
  4013. }
  4014. mutex_unlock(&iwdev->ah_tbl_lock);
  4015. uresp.ah_id = ah->sc_ah.ah_info.ah_idx;
  4016. err = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), udata->outlen));
  4017. if (err)
  4018. irdma_destroy_ah(ibah, attr->flags);
  4019. return err;
  4020. }
  4021. /**
  4022. * irdma_create_ah - create address handle
  4023. * @ibah: address handle
  4024. * @attr: address handle attributes
  4025. * @udata: NULL
  4026. *
  4027. * returns 0 on success, error otherwise
  4028. */
  4029. static int irdma_create_ah(struct ib_ah *ibah, struct rdma_ah_init_attr *attr,
  4030. struct ib_udata *udata)
  4031. {
  4032. struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);
  4033. struct irdma_device *iwdev = to_iwdev(ibah->pd->device);
  4034. int err;
  4035. err = irdma_setup_ah(ibah, attr);
  4036. if (err)
  4037. return err;
  4038. err = irdma_create_hw_ah(iwdev, ah, attr->flags & RDMA_CREATE_AH_SLEEPABLE);
  4039. return err;
  4040. }
  4041. /**
  4042. * irdma_query_ah - Query address handle
  4043. * @ibah: pointer to address handle
  4044. * @ah_attr: address handle attributes
  4045. */
  4046. static int irdma_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr)
  4047. {
  4048. struct irdma_ah *ah = to_iwah(ibah);
  4049. memset(ah_attr, 0, sizeof(*ah_attr));
  4050. if (ah->av.attrs.ah_flags & IB_AH_GRH) {
  4051. ah_attr->ah_flags = IB_AH_GRH;
  4052. ah_attr->grh.flow_label = ah->sc_ah.ah_info.flow_label;
  4053. ah_attr->grh.traffic_class = ah->sc_ah.ah_info.tc_tos;
  4054. ah_attr->grh.hop_limit = ah->sc_ah.ah_info.hop_ttl;
  4055. ah_attr->grh.sgid_index = ah->sgid_index;
  4056. memcpy(&ah_attr->grh.dgid, &ah->dgid,
  4057. sizeof(ah_attr->grh.dgid));
  4058. }
  4059. return 0;
  4060. }
  4061. static enum rdma_link_layer irdma_get_link_layer(struct ib_device *ibdev,
  4062. u32 port_num)
  4063. {
  4064. return IB_LINK_LAYER_ETHERNET;
  4065. }
  4066. static const struct ib_device_ops irdma_roce_dev_ops = {
  4067. .attach_mcast = irdma_attach_mcast,
  4068. .create_ah = irdma_create_ah,
  4069. .create_user_ah = irdma_create_user_ah,
  4070. .destroy_ah = irdma_destroy_ah,
  4071. .detach_mcast = irdma_detach_mcast,
  4072. .get_link_layer = irdma_get_link_layer,
  4073. .get_port_immutable = irdma_roce_port_immutable,
  4074. .modify_qp = irdma_modify_qp_roce,
  4075. .query_ah = irdma_query_ah,
  4076. .query_pkey = irdma_query_pkey,
  4077. };
  4078. static const struct ib_device_ops irdma_iw_dev_ops = {
  4079. .get_port_immutable = irdma_iw_port_immutable,
  4080. .iw_accept = irdma_accept,
  4081. .iw_add_ref = irdma_qp_add_ref,
  4082. .iw_connect = irdma_connect,
  4083. .iw_create_listen = irdma_create_listen,
  4084. .iw_destroy_listen = irdma_destroy_listen,
  4085. .iw_get_qp = irdma_get_qp,
  4086. .iw_reject = irdma_reject,
  4087. .iw_rem_ref = irdma_qp_rem_ref,
  4088. .modify_qp = irdma_modify_qp,
  4089. .query_gid = irdma_query_gid,
  4090. };
  4091. static const struct ib_device_ops irdma_dev_ops = {
  4092. .owner = THIS_MODULE,
  4093. .driver_id = RDMA_DRIVER_IRDMA,
  4094. .uverbs_abi_ver = IRDMA_ABI_VER,
  4095. .alloc_hw_port_stats = irdma_alloc_hw_port_stats,
  4096. .alloc_mr = irdma_alloc_mr,
  4097. .alloc_mw = irdma_alloc_mw,
  4098. .alloc_pd = irdma_alloc_pd,
  4099. .alloc_ucontext = irdma_alloc_ucontext,
  4100. .create_cq = irdma_create_cq,
  4101. .create_qp = irdma_create_qp,
  4102. .dealloc_driver = irdma_ib_dealloc_device,
  4103. .dealloc_mw = irdma_dealloc_mw,
  4104. .dealloc_pd = irdma_dealloc_pd,
  4105. .dealloc_ucontext = irdma_dealloc_ucontext,
  4106. .dereg_mr = irdma_dereg_mr,
  4107. .destroy_cq = irdma_destroy_cq,
  4108. .destroy_qp = irdma_destroy_qp,
  4109. .disassociate_ucontext = irdma_disassociate_ucontext,
  4110. .get_dev_fw_str = irdma_get_dev_fw_str,
  4111. .get_dma_mr = irdma_get_dma_mr,
  4112. .get_hw_stats = irdma_get_hw_stats,
  4113. .map_mr_sg = irdma_map_mr_sg,
  4114. .mmap = irdma_mmap,
  4115. .mmap_free = irdma_mmap_free,
  4116. .poll_cq = irdma_poll_cq,
  4117. .post_recv = irdma_post_recv,
  4118. .post_send = irdma_post_send,
  4119. .query_device = irdma_query_device,
  4120. .query_port = irdma_query_port,
  4121. .query_qp = irdma_query_qp,
  4122. .reg_user_mr = irdma_reg_user_mr,
  4123. .reg_user_mr_dmabuf = irdma_reg_user_mr_dmabuf,
  4124. .rereg_user_mr = irdma_rereg_user_mr,
  4125. .req_notify_cq = irdma_req_notify_cq,
  4126. .resize_cq = irdma_resize_cq,
  4127. INIT_RDMA_OBJ_SIZE(ib_pd, irdma_pd, ibpd),
  4128. INIT_RDMA_OBJ_SIZE(ib_ucontext, irdma_ucontext, ibucontext),
  4129. INIT_RDMA_OBJ_SIZE(ib_ah, irdma_ah, ibah),
  4130. INIT_RDMA_OBJ_SIZE(ib_cq, irdma_cq, ibcq),
  4131. INIT_RDMA_OBJ_SIZE(ib_mw, irdma_mr, ibmw),
  4132. INIT_RDMA_OBJ_SIZE(ib_qp, irdma_qp, ibqp),
  4133. };
  4134. /**
  4135. * irdma_init_roce_device - initialization of roce rdma device
  4136. * @iwdev: irdma device
  4137. */
  4138. static void irdma_init_roce_device(struct irdma_device *iwdev)
  4139. {
  4140. iwdev->ibdev.node_type = RDMA_NODE_IB_CA;
  4141. addrconf_addr_eui48((u8 *)&iwdev->ibdev.node_guid,
  4142. iwdev->netdev->dev_addr);
  4143. ib_set_device_ops(&iwdev->ibdev, &irdma_roce_dev_ops);
  4144. }
  4145. /**
  4146. * irdma_init_iw_device - initialization of iwarp rdma device
  4147. * @iwdev: irdma device
  4148. */
  4149. static void irdma_init_iw_device(struct irdma_device *iwdev)
  4150. {
  4151. struct net_device *netdev = iwdev->netdev;
  4152. iwdev->ibdev.node_type = RDMA_NODE_RNIC;
  4153. addrconf_addr_eui48((u8 *)&iwdev->ibdev.node_guid,
  4154. netdev->dev_addr);
  4155. memcpy(iwdev->ibdev.iw_ifname, netdev->name,
  4156. sizeof(iwdev->ibdev.iw_ifname));
  4157. ib_set_device_ops(&iwdev->ibdev, &irdma_iw_dev_ops);
  4158. }
  4159. /**
  4160. * irdma_init_rdma_device - initialization of rdma device
  4161. * @iwdev: irdma device
  4162. */
  4163. static void irdma_init_rdma_device(struct irdma_device *iwdev)
  4164. {
  4165. struct pci_dev *pcidev = iwdev->rf->pcidev;
  4166. if (iwdev->roce_mode)
  4167. irdma_init_roce_device(iwdev);
  4168. else
  4169. irdma_init_iw_device(iwdev);
  4170. iwdev->ibdev.phys_port_cnt = 1;
  4171. iwdev->ibdev.num_comp_vectors = iwdev->rf->ceqs_count;
  4172. iwdev->ibdev.dev.parent = &pcidev->dev;
  4173. ib_set_device_ops(&iwdev->ibdev, &irdma_dev_ops);
  4174. }
  4175. /**
  4176. * irdma_port_ibevent - indicate port event
  4177. * @iwdev: irdma device
  4178. */
  4179. void irdma_port_ibevent(struct irdma_device *iwdev)
  4180. {
  4181. struct ib_event event;
  4182. event.device = &iwdev->ibdev;
  4183. event.element.port_num = 1;
  4184. event.event =
  4185. iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  4186. ib_dispatch_event(&event);
  4187. }
  4188. /**
  4189. * irdma_ib_unregister_device - unregister rdma device from IB
  4190. * core
  4191. * @iwdev: irdma device
  4192. */
  4193. void irdma_ib_unregister_device(struct irdma_device *iwdev)
  4194. {
  4195. iwdev->iw_status = 0;
  4196. irdma_port_ibevent(iwdev);
  4197. ib_unregister_device(&iwdev->ibdev);
  4198. }
  4199. /**
  4200. * irdma_ib_register_device - register irdma device to IB core
  4201. * @iwdev: irdma device
  4202. */
  4203. int irdma_ib_register_device(struct irdma_device *iwdev)
  4204. {
  4205. int ret;
  4206. irdma_init_rdma_device(iwdev);
  4207. ret = ib_device_set_netdev(&iwdev->ibdev, iwdev->netdev, 1);
  4208. if (ret)
  4209. goto error;
  4210. dma_set_max_seg_size(iwdev->rf->hw.device, UINT_MAX);
  4211. ret = ib_register_device(&iwdev->ibdev, "irdma%d", iwdev->rf->hw.device);
  4212. if (ret)
  4213. goto error;
  4214. iwdev->iw_status = 1;
  4215. irdma_port_ibevent(iwdev);
  4216. return 0;
  4217. error:
  4218. if (ret)
  4219. ibdev_dbg(&iwdev->ibdev, "VERBS: Register RDMA device fail\n");
  4220. return ret;
  4221. }
  4222. /**
  4223. * irdma_ib_dealloc_device
  4224. * @ibdev: ib device
  4225. *
  4226. * callback from ibdev dealloc_driver to deallocate resources
  4227. * unber irdma device
  4228. */
  4229. void irdma_ib_dealloc_device(struct ib_device *ibdev)
  4230. {
  4231. struct irdma_device *iwdev = to_iwdev(ibdev);
  4232. irdma_rt_deinit_hw(iwdev);
  4233. irdma_ctrl_deinit_hw(iwdev->rf);
  4234. kfree(iwdev->rf);
  4235. }