mtk-pmic-keys.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2017 MediaTek, Inc.
  4. *
  5. * Author: Chen Zhong <chen.zhong@mediatek.com>
  6. */
  7. #include <linux/input.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/kernel.h>
  10. #include <linux/mfd/mt6323/registers.h>
  11. #include <linux/mfd/mt6331/registers.h>
  12. #include <linux/mfd/mt6357/registers.h>
  13. #include <linux/mfd/mt6358/registers.h>
  14. #include <linux/mfd/mt6397/core.h>
  15. #include <linux/mfd/mt6397/registers.h>
  16. #include <linux/module.h>
  17. #include <linux/of_device.h>
  18. #include <linux/of.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/regmap.h>
  21. #define MTK_PMIC_RST_DU_MASK GENMASK(9, 8)
  22. #define MTK_PMIC_PWRKEY_RST BIT(6)
  23. #define MTK_PMIC_HOMEKEY_RST BIT(5)
  24. #define MTK_PMIC_MT6331_RST_DU_MASK GENMASK(13, 12)
  25. #define MTK_PMIC_MT6331_PWRKEY_RST BIT(9)
  26. #define MTK_PMIC_MT6331_HOMEKEY_RST BIT(8)
  27. #define MTK_PMIC_PWRKEY_INDEX 0
  28. #define MTK_PMIC_HOMEKEY_INDEX 1
  29. #define MTK_PMIC_MAX_KEY_COUNT 2
  30. struct mtk_pmic_keys_regs {
  31. u32 deb_reg;
  32. u32 deb_mask;
  33. u32 intsel_reg;
  34. u32 intsel_mask;
  35. u32 rst_en_mask;
  36. };
  37. #define MTK_PMIC_KEYS_REGS(_deb_reg, _deb_mask, \
  38. _intsel_reg, _intsel_mask, _rst_mask) \
  39. { \
  40. .deb_reg = _deb_reg, \
  41. .deb_mask = _deb_mask, \
  42. .intsel_reg = _intsel_reg, \
  43. .intsel_mask = _intsel_mask, \
  44. .rst_en_mask = _rst_mask, \
  45. }
  46. struct mtk_pmic_regs {
  47. const struct mtk_pmic_keys_regs keys_regs[MTK_PMIC_MAX_KEY_COUNT];
  48. u32 pmic_rst_reg;
  49. u32 rst_lprst_mask; /* Long-press reset timeout bitmask */
  50. };
  51. static const struct mtk_pmic_regs mt6397_regs = {
  52. .keys_regs[MTK_PMIC_PWRKEY_INDEX] =
  53. MTK_PMIC_KEYS_REGS(MT6397_CHRSTATUS,
  54. 0x8, MT6397_INT_RSV, 0x10, MTK_PMIC_PWRKEY_RST),
  55. .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
  56. MTK_PMIC_KEYS_REGS(MT6397_OCSTATUS2,
  57. 0x10, MT6397_INT_RSV, 0x8, MTK_PMIC_HOMEKEY_RST),
  58. .pmic_rst_reg = MT6397_TOP_RST_MISC,
  59. .rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
  60. };
  61. static const struct mtk_pmic_regs mt6323_regs = {
  62. .keys_regs[MTK_PMIC_PWRKEY_INDEX] =
  63. MTK_PMIC_KEYS_REGS(MT6323_CHRSTATUS,
  64. 0x2, MT6323_INT_MISC_CON, 0x10, MTK_PMIC_PWRKEY_RST),
  65. .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
  66. MTK_PMIC_KEYS_REGS(MT6323_CHRSTATUS,
  67. 0x4, MT6323_INT_MISC_CON, 0x8, MTK_PMIC_HOMEKEY_RST),
  68. .pmic_rst_reg = MT6323_TOP_RST_MISC,
  69. .rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
  70. };
  71. static const struct mtk_pmic_regs mt6331_regs = {
  72. .keys_regs[MTK_PMIC_PWRKEY_INDEX] =
  73. MTK_PMIC_KEYS_REGS(MT6331_TOPSTATUS, 0x2,
  74. MT6331_INT_MISC_CON, 0x4,
  75. MTK_PMIC_MT6331_PWRKEY_RST),
  76. .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
  77. MTK_PMIC_KEYS_REGS(MT6331_TOPSTATUS, 0x4,
  78. MT6331_INT_MISC_CON, 0x2,
  79. MTK_PMIC_MT6331_HOMEKEY_RST),
  80. .pmic_rst_reg = MT6331_TOP_RST_MISC,
  81. .rst_lprst_mask = MTK_PMIC_MT6331_RST_DU_MASK,
  82. };
  83. static const struct mtk_pmic_regs mt6357_regs = {
  84. .keys_regs[MTK_PMIC_PWRKEY_INDEX] =
  85. MTK_PMIC_KEYS_REGS(MT6357_TOPSTATUS,
  86. 0x2, MT6357_PSC_TOP_INT_CON0, 0x5,
  87. MTK_PMIC_PWRKEY_RST),
  88. .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
  89. MTK_PMIC_KEYS_REGS(MT6357_TOPSTATUS,
  90. 0x8, MT6357_PSC_TOP_INT_CON0, 0xa,
  91. MTK_PMIC_HOMEKEY_INDEX),
  92. .pmic_rst_reg = MT6357_TOP_RST_MISC,
  93. .rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
  94. };
  95. static const struct mtk_pmic_regs mt6358_regs = {
  96. .keys_regs[MTK_PMIC_PWRKEY_INDEX] =
  97. MTK_PMIC_KEYS_REGS(MT6358_TOPSTATUS,
  98. 0x2, MT6358_PSC_TOP_INT_CON0, 0x5,
  99. MTK_PMIC_PWRKEY_RST),
  100. .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
  101. MTK_PMIC_KEYS_REGS(MT6358_TOPSTATUS,
  102. 0x8, MT6358_PSC_TOP_INT_CON0, 0xa,
  103. MTK_PMIC_HOMEKEY_RST),
  104. .pmic_rst_reg = MT6358_TOP_RST_MISC,
  105. .rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
  106. };
  107. struct mtk_pmic_keys_info {
  108. struct mtk_pmic_keys *keys;
  109. const struct mtk_pmic_keys_regs *regs;
  110. unsigned int keycode;
  111. int irq;
  112. int irq_r; /* optional: release irq if different */
  113. bool wakeup:1;
  114. };
  115. struct mtk_pmic_keys {
  116. struct input_dev *input_dev;
  117. struct device *dev;
  118. struct regmap *regmap;
  119. struct mtk_pmic_keys_info keys[MTK_PMIC_MAX_KEY_COUNT];
  120. };
  121. enum mtk_pmic_keys_lp_mode {
  122. LP_DISABLE,
  123. LP_ONEKEY,
  124. LP_TWOKEY,
  125. };
  126. static void mtk_pmic_keys_lp_reset_setup(struct mtk_pmic_keys *keys,
  127. const struct mtk_pmic_regs *regs)
  128. {
  129. const struct mtk_pmic_keys_regs *kregs_home, *kregs_pwr;
  130. u32 long_press_mode, long_press_debounce;
  131. u32 value, mask;
  132. int error;
  133. kregs_home = &regs->keys_regs[MTK_PMIC_HOMEKEY_INDEX];
  134. kregs_pwr = &regs->keys_regs[MTK_PMIC_PWRKEY_INDEX];
  135. error = of_property_read_u32(keys->dev->of_node, "power-off-time-sec",
  136. &long_press_debounce);
  137. if (error)
  138. long_press_debounce = 0;
  139. mask = regs->rst_lprst_mask;
  140. value = long_press_debounce << (ffs(regs->rst_lprst_mask) - 1);
  141. error = of_property_read_u32(keys->dev->of_node,
  142. "mediatek,long-press-mode",
  143. &long_press_mode);
  144. if (error)
  145. long_press_mode = LP_DISABLE;
  146. switch (long_press_mode) {
  147. case LP_TWOKEY:
  148. value |= kregs_home->rst_en_mask;
  149. fallthrough;
  150. case LP_ONEKEY:
  151. value |= kregs_pwr->rst_en_mask;
  152. fallthrough;
  153. case LP_DISABLE:
  154. mask |= kregs_home->rst_en_mask;
  155. mask |= kregs_pwr->rst_en_mask;
  156. break;
  157. default:
  158. break;
  159. }
  160. regmap_update_bits(keys->regmap, regs->pmic_rst_reg, mask, value);
  161. }
  162. static irqreturn_t mtk_pmic_keys_irq_handler_thread(int irq, void *data)
  163. {
  164. struct mtk_pmic_keys_info *info = data;
  165. u32 key_deb, pressed;
  166. regmap_read(info->keys->regmap, info->regs->deb_reg, &key_deb);
  167. key_deb &= info->regs->deb_mask;
  168. pressed = !key_deb;
  169. input_report_key(info->keys->input_dev, info->keycode, pressed);
  170. input_sync(info->keys->input_dev);
  171. dev_dbg(info->keys->dev, "(%s) key =%d using PMIC\n",
  172. pressed ? "pressed" : "released", info->keycode);
  173. return IRQ_HANDLED;
  174. }
  175. static int mtk_pmic_key_setup(struct mtk_pmic_keys *keys,
  176. struct mtk_pmic_keys_info *info)
  177. {
  178. int ret;
  179. info->keys = keys;
  180. ret = regmap_update_bits(keys->regmap, info->regs->intsel_reg,
  181. info->regs->intsel_mask,
  182. info->regs->intsel_mask);
  183. if (ret < 0)
  184. return ret;
  185. ret = devm_request_threaded_irq(keys->dev, info->irq, NULL,
  186. mtk_pmic_keys_irq_handler_thread,
  187. IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
  188. "mtk-pmic-keys", info);
  189. if (ret) {
  190. dev_err(keys->dev, "Failed to request IRQ: %d: %d\n",
  191. info->irq, ret);
  192. return ret;
  193. }
  194. if (info->irq_r > 0) {
  195. ret = devm_request_threaded_irq(keys->dev, info->irq_r, NULL,
  196. mtk_pmic_keys_irq_handler_thread,
  197. IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
  198. "mtk-pmic-keys", info);
  199. if (ret) {
  200. dev_err(keys->dev, "Failed to request IRQ_r: %d: %d\n",
  201. info->irq, ret);
  202. return ret;
  203. }
  204. }
  205. input_set_capability(keys->input_dev, EV_KEY, info->keycode);
  206. return 0;
  207. }
  208. static int mtk_pmic_keys_suspend(struct device *dev)
  209. {
  210. struct mtk_pmic_keys *keys = dev_get_drvdata(dev);
  211. int index;
  212. for (index = 0; index < MTK_PMIC_MAX_KEY_COUNT; index++) {
  213. if (keys->keys[index].wakeup) {
  214. enable_irq_wake(keys->keys[index].irq);
  215. if (keys->keys[index].irq_r > 0)
  216. enable_irq_wake(keys->keys[index].irq_r);
  217. }
  218. }
  219. return 0;
  220. }
  221. static int mtk_pmic_keys_resume(struct device *dev)
  222. {
  223. struct mtk_pmic_keys *keys = dev_get_drvdata(dev);
  224. int index;
  225. for (index = 0; index < MTK_PMIC_MAX_KEY_COUNT; index++) {
  226. if (keys->keys[index].wakeup) {
  227. disable_irq_wake(keys->keys[index].irq);
  228. if (keys->keys[index].irq_r > 0)
  229. disable_irq_wake(keys->keys[index].irq_r);
  230. }
  231. }
  232. return 0;
  233. }
  234. static DEFINE_SIMPLE_DEV_PM_OPS(mtk_pmic_keys_pm_ops, mtk_pmic_keys_suspend,
  235. mtk_pmic_keys_resume);
  236. static const struct of_device_id of_mtk_pmic_keys_match_tbl[] = {
  237. {
  238. .compatible = "mediatek,mt6397-keys",
  239. .data = &mt6397_regs,
  240. }, {
  241. .compatible = "mediatek,mt6323-keys",
  242. .data = &mt6323_regs,
  243. }, {
  244. .compatible = "mediatek,mt6331-keys",
  245. .data = &mt6331_regs,
  246. }, {
  247. .compatible = "mediatek,mt6357-keys",
  248. .data = &mt6357_regs,
  249. }, {
  250. .compatible = "mediatek,mt6358-keys",
  251. .data = &mt6358_regs,
  252. }, {
  253. /* sentinel */
  254. }
  255. };
  256. MODULE_DEVICE_TABLE(of, of_mtk_pmic_keys_match_tbl);
  257. static int mtk_pmic_keys_probe(struct platform_device *pdev)
  258. {
  259. int error, index = 0;
  260. unsigned int keycount;
  261. struct mt6397_chip *pmic_chip = dev_get_drvdata(pdev->dev.parent);
  262. struct device_node *node = pdev->dev.of_node, *child;
  263. static const char *const irqnames[] = { "powerkey", "homekey" };
  264. static const char *const irqnames_r[] = { "powerkey_r", "homekey_r" };
  265. struct mtk_pmic_keys *keys;
  266. const struct mtk_pmic_regs *mtk_pmic_regs;
  267. struct input_dev *input_dev;
  268. const struct of_device_id *of_id =
  269. of_match_device(of_mtk_pmic_keys_match_tbl, &pdev->dev);
  270. keys = devm_kzalloc(&pdev->dev, sizeof(*keys), GFP_KERNEL);
  271. if (!keys)
  272. return -ENOMEM;
  273. keys->dev = &pdev->dev;
  274. keys->regmap = pmic_chip->regmap;
  275. mtk_pmic_regs = of_id->data;
  276. keys->input_dev = input_dev = devm_input_allocate_device(keys->dev);
  277. if (!input_dev) {
  278. dev_err(keys->dev, "input allocate device fail.\n");
  279. return -ENOMEM;
  280. }
  281. input_dev->name = "mtk-pmic-keys";
  282. input_dev->id.bustype = BUS_HOST;
  283. input_dev->id.vendor = 0x0001;
  284. input_dev->id.product = 0x0001;
  285. input_dev->id.version = 0x0001;
  286. keycount = of_get_available_child_count(node);
  287. if (keycount > MTK_PMIC_MAX_KEY_COUNT ||
  288. keycount > ARRAY_SIZE(irqnames)) {
  289. dev_err(keys->dev, "too many keys defined (%d)\n", keycount);
  290. return -EINVAL;
  291. }
  292. for_each_child_of_node(node, child) {
  293. keys->keys[index].regs = &mtk_pmic_regs->keys_regs[index];
  294. keys->keys[index].irq =
  295. platform_get_irq_byname(pdev, irqnames[index]);
  296. if (keys->keys[index].irq < 0) {
  297. of_node_put(child);
  298. return keys->keys[index].irq;
  299. }
  300. if (of_device_is_compatible(node, "mediatek,mt6358-keys")) {
  301. keys->keys[index].irq_r = platform_get_irq_byname(pdev,
  302. irqnames_r[index]);
  303. if (keys->keys[index].irq_r < 0) {
  304. of_node_put(child);
  305. return keys->keys[index].irq_r;
  306. }
  307. }
  308. error = of_property_read_u32(child,
  309. "linux,keycodes", &keys->keys[index].keycode);
  310. if (error) {
  311. dev_err(keys->dev,
  312. "failed to read key:%d linux,keycode property: %d\n",
  313. index, error);
  314. of_node_put(child);
  315. return error;
  316. }
  317. if (of_property_read_bool(child, "wakeup-source"))
  318. keys->keys[index].wakeup = true;
  319. error = mtk_pmic_key_setup(keys, &keys->keys[index]);
  320. if (error) {
  321. of_node_put(child);
  322. return error;
  323. }
  324. index++;
  325. }
  326. error = input_register_device(input_dev);
  327. if (error) {
  328. dev_err(&pdev->dev,
  329. "register input device failed (%d)\n", error);
  330. return error;
  331. }
  332. mtk_pmic_keys_lp_reset_setup(keys, mtk_pmic_regs);
  333. platform_set_drvdata(pdev, keys);
  334. return 0;
  335. }
  336. static struct platform_driver pmic_keys_pdrv = {
  337. .probe = mtk_pmic_keys_probe,
  338. .driver = {
  339. .name = "mtk-pmic-keys",
  340. .of_match_table = of_mtk_pmic_keys_match_tbl,
  341. .pm = pm_sleep_ptr(&mtk_pmic_keys_pm_ops),
  342. },
  343. };
  344. module_platform_driver(pmic_keys_pdrv);
  345. MODULE_LICENSE("GPL v2");
  346. MODULE_AUTHOR("Chen Zhong <chen.zhong@mediatek.com>");
  347. MODULE_DESCRIPTION("MTK pmic-keys driver v0.1");