f81604.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Fintek F81604 USB-to-2CAN controller driver.
  3. *
  4. * Copyright (C) 2023 Ji-Ze Hong (Peter Hong) <peter_hong@fintek.com.tw>
  5. */
  6. #include <linux/bitfield.h>
  7. #include <linux/netdevice.h>
  8. #include <linux/units.h>
  9. #include <linux/usb.h>
  10. #include <linux/can.h>
  11. #include <linux/can/dev.h>
  12. #include <linux/can/error.h>
  13. #include <linux/can/platform/sja1000.h>
  14. #include <linux/unaligned.h>
  15. /* vendor and product id */
  16. #define F81604_VENDOR_ID 0x2c42
  17. #define F81604_PRODUCT_ID 0x1709
  18. #define F81604_CAN_CLOCK (12 * MEGA)
  19. #define F81604_MAX_DEV 2
  20. #define F81604_SET_DEVICE_RETRY 10
  21. #define F81604_USB_TIMEOUT 2000
  22. #define F81604_SET_GET_REGISTER 0xA0
  23. #define F81604_PORT_OFFSET 0x1000
  24. #define F81604_MAX_RX_URBS 4
  25. #define F81604_CMD_DATA 0x00
  26. #define F81604_DLC_LEN_MASK GENMASK(3, 0)
  27. #define F81604_DLC_EFF_BIT BIT(7)
  28. #define F81604_DLC_RTR_BIT BIT(6)
  29. #define F81604_SFF_SHIFT 5
  30. #define F81604_EFF_SHIFT 3
  31. #define F81604_BRP_MASK GENMASK(5, 0)
  32. #define F81604_SJW_MASK GENMASK(7, 6)
  33. #define F81604_SEG1_MASK GENMASK(3, 0)
  34. #define F81604_SEG2_MASK GENMASK(6, 4)
  35. #define F81604_CLEAR_ALC 0
  36. #define F81604_CLEAR_ECC 1
  37. #define F81604_CLEAR_OVERRUN 2
  38. /* device setting */
  39. #define F81604_CTRL_MODE_REG 0x80
  40. #define F81604_TX_ONESHOT (0x03 << 3)
  41. #define F81604_TX_NORMAL (0x01 << 3)
  42. #define F81604_RX_AUTO_RELEASE_BUF BIT(1)
  43. #define F81604_INT_WHEN_CHANGE BIT(0)
  44. #define F81604_TERMINATOR_REG 0x105
  45. #define F81604_CAN0_TERM BIT(2)
  46. #define F81604_CAN1_TERM BIT(3)
  47. #define F81604_TERMINATION_DISABLED CAN_TERMINATION_DISABLED
  48. #define F81604_TERMINATION_ENABLED 120
  49. /* SJA1000 registers - manual section 6.4 (Pelican Mode) */
  50. #define F81604_SJA1000_MOD 0x00
  51. #define F81604_SJA1000_CMR 0x01
  52. #define F81604_SJA1000_IR 0x03
  53. #define F81604_SJA1000_IER 0x04
  54. #define F81604_SJA1000_ALC 0x0B
  55. #define F81604_SJA1000_ECC 0x0C
  56. #define F81604_SJA1000_RXERR 0x0E
  57. #define F81604_SJA1000_TXERR 0x0F
  58. #define F81604_SJA1000_ACCC0 0x10
  59. #define F81604_SJA1000_ACCM0 0x14
  60. #define F81604_MAX_FILTER_CNT 4
  61. /* Common registers - manual section 6.5 */
  62. #define F81604_SJA1000_BTR0 0x06
  63. #define F81604_SJA1000_BTR1 0x07
  64. #define F81604_SJA1000_BTR1_SAMPLE_TRIPLE BIT(7)
  65. #define F81604_SJA1000_OCR 0x08
  66. #define F81604_SJA1000_CDR 0x1F
  67. /* mode register */
  68. #define F81604_SJA1000_MOD_RM 0x01
  69. #define F81604_SJA1000_MOD_LOM 0x02
  70. #define F81604_SJA1000_MOD_STM 0x04
  71. /* commands */
  72. #define F81604_SJA1000_CMD_CDO 0x08
  73. /* interrupt sources */
  74. #define F81604_SJA1000_IRQ_BEI 0x80
  75. #define F81604_SJA1000_IRQ_ALI 0x40
  76. #define F81604_SJA1000_IRQ_EPI 0x20
  77. #define F81604_SJA1000_IRQ_DOI 0x08
  78. #define F81604_SJA1000_IRQ_EI 0x04
  79. #define F81604_SJA1000_IRQ_TI 0x02
  80. #define F81604_SJA1000_IRQ_RI 0x01
  81. #define F81604_SJA1000_IRQ_ALL 0xFF
  82. #define F81604_SJA1000_IRQ_OFF 0x00
  83. /* status register content */
  84. #define F81604_SJA1000_SR_BS 0x80
  85. #define F81604_SJA1000_SR_ES 0x40
  86. #define F81604_SJA1000_SR_TCS 0x08
  87. /* ECC register */
  88. #define F81604_SJA1000_ECC_SEG 0x1F
  89. #define F81604_SJA1000_ECC_DIR 0x20
  90. #define F81604_SJA1000_ECC_BIT 0x00
  91. #define F81604_SJA1000_ECC_FORM 0x40
  92. #define F81604_SJA1000_ECC_STUFF 0x80
  93. #define F81604_SJA1000_ECC_MASK 0xc0
  94. /* ALC register */
  95. #define F81604_SJA1000_ALC_MASK 0x1f
  96. /* table of devices that work with this driver */
  97. static const struct usb_device_id f81604_table[] = {
  98. { USB_DEVICE(F81604_VENDOR_ID, F81604_PRODUCT_ID) },
  99. {} /* Terminating entry */
  100. };
  101. MODULE_DEVICE_TABLE(usb, f81604_table);
  102. static const struct ethtool_ops f81604_ethtool_ops = {
  103. .get_ts_info = ethtool_op_get_ts_info,
  104. };
  105. static const u16 f81604_termination[] = { F81604_TERMINATION_DISABLED,
  106. F81604_TERMINATION_ENABLED };
  107. struct f81604_priv {
  108. struct net_device *netdev[F81604_MAX_DEV];
  109. };
  110. struct f81604_port_priv {
  111. struct can_priv can;
  112. struct net_device *netdev;
  113. struct sk_buff *echo_skb;
  114. unsigned long clear_flags;
  115. struct work_struct clear_reg_work;
  116. struct usb_device *dev;
  117. struct usb_interface *intf;
  118. struct usb_anchor urbs_anchor;
  119. };
  120. /* Interrupt endpoint data format:
  121. * Byte 0: Status register.
  122. * Byte 1: Interrupt register.
  123. * Byte 2: Interrupt enable register.
  124. * Byte 3: Arbitration lost capture(ALC) register.
  125. * Byte 4: Error code capture(ECC) register.
  126. * Byte 5: Error warning limit register.
  127. * Byte 6: RX error counter register.
  128. * Byte 7: TX error counter register.
  129. * Byte 8: Reserved.
  130. */
  131. struct f81604_int_data {
  132. u8 sr;
  133. u8 isrc;
  134. u8 ier;
  135. u8 alc;
  136. u8 ecc;
  137. u8 ewlr;
  138. u8 rxerr;
  139. u8 txerr;
  140. u8 val;
  141. } __packed __aligned(4);
  142. struct f81604_sff {
  143. __be16 id;
  144. u8 data[CAN_MAX_DLEN];
  145. } __packed __aligned(2);
  146. struct f81604_eff {
  147. __be32 id;
  148. u8 data[CAN_MAX_DLEN];
  149. } __packed __aligned(2);
  150. struct f81604_can_frame {
  151. u8 cmd;
  152. /* According for F81604 DLC define:
  153. * bit 3~0: data length (0~8)
  154. * bit6: is RTR flag.
  155. * bit7: is EFF frame.
  156. */
  157. u8 dlc;
  158. union {
  159. struct f81604_sff sff;
  160. struct f81604_eff eff;
  161. };
  162. } __packed __aligned(2);
  163. static const u8 bulk_in_addr[F81604_MAX_DEV] = { 2, 4 };
  164. static const u8 bulk_out_addr[F81604_MAX_DEV] = { 1, 3 };
  165. static const u8 int_in_addr[F81604_MAX_DEV] = { 1, 3 };
  166. static int f81604_write(struct usb_device *dev, u16 reg, u8 data)
  167. {
  168. int ret;
  169. ret = usb_control_msg_send(dev, 0, F81604_SET_GET_REGISTER,
  170. USB_TYPE_VENDOR | USB_DIR_OUT, 0, reg,
  171. &data, sizeof(data), F81604_USB_TIMEOUT,
  172. GFP_KERNEL);
  173. if (ret)
  174. dev_err(&dev->dev, "%s: reg: %x data: %x failed: %pe\n",
  175. __func__, reg, data, ERR_PTR(ret));
  176. return ret;
  177. }
  178. static int f81604_read(struct usb_device *dev, u16 reg, u8 *data)
  179. {
  180. int ret;
  181. ret = usb_control_msg_recv(dev, 0, F81604_SET_GET_REGISTER,
  182. USB_TYPE_VENDOR | USB_DIR_IN, 0, reg, data,
  183. sizeof(*data), F81604_USB_TIMEOUT,
  184. GFP_KERNEL);
  185. if (ret < 0)
  186. dev_err(&dev->dev, "%s: reg: %x failed: %pe\n", __func__, reg,
  187. ERR_PTR(ret));
  188. return ret;
  189. }
  190. static int f81604_update_bits(struct usb_device *dev, u16 reg, u8 mask,
  191. u8 data)
  192. {
  193. int ret;
  194. u8 tmp;
  195. ret = f81604_read(dev, reg, &tmp);
  196. if (ret)
  197. return ret;
  198. tmp &= ~mask;
  199. tmp |= (mask & data);
  200. return f81604_write(dev, reg, tmp);
  201. }
  202. static int f81604_sja1000_write(struct f81604_port_priv *priv, u16 reg,
  203. u8 data)
  204. {
  205. int port = priv->netdev->dev_port;
  206. int real_reg;
  207. real_reg = reg + F81604_PORT_OFFSET * port + F81604_PORT_OFFSET;
  208. return f81604_write(priv->dev, real_reg, data);
  209. }
  210. static int f81604_sja1000_read(struct f81604_port_priv *priv, u16 reg,
  211. u8 *data)
  212. {
  213. int port = priv->netdev->dev_port;
  214. int real_reg;
  215. real_reg = reg + F81604_PORT_OFFSET * port + F81604_PORT_OFFSET;
  216. return f81604_read(priv->dev, real_reg, data);
  217. }
  218. static int f81604_set_reset_mode(struct f81604_port_priv *priv)
  219. {
  220. int ret, i;
  221. u8 tmp;
  222. /* disable interrupts */
  223. ret = f81604_sja1000_write(priv, F81604_SJA1000_IER,
  224. F81604_SJA1000_IRQ_OFF);
  225. if (ret)
  226. return ret;
  227. for (i = 0; i < F81604_SET_DEVICE_RETRY; i++) {
  228. ret = f81604_sja1000_read(priv, F81604_SJA1000_MOD, &tmp);
  229. if (ret)
  230. return ret;
  231. /* check reset bit */
  232. if (tmp & F81604_SJA1000_MOD_RM) {
  233. priv->can.state = CAN_STATE_STOPPED;
  234. return 0;
  235. }
  236. /* reset chip */
  237. ret = f81604_sja1000_write(priv, F81604_SJA1000_MOD,
  238. F81604_SJA1000_MOD_RM);
  239. if (ret)
  240. return ret;
  241. }
  242. return -EPERM;
  243. }
  244. static int f81604_set_normal_mode(struct f81604_port_priv *priv)
  245. {
  246. u8 tmp, ier = 0;
  247. u8 mod_reg = 0;
  248. int ret, i;
  249. for (i = 0; i < F81604_SET_DEVICE_RETRY; i++) {
  250. ret = f81604_sja1000_read(priv, F81604_SJA1000_MOD, &tmp);
  251. if (ret)
  252. return ret;
  253. /* check reset bit */
  254. if ((tmp & F81604_SJA1000_MOD_RM) == 0) {
  255. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  256. /* enable interrupts, RI handled by bulk-in */
  257. ier = F81604_SJA1000_IRQ_ALL & ~F81604_SJA1000_IRQ_RI;
  258. if (!(priv->can.ctrlmode &
  259. CAN_CTRLMODE_BERR_REPORTING))
  260. ier &= ~F81604_SJA1000_IRQ_BEI;
  261. return f81604_sja1000_write(priv, F81604_SJA1000_IER,
  262. ier);
  263. }
  264. /* set chip to normal mode */
  265. if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
  266. mod_reg |= F81604_SJA1000_MOD_LOM;
  267. if (priv->can.ctrlmode & CAN_CTRLMODE_PRESUME_ACK)
  268. mod_reg |= F81604_SJA1000_MOD_STM;
  269. ret = f81604_sja1000_write(priv, F81604_SJA1000_MOD, mod_reg);
  270. if (ret)
  271. return ret;
  272. }
  273. return -EPERM;
  274. }
  275. static int f81604_chipset_init(struct f81604_port_priv *priv)
  276. {
  277. int i, ret;
  278. /* set clock divider and output control register */
  279. ret = f81604_sja1000_write(priv, F81604_SJA1000_CDR,
  280. CDR_CBP | CDR_PELICAN);
  281. if (ret)
  282. return ret;
  283. /* set acceptance filter (accept all) */
  284. for (i = 0; i < F81604_MAX_FILTER_CNT; ++i) {
  285. ret = f81604_sja1000_write(priv, F81604_SJA1000_ACCC0 + i, 0);
  286. if (ret)
  287. return ret;
  288. }
  289. for (i = 0; i < F81604_MAX_FILTER_CNT; ++i) {
  290. ret = f81604_sja1000_write(priv, F81604_SJA1000_ACCM0 + i,
  291. 0xFF);
  292. if (ret)
  293. return ret;
  294. }
  295. return f81604_sja1000_write(priv, F81604_SJA1000_OCR,
  296. OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL |
  297. OCR_MODE_NORMAL);
  298. }
  299. static void f81604_process_rx_packet(struct net_device *netdev,
  300. struct f81604_can_frame *frame)
  301. {
  302. struct net_device_stats *stats = &netdev->stats;
  303. struct can_frame *cf;
  304. struct sk_buff *skb;
  305. if (frame->cmd != F81604_CMD_DATA)
  306. return;
  307. skb = alloc_can_skb(netdev, &cf);
  308. if (!skb) {
  309. stats->rx_dropped++;
  310. return;
  311. }
  312. cf->len = can_cc_dlc2len(frame->dlc & F81604_DLC_LEN_MASK);
  313. if (frame->dlc & F81604_DLC_EFF_BIT) {
  314. cf->can_id = get_unaligned_be32(&frame->eff.id) >>
  315. F81604_EFF_SHIFT;
  316. cf->can_id |= CAN_EFF_FLAG;
  317. if (!(frame->dlc & F81604_DLC_RTR_BIT))
  318. memcpy(cf->data, frame->eff.data, cf->len);
  319. } else {
  320. cf->can_id = get_unaligned_be16(&frame->sff.id) >>
  321. F81604_SFF_SHIFT;
  322. if (!(frame->dlc & F81604_DLC_RTR_BIT))
  323. memcpy(cf->data, frame->sff.data, cf->len);
  324. }
  325. if (frame->dlc & F81604_DLC_RTR_BIT)
  326. cf->can_id |= CAN_RTR_FLAG;
  327. else
  328. stats->rx_bytes += cf->len;
  329. stats->rx_packets++;
  330. netif_rx(skb);
  331. }
  332. static void f81604_read_bulk_callback(struct urb *urb)
  333. {
  334. struct f81604_can_frame *frame = urb->transfer_buffer;
  335. struct net_device *netdev = urb->context;
  336. int ret;
  337. if (!netif_device_present(netdev))
  338. return;
  339. if (urb->status)
  340. netdev_info(netdev, "%s: URB aborted %pe\n", __func__,
  341. ERR_PTR(urb->status));
  342. switch (urb->status) {
  343. case 0: /* success */
  344. break;
  345. case -ENOENT:
  346. case -EPIPE:
  347. case -EPROTO:
  348. case -ESHUTDOWN:
  349. return;
  350. default:
  351. goto resubmit_urb;
  352. }
  353. if (urb->actual_length != sizeof(*frame)) {
  354. netdev_warn(netdev, "URB length %u not equal to %zu\n",
  355. urb->actual_length, sizeof(*frame));
  356. goto resubmit_urb;
  357. }
  358. f81604_process_rx_packet(netdev, frame);
  359. resubmit_urb:
  360. ret = usb_submit_urb(urb, GFP_ATOMIC);
  361. if (ret == -ENODEV)
  362. netif_device_detach(netdev);
  363. else if (ret)
  364. netdev_err(netdev,
  365. "%s: failed to resubmit read bulk urb: %pe\n",
  366. __func__, ERR_PTR(ret));
  367. }
  368. static void f81604_handle_tx(struct f81604_port_priv *priv,
  369. struct f81604_int_data *data)
  370. {
  371. struct net_device *netdev = priv->netdev;
  372. struct net_device_stats *stats = &netdev->stats;
  373. /* transmission buffer released */
  374. if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT &&
  375. !(data->sr & F81604_SJA1000_SR_TCS)) {
  376. stats->tx_errors++;
  377. can_free_echo_skb(netdev, 0, NULL);
  378. } else {
  379. /* transmission complete */
  380. stats->tx_bytes += can_get_echo_skb(netdev, 0, NULL);
  381. stats->tx_packets++;
  382. }
  383. netif_wake_queue(netdev);
  384. }
  385. static void f81604_handle_can_bus_errors(struct f81604_port_priv *priv,
  386. struct f81604_int_data *data)
  387. {
  388. enum can_state can_state = priv->can.state;
  389. struct net_device *netdev = priv->netdev;
  390. struct net_device_stats *stats = &netdev->stats;
  391. struct can_frame *cf;
  392. struct sk_buff *skb;
  393. /* Note: ALC/ECC will not auto clear by read here, must be cleared by
  394. * read register (via clear_reg_work).
  395. */
  396. skb = alloc_can_err_skb(netdev, &cf);
  397. if (skb) {
  398. cf->can_id |= CAN_ERR_CNT;
  399. cf->data[6] = data->txerr;
  400. cf->data[7] = data->rxerr;
  401. }
  402. if (data->isrc & F81604_SJA1000_IRQ_DOI) {
  403. /* data overrun interrupt */
  404. netdev_dbg(netdev, "data overrun interrupt\n");
  405. if (skb) {
  406. cf->can_id |= CAN_ERR_CRTL;
  407. cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  408. }
  409. stats->rx_over_errors++;
  410. stats->rx_errors++;
  411. set_bit(F81604_CLEAR_OVERRUN, &priv->clear_flags);
  412. }
  413. if (data->isrc & F81604_SJA1000_IRQ_EI) {
  414. /* error warning interrupt */
  415. netdev_dbg(netdev, "error warning interrupt\n");
  416. if (data->sr & F81604_SJA1000_SR_BS)
  417. can_state = CAN_STATE_BUS_OFF;
  418. else if (data->sr & F81604_SJA1000_SR_ES)
  419. can_state = CAN_STATE_ERROR_WARNING;
  420. else
  421. can_state = CAN_STATE_ERROR_ACTIVE;
  422. }
  423. if (data->isrc & F81604_SJA1000_IRQ_BEI) {
  424. /* bus error interrupt */
  425. netdev_dbg(netdev, "bus error interrupt\n");
  426. priv->can.can_stats.bus_error++;
  427. if (skb) {
  428. cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  429. /* set error type */
  430. switch (data->ecc & F81604_SJA1000_ECC_MASK) {
  431. case F81604_SJA1000_ECC_BIT:
  432. cf->data[2] |= CAN_ERR_PROT_BIT;
  433. break;
  434. case F81604_SJA1000_ECC_FORM:
  435. cf->data[2] |= CAN_ERR_PROT_FORM;
  436. break;
  437. case F81604_SJA1000_ECC_STUFF:
  438. cf->data[2] |= CAN_ERR_PROT_STUFF;
  439. break;
  440. default:
  441. break;
  442. }
  443. /* set error location */
  444. cf->data[3] = data->ecc & F81604_SJA1000_ECC_SEG;
  445. }
  446. /* Error occurred during transmission? */
  447. if ((data->ecc & F81604_SJA1000_ECC_DIR) == 0) {
  448. stats->tx_errors++;
  449. if (skb)
  450. cf->data[2] |= CAN_ERR_PROT_TX;
  451. } else {
  452. stats->rx_errors++;
  453. }
  454. set_bit(F81604_CLEAR_ECC, &priv->clear_flags);
  455. }
  456. if (data->isrc & F81604_SJA1000_IRQ_EPI) {
  457. if (can_state == CAN_STATE_ERROR_PASSIVE)
  458. can_state = CAN_STATE_ERROR_WARNING;
  459. else
  460. can_state = CAN_STATE_ERROR_PASSIVE;
  461. /* error passive interrupt */
  462. netdev_dbg(netdev, "error passive interrupt: %d\n", can_state);
  463. }
  464. if (data->isrc & F81604_SJA1000_IRQ_ALI) {
  465. /* arbitration lost interrupt */
  466. netdev_dbg(netdev, "arbitration lost interrupt\n");
  467. priv->can.can_stats.arbitration_lost++;
  468. if (skb) {
  469. cf->can_id |= CAN_ERR_LOSTARB;
  470. cf->data[0] = data->alc & F81604_SJA1000_ALC_MASK;
  471. }
  472. set_bit(F81604_CLEAR_ALC, &priv->clear_flags);
  473. }
  474. if (can_state != priv->can.state) {
  475. enum can_state tx_state, rx_state;
  476. tx_state = data->txerr >= data->rxerr ? can_state : 0;
  477. rx_state = data->txerr <= data->rxerr ? can_state : 0;
  478. can_change_state(netdev, cf, tx_state, rx_state);
  479. if (can_state == CAN_STATE_BUS_OFF)
  480. can_bus_off(netdev);
  481. }
  482. if (priv->clear_flags)
  483. schedule_work(&priv->clear_reg_work);
  484. if (skb)
  485. netif_rx(skb);
  486. }
  487. static void f81604_read_int_callback(struct urb *urb)
  488. {
  489. struct f81604_int_data *data = urb->transfer_buffer;
  490. struct net_device *netdev = urb->context;
  491. struct f81604_port_priv *priv;
  492. int ret;
  493. priv = netdev_priv(netdev);
  494. if (!netif_device_present(netdev))
  495. return;
  496. if (urb->status)
  497. netdev_info(netdev, "%s: Int URB aborted: %pe\n", __func__,
  498. ERR_PTR(urb->status));
  499. switch (urb->status) {
  500. case 0: /* success */
  501. break;
  502. case -ENOENT:
  503. case -EPIPE:
  504. case -EPROTO:
  505. case -ESHUTDOWN:
  506. return;
  507. default:
  508. goto resubmit_urb;
  509. }
  510. /* handle Errors */
  511. if (data->isrc & (F81604_SJA1000_IRQ_DOI | F81604_SJA1000_IRQ_EI |
  512. F81604_SJA1000_IRQ_BEI | F81604_SJA1000_IRQ_EPI |
  513. F81604_SJA1000_IRQ_ALI))
  514. f81604_handle_can_bus_errors(priv, data);
  515. /* handle TX */
  516. if (priv->can.state != CAN_STATE_BUS_OFF &&
  517. (data->isrc & F81604_SJA1000_IRQ_TI))
  518. f81604_handle_tx(priv, data);
  519. resubmit_urb:
  520. ret = usb_submit_urb(urb, GFP_ATOMIC);
  521. if (ret == -ENODEV)
  522. netif_device_detach(netdev);
  523. else if (ret)
  524. netdev_err(netdev, "%s: failed to resubmit int urb: %pe\n",
  525. __func__, ERR_PTR(ret));
  526. }
  527. static void f81604_unregister_urbs(struct f81604_port_priv *priv)
  528. {
  529. usb_kill_anchored_urbs(&priv->urbs_anchor);
  530. }
  531. static int f81604_register_urbs(struct f81604_port_priv *priv)
  532. {
  533. struct net_device *netdev = priv->netdev;
  534. struct f81604_int_data *int_data;
  535. int id = netdev->dev_port;
  536. struct urb *int_urb;
  537. int rx_urb_cnt;
  538. int ret;
  539. for (rx_urb_cnt = 0; rx_urb_cnt < F81604_MAX_RX_URBS; ++rx_urb_cnt) {
  540. struct f81604_can_frame *frame;
  541. struct urb *rx_urb;
  542. rx_urb = usb_alloc_urb(0, GFP_KERNEL);
  543. if (!rx_urb) {
  544. ret = -ENOMEM;
  545. break;
  546. }
  547. frame = kmalloc(sizeof(*frame), GFP_KERNEL);
  548. if (!frame) {
  549. usb_free_urb(rx_urb);
  550. ret = -ENOMEM;
  551. break;
  552. }
  553. usb_fill_bulk_urb(rx_urb, priv->dev,
  554. usb_rcvbulkpipe(priv->dev, bulk_in_addr[id]),
  555. frame, sizeof(*frame),
  556. f81604_read_bulk_callback, netdev);
  557. rx_urb->transfer_flags |= URB_FREE_BUFFER;
  558. usb_anchor_urb(rx_urb, &priv->urbs_anchor);
  559. ret = usb_submit_urb(rx_urb, GFP_KERNEL);
  560. if (ret) {
  561. usb_unanchor_urb(rx_urb);
  562. usb_free_urb(rx_urb);
  563. break;
  564. }
  565. /* Drop reference, USB core will take care of freeing it */
  566. usb_free_urb(rx_urb);
  567. }
  568. if (rx_urb_cnt == 0) {
  569. netdev_warn(netdev, "%s: submit rx urb failed: %pe\n",
  570. __func__, ERR_PTR(ret));
  571. goto error;
  572. }
  573. int_urb = usb_alloc_urb(0, GFP_KERNEL);
  574. if (!int_urb) {
  575. ret = -ENOMEM;
  576. goto error;
  577. }
  578. int_data = kmalloc(sizeof(*int_data), GFP_KERNEL);
  579. if (!int_data) {
  580. usb_free_urb(int_urb);
  581. ret = -ENOMEM;
  582. goto error;
  583. }
  584. usb_fill_int_urb(int_urb, priv->dev,
  585. usb_rcvintpipe(priv->dev, int_in_addr[id]), int_data,
  586. sizeof(*int_data), f81604_read_int_callback, netdev,
  587. 1);
  588. int_urb->transfer_flags |= URB_FREE_BUFFER;
  589. usb_anchor_urb(int_urb, &priv->urbs_anchor);
  590. ret = usb_submit_urb(int_urb, GFP_KERNEL);
  591. if (ret) {
  592. usb_unanchor_urb(int_urb);
  593. usb_free_urb(int_urb);
  594. netdev_warn(netdev, "%s: submit int urb failed: %pe\n",
  595. __func__, ERR_PTR(ret));
  596. goto error;
  597. }
  598. /* Drop reference, USB core will take care of freeing it */
  599. usb_free_urb(int_urb);
  600. return 0;
  601. error:
  602. f81604_unregister_urbs(priv);
  603. return ret;
  604. }
  605. static int f81604_start(struct net_device *netdev)
  606. {
  607. struct f81604_port_priv *priv = netdev_priv(netdev);
  608. int ret;
  609. u8 mode;
  610. u8 tmp;
  611. mode = F81604_RX_AUTO_RELEASE_BUF | F81604_INT_WHEN_CHANGE;
  612. /* Set TR/AT mode */
  613. if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
  614. mode |= F81604_TX_ONESHOT;
  615. else
  616. mode |= F81604_TX_NORMAL;
  617. ret = f81604_sja1000_write(priv, F81604_CTRL_MODE_REG, mode);
  618. if (ret)
  619. return ret;
  620. /* set reset mode */
  621. ret = f81604_set_reset_mode(priv);
  622. if (ret)
  623. return ret;
  624. ret = f81604_chipset_init(priv);
  625. if (ret)
  626. return ret;
  627. /* Clear error counters and error code capture */
  628. ret = f81604_sja1000_write(priv, F81604_SJA1000_TXERR, 0);
  629. if (ret)
  630. return ret;
  631. ret = f81604_sja1000_write(priv, F81604_SJA1000_RXERR, 0);
  632. if (ret)
  633. return ret;
  634. /* Read clear for ECC/ALC/IR register */
  635. ret = f81604_sja1000_read(priv, F81604_SJA1000_ECC, &tmp);
  636. if (ret)
  637. return ret;
  638. ret = f81604_sja1000_read(priv, F81604_SJA1000_ALC, &tmp);
  639. if (ret)
  640. return ret;
  641. ret = f81604_sja1000_read(priv, F81604_SJA1000_IR, &tmp);
  642. if (ret)
  643. return ret;
  644. ret = f81604_register_urbs(priv);
  645. if (ret)
  646. return ret;
  647. ret = f81604_set_normal_mode(priv);
  648. if (ret) {
  649. f81604_unregister_urbs(priv);
  650. return ret;
  651. }
  652. return 0;
  653. }
  654. static int f81604_set_bittiming(struct net_device *dev)
  655. {
  656. struct f81604_port_priv *priv = netdev_priv(dev);
  657. struct can_bittiming *bt = &priv->can.bittiming;
  658. u8 btr0, btr1;
  659. int ret;
  660. btr0 = FIELD_PREP(F81604_BRP_MASK, bt->brp - 1) |
  661. FIELD_PREP(F81604_SJW_MASK, bt->sjw - 1);
  662. btr1 = FIELD_PREP(F81604_SEG1_MASK,
  663. bt->prop_seg + bt->phase_seg1 - 1) |
  664. FIELD_PREP(F81604_SEG2_MASK, bt->phase_seg2 - 1);
  665. if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
  666. btr1 |= F81604_SJA1000_BTR1_SAMPLE_TRIPLE;
  667. ret = f81604_sja1000_write(priv, F81604_SJA1000_BTR0, btr0);
  668. if (ret) {
  669. netdev_warn(dev, "%s: Set BTR0 failed: %pe\n", __func__,
  670. ERR_PTR(ret));
  671. return ret;
  672. }
  673. ret = f81604_sja1000_write(priv, F81604_SJA1000_BTR1, btr1);
  674. if (ret) {
  675. netdev_warn(dev, "%s: Set BTR1 failed: %pe\n", __func__,
  676. ERR_PTR(ret));
  677. return ret;
  678. }
  679. return 0;
  680. }
  681. static int f81604_set_mode(struct net_device *netdev, enum can_mode mode)
  682. {
  683. int ret;
  684. switch (mode) {
  685. case CAN_MODE_START:
  686. ret = f81604_start(netdev);
  687. if (!ret && netif_queue_stopped(netdev))
  688. netif_wake_queue(netdev);
  689. break;
  690. default:
  691. ret = -EOPNOTSUPP;
  692. }
  693. return ret;
  694. }
  695. static void f81604_write_bulk_callback(struct urb *urb)
  696. {
  697. struct net_device *netdev = urb->context;
  698. if (!netif_device_present(netdev))
  699. return;
  700. if (urb->status)
  701. netdev_info(netdev, "%s: Tx URB error: %pe\n", __func__,
  702. ERR_PTR(urb->status));
  703. }
  704. static void f81604_clear_reg_work(struct work_struct *work)
  705. {
  706. struct f81604_port_priv *priv;
  707. u8 tmp;
  708. priv = container_of(work, struct f81604_port_priv, clear_reg_work);
  709. /* dummy read for clear Arbitration lost capture(ALC) register. */
  710. if (test_and_clear_bit(F81604_CLEAR_ALC, &priv->clear_flags))
  711. f81604_sja1000_read(priv, F81604_SJA1000_ALC, &tmp);
  712. /* dummy read for clear Error code capture(ECC) register. */
  713. if (test_and_clear_bit(F81604_CLEAR_ECC, &priv->clear_flags))
  714. f81604_sja1000_read(priv, F81604_SJA1000_ECC, &tmp);
  715. /* dummy write for clear data overrun flag. */
  716. if (test_and_clear_bit(F81604_CLEAR_OVERRUN, &priv->clear_flags))
  717. f81604_sja1000_write(priv, F81604_SJA1000_CMR,
  718. F81604_SJA1000_CMD_CDO);
  719. }
  720. static netdev_tx_t f81604_start_xmit(struct sk_buff *skb,
  721. struct net_device *netdev)
  722. {
  723. struct can_frame *cf = (struct can_frame *)skb->data;
  724. struct f81604_port_priv *priv = netdev_priv(netdev);
  725. struct net_device_stats *stats = &netdev->stats;
  726. struct f81604_can_frame *frame;
  727. struct urb *write_urb;
  728. int ret;
  729. if (can_dev_dropped_skb(netdev, skb))
  730. return NETDEV_TX_OK;
  731. netif_stop_queue(netdev);
  732. write_urb = usb_alloc_urb(0, GFP_ATOMIC);
  733. if (!write_urb)
  734. goto nomem_urb;
  735. frame = kzalloc(sizeof(*frame), GFP_ATOMIC);
  736. if (!frame)
  737. goto nomem_buf;
  738. usb_fill_bulk_urb(write_urb, priv->dev,
  739. usb_sndbulkpipe(priv->dev,
  740. bulk_out_addr[netdev->dev_port]),
  741. frame, sizeof(*frame), f81604_write_bulk_callback,
  742. priv->netdev);
  743. write_urb->transfer_flags |= URB_FREE_BUFFER;
  744. frame->cmd = F81604_CMD_DATA;
  745. frame->dlc = cf->len;
  746. if (cf->can_id & CAN_RTR_FLAG)
  747. frame->dlc |= F81604_DLC_RTR_BIT;
  748. if (cf->can_id & CAN_EFF_FLAG) {
  749. u32 id = (cf->can_id & CAN_EFF_MASK) << F81604_EFF_SHIFT;
  750. put_unaligned_be32(id, &frame->eff.id);
  751. frame->dlc |= F81604_DLC_EFF_BIT;
  752. if (!(cf->can_id & CAN_RTR_FLAG))
  753. memcpy(&frame->eff.data, cf->data, cf->len);
  754. } else {
  755. u32 id = (cf->can_id & CAN_SFF_MASK) << F81604_SFF_SHIFT;
  756. put_unaligned_be16(id, &frame->sff.id);
  757. if (!(cf->can_id & CAN_RTR_FLAG))
  758. memcpy(&frame->sff.data, cf->data, cf->len);
  759. }
  760. can_put_echo_skb(skb, netdev, 0, 0);
  761. ret = usb_submit_urb(write_urb, GFP_ATOMIC);
  762. if (ret) {
  763. netdev_err(netdev, "%s: failed to resubmit tx bulk urb: %pe\n",
  764. __func__, ERR_PTR(ret));
  765. can_free_echo_skb(netdev, 0, NULL);
  766. stats->tx_dropped++;
  767. stats->tx_errors++;
  768. if (ret == -ENODEV)
  769. netif_device_detach(netdev);
  770. else
  771. netif_wake_queue(netdev);
  772. }
  773. /* let usb core take care of this urb */
  774. usb_free_urb(write_urb);
  775. return NETDEV_TX_OK;
  776. nomem_buf:
  777. usb_free_urb(write_urb);
  778. nomem_urb:
  779. dev_kfree_skb(skb);
  780. stats->tx_dropped++;
  781. stats->tx_errors++;
  782. netif_wake_queue(netdev);
  783. return NETDEV_TX_OK;
  784. }
  785. static int f81604_get_berr_counter(const struct net_device *netdev,
  786. struct can_berr_counter *bec)
  787. {
  788. struct f81604_port_priv *priv = netdev_priv(netdev);
  789. u8 txerr, rxerr;
  790. int ret;
  791. ret = f81604_sja1000_read(priv, F81604_SJA1000_TXERR, &txerr);
  792. if (ret)
  793. return ret;
  794. ret = f81604_sja1000_read(priv, F81604_SJA1000_RXERR, &rxerr);
  795. if (ret)
  796. return ret;
  797. bec->txerr = txerr;
  798. bec->rxerr = rxerr;
  799. return 0;
  800. }
  801. /* Open USB device */
  802. static int f81604_open(struct net_device *netdev)
  803. {
  804. int ret;
  805. ret = open_candev(netdev);
  806. if (ret)
  807. return ret;
  808. ret = f81604_start(netdev);
  809. if (ret) {
  810. if (ret == -ENODEV)
  811. netif_device_detach(netdev);
  812. close_candev(netdev);
  813. return ret;
  814. }
  815. netif_start_queue(netdev);
  816. return 0;
  817. }
  818. /* Close USB device */
  819. static int f81604_close(struct net_device *netdev)
  820. {
  821. struct f81604_port_priv *priv = netdev_priv(netdev);
  822. f81604_set_reset_mode(priv);
  823. netif_stop_queue(netdev);
  824. cancel_work_sync(&priv->clear_reg_work);
  825. close_candev(netdev);
  826. f81604_unregister_urbs(priv);
  827. return 0;
  828. }
  829. static const struct net_device_ops f81604_netdev_ops = {
  830. .ndo_open = f81604_open,
  831. .ndo_stop = f81604_close,
  832. .ndo_start_xmit = f81604_start_xmit,
  833. .ndo_change_mtu = can_change_mtu,
  834. };
  835. static const struct can_bittiming_const f81604_bittiming_const = {
  836. .name = KBUILD_MODNAME,
  837. .tseg1_min = 1,
  838. .tseg1_max = 16,
  839. .tseg2_min = 1,
  840. .tseg2_max = 8,
  841. .sjw_max = 4,
  842. .brp_min = 1,
  843. .brp_max = 64,
  844. .brp_inc = 1,
  845. };
  846. /* Called by the usb core when driver is unloaded or device is removed */
  847. static void f81604_disconnect(struct usb_interface *intf)
  848. {
  849. struct f81604_priv *priv = usb_get_intfdata(intf);
  850. int i;
  851. for (i = 0; i < ARRAY_SIZE(priv->netdev); ++i) {
  852. if (!priv->netdev[i])
  853. continue;
  854. unregister_netdev(priv->netdev[i]);
  855. free_candev(priv->netdev[i]);
  856. }
  857. }
  858. static int __f81604_set_termination(struct usb_device *dev, int idx, u16 term)
  859. {
  860. u8 mask, data = 0;
  861. if (idx == 0)
  862. mask = F81604_CAN0_TERM;
  863. else
  864. mask = F81604_CAN1_TERM;
  865. if (term)
  866. data = mask;
  867. return f81604_update_bits(dev, F81604_TERMINATOR_REG, mask, data);
  868. }
  869. static int f81604_set_termination(struct net_device *netdev, u16 term)
  870. {
  871. struct f81604_port_priv *port_priv = netdev_priv(netdev);
  872. ASSERT_RTNL();
  873. return __f81604_set_termination(port_priv->dev, netdev->dev_port,
  874. term);
  875. }
  876. static int f81604_probe(struct usb_interface *intf,
  877. const struct usb_device_id *id)
  878. {
  879. struct usb_device *dev = interface_to_usbdev(intf);
  880. struct net_device *netdev;
  881. struct f81604_priv *priv;
  882. int i, ret;
  883. priv = devm_kzalloc(&intf->dev, sizeof(*priv), GFP_KERNEL);
  884. if (!priv)
  885. return -ENOMEM;
  886. usb_set_intfdata(intf, priv);
  887. for (i = 0; i < ARRAY_SIZE(priv->netdev); ++i) {
  888. ret = __f81604_set_termination(dev, i, 0);
  889. if (ret) {
  890. dev_err(&intf->dev,
  891. "Setting termination of CH#%d failed: %pe\n",
  892. i, ERR_PTR(ret));
  893. return ret;
  894. }
  895. }
  896. for (i = 0; i < ARRAY_SIZE(priv->netdev); ++i) {
  897. struct f81604_port_priv *port_priv;
  898. netdev = alloc_candev(sizeof(*port_priv), 1);
  899. if (!netdev) {
  900. dev_err(&intf->dev, "Couldn't alloc candev: %d\n", i);
  901. ret = -ENOMEM;
  902. goto failure_cleanup;
  903. }
  904. port_priv = netdev_priv(netdev);
  905. INIT_WORK(&port_priv->clear_reg_work, f81604_clear_reg_work);
  906. init_usb_anchor(&port_priv->urbs_anchor);
  907. port_priv->intf = intf;
  908. port_priv->dev = dev;
  909. port_priv->netdev = netdev;
  910. port_priv->can.clock.freq = F81604_CAN_CLOCK;
  911. port_priv->can.termination_const = f81604_termination;
  912. port_priv->can.termination_const_cnt =
  913. ARRAY_SIZE(f81604_termination);
  914. port_priv->can.bittiming_const = &f81604_bittiming_const;
  915. port_priv->can.do_set_bittiming = f81604_set_bittiming;
  916. port_priv->can.do_set_mode = f81604_set_mode;
  917. port_priv->can.do_set_termination = f81604_set_termination;
  918. port_priv->can.do_get_berr_counter = f81604_get_berr_counter;
  919. port_priv->can.ctrlmode_supported =
  920. CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
  921. CAN_CTRLMODE_ONE_SHOT | CAN_CTRLMODE_BERR_REPORTING |
  922. CAN_CTRLMODE_PRESUME_ACK;
  923. netdev->ethtool_ops = &f81604_ethtool_ops;
  924. netdev->netdev_ops = &f81604_netdev_ops;
  925. netdev->flags |= IFF_ECHO;
  926. netdev->dev_port = i;
  927. SET_NETDEV_DEV(netdev, &intf->dev);
  928. ret = register_candev(netdev);
  929. if (ret) {
  930. netdev_err(netdev, "register CAN device failed: %pe\n",
  931. ERR_PTR(ret));
  932. free_candev(netdev);
  933. goto failure_cleanup;
  934. }
  935. priv->netdev[i] = netdev;
  936. }
  937. return 0;
  938. failure_cleanup:
  939. f81604_disconnect(intf);
  940. return ret;
  941. }
  942. static struct usb_driver f81604_driver = {
  943. .name = KBUILD_MODNAME,
  944. .probe = f81604_probe,
  945. .disconnect = f81604_disconnect,
  946. .id_table = f81604_table,
  947. };
  948. module_usb_driver(f81604_driver);
  949. MODULE_AUTHOR("Ji-Ze Hong (Peter Hong) <peter_hong@fintek.com.tw>");
  950. MODULE_DESCRIPTION("Fintek F81604 USB to 2xCANBUS");
  951. MODULE_LICENSE("GPL");