xgbe-platform.c 17 KB

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  1. /*
  2. * AMD 10Gb Ethernet driver
  3. *
  4. * This file is available to you under your choice of the following two
  5. * licenses:
  6. *
  7. * License 1: GPLv2
  8. *
  9. * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  10. *
  11. * This file is free software; you may copy, redistribute and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation, either version 2 of the License, or (at
  14. * your option) any later version.
  15. *
  16. * This file is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  23. *
  24. * This file incorporates work covered by the following copyright and
  25. * permission notice:
  26. * The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27. * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28. * Inc. unless otherwise expressly agreed to in writing between Synopsys
  29. * and you.
  30. *
  31. * The Software IS NOT an item of Licensed Software or Licensed Product
  32. * under any End User Software License Agreement or Agreement for Licensed
  33. * Product with Synopsys or any supplement thereto. Permission is hereby
  34. * granted, free of charge, to any person obtaining a copy of this software
  35. * annotated with this license and the Software, to deal in the Software
  36. * without restriction, including without limitation the rights to use,
  37. * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38. * of the Software, and to permit persons to whom the Software is furnished
  39. * to do so, subject to the following conditions:
  40. *
  41. * The above copyright notice and this permission notice shall be included
  42. * in all copies or substantial portions of the Software.
  43. *
  44. * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45. * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46. * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47. * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54. * THE POSSIBILITY OF SUCH DAMAGE.
  55. *
  56. *
  57. * License 2: Modified BSD
  58. *
  59. * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  60. * All rights reserved.
  61. *
  62. * Redistribution and use in source and binary forms, with or without
  63. * modification, are permitted provided that the following conditions are met:
  64. * * Redistributions of source code must retain the above copyright
  65. * notice, this list of conditions and the following disclaimer.
  66. * * Redistributions in binary form must reproduce the above copyright
  67. * notice, this list of conditions and the following disclaimer in the
  68. * documentation and/or other materials provided with the distribution.
  69. * * Neither the name of Advanced Micro Devices, Inc. nor the
  70. * names of its contributors may be used to endorse or promote products
  71. * derived from this software without specific prior written permission.
  72. *
  73. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76. * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83. *
  84. * This file incorporates work covered by the following copyright and
  85. * permission notice:
  86. * The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87. * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88. * Inc. unless otherwise expressly agreed to in writing between Synopsys
  89. * and you.
  90. *
  91. * The Software IS NOT an item of Licensed Software or Licensed Product
  92. * under any End User Software License Agreement or Agreement for Licensed
  93. * Product with Synopsys or any supplement thereto. Permission is hereby
  94. * granted, free of charge, to any person obtaining a copy of this software
  95. * annotated with this license and the Software, to deal in the Software
  96. * without restriction, including without limitation the rights to use,
  97. * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98. * of the Software, and to permit persons to whom the Software is furnished
  99. * to do so, subject to the following conditions:
  100. *
  101. * The above copyright notice and this permission notice shall be included
  102. * in all copies or substantial portions of the Software.
  103. *
  104. * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  105. * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  106. * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  107. * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  108. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  109. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  110. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  111. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  112. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  113. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  114. * THE POSSIBILITY OF SUCH DAMAGE.
  115. */
  116. #include <linux/module.h>
  117. #include <linux/device.h>
  118. #include <linux/platform_device.h>
  119. #include <linux/spinlock.h>
  120. #include <linux/netdevice.h>
  121. #include <linux/etherdevice.h>
  122. #include <linux/io.h>
  123. #include <linux/of.h>
  124. #include <linux/of_net.h>
  125. #include <linux/of_platform.h>
  126. #include <linux/clk.h>
  127. #include <linux/property.h>
  128. #include <linux/acpi.h>
  129. #include <linux/mdio.h>
  130. #include "xgbe.h"
  131. #include "xgbe-common.h"
  132. #ifdef CONFIG_ACPI
  133. static int xgbe_acpi_support(struct xgbe_prv_data *pdata)
  134. {
  135. struct device *dev = pdata->dev;
  136. u32 property;
  137. int ret;
  138. /* Obtain the system clock setting */
  139. ret = device_property_read_u32(dev, XGBE_ACPI_DMA_FREQ, &property);
  140. if (ret) {
  141. dev_err(dev, "unable to obtain %s property\n",
  142. XGBE_ACPI_DMA_FREQ);
  143. return ret;
  144. }
  145. pdata->sysclk_rate = property;
  146. /* Obtain the PTP clock setting */
  147. ret = device_property_read_u32(dev, XGBE_ACPI_PTP_FREQ, &property);
  148. if (ret) {
  149. dev_err(dev, "unable to obtain %s property\n",
  150. XGBE_ACPI_PTP_FREQ);
  151. return ret;
  152. }
  153. pdata->ptpclk_rate = property;
  154. return 0;
  155. }
  156. #else /* CONFIG_ACPI */
  157. static int xgbe_acpi_support(struct xgbe_prv_data *pdata)
  158. {
  159. return -EINVAL;
  160. }
  161. #endif /* CONFIG_ACPI */
  162. #ifdef CONFIG_OF
  163. static int xgbe_of_support(struct xgbe_prv_data *pdata)
  164. {
  165. struct device *dev = pdata->dev;
  166. /* Obtain the system clock setting */
  167. pdata->sysclk = devm_clk_get(dev, XGBE_DMA_CLOCK);
  168. if (IS_ERR(pdata->sysclk)) {
  169. dev_err(dev, "dma devm_clk_get failed\n");
  170. return PTR_ERR(pdata->sysclk);
  171. }
  172. pdata->sysclk_rate = clk_get_rate(pdata->sysclk);
  173. /* Obtain the PTP clock setting */
  174. pdata->ptpclk = devm_clk_get(dev, XGBE_PTP_CLOCK);
  175. if (IS_ERR(pdata->ptpclk)) {
  176. dev_err(dev, "ptp devm_clk_get failed\n");
  177. return PTR_ERR(pdata->ptpclk);
  178. }
  179. pdata->ptpclk_rate = clk_get_rate(pdata->ptpclk);
  180. return 0;
  181. }
  182. static struct platform_device *xgbe_of_get_phy_pdev(struct xgbe_prv_data *pdata)
  183. {
  184. struct device *dev = pdata->dev;
  185. struct device_node *phy_node;
  186. struct platform_device *phy_pdev;
  187. phy_node = of_parse_phandle(dev->of_node, "phy-handle", 0);
  188. if (phy_node) {
  189. /* Old style device tree:
  190. * The XGBE and PHY resources are separate
  191. */
  192. phy_pdev = of_find_device_by_node(phy_node);
  193. of_node_put(phy_node);
  194. } else {
  195. /* New style device tree:
  196. * The XGBE and PHY resources are grouped together with
  197. * the PHY resources listed last
  198. */
  199. get_device(dev);
  200. phy_pdev = pdata->platdev;
  201. }
  202. return phy_pdev;
  203. }
  204. #else /* CONFIG_OF */
  205. static int xgbe_of_support(struct xgbe_prv_data *pdata)
  206. {
  207. return -EINVAL;
  208. }
  209. static struct platform_device *xgbe_of_get_phy_pdev(struct xgbe_prv_data *pdata)
  210. {
  211. return NULL;
  212. }
  213. #endif /* CONFIG_OF */
  214. static unsigned int xgbe_resource_count(struct platform_device *pdev,
  215. unsigned int type)
  216. {
  217. unsigned int count;
  218. int i;
  219. for (i = 0, count = 0; i < pdev->num_resources; i++) {
  220. struct resource *res = &pdev->resource[i];
  221. if (type == resource_type(res))
  222. count++;
  223. }
  224. return count;
  225. }
  226. static struct platform_device *xgbe_get_phy_pdev(struct xgbe_prv_data *pdata)
  227. {
  228. struct platform_device *phy_pdev;
  229. if (pdata->use_acpi) {
  230. get_device(pdata->dev);
  231. phy_pdev = pdata->platdev;
  232. } else {
  233. phy_pdev = xgbe_of_get_phy_pdev(pdata);
  234. }
  235. return phy_pdev;
  236. }
  237. static int xgbe_platform_probe(struct platform_device *pdev)
  238. {
  239. struct xgbe_prv_data *pdata;
  240. struct device *dev = &pdev->dev;
  241. struct platform_device *phy_pdev;
  242. const char *phy_mode;
  243. unsigned int phy_memnum, phy_irqnum;
  244. unsigned int dma_irqnum, dma_irqend;
  245. enum dev_dma_attr attr;
  246. int ret;
  247. pdata = xgbe_alloc_pdata(dev);
  248. if (IS_ERR(pdata)) {
  249. ret = PTR_ERR(pdata);
  250. goto err_alloc;
  251. }
  252. pdata->platdev = pdev;
  253. pdata->adev = ACPI_COMPANION(dev);
  254. platform_set_drvdata(pdev, pdata);
  255. /* Check if we should use ACPI or DT */
  256. pdata->use_acpi = dev->of_node ? 0 : 1;
  257. /* Get the version data */
  258. pdata->vdata = (struct xgbe_version_data *)device_get_match_data(dev);
  259. phy_pdev = xgbe_get_phy_pdev(pdata);
  260. if (!phy_pdev) {
  261. dev_err(dev, "unable to obtain phy device\n");
  262. ret = -EINVAL;
  263. goto err_phydev;
  264. }
  265. pdata->phy_platdev = phy_pdev;
  266. pdata->phy_dev = &phy_pdev->dev;
  267. if (pdev == phy_pdev) {
  268. /* New style device tree or ACPI:
  269. * The XGBE and PHY resources are grouped together with
  270. * the PHY resources listed last
  271. */
  272. phy_memnum = xgbe_resource_count(pdev, IORESOURCE_MEM) - 3;
  273. phy_irqnum = platform_irq_count(pdev) - 1;
  274. dma_irqnum = 1;
  275. dma_irqend = phy_irqnum;
  276. } else {
  277. /* Old style device tree:
  278. * The XGBE and PHY resources are separate
  279. */
  280. phy_memnum = 0;
  281. phy_irqnum = 0;
  282. dma_irqnum = 1;
  283. dma_irqend = platform_irq_count(pdev);
  284. }
  285. /* Obtain the mmio areas for the device */
  286. pdata->xgmac_regs = devm_platform_ioremap_resource(pdev, 0);
  287. if (IS_ERR(pdata->xgmac_regs)) {
  288. dev_err(dev, "xgmac ioremap failed\n");
  289. ret = PTR_ERR(pdata->xgmac_regs);
  290. goto err_io;
  291. }
  292. if (netif_msg_probe(pdata))
  293. dev_dbg(dev, "xgmac_regs = %p\n", pdata->xgmac_regs);
  294. pdata->xpcs_regs = devm_platform_ioremap_resource(pdev, 1);
  295. if (IS_ERR(pdata->xpcs_regs)) {
  296. dev_err(dev, "xpcs ioremap failed\n");
  297. ret = PTR_ERR(pdata->xpcs_regs);
  298. goto err_io;
  299. }
  300. if (netif_msg_probe(pdata))
  301. dev_dbg(dev, "xpcs_regs = %p\n", pdata->xpcs_regs);
  302. pdata->rxtx_regs = devm_platform_ioremap_resource(phy_pdev,
  303. phy_memnum++);
  304. if (IS_ERR(pdata->rxtx_regs)) {
  305. dev_err(dev, "rxtx ioremap failed\n");
  306. ret = PTR_ERR(pdata->rxtx_regs);
  307. goto err_io;
  308. }
  309. if (netif_msg_probe(pdata))
  310. dev_dbg(dev, "rxtx_regs = %p\n", pdata->rxtx_regs);
  311. pdata->sir0_regs = devm_platform_ioremap_resource(phy_pdev,
  312. phy_memnum++);
  313. if (IS_ERR(pdata->sir0_regs)) {
  314. dev_err(dev, "sir0 ioremap failed\n");
  315. ret = PTR_ERR(pdata->sir0_regs);
  316. goto err_io;
  317. }
  318. if (netif_msg_probe(pdata))
  319. dev_dbg(dev, "sir0_regs = %p\n", pdata->sir0_regs);
  320. pdata->sir1_regs = devm_platform_ioremap_resource(phy_pdev,
  321. phy_memnum++);
  322. if (IS_ERR(pdata->sir1_regs)) {
  323. dev_err(dev, "sir1 ioremap failed\n");
  324. ret = PTR_ERR(pdata->sir1_regs);
  325. goto err_io;
  326. }
  327. if (netif_msg_probe(pdata))
  328. dev_dbg(dev, "sir1_regs = %p\n", pdata->sir1_regs);
  329. /* Retrieve the MAC address */
  330. ret = device_property_read_u8_array(dev, XGBE_MAC_ADDR_PROPERTY,
  331. pdata->mac_addr,
  332. sizeof(pdata->mac_addr));
  333. if (ret || !is_valid_ether_addr(pdata->mac_addr)) {
  334. dev_err(dev, "invalid %s property\n", XGBE_MAC_ADDR_PROPERTY);
  335. if (!ret)
  336. ret = -EINVAL;
  337. goto err_io;
  338. }
  339. /* Retrieve the PHY mode - it must be "xgmii" */
  340. ret = device_property_read_string(dev, XGBE_PHY_MODE_PROPERTY,
  341. &phy_mode);
  342. if (ret || strcmp(phy_mode, phy_modes(PHY_INTERFACE_MODE_XGMII))) {
  343. dev_err(dev, "invalid %s property\n", XGBE_PHY_MODE_PROPERTY);
  344. if (!ret)
  345. ret = -EINVAL;
  346. goto err_io;
  347. }
  348. pdata->phy_mode = PHY_INTERFACE_MODE_XGMII;
  349. /* Check for per channel interrupt support */
  350. if (device_property_present(dev, XGBE_DMA_IRQS_PROPERTY)) {
  351. pdata->per_channel_irq = 1;
  352. pdata->channel_irq_mode = XGBE_IRQ_MODE_EDGE;
  353. }
  354. /* Obtain device settings unique to ACPI/OF */
  355. if (pdata->use_acpi)
  356. ret = xgbe_acpi_support(pdata);
  357. else
  358. ret = xgbe_of_support(pdata);
  359. if (ret)
  360. goto err_io;
  361. /* Set the DMA coherency values */
  362. attr = device_get_dma_attr(dev);
  363. if (attr == DEV_DMA_NOT_SUPPORTED) {
  364. dev_err(dev, "DMA is not supported");
  365. ret = -ENODEV;
  366. goto err_io;
  367. }
  368. pdata->coherent = (attr == DEV_DMA_COHERENT);
  369. if (pdata->coherent) {
  370. pdata->arcr = XGBE_DMA_OS_ARCR;
  371. pdata->awcr = XGBE_DMA_OS_AWCR;
  372. } else {
  373. pdata->arcr = XGBE_DMA_SYS_ARCR;
  374. pdata->awcr = XGBE_DMA_SYS_AWCR;
  375. }
  376. /* Set the maximum fifo amounts */
  377. pdata->tx_max_fifo_size = pdata->vdata->tx_max_fifo_size;
  378. pdata->rx_max_fifo_size = pdata->vdata->rx_max_fifo_size;
  379. /* Set the hardware channel and queue counts */
  380. xgbe_set_counts(pdata);
  381. /* Always have XGMAC and XPCS (auto-negotiation) interrupts */
  382. pdata->irq_count = 2;
  383. /* Get the device interrupt */
  384. ret = platform_get_irq(pdev, 0);
  385. if (ret < 0)
  386. goto err_io;
  387. pdata->dev_irq = ret;
  388. /* Get the per channel DMA interrupts */
  389. if (pdata->per_channel_irq) {
  390. unsigned int i, max = ARRAY_SIZE(pdata->channel_irq);
  391. for (i = 0; (i < max) && (dma_irqnum < dma_irqend); i++) {
  392. ret = platform_get_irq(pdata->platdev, dma_irqnum++);
  393. if (ret < 0)
  394. goto err_io;
  395. pdata->channel_irq[i] = ret;
  396. }
  397. pdata->channel_irq_count = max;
  398. pdata->irq_count += max;
  399. }
  400. /* Get the auto-negotiation interrupt */
  401. ret = platform_get_irq(phy_pdev, phy_irqnum++);
  402. if (ret < 0)
  403. goto err_io;
  404. pdata->an_irq = ret;
  405. /* Configure the netdev resource */
  406. ret = xgbe_config_netdev(pdata);
  407. if (ret)
  408. goto err_io;
  409. netdev_notice(pdata->netdev, "net device enabled\n");
  410. return 0;
  411. err_io:
  412. platform_device_put(phy_pdev);
  413. err_phydev:
  414. xgbe_free_pdata(pdata);
  415. err_alloc:
  416. dev_notice(dev, "net device not enabled\n");
  417. return ret;
  418. }
  419. static void xgbe_platform_remove(struct platform_device *pdev)
  420. {
  421. struct xgbe_prv_data *pdata = platform_get_drvdata(pdev);
  422. xgbe_deconfig_netdev(pdata);
  423. platform_device_put(pdata->phy_platdev);
  424. xgbe_free_pdata(pdata);
  425. }
  426. #ifdef CONFIG_PM_SLEEP
  427. static int xgbe_platform_suspend(struct device *dev)
  428. {
  429. struct xgbe_prv_data *pdata = dev_get_drvdata(dev);
  430. struct net_device *netdev = pdata->netdev;
  431. int ret = 0;
  432. DBGPR("-->xgbe_suspend\n");
  433. if (netif_running(netdev))
  434. ret = xgbe_powerdown(netdev, XGMAC_DRIVER_CONTEXT);
  435. pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
  436. pdata->lpm_ctrl |= MDIO_CTRL1_LPOWER;
  437. XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
  438. DBGPR("<--xgbe_suspend\n");
  439. return ret;
  440. }
  441. static int xgbe_platform_resume(struct device *dev)
  442. {
  443. struct xgbe_prv_data *pdata = dev_get_drvdata(dev);
  444. struct net_device *netdev = pdata->netdev;
  445. int ret = 0;
  446. DBGPR("-->xgbe_resume\n");
  447. pdata->lpm_ctrl &= ~MDIO_CTRL1_LPOWER;
  448. XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
  449. if (netif_running(netdev)) {
  450. ret = xgbe_powerup(netdev, XGMAC_DRIVER_CONTEXT);
  451. /* Schedule a restart in case the link or phy state changed
  452. * while we were powered down.
  453. */
  454. schedule_work(&pdata->restart_work);
  455. }
  456. DBGPR("<--xgbe_resume\n");
  457. return ret;
  458. }
  459. #endif /* CONFIG_PM_SLEEP */
  460. static const struct xgbe_version_data xgbe_v1 = {
  461. .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v1,
  462. .xpcs_access = XGBE_XPCS_ACCESS_V1,
  463. .tx_max_fifo_size = 81920,
  464. .rx_max_fifo_size = 81920,
  465. .tx_tstamp_workaround = 1,
  466. };
  467. static const struct acpi_device_id xgbe_acpi_match[] = {
  468. { .id = "AMDI8001",
  469. .driver_data = (kernel_ulong_t)&xgbe_v1 },
  470. {},
  471. };
  472. MODULE_DEVICE_TABLE(acpi, xgbe_acpi_match);
  473. static const struct of_device_id xgbe_of_match[] = {
  474. { .compatible = "amd,xgbe-seattle-v1a",
  475. .data = &xgbe_v1 },
  476. {},
  477. };
  478. MODULE_DEVICE_TABLE(of, xgbe_of_match);
  479. static SIMPLE_DEV_PM_OPS(xgbe_platform_pm_ops,
  480. xgbe_platform_suspend, xgbe_platform_resume);
  481. static struct platform_driver xgbe_driver = {
  482. .driver = {
  483. .name = XGBE_DRV_NAME,
  484. .acpi_match_table = xgbe_acpi_match,
  485. .of_match_table = xgbe_of_match,
  486. .pm = &xgbe_platform_pm_ops,
  487. },
  488. .probe = xgbe_platform_probe,
  489. .remove_new = xgbe_platform_remove,
  490. };
  491. int xgbe_platform_init(void)
  492. {
  493. return platform_driver_register(&xgbe_driver);
  494. }
  495. void xgbe_platform_exit(void)
  496. {
  497. platform_driver_unregister(&xgbe_driver);
  498. }