vnic_dev.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
  4. * Copyright 2007 Nuova Systems, Inc. All rights reserved.
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/errno.h>
  8. #include <linux/types.h>
  9. #include <linux/pci.h>
  10. #include <linux/delay.h>
  11. #include <linux/if_ether.h>
  12. #include "vnic_resource.h"
  13. #include "vnic_devcmd.h"
  14. #include "vnic_dev.h"
  15. #include "vnic_wq.h"
  16. #include "vnic_stats.h"
  17. #include "enic.h"
  18. #define VNIC_MAX_RES_HDR_SIZE \
  19. (sizeof(struct vnic_resource_header) + \
  20. sizeof(struct vnic_resource) * RES_TYPE_MAX)
  21. #define VNIC_RES_STRIDE 128
  22. void *vnic_dev_priv(struct vnic_dev *vdev)
  23. {
  24. return vdev->priv;
  25. }
  26. static int vnic_dev_discover_res(struct vnic_dev *vdev,
  27. struct vnic_dev_bar *bar, unsigned int num_bars)
  28. {
  29. struct vnic_resource_header __iomem *rh;
  30. struct mgmt_barmap_hdr __iomem *mrh;
  31. struct vnic_resource __iomem *r;
  32. u8 type;
  33. if (num_bars == 0)
  34. return -EINVAL;
  35. if (bar->len < VNIC_MAX_RES_HDR_SIZE) {
  36. vdev_err(vdev, "vNIC BAR0 res hdr length error\n");
  37. return -EINVAL;
  38. }
  39. rh = bar->vaddr;
  40. mrh = bar->vaddr;
  41. if (!rh) {
  42. vdev_err(vdev, "vNIC BAR0 res hdr not mem-mapped\n");
  43. return -EINVAL;
  44. }
  45. /* Check for mgmt vnic in addition to normal vnic */
  46. if ((ioread32(&rh->magic) != VNIC_RES_MAGIC) ||
  47. (ioread32(&rh->version) != VNIC_RES_VERSION)) {
  48. if ((ioread32(&mrh->magic) != MGMTVNIC_MAGIC) ||
  49. (ioread32(&mrh->version) != MGMTVNIC_VERSION)) {
  50. vdev_err(vdev, "vNIC BAR0 res magic/version error exp (%lx/%lx) or (%lx/%lx), curr (%x/%x)\n",
  51. VNIC_RES_MAGIC, VNIC_RES_VERSION,
  52. MGMTVNIC_MAGIC, MGMTVNIC_VERSION,
  53. ioread32(&rh->magic), ioread32(&rh->version));
  54. return -EINVAL;
  55. }
  56. }
  57. if (ioread32(&mrh->magic) == MGMTVNIC_MAGIC)
  58. r = (struct vnic_resource __iomem *)(mrh + 1);
  59. else
  60. r = (struct vnic_resource __iomem *)(rh + 1);
  61. while ((type = ioread8(&r->type)) != RES_TYPE_EOL) {
  62. u8 bar_num = ioread8(&r->bar);
  63. u32 bar_offset = ioread32(&r->bar_offset);
  64. u32 count = ioread32(&r->count);
  65. u32 len;
  66. r++;
  67. if (bar_num >= num_bars)
  68. continue;
  69. if (!bar[bar_num].len || !bar[bar_num].vaddr)
  70. continue;
  71. switch (type) {
  72. case RES_TYPE_WQ:
  73. case RES_TYPE_RQ:
  74. case RES_TYPE_CQ:
  75. case RES_TYPE_INTR_CTRL:
  76. /* each count is stride bytes long */
  77. len = count * VNIC_RES_STRIDE;
  78. if (len + bar_offset > bar[bar_num].len) {
  79. vdev_err(vdev, "vNIC BAR0 resource %d out-of-bounds, offset 0x%x + size 0x%x > bar len 0x%lx\n",
  80. type, bar_offset, len,
  81. bar[bar_num].len);
  82. return -EINVAL;
  83. }
  84. break;
  85. case RES_TYPE_INTR_PBA_LEGACY:
  86. case RES_TYPE_DEVCMD:
  87. case RES_TYPE_DEVCMD2:
  88. len = count;
  89. break;
  90. default:
  91. continue;
  92. }
  93. vdev->res[type].count = count;
  94. vdev->res[type].vaddr = (char __iomem *)bar[bar_num].vaddr +
  95. bar_offset;
  96. vdev->res[type].bus_addr = bar[bar_num].bus_addr + bar_offset;
  97. }
  98. return 0;
  99. }
  100. unsigned int vnic_dev_get_res_count(struct vnic_dev *vdev,
  101. enum vnic_res_type type)
  102. {
  103. return vdev->res[type].count;
  104. }
  105. EXPORT_SYMBOL(vnic_dev_get_res_count);
  106. void __iomem *vnic_dev_get_res(struct vnic_dev *vdev, enum vnic_res_type type,
  107. unsigned int index)
  108. {
  109. if (!vdev->res[type].vaddr)
  110. return NULL;
  111. switch (type) {
  112. case RES_TYPE_WQ:
  113. case RES_TYPE_RQ:
  114. case RES_TYPE_CQ:
  115. case RES_TYPE_INTR_CTRL:
  116. return (char __iomem *)vdev->res[type].vaddr +
  117. index * VNIC_RES_STRIDE;
  118. default:
  119. return (char __iomem *)vdev->res[type].vaddr;
  120. }
  121. }
  122. EXPORT_SYMBOL(vnic_dev_get_res);
  123. static unsigned int vnic_dev_desc_ring_size(struct vnic_dev_ring *ring,
  124. unsigned int desc_count, unsigned int desc_size)
  125. {
  126. /* Descriptor ring base address alignment in bytes*/
  127. ring->base_align = VNIC_DESC_BASE_ALIGN;
  128. /* A count of 0 means the maximum descriptors */
  129. if (desc_count == 0)
  130. desc_count = VNIC_DESC_MAX_COUNT;
  131. /* Descriptor count aligned in groups of VNIC_DESC_COUNT_ALIGN descriptors */
  132. ring->desc_count = ALIGN(desc_count, VNIC_DESC_COUNT_ALIGN);
  133. /* Descriptor size alignment in bytes */
  134. ring->desc_size = ALIGN(desc_size, VNIC_DESC_SIZE_ALIGN);
  135. ring->size = ring->desc_count * ring->desc_size;
  136. ring->size_unaligned = ring->size + ring->base_align;
  137. return ring->size_unaligned;
  138. }
  139. void vnic_dev_clear_desc_ring(struct vnic_dev_ring *ring)
  140. {
  141. memset(ring->descs, 0, ring->size);
  142. }
  143. int vnic_dev_alloc_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring,
  144. unsigned int desc_count, unsigned int desc_size)
  145. {
  146. vnic_dev_desc_ring_size(ring, desc_count, desc_size);
  147. ring->descs_unaligned = dma_alloc_coherent(&vdev->pdev->dev,
  148. ring->size_unaligned,
  149. &ring->base_addr_unaligned,
  150. GFP_KERNEL);
  151. if (!ring->descs_unaligned) {
  152. vdev_err(vdev, "Failed to allocate ring (size=%d), aborting\n",
  153. (int)ring->size);
  154. return -ENOMEM;
  155. }
  156. ring->base_addr = ALIGN(ring->base_addr_unaligned,
  157. ring->base_align);
  158. ring->descs = (u8 *)ring->descs_unaligned +
  159. (ring->base_addr - ring->base_addr_unaligned);
  160. vnic_dev_clear_desc_ring(ring);
  161. ring->desc_avail = ring->desc_count - 1;
  162. return 0;
  163. }
  164. void vnic_dev_free_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring)
  165. {
  166. if (ring->descs) {
  167. dma_free_coherent(&vdev->pdev->dev, ring->size_unaligned,
  168. ring->descs_unaligned,
  169. ring->base_addr_unaligned);
  170. ring->descs = NULL;
  171. }
  172. }
  173. static int _vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
  174. int wait)
  175. {
  176. struct vnic_devcmd __iomem *devcmd = vdev->devcmd;
  177. unsigned int i;
  178. int delay;
  179. u32 status;
  180. int err;
  181. status = ioread32(&devcmd->status);
  182. if (status == 0xFFFFFFFF) {
  183. /* PCI-e target device is gone */
  184. return -ENODEV;
  185. }
  186. if (status & STAT_BUSY) {
  187. vdev_neterr(vdev, "Busy devcmd %d\n", _CMD_N(cmd));
  188. return -EBUSY;
  189. }
  190. if (_CMD_DIR(cmd) & _CMD_DIR_WRITE) {
  191. for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
  192. writeq(vdev->args[i], &devcmd->args[i]);
  193. wmb();
  194. }
  195. iowrite32(cmd, &devcmd->cmd);
  196. if ((_CMD_FLAGS(cmd) & _CMD_FLAGS_NOWAIT))
  197. return 0;
  198. for (delay = 0; delay < wait; delay++) {
  199. udelay(100);
  200. status = ioread32(&devcmd->status);
  201. if (status == 0xFFFFFFFF) {
  202. /* PCI-e target device is gone */
  203. return -ENODEV;
  204. }
  205. if (!(status & STAT_BUSY)) {
  206. if (status & STAT_ERROR) {
  207. err = (int)readq(&devcmd->args[0]);
  208. if (err == ERR_EINVAL &&
  209. cmd == CMD_CAPABILITY)
  210. return -err;
  211. if (err != ERR_ECMDUNKNOWN ||
  212. cmd != CMD_CAPABILITY)
  213. vdev_neterr(vdev, "Error %d devcmd %d\n",
  214. err, _CMD_N(cmd));
  215. return -err;
  216. }
  217. if (_CMD_DIR(cmd) & _CMD_DIR_READ) {
  218. rmb();
  219. for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
  220. vdev->args[i] = readq(&devcmd->args[i]);
  221. }
  222. return 0;
  223. }
  224. }
  225. vdev_neterr(vdev, "Timedout devcmd %d\n", _CMD_N(cmd));
  226. return -ETIMEDOUT;
  227. }
  228. static int _vnic_dev_cmd2(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
  229. int wait)
  230. {
  231. struct devcmd2_controller *dc2c = vdev->devcmd2;
  232. struct devcmd2_result *result;
  233. u8 color;
  234. unsigned int i;
  235. int delay, err;
  236. u32 fetch_index, new_posted;
  237. u32 posted = dc2c->posted;
  238. fetch_index = ioread32(&dc2c->wq_ctrl->fetch_index);
  239. if (fetch_index == 0xFFFFFFFF)
  240. return -ENODEV;
  241. new_posted = (posted + 1) % DEVCMD2_RING_SIZE;
  242. if (new_posted == fetch_index) {
  243. vdev_neterr(vdev, "devcmd2 %d: wq is full. fetch index: %u, posted index: %u\n",
  244. _CMD_N(cmd), fetch_index, posted);
  245. return -EBUSY;
  246. }
  247. dc2c->cmd_ring[posted].cmd = cmd;
  248. dc2c->cmd_ring[posted].flags = 0;
  249. if ((_CMD_FLAGS(cmd) & _CMD_FLAGS_NOWAIT))
  250. dc2c->cmd_ring[posted].flags |= DEVCMD2_FNORESULT;
  251. if (_CMD_DIR(cmd) & _CMD_DIR_WRITE)
  252. for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
  253. dc2c->cmd_ring[posted].args[i] = vdev->args[i];
  254. /* Adding write memory barrier prevents compiler and/or CPU reordering,
  255. * thus avoiding descriptor posting before descriptor is initialized.
  256. * Otherwise, hardware can read stale descriptor fields.
  257. */
  258. wmb();
  259. iowrite32(new_posted, &dc2c->wq_ctrl->posted_index);
  260. dc2c->posted = new_posted;
  261. if (dc2c->cmd_ring[posted].flags & DEVCMD2_FNORESULT)
  262. return 0;
  263. result = dc2c->result + dc2c->next_result;
  264. color = dc2c->color;
  265. dc2c->next_result++;
  266. if (dc2c->next_result == dc2c->result_size) {
  267. dc2c->next_result = 0;
  268. dc2c->color = dc2c->color ? 0 : 1;
  269. }
  270. for (delay = 0; delay < wait; delay++) {
  271. if (result->color == color) {
  272. if (result->error) {
  273. err = result->error;
  274. if (err != ERR_ECMDUNKNOWN ||
  275. cmd != CMD_CAPABILITY)
  276. vdev_neterr(vdev, "Error %d devcmd %d\n",
  277. err, _CMD_N(cmd));
  278. return -err;
  279. }
  280. if (_CMD_DIR(cmd) & _CMD_DIR_READ)
  281. for (i = 0; i < VNIC_DEVCMD2_NARGS; i++)
  282. vdev->args[i] = result->results[i];
  283. return 0;
  284. }
  285. udelay(100);
  286. }
  287. vdev_neterr(vdev, "devcmd %d timed out\n", _CMD_N(cmd));
  288. return -ETIMEDOUT;
  289. }
  290. static int vnic_dev_init_devcmd1(struct vnic_dev *vdev)
  291. {
  292. vdev->devcmd = vnic_dev_get_res(vdev, RES_TYPE_DEVCMD, 0);
  293. if (!vdev->devcmd)
  294. return -ENODEV;
  295. vdev->devcmd_rtn = _vnic_dev_cmd;
  296. return 0;
  297. }
  298. static int vnic_dev_init_devcmd2(struct vnic_dev *vdev)
  299. {
  300. int err;
  301. unsigned int fetch_index;
  302. if (vdev->devcmd2)
  303. return 0;
  304. vdev->devcmd2 = kzalloc(sizeof(*vdev->devcmd2), GFP_KERNEL);
  305. if (!vdev->devcmd2)
  306. return -ENOMEM;
  307. vdev->devcmd2->color = 1;
  308. vdev->devcmd2->result_size = DEVCMD2_RING_SIZE;
  309. err = enic_wq_devcmd2_alloc(vdev, &vdev->devcmd2->wq, DEVCMD2_RING_SIZE,
  310. DEVCMD2_DESC_SIZE);
  311. if (err)
  312. goto err_free_devcmd2;
  313. fetch_index = ioread32(&vdev->devcmd2->wq.ctrl->fetch_index);
  314. if (fetch_index == 0xFFFFFFFF) { /* check for hardware gone */
  315. vdev_err(vdev, "Fatal error in devcmd2 init - hardware surprise removal\n");
  316. err = -ENODEV;
  317. goto err_free_wq;
  318. }
  319. enic_wq_init_start(&vdev->devcmd2->wq, 0, fetch_index, fetch_index, 0,
  320. 0);
  321. vdev->devcmd2->posted = fetch_index;
  322. vnic_wq_enable(&vdev->devcmd2->wq);
  323. err = vnic_dev_alloc_desc_ring(vdev, &vdev->devcmd2->results_ring,
  324. DEVCMD2_RING_SIZE, DEVCMD2_DESC_SIZE);
  325. if (err)
  326. goto err_disable_wq;
  327. vdev->devcmd2->result = vdev->devcmd2->results_ring.descs;
  328. vdev->devcmd2->cmd_ring = vdev->devcmd2->wq.ring.descs;
  329. vdev->devcmd2->wq_ctrl = vdev->devcmd2->wq.ctrl;
  330. vdev->args[0] = (u64)vdev->devcmd2->results_ring.base_addr |
  331. VNIC_PADDR_TARGET;
  332. vdev->args[1] = DEVCMD2_RING_SIZE;
  333. err = _vnic_dev_cmd2(vdev, CMD_INITIALIZE_DEVCMD2, 1000);
  334. if (err)
  335. goto err_free_desc_ring;
  336. vdev->devcmd_rtn = _vnic_dev_cmd2;
  337. return 0;
  338. err_free_desc_ring:
  339. vnic_dev_free_desc_ring(vdev, &vdev->devcmd2->results_ring);
  340. err_disable_wq:
  341. vnic_wq_disable(&vdev->devcmd2->wq);
  342. err_free_wq:
  343. vnic_wq_free(&vdev->devcmd2->wq);
  344. err_free_devcmd2:
  345. kfree(vdev->devcmd2);
  346. vdev->devcmd2 = NULL;
  347. return err;
  348. }
  349. static void vnic_dev_deinit_devcmd2(struct vnic_dev *vdev)
  350. {
  351. vnic_dev_free_desc_ring(vdev, &vdev->devcmd2->results_ring);
  352. vnic_wq_disable(&vdev->devcmd2->wq);
  353. vnic_wq_free(&vdev->devcmd2->wq);
  354. kfree(vdev->devcmd2);
  355. }
  356. static int vnic_dev_cmd_proxy(struct vnic_dev *vdev,
  357. enum vnic_devcmd_cmd proxy_cmd, enum vnic_devcmd_cmd cmd,
  358. u64 *a0, u64 *a1, int wait)
  359. {
  360. u32 status;
  361. int err;
  362. memset(vdev->args, 0, sizeof(vdev->args));
  363. vdev->args[0] = vdev->proxy_index;
  364. vdev->args[1] = cmd;
  365. vdev->args[2] = *a0;
  366. vdev->args[3] = *a1;
  367. err = vdev->devcmd_rtn(vdev, proxy_cmd, wait);
  368. if (err)
  369. return err;
  370. status = (u32)vdev->args[0];
  371. if (status & STAT_ERROR) {
  372. err = (int)vdev->args[1];
  373. if (err != ERR_ECMDUNKNOWN ||
  374. cmd != CMD_CAPABILITY)
  375. vdev_neterr(vdev, "Error %d proxy devcmd %d\n",
  376. err, _CMD_N(cmd));
  377. return err;
  378. }
  379. *a0 = vdev->args[1];
  380. *a1 = vdev->args[2];
  381. return 0;
  382. }
  383. static int vnic_dev_cmd_no_proxy(struct vnic_dev *vdev,
  384. enum vnic_devcmd_cmd cmd, u64 *a0, u64 *a1, int wait)
  385. {
  386. int err;
  387. vdev->args[0] = *a0;
  388. vdev->args[1] = *a1;
  389. err = vdev->devcmd_rtn(vdev, cmd, wait);
  390. *a0 = vdev->args[0];
  391. *a1 = vdev->args[1];
  392. return err;
  393. }
  394. void vnic_dev_cmd_proxy_by_index_start(struct vnic_dev *vdev, u16 index)
  395. {
  396. vdev->proxy = PROXY_BY_INDEX;
  397. vdev->proxy_index = index;
  398. }
  399. void vnic_dev_cmd_proxy_end(struct vnic_dev *vdev)
  400. {
  401. vdev->proxy = PROXY_NONE;
  402. vdev->proxy_index = 0;
  403. }
  404. int vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
  405. u64 *a0, u64 *a1, int wait)
  406. {
  407. memset(vdev->args, 0, sizeof(vdev->args));
  408. switch (vdev->proxy) {
  409. case PROXY_BY_INDEX:
  410. return vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_INDEX, cmd,
  411. a0, a1, wait);
  412. case PROXY_BY_BDF:
  413. return vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_BDF, cmd,
  414. a0, a1, wait);
  415. case PROXY_NONE:
  416. default:
  417. return vnic_dev_cmd_no_proxy(vdev, cmd, a0, a1, wait);
  418. }
  419. }
  420. static int vnic_dev_capable(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd)
  421. {
  422. u64 a0 = (u32)cmd, a1 = 0;
  423. int wait = 1000;
  424. int err;
  425. err = vnic_dev_cmd(vdev, CMD_CAPABILITY, &a0, &a1, wait);
  426. return !(err || a0);
  427. }
  428. int vnic_dev_fw_info(struct vnic_dev *vdev,
  429. struct vnic_devcmd_fw_info **fw_info)
  430. {
  431. u64 a0, a1 = 0;
  432. int wait = 1000;
  433. int err = 0;
  434. if (!vdev->fw_info) {
  435. vdev->fw_info = dma_alloc_coherent(&vdev->pdev->dev,
  436. sizeof(struct vnic_devcmd_fw_info),
  437. &vdev->fw_info_pa, GFP_ATOMIC);
  438. if (!vdev->fw_info)
  439. return -ENOMEM;
  440. a0 = vdev->fw_info_pa;
  441. a1 = sizeof(struct vnic_devcmd_fw_info);
  442. /* only get fw_info once and cache it */
  443. if (vnic_dev_capable(vdev, CMD_MCPU_FW_INFO))
  444. err = vnic_dev_cmd(vdev, CMD_MCPU_FW_INFO,
  445. &a0, &a1, wait);
  446. else
  447. err = vnic_dev_cmd(vdev, CMD_MCPU_FW_INFO_OLD,
  448. &a0, &a1, wait);
  449. }
  450. *fw_info = vdev->fw_info;
  451. return err;
  452. }
  453. int vnic_dev_spec(struct vnic_dev *vdev, unsigned int offset, unsigned int size,
  454. void *value)
  455. {
  456. u64 a0, a1;
  457. int wait = 1000;
  458. int err;
  459. a0 = offset;
  460. a1 = size;
  461. err = vnic_dev_cmd(vdev, CMD_DEV_SPEC, &a0, &a1, wait);
  462. switch (size) {
  463. case 1: *(u8 *)value = (u8)a0; break;
  464. case 2: *(u16 *)value = (u16)a0; break;
  465. case 4: *(u32 *)value = (u32)a0; break;
  466. case 8: *(u64 *)value = a0; break;
  467. default: BUG(); break;
  468. }
  469. return err;
  470. }
  471. int vnic_dev_stats_dump(struct vnic_dev *vdev, struct vnic_stats **stats)
  472. {
  473. u64 a0, a1;
  474. int wait = 1000;
  475. if (!vdev->stats) {
  476. vdev->stats = dma_alloc_coherent(&vdev->pdev->dev,
  477. sizeof(struct vnic_stats),
  478. &vdev->stats_pa, GFP_ATOMIC);
  479. if (!vdev->stats)
  480. return -ENOMEM;
  481. }
  482. *stats = vdev->stats;
  483. a0 = vdev->stats_pa;
  484. a1 = sizeof(struct vnic_stats);
  485. return vnic_dev_cmd(vdev, CMD_STATS_DUMP, &a0, &a1, wait);
  486. }
  487. int vnic_dev_close(struct vnic_dev *vdev)
  488. {
  489. u64 a0 = 0, a1 = 0;
  490. int wait = 1000;
  491. return vnic_dev_cmd(vdev, CMD_CLOSE, &a0, &a1, wait);
  492. }
  493. int vnic_dev_enable_wait(struct vnic_dev *vdev)
  494. {
  495. u64 a0 = 0, a1 = 0;
  496. int wait = 1000;
  497. if (vnic_dev_capable(vdev, CMD_ENABLE_WAIT))
  498. return vnic_dev_cmd(vdev, CMD_ENABLE_WAIT, &a0, &a1, wait);
  499. else
  500. return vnic_dev_cmd(vdev, CMD_ENABLE, &a0, &a1, wait);
  501. }
  502. int vnic_dev_disable(struct vnic_dev *vdev)
  503. {
  504. u64 a0 = 0, a1 = 0;
  505. int wait = 1000;
  506. return vnic_dev_cmd(vdev, CMD_DISABLE, &a0, &a1, wait);
  507. }
  508. int vnic_dev_open(struct vnic_dev *vdev, int arg)
  509. {
  510. u64 a0 = (u32)arg, a1 = 0;
  511. int wait = 1000;
  512. return vnic_dev_cmd(vdev, CMD_OPEN, &a0, &a1, wait);
  513. }
  514. int vnic_dev_open_done(struct vnic_dev *vdev, int *done)
  515. {
  516. u64 a0 = 0, a1 = 0;
  517. int wait = 1000;
  518. int err;
  519. *done = 0;
  520. err = vnic_dev_cmd(vdev, CMD_OPEN_STATUS, &a0, &a1, wait);
  521. if (err)
  522. return err;
  523. *done = (a0 == 0);
  524. return 0;
  525. }
  526. int vnic_dev_soft_reset(struct vnic_dev *vdev, int arg)
  527. {
  528. u64 a0 = (u32)arg, a1 = 0;
  529. int wait = 1000;
  530. return vnic_dev_cmd(vdev, CMD_SOFT_RESET, &a0, &a1, wait);
  531. }
  532. int vnic_dev_soft_reset_done(struct vnic_dev *vdev, int *done)
  533. {
  534. u64 a0 = 0, a1 = 0;
  535. int wait = 1000;
  536. int err;
  537. *done = 0;
  538. err = vnic_dev_cmd(vdev, CMD_SOFT_RESET_STATUS, &a0, &a1, wait);
  539. if (err)
  540. return err;
  541. *done = (a0 == 0);
  542. return 0;
  543. }
  544. int vnic_dev_hang_reset(struct vnic_dev *vdev, int arg)
  545. {
  546. u64 a0 = (u32)arg, a1 = 0;
  547. int wait = 1000;
  548. int err;
  549. if (vnic_dev_capable(vdev, CMD_HANG_RESET)) {
  550. return vnic_dev_cmd(vdev, CMD_HANG_RESET,
  551. &a0, &a1, wait);
  552. } else {
  553. err = vnic_dev_soft_reset(vdev, arg);
  554. if (err)
  555. return err;
  556. return vnic_dev_init(vdev, 0);
  557. }
  558. }
  559. int vnic_dev_hang_reset_done(struct vnic_dev *vdev, int *done)
  560. {
  561. u64 a0 = 0, a1 = 0;
  562. int wait = 1000;
  563. int err;
  564. *done = 0;
  565. if (vnic_dev_capable(vdev, CMD_HANG_RESET_STATUS)) {
  566. err = vnic_dev_cmd(vdev, CMD_HANG_RESET_STATUS,
  567. &a0, &a1, wait);
  568. if (err)
  569. return err;
  570. } else {
  571. return vnic_dev_soft_reset_done(vdev, done);
  572. }
  573. *done = (a0 == 0);
  574. return 0;
  575. }
  576. int vnic_dev_hang_notify(struct vnic_dev *vdev)
  577. {
  578. u64 a0, a1;
  579. int wait = 1000;
  580. return vnic_dev_cmd(vdev, CMD_HANG_NOTIFY, &a0, &a1, wait);
  581. }
  582. int vnic_dev_get_mac_addr(struct vnic_dev *vdev, u8 *mac_addr)
  583. {
  584. u64 a0, a1;
  585. int wait = 1000;
  586. int err, i;
  587. for (i = 0; i < ETH_ALEN; i++)
  588. mac_addr[i] = 0;
  589. err = vnic_dev_cmd(vdev, CMD_GET_MAC_ADDR, &a0, &a1, wait);
  590. if (err)
  591. return err;
  592. for (i = 0; i < ETH_ALEN; i++)
  593. mac_addr[i] = ((u8 *)&a0)[i];
  594. return 0;
  595. }
  596. int vnic_dev_packet_filter(struct vnic_dev *vdev, int directed, int multicast,
  597. int broadcast, int promisc, int allmulti)
  598. {
  599. u64 a0, a1 = 0;
  600. int wait = 1000;
  601. int err;
  602. a0 = (directed ? CMD_PFILTER_DIRECTED : 0) |
  603. (multicast ? CMD_PFILTER_MULTICAST : 0) |
  604. (broadcast ? CMD_PFILTER_BROADCAST : 0) |
  605. (promisc ? CMD_PFILTER_PROMISCUOUS : 0) |
  606. (allmulti ? CMD_PFILTER_ALL_MULTICAST : 0);
  607. err = vnic_dev_cmd(vdev, CMD_PACKET_FILTER, &a0, &a1, wait);
  608. if (err)
  609. vdev_neterr(vdev, "Can't set packet filter\n");
  610. return err;
  611. }
  612. int vnic_dev_add_addr(struct vnic_dev *vdev, const u8 *addr)
  613. {
  614. u64 a0 = 0, a1 = 0;
  615. int wait = 1000;
  616. int err;
  617. int i;
  618. for (i = 0; i < ETH_ALEN; i++)
  619. ((u8 *)&a0)[i] = addr[i];
  620. err = vnic_dev_cmd(vdev, CMD_ADDR_ADD, &a0, &a1, wait);
  621. if (err)
  622. vdev_neterr(vdev, "Can't add addr [%pM], %d\n", addr, err);
  623. return err;
  624. }
  625. int vnic_dev_del_addr(struct vnic_dev *vdev, const u8 *addr)
  626. {
  627. u64 a0 = 0, a1 = 0;
  628. int wait = 1000;
  629. int err;
  630. int i;
  631. for (i = 0; i < ETH_ALEN; i++)
  632. ((u8 *)&a0)[i] = addr[i];
  633. err = vnic_dev_cmd(vdev, CMD_ADDR_DEL, &a0, &a1, wait);
  634. if (err)
  635. vdev_neterr(vdev, "Can't del addr [%pM], %d\n", addr, err);
  636. return err;
  637. }
  638. int vnic_dev_set_ig_vlan_rewrite_mode(struct vnic_dev *vdev,
  639. u8 ig_vlan_rewrite_mode)
  640. {
  641. u64 a0 = ig_vlan_rewrite_mode, a1 = 0;
  642. int wait = 1000;
  643. if (vnic_dev_capable(vdev, CMD_IG_VLAN_REWRITE_MODE))
  644. return vnic_dev_cmd(vdev, CMD_IG_VLAN_REWRITE_MODE,
  645. &a0, &a1, wait);
  646. else
  647. return 0;
  648. }
  649. static int vnic_dev_notify_setcmd(struct vnic_dev *vdev,
  650. void *notify_addr, dma_addr_t notify_pa, u16 intr)
  651. {
  652. u64 a0, a1;
  653. int wait = 1000;
  654. int r;
  655. memset(notify_addr, 0, sizeof(struct vnic_devcmd_notify));
  656. vdev->notify = notify_addr;
  657. vdev->notify_pa = notify_pa;
  658. a0 = (u64)notify_pa;
  659. a1 = ((u64)intr << 32) & 0x0000ffff00000000ULL;
  660. a1 += sizeof(struct vnic_devcmd_notify);
  661. r = vnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);
  662. vdev->notify_sz = (r == 0) ? (u32)a1 : 0;
  663. return r;
  664. }
  665. int vnic_dev_notify_set(struct vnic_dev *vdev, u16 intr)
  666. {
  667. void *notify_addr;
  668. dma_addr_t notify_pa;
  669. if (vdev->notify || vdev->notify_pa) {
  670. vdev_neterr(vdev, "notify block %p still allocated\n",
  671. vdev->notify);
  672. return -EINVAL;
  673. }
  674. notify_addr = dma_alloc_coherent(&vdev->pdev->dev,
  675. sizeof(struct vnic_devcmd_notify),
  676. &notify_pa, GFP_ATOMIC);
  677. if (!notify_addr)
  678. return -ENOMEM;
  679. return vnic_dev_notify_setcmd(vdev, notify_addr, notify_pa, intr);
  680. }
  681. static int vnic_dev_notify_unsetcmd(struct vnic_dev *vdev)
  682. {
  683. u64 a0, a1;
  684. int wait = 1000;
  685. int err;
  686. a0 = 0; /* paddr = 0 to unset notify buffer */
  687. a1 = 0x0000ffff00000000ULL; /* intr num = -1 to unreg for intr */
  688. a1 += sizeof(struct vnic_devcmd_notify);
  689. err = vnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);
  690. vdev->notify = NULL;
  691. vdev->notify_pa = 0;
  692. vdev->notify_sz = 0;
  693. return err;
  694. }
  695. int vnic_dev_notify_unset(struct vnic_dev *vdev)
  696. {
  697. if (vdev->notify) {
  698. dma_free_coherent(&vdev->pdev->dev,
  699. sizeof(struct vnic_devcmd_notify),
  700. vdev->notify, vdev->notify_pa);
  701. }
  702. return vnic_dev_notify_unsetcmd(vdev);
  703. }
  704. static int vnic_dev_notify_ready(struct vnic_dev *vdev)
  705. {
  706. u32 *words;
  707. unsigned int nwords = vdev->notify_sz / 4;
  708. unsigned int i;
  709. u32 csum;
  710. if (!vdev->notify || !vdev->notify_sz)
  711. return 0;
  712. do {
  713. csum = 0;
  714. memcpy(&vdev->notify_copy, vdev->notify, vdev->notify_sz);
  715. words = (u32 *)&vdev->notify_copy;
  716. for (i = 1; i < nwords; i++)
  717. csum += words[i];
  718. } while (csum != words[0]);
  719. return 1;
  720. }
  721. int vnic_dev_init(struct vnic_dev *vdev, int arg)
  722. {
  723. u64 a0 = (u32)arg, a1 = 0;
  724. int wait = 1000;
  725. int r = 0;
  726. if (vnic_dev_capable(vdev, CMD_INIT))
  727. r = vnic_dev_cmd(vdev, CMD_INIT, &a0, &a1, wait);
  728. else {
  729. vnic_dev_cmd(vdev, CMD_INIT_v1, &a0, &a1, wait);
  730. if (a0 & CMD_INITF_DEFAULT_MAC) {
  731. /* Emulate these for old CMD_INIT_v1 which
  732. * didn't pass a0 so no CMD_INITF_*.
  733. */
  734. vnic_dev_cmd(vdev, CMD_GET_MAC_ADDR, &a0, &a1, wait);
  735. vnic_dev_cmd(vdev, CMD_ADDR_ADD, &a0, &a1, wait);
  736. }
  737. }
  738. return r;
  739. }
  740. int vnic_dev_deinit(struct vnic_dev *vdev)
  741. {
  742. u64 a0 = 0, a1 = 0;
  743. int wait = 1000;
  744. return vnic_dev_cmd(vdev, CMD_DEINIT, &a0, &a1, wait);
  745. }
  746. void vnic_dev_intr_coal_timer_info_default(struct vnic_dev *vdev)
  747. {
  748. /* Default: hardware intr coal timer is in units of 1.5 usecs */
  749. vdev->intr_coal_timer_info.mul = 2;
  750. vdev->intr_coal_timer_info.div = 3;
  751. vdev->intr_coal_timer_info.max_usec =
  752. vnic_dev_intr_coal_timer_hw_to_usec(vdev, 0xffff);
  753. }
  754. int vnic_dev_intr_coal_timer_info(struct vnic_dev *vdev)
  755. {
  756. int wait = 1000;
  757. int err;
  758. memset(vdev->args, 0, sizeof(vdev->args));
  759. if (vnic_dev_capable(vdev, CMD_INTR_COAL_CONVERT))
  760. err = vdev->devcmd_rtn(vdev, CMD_INTR_COAL_CONVERT, wait);
  761. else
  762. err = ERR_ECMDUNKNOWN;
  763. /* Use defaults when firmware doesn't support the devcmd at all or
  764. * supports it for only specific hardware
  765. */
  766. if ((err == ERR_ECMDUNKNOWN) ||
  767. (!err && !(vdev->args[0] && vdev->args[1] && vdev->args[2]))) {
  768. vdev_netwarn(vdev, "Using default conversion factor for interrupt coalesce timer\n");
  769. vnic_dev_intr_coal_timer_info_default(vdev);
  770. return 0;
  771. }
  772. if (!err) {
  773. vdev->intr_coal_timer_info.mul = (u32) vdev->args[0];
  774. vdev->intr_coal_timer_info.div = (u32) vdev->args[1];
  775. vdev->intr_coal_timer_info.max_usec = (u32) vdev->args[2];
  776. }
  777. return err;
  778. }
  779. int vnic_dev_link_status(struct vnic_dev *vdev)
  780. {
  781. if (!vnic_dev_notify_ready(vdev))
  782. return 0;
  783. return vdev->notify_copy.link_state;
  784. }
  785. u32 vnic_dev_port_speed(struct vnic_dev *vdev)
  786. {
  787. if (!vnic_dev_notify_ready(vdev))
  788. return 0;
  789. return vdev->notify_copy.port_speed;
  790. }
  791. u32 vnic_dev_msg_lvl(struct vnic_dev *vdev)
  792. {
  793. if (!vnic_dev_notify_ready(vdev))
  794. return 0;
  795. return vdev->notify_copy.msglvl;
  796. }
  797. u32 vnic_dev_mtu(struct vnic_dev *vdev)
  798. {
  799. if (!vnic_dev_notify_ready(vdev))
  800. return 0;
  801. return vdev->notify_copy.mtu;
  802. }
  803. void vnic_dev_set_intr_mode(struct vnic_dev *vdev,
  804. enum vnic_dev_intr_mode intr_mode)
  805. {
  806. vdev->intr_mode = intr_mode;
  807. }
  808. enum vnic_dev_intr_mode vnic_dev_get_intr_mode(
  809. struct vnic_dev *vdev)
  810. {
  811. return vdev->intr_mode;
  812. }
  813. u32 vnic_dev_intr_coal_timer_usec_to_hw(struct vnic_dev *vdev, u32 usec)
  814. {
  815. return (usec * vdev->intr_coal_timer_info.mul) /
  816. vdev->intr_coal_timer_info.div;
  817. }
  818. u32 vnic_dev_intr_coal_timer_hw_to_usec(struct vnic_dev *vdev, u32 hw_cycles)
  819. {
  820. return (hw_cycles * vdev->intr_coal_timer_info.div) /
  821. vdev->intr_coal_timer_info.mul;
  822. }
  823. u32 vnic_dev_get_intr_coal_timer_max(struct vnic_dev *vdev)
  824. {
  825. return vdev->intr_coal_timer_info.max_usec;
  826. }
  827. void vnic_dev_unregister(struct vnic_dev *vdev)
  828. {
  829. if (vdev) {
  830. if (vdev->notify)
  831. dma_free_coherent(&vdev->pdev->dev,
  832. sizeof(struct vnic_devcmd_notify),
  833. vdev->notify, vdev->notify_pa);
  834. if (vdev->stats)
  835. dma_free_coherent(&vdev->pdev->dev,
  836. sizeof(struct vnic_stats),
  837. vdev->stats, vdev->stats_pa);
  838. if (vdev->fw_info)
  839. dma_free_coherent(&vdev->pdev->dev,
  840. sizeof(struct vnic_devcmd_fw_info),
  841. vdev->fw_info, vdev->fw_info_pa);
  842. if (vdev->devcmd2)
  843. vnic_dev_deinit_devcmd2(vdev);
  844. kfree(vdev);
  845. }
  846. }
  847. EXPORT_SYMBOL(vnic_dev_unregister);
  848. struct vnic_dev *vnic_dev_register(struct vnic_dev *vdev,
  849. void *priv, struct pci_dev *pdev, struct vnic_dev_bar *bar,
  850. unsigned int num_bars)
  851. {
  852. if (!vdev) {
  853. vdev = kzalloc(sizeof(struct vnic_dev), GFP_KERNEL);
  854. if (!vdev)
  855. return NULL;
  856. }
  857. vdev->priv = priv;
  858. vdev->pdev = pdev;
  859. if (vnic_dev_discover_res(vdev, bar, num_bars))
  860. goto err_out;
  861. return vdev;
  862. err_out:
  863. vnic_dev_unregister(vdev);
  864. return NULL;
  865. }
  866. EXPORT_SYMBOL(vnic_dev_register);
  867. struct pci_dev *vnic_dev_get_pdev(struct vnic_dev *vdev)
  868. {
  869. return vdev->pdev;
  870. }
  871. EXPORT_SYMBOL(vnic_dev_get_pdev);
  872. int vnic_devcmd_init(struct vnic_dev *vdev)
  873. {
  874. void __iomem *res;
  875. int err;
  876. res = vnic_dev_get_res(vdev, RES_TYPE_DEVCMD2, 0);
  877. if (res) {
  878. err = vnic_dev_init_devcmd2(vdev);
  879. if (err)
  880. vdev_warn(vdev, "DEVCMD2 init failed: %d, Using DEVCMD1\n",
  881. err);
  882. else
  883. return 0;
  884. } else {
  885. vdev_warn(vdev, "DEVCMD2 resource not found (old firmware?) Using DEVCMD1\n");
  886. }
  887. err = vnic_dev_init_devcmd1(vdev);
  888. if (err)
  889. vdev_err(vdev, "DEVCMD1 initialization failed: %d\n", err);
  890. return err;
  891. }
  892. int vnic_dev_init_prov2(struct vnic_dev *vdev, u8 *buf, u32 len)
  893. {
  894. u64 a0, a1 = len;
  895. int wait = 1000;
  896. dma_addr_t prov_pa;
  897. void *prov_buf;
  898. int ret;
  899. prov_buf = dma_alloc_coherent(&vdev->pdev->dev, len, &prov_pa, GFP_ATOMIC);
  900. if (!prov_buf)
  901. return -ENOMEM;
  902. memcpy(prov_buf, buf, len);
  903. a0 = prov_pa;
  904. ret = vnic_dev_cmd(vdev, CMD_INIT_PROV_INFO2, &a0, &a1, wait);
  905. dma_free_coherent(&vdev->pdev->dev, len, prov_buf, prov_pa);
  906. return ret;
  907. }
  908. int vnic_dev_enable2(struct vnic_dev *vdev, int active)
  909. {
  910. u64 a0, a1 = 0;
  911. int wait = 1000;
  912. a0 = (active ? CMD_ENABLE2_ACTIVE : 0);
  913. return vnic_dev_cmd(vdev, CMD_ENABLE2, &a0, &a1, wait);
  914. }
  915. static int vnic_dev_cmd_status(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
  916. int *status)
  917. {
  918. u64 a0 = cmd, a1 = 0;
  919. int wait = 1000;
  920. int ret;
  921. ret = vnic_dev_cmd(vdev, CMD_STATUS, &a0, &a1, wait);
  922. if (!ret)
  923. *status = (int)a0;
  924. return ret;
  925. }
  926. int vnic_dev_enable2_done(struct vnic_dev *vdev, int *status)
  927. {
  928. return vnic_dev_cmd_status(vdev, CMD_ENABLE2, status);
  929. }
  930. int vnic_dev_deinit_done(struct vnic_dev *vdev, int *status)
  931. {
  932. return vnic_dev_cmd_status(vdev, CMD_DEINIT, status);
  933. }
  934. int vnic_dev_set_mac_addr(struct vnic_dev *vdev, u8 *mac_addr)
  935. {
  936. u64 a0, a1;
  937. int wait = 1000;
  938. int i;
  939. for (i = 0; i < ETH_ALEN; i++)
  940. ((u8 *)&a0)[i] = mac_addr[i];
  941. return vnic_dev_cmd(vdev, CMD_SET_MAC_ADDR, &a0, &a1, wait);
  942. }
  943. /* vnic_dev_classifier: Add/Delete classifier entries
  944. * @vdev: vdev of the device
  945. * @cmd: CLSF_ADD for Add filter
  946. * CLSF_DEL for Delete filter
  947. * @entry: In case of ADD filter, the caller passes the RQ number in this
  948. * variable.
  949. *
  950. * This function stores the filter_id returned by the firmware in the
  951. * same variable before return;
  952. *
  953. * In case of DEL filter, the caller passes the RQ number. Return
  954. * value is irrelevant.
  955. * @data: filter data
  956. */
  957. int vnic_dev_classifier(struct vnic_dev *vdev, u8 cmd, u16 *entry,
  958. struct filter *data)
  959. {
  960. u64 a0, a1;
  961. int wait = 1000;
  962. dma_addr_t tlv_pa;
  963. int ret = -EINVAL;
  964. struct filter_tlv *tlv, *tlv_va;
  965. struct filter_action *action;
  966. u64 tlv_size;
  967. if (cmd == CLSF_ADD) {
  968. tlv_size = sizeof(struct filter) +
  969. sizeof(struct filter_action) +
  970. 2 * sizeof(struct filter_tlv);
  971. tlv_va = dma_alloc_coherent(&vdev->pdev->dev, tlv_size,
  972. &tlv_pa, GFP_ATOMIC);
  973. if (!tlv_va)
  974. return -ENOMEM;
  975. tlv = tlv_va;
  976. a0 = tlv_pa;
  977. a1 = tlv_size;
  978. memset(tlv, 0, tlv_size);
  979. tlv->type = CLSF_TLV_FILTER;
  980. tlv->length = sizeof(struct filter);
  981. *(struct filter *)&tlv->val = *data;
  982. tlv = (struct filter_tlv *)((char *)tlv +
  983. sizeof(struct filter_tlv) +
  984. sizeof(struct filter));
  985. tlv->type = CLSF_TLV_ACTION;
  986. tlv->length = sizeof(struct filter_action);
  987. action = (struct filter_action *)&tlv->val;
  988. action->type = FILTER_ACTION_RQ_STEERING;
  989. action->u.rq_idx = *entry;
  990. ret = vnic_dev_cmd(vdev, CMD_ADD_FILTER, &a0, &a1, wait);
  991. *entry = (u16)a0;
  992. dma_free_coherent(&vdev->pdev->dev, tlv_size, tlv_va, tlv_pa);
  993. } else if (cmd == CLSF_DEL) {
  994. a0 = *entry;
  995. ret = vnic_dev_cmd(vdev, CMD_DEL_FILTER, &a0, &a1, wait);
  996. }
  997. return ret;
  998. }
  999. int vnic_dev_overlay_offload_ctrl(struct vnic_dev *vdev, u8 overlay, u8 config)
  1000. {
  1001. u64 a0 = overlay;
  1002. u64 a1 = config;
  1003. int wait = 1000;
  1004. return vnic_dev_cmd(vdev, CMD_OVERLAY_OFFLOAD_CTRL, &a0, &a1, wait);
  1005. }
  1006. int vnic_dev_overlay_offload_cfg(struct vnic_dev *vdev, u8 overlay,
  1007. u16 vxlan_udp_port_number)
  1008. {
  1009. u64 a1 = vxlan_udp_port_number;
  1010. u64 a0 = overlay;
  1011. int wait = 1000;
  1012. return vnic_dev_cmd(vdev, CMD_OVERLAY_OFFLOAD_CFG, &a0, &a1, wait);
  1013. }
  1014. int vnic_dev_get_supported_feature_ver(struct vnic_dev *vdev, u8 feature,
  1015. u64 *supported_versions, u64 *a1)
  1016. {
  1017. u64 a0 = feature;
  1018. int wait = 1000;
  1019. int ret;
  1020. ret = vnic_dev_cmd(vdev, CMD_GET_SUPP_FEATURE_VER, &a0, a1, wait);
  1021. if (!ret)
  1022. *supported_versions = a0;
  1023. return ret;
  1024. }
  1025. int vnic_dev_capable_rss_hash_type(struct vnic_dev *vdev, u8 *rss_hash_type)
  1026. {
  1027. u64 a0 = CMD_NIC_CFG, a1 = 0;
  1028. int wait = 1000;
  1029. int err;
  1030. err = vnic_dev_cmd(vdev, CMD_CAPABILITY, &a0, &a1, wait);
  1031. /* rss_hash_type is valid only when a0 is 1. Adapter which does not
  1032. * support CMD_CAPABILITY for rss_hash_type has a0 = 0
  1033. */
  1034. if (err || (a0 != 1))
  1035. return -EOPNOTSUPP;
  1036. a1 = (a1 >> NIC_CFG_RSS_HASH_TYPE_SHIFT) &
  1037. NIC_CFG_RSS_HASH_TYPE_MASK_FIELD;
  1038. *rss_hash_type = (u8)a1;
  1039. return 0;
  1040. }