spectrum.c 157 KB

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  1. // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
  2. /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
  3. #include <linux/kernel.h>
  4. #include <linux/module.h>
  5. #include <linux/types.h>
  6. #include <linux/pci.h>
  7. #include <linux/netdevice.h>
  8. #include <linux/etherdevice.h>
  9. #include <linux/ethtool.h>
  10. #include <linux/slab.h>
  11. #include <linux/device.h>
  12. #include <linux/skbuff.h>
  13. #include <linux/if_vlan.h>
  14. #include <linux/if_bridge.h>
  15. #include <linux/workqueue.h>
  16. #include <linux/jiffies.h>
  17. #include <linux/bitops.h>
  18. #include <linux/list.h>
  19. #include <linux/notifier.h>
  20. #include <linux/dcbnl.h>
  21. #include <linux/inetdevice.h>
  22. #include <linux/netlink.h>
  23. #include <linux/jhash.h>
  24. #include <linux/log2.h>
  25. #include <linux/refcount.h>
  26. #include <linux/rhashtable.h>
  27. #include <net/switchdev.h>
  28. #include <net/pkt_cls.h>
  29. #include <net/netevent.h>
  30. #include <net/addrconf.h>
  31. #include <linux/ptp_classify.h>
  32. #include "spectrum.h"
  33. #include "pci.h"
  34. #include "core.h"
  35. #include "core_env.h"
  36. #include "reg.h"
  37. #include "port.h"
  38. #include "trap.h"
  39. #include "txheader.h"
  40. #include "spectrum_cnt.h"
  41. #include "spectrum_dpipe.h"
  42. #include "spectrum_acl_flex_actions.h"
  43. #include "spectrum_span.h"
  44. #include "spectrum_ptp.h"
  45. #include "spectrum_trap.h"
  46. #define MLXSW_SP_FWREV_MINOR 2010
  47. #define MLXSW_SP_FWREV_SUBMINOR 1006
  48. #define MLXSW_SP1_FWREV_MAJOR 13
  49. #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
  50. static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
  51. .major = MLXSW_SP1_FWREV_MAJOR,
  52. .minor = MLXSW_SP_FWREV_MINOR,
  53. .subminor = MLXSW_SP_FWREV_SUBMINOR,
  54. .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
  55. };
  56. #define MLXSW_SP1_FW_FILENAME \
  57. "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
  58. "." __stringify(MLXSW_SP_FWREV_MINOR) \
  59. "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2"
  60. #define MLXSW_SP2_FWREV_MAJOR 29
  61. static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = {
  62. .major = MLXSW_SP2_FWREV_MAJOR,
  63. .minor = MLXSW_SP_FWREV_MINOR,
  64. .subminor = MLXSW_SP_FWREV_SUBMINOR,
  65. };
  66. #define MLXSW_SP2_FW_FILENAME \
  67. "mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \
  68. "." __stringify(MLXSW_SP_FWREV_MINOR) \
  69. "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2"
  70. #define MLXSW_SP3_FWREV_MAJOR 30
  71. static const struct mlxsw_fw_rev mlxsw_sp3_fw_rev = {
  72. .major = MLXSW_SP3_FWREV_MAJOR,
  73. .minor = MLXSW_SP_FWREV_MINOR,
  74. .subminor = MLXSW_SP_FWREV_SUBMINOR,
  75. };
  76. #define MLXSW_SP3_FW_FILENAME \
  77. "mellanox/mlxsw_spectrum3-" __stringify(MLXSW_SP3_FWREV_MAJOR) \
  78. "." __stringify(MLXSW_SP_FWREV_MINOR) \
  79. "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2"
  80. #define MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME \
  81. "mellanox/lc_ini_bundle_" \
  82. __stringify(MLXSW_SP_FWREV_MINOR) "_" \
  83. __stringify(MLXSW_SP_FWREV_SUBMINOR) ".bin"
  84. static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
  85. static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
  86. static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3";
  87. static const char mlxsw_sp4_driver_name[] = "mlxsw_spectrum4";
  88. static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
  89. 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
  90. };
  91. static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
  92. 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
  93. };
  94. /* tx_hdr_version
  95. * Tx header version.
  96. * Must be set to 1.
  97. */
  98. MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
  99. /* tx_hdr_ctl
  100. * Packet control type.
  101. * 0 - Ethernet control (e.g. EMADs, LACP)
  102. * 1 - Ethernet data
  103. */
  104. MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
  105. /* tx_hdr_proto
  106. * Packet protocol type. Must be set to 1 (Ethernet).
  107. */
  108. MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
  109. /* tx_hdr_rx_is_router
  110. * Packet is sent from the router. Valid for data packets only.
  111. */
  112. MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
  113. /* tx_hdr_fid_valid
  114. * Indicates if the 'fid' field is valid and should be used for
  115. * forwarding lookup. Valid for data packets only.
  116. */
  117. MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
  118. /* tx_hdr_swid
  119. * Switch partition ID. Must be set to 0.
  120. */
  121. MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
  122. /* tx_hdr_control_tclass
  123. * Indicates if the packet should use the control TClass and not one
  124. * of the data TClasses.
  125. */
  126. MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
  127. /* tx_hdr_etclass
  128. * Egress TClass to be used on the egress device on the egress port.
  129. */
  130. MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
  131. /* tx_hdr_port_mid
  132. * Destination local port for unicast packets.
  133. * Destination multicast ID for multicast packets.
  134. *
  135. * Control packets are directed to a specific egress port, while data
  136. * packets are transmitted through the CPU port (0) into the switch partition,
  137. * where forwarding rules are applied.
  138. */
  139. MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
  140. /* tx_hdr_fid
  141. * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
  142. * set, otherwise calculated based on the packet's VID using VID to FID mapping.
  143. * Valid for data packets only.
  144. */
  145. MLXSW_ITEM32(tx, hdr, fid, 0x08, 16, 16);
  146. /* tx_hdr_type
  147. * 0 - Data packets
  148. * 6 - Control packets
  149. */
  150. MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
  151. int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
  152. unsigned int counter_index, bool clear,
  153. u64 *packets, u64 *bytes)
  154. {
  155. enum mlxsw_reg_mgpc_opcode op = clear ? MLXSW_REG_MGPC_OPCODE_CLEAR :
  156. MLXSW_REG_MGPC_OPCODE_NOP;
  157. char mgpc_pl[MLXSW_REG_MGPC_LEN];
  158. int err;
  159. mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, op,
  160. MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
  161. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
  162. if (err)
  163. return err;
  164. if (packets)
  165. *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
  166. if (bytes)
  167. *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
  168. return 0;
  169. }
  170. static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
  171. unsigned int counter_index)
  172. {
  173. char mgpc_pl[MLXSW_REG_MGPC_LEN];
  174. mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
  175. MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
  176. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
  177. }
  178. int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
  179. unsigned int *p_counter_index)
  180. {
  181. int err;
  182. err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
  183. p_counter_index);
  184. if (err)
  185. return err;
  186. err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
  187. if (err)
  188. goto err_counter_clear;
  189. return 0;
  190. err_counter_clear:
  191. mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
  192. *p_counter_index);
  193. return err;
  194. }
  195. void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
  196. unsigned int counter_index)
  197. {
  198. mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
  199. counter_index);
  200. }
  201. void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
  202. const struct mlxsw_tx_info *tx_info)
  203. {
  204. char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
  205. memset(txhdr, 0, MLXSW_TXHDR_LEN);
  206. mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
  207. mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
  208. mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
  209. mlxsw_tx_hdr_swid_set(txhdr, 0);
  210. mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
  211. mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
  212. mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
  213. }
  214. int
  215. mlxsw_sp_txhdr_ptp_data_construct(struct mlxsw_core *mlxsw_core,
  216. struct mlxsw_sp_port *mlxsw_sp_port,
  217. struct sk_buff *skb,
  218. const struct mlxsw_tx_info *tx_info)
  219. {
  220. char *txhdr;
  221. u16 max_fid;
  222. int err;
  223. if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
  224. err = -ENOMEM;
  225. goto err_skb_cow_head;
  226. }
  227. if (!MLXSW_CORE_RES_VALID(mlxsw_core, FID)) {
  228. err = -EIO;
  229. goto err_res_valid;
  230. }
  231. max_fid = MLXSW_CORE_RES_GET(mlxsw_core, FID);
  232. txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
  233. memset(txhdr, 0, MLXSW_TXHDR_LEN);
  234. mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
  235. mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
  236. mlxsw_tx_hdr_rx_is_router_set(txhdr, true);
  237. mlxsw_tx_hdr_fid_valid_set(txhdr, true);
  238. mlxsw_tx_hdr_fid_set(txhdr, max_fid + tx_info->local_port - 1);
  239. mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_DATA);
  240. return 0;
  241. err_res_valid:
  242. err_skb_cow_head:
  243. this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
  244. dev_kfree_skb_any(skb);
  245. return err;
  246. }
  247. static bool mlxsw_sp_skb_requires_ts(struct sk_buff *skb)
  248. {
  249. unsigned int type;
  250. if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
  251. return false;
  252. type = ptp_classify_raw(skb);
  253. return !!ptp_parse_header(skb, type);
  254. }
  255. static int mlxsw_sp_txhdr_handle(struct mlxsw_core *mlxsw_core,
  256. struct mlxsw_sp_port *mlxsw_sp_port,
  257. struct sk_buff *skb,
  258. const struct mlxsw_tx_info *tx_info)
  259. {
  260. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  261. /* In Spectrum-2 and Spectrum-3, PTP events that require a time stamp
  262. * need special handling and cannot be transmitted as regular control
  263. * packets.
  264. */
  265. if (unlikely(mlxsw_sp_skb_requires_ts(skb)))
  266. return mlxsw_sp->ptp_ops->txhdr_construct(mlxsw_core,
  267. mlxsw_sp_port, skb,
  268. tx_info);
  269. if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
  270. this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
  271. dev_kfree_skb_any(skb);
  272. return -ENOMEM;
  273. }
  274. mlxsw_sp_txhdr_construct(skb, tx_info);
  275. return 0;
  276. }
  277. enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
  278. {
  279. switch (state) {
  280. case BR_STATE_FORWARDING:
  281. return MLXSW_REG_SPMS_STATE_FORWARDING;
  282. case BR_STATE_LEARNING:
  283. return MLXSW_REG_SPMS_STATE_LEARNING;
  284. case BR_STATE_LISTENING:
  285. case BR_STATE_DISABLED:
  286. case BR_STATE_BLOCKING:
  287. return MLXSW_REG_SPMS_STATE_DISCARDING;
  288. default:
  289. BUG();
  290. }
  291. }
  292. int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
  293. u8 state)
  294. {
  295. enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
  296. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  297. char *spms_pl;
  298. int err;
  299. spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
  300. if (!spms_pl)
  301. return -ENOMEM;
  302. mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
  303. mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
  304. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
  305. kfree(spms_pl);
  306. return err;
  307. }
  308. static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
  309. {
  310. char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
  311. int err;
  312. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
  313. if (err)
  314. return err;
  315. mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
  316. return 0;
  317. }
  318. int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
  319. bool is_up)
  320. {
  321. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  322. char paos_pl[MLXSW_REG_PAOS_LEN];
  323. mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
  324. is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
  325. MLXSW_PORT_ADMIN_STATUS_DOWN);
  326. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
  327. }
  328. static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
  329. const unsigned char *addr)
  330. {
  331. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  332. char ppad_pl[MLXSW_REG_PPAD_LEN];
  333. mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
  334. mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
  335. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
  336. }
  337. static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
  338. {
  339. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  340. eth_hw_addr_gen(mlxsw_sp_port->dev, mlxsw_sp->base_mac,
  341. mlxsw_sp_port->local_port);
  342. return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port,
  343. mlxsw_sp_port->dev->dev_addr);
  344. }
  345. static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
  346. {
  347. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  348. char pmtu_pl[MLXSW_REG_PMTU_LEN];
  349. mtu += MLXSW_PORT_ETH_FRAME_HDR;
  350. mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
  351. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
  352. }
  353. static int mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp,
  354. u16 local_port, u8 swid)
  355. {
  356. char pspa_pl[MLXSW_REG_PSPA_LEN];
  357. mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
  358. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
  359. }
  360. int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
  361. {
  362. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  363. char svpe_pl[MLXSW_REG_SVPE_LEN];
  364. mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
  365. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
  366. }
  367. int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
  368. bool learn_enable)
  369. {
  370. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  371. char *spvmlr_pl;
  372. int err;
  373. spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
  374. if (!spvmlr_pl)
  375. return -ENOMEM;
  376. mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
  377. learn_enable);
  378. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
  379. kfree(spvmlr_pl);
  380. return err;
  381. }
  382. int mlxsw_sp_port_security_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
  383. {
  384. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  385. char spfsr_pl[MLXSW_REG_SPFSR_LEN];
  386. int err;
  387. if (mlxsw_sp_port->security == enable)
  388. return 0;
  389. mlxsw_reg_spfsr_pack(spfsr_pl, mlxsw_sp_port->local_port, enable);
  390. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spfsr), spfsr_pl);
  391. if (err)
  392. return err;
  393. mlxsw_sp_port->security = enable;
  394. return 0;
  395. }
  396. int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type)
  397. {
  398. switch (ethtype) {
  399. case ETH_P_8021Q:
  400. *p_sver_type = 0;
  401. break;
  402. case ETH_P_8021AD:
  403. *p_sver_type = 1;
  404. break;
  405. default:
  406. return -EINVAL;
  407. }
  408. return 0;
  409. }
  410. int mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port *mlxsw_sp_port,
  411. u16 ethtype)
  412. {
  413. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  414. char spevet_pl[MLXSW_REG_SPEVET_LEN];
  415. u8 sver_type;
  416. int err;
  417. err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type);
  418. if (err)
  419. return err;
  420. mlxsw_reg_spevet_pack(spevet_pl, mlxsw_sp_port->local_port, sver_type);
  421. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spevet), spevet_pl);
  422. }
  423. static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
  424. u16 vid, u16 ethtype)
  425. {
  426. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  427. char spvid_pl[MLXSW_REG_SPVID_LEN];
  428. u8 sver_type;
  429. int err;
  430. err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type);
  431. if (err)
  432. return err;
  433. mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid,
  434. sver_type);
  435. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
  436. }
  437. static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
  438. bool allow)
  439. {
  440. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  441. char spaft_pl[MLXSW_REG_SPAFT_LEN];
  442. mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
  443. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
  444. }
  445. int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
  446. u16 ethtype)
  447. {
  448. int err;
  449. if (!vid) {
  450. err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
  451. if (err)
  452. return err;
  453. } else {
  454. err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid, ethtype);
  455. if (err)
  456. return err;
  457. err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
  458. if (err)
  459. goto err_port_allow_untagged_set;
  460. }
  461. mlxsw_sp_port->pvid = vid;
  462. return 0;
  463. err_port_allow_untagged_set:
  464. __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid, ethtype);
  465. return err;
  466. }
  467. static int
  468. mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
  469. {
  470. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  471. char sspr_pl[MLXSW_REG_SSPR_LEN];
  472. mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
  473. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
  474. }
  475. static int
  476. mlxsw_sp_port_module_info_parse(struct mlxsw_sp *mlxsw_sp,
  477. u16 local_port, char *pmlp_pl,
  478. struct mlxsw_sp_port_mapping *port_mapping)
  479. {
  480. bool separate_rxtx;
  481. u8 first_lane;
  482. u8 slot_index;
  483. u8 module;
  484. u8 width;
  485. int i;
  486. module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
  487. slot_index = mlxsw_reg_pmlp_slot_index_get(pmlp_pl, 0);
  488. width = mlxsw_reg_pmlp_width_get(pmlp_pl);
  489. separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl);
  490. first_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
  491. if (width && !is_power_of_2(width)) {
  492. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n",
  493. local_port);
  494. return -EINVAL;
  495. }
  496. for (i = 0; i < width; i++) {
  497. if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) {
  498. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n",
  499. local_port);
  500. return -EINVAL;
  501. }
  502. if (mlxsw_reg_pmlp_slot_index_get(pmlp_pl, i) != slot_index) {
  503. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple slot indexes\n",
  504. local_port);
  505. return -EINVAL;
  506. }
  507. if (separate_rxtx &&
  508. mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) !=
  509. mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) {
  510. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n",
  511. local_port);
  512. return -EINVAL;
  513. }
  514. if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i + first_lane) {
  515. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n",
  516. local_port);
  517. return -EINVAL;
  518. }
  519. }
  520. port_mapping->module = module;
  521. port_mapping->slot_index = slot_index;
  522. port_mapping->width = width;
  523. port_mapping->module_width = width;
  524. port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
  525. return 0;
  526. }
  527. static int
  528. mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u16 local_port,
  529. struct mlxsw_sp_port_mapping *port_mapping)
  530. {
  531. char pmlp_pl[MLXSW_REG_PMLP_LEN];
  532. int err;
  533. mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
  534. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
  535. if (err)
  536. return err;
  537. return mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port,
  538. pmlp_pl, port_mapping);
  539. }
  540. static int
  541. mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u16 local_port,
  542. const struct mlxsw_sp_port_mapping *port_mapping)
  543. {
  544. char pmlp_pl[MLXSW_REG_PMLP_LEN];
  545. int i, err;
  546. mlxsw_env_module_port_map(mlxsw_sp->core, port_mapping->slot_index,
  547. port_mapping->module);
  548. mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
  549. mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width);
  550. for (i = 0; i < port_mapping->width; i++) {
  551. mlxsw_reg_pmlp_slot_index_set(pmlp_pl, i,
  552. port_mapping->slot_index);
  553. mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module);
  554. mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */
  555. }
  556. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
  557. if (err)
  558. goto err_pmlp_write;
  559. return 0;
  560. err_pmlp_write:
  561. mlxsw_env_module_port_unmap(mlxsw_sp->core, port_mapping->slot_index,
  562. port_mapping->module);
  563. return err;
  564. }
  565. static void mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u16 local_port,
  566. u8 slot_index, u8 module)
  567. {
  568. char pmlp_pl[MLXSW_REG_PMLP_LEN];
  569. mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
  570. mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
  571. mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
  572. mlxsw_env_module_port_unmap(mlxsw_sp->core, slot_index, module);
  573. }
  574. static int mlxsw_sp_port_open(struct net_device *dev)
  575. {
  576. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  577. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  578. int err;
  579. err = mlxsw_env_module_port_up(mlxsw_sp->core,
  580. mlxsw_sp_port->mapping.slot_index,
  581. mlxsw_sp_port->mapping.module);
  582. if (err)
  583. return err;
  584. err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
  585. if (err)
  586. goto err_port_admin_status_set;
  587. netif_start_queue(dev);
  588. return 0;
  589. err_port_admin_status_set:
  590. mlxsw_env_module_port_down(mlxsw_sp->core,
  591. mlxsw_sp_port->mapping.slot_index,
  592. mlxsw_sp_port->mapping.module);
  593. return err;
  594. }
  595. static int mlxsw_sp_port_stop(struct net_device *dev)
  596. {
  597. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  598. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  599. netif_stop_queue(dev);
  600. mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
  601. mlxsw_env_module_port_down(mlxsw_sp->core,
  602. mlxsw_sp_port->mapping.slot_index,
  603. mlxsw_sp_port->mapping.module);
  604. return 0;
  605. }
  606. static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
  607. struct net_device *dev)
  608. {
  609. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  610. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  611. struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
  612. const struct mlxsw_tx_info tx_info = {
  613. .local_port = mlxsw_sp_port->local_port,
  614. .is_emad = false,
  615. };
  616. u64 len;
  617. int err;
  618. memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
  619. if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
  620. return NETDEV_TX_BUSY;
  621. if (eth_skb_pad(skb)) {
  622. this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
  623. return NETDEV_TX_OK;
  624. }
  625. err = mlxsw_sp_txhdr_handle(mlxsw_sp->core, mlxsw_sp_port, skb,
  626. &tx_info);
  627. if (err)
  628. return NETDEV_TX_OK;
  629. /* TX header is consumed by HW on the way so we shouldn't count its
  630. * bytes as being sent.
  631. */
  632. len = skb->len - MLXSW_TXHDR_LEN;
  633. /* Due to a race we might fail here because of a full queue. In that
  634. * unlikely case we simply drop the packet.
  635. */
  636. err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
  637. if (!err) {
  638. pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
  639. u64_stats_update_begin(&pcpu_stats->syncp);
  640. pcpu_stats->tx_packets++;
  641. pcpu_stats->tx_bytes += len;
  642. u64_stats_update_end(&pcpu_stats->syncp);
  643. } else {
  644. this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
  645. dev_kfree_skb_any(skb);
  646. }
  647. return NETDEV_TX_OK;
  648. }
  649. static void mlxsw_sp_set_rx_mode(struct net_device *dev)
  650. {
  651. }
  652. static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
  653. {
  654. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  655. struct sockaddr *addr = p;
  656. int err;
  657. if (!is_valid_ether_addr(addr->sa_data))
  658. return -EADDRNOTAVAIL;
  659. err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
  660. if (err)
  661. return err;
  662. eth_hw_addr_set(dev, addr->sa_data);
  663. return 0;
  664. }
  665. static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
  666. {
  667. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  668. struct mlxsw_sp_hdroom orig_hdroom;
  669. struct mlxsw_sp_hdroom hdroom;
  670. int err;
  671. orig_hdroom = *mlxsw_sp_port->hdroom;
  672. hdroom = orig_hdroom;
  673. hdroom.mtu = mtu;
  674. mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
  675. err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
  676. if (err) {
  677. netdev_err(dev, "Failed to configure port's headroom\n");
  678. return err;
  679. }
  680. err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
  681. if (err)
  682. goto err_port_mtu_set;
  683. WRITE_ONCE(dev->mtu, mtu);
  684. return 0;
  685. err_port_mtu_set:
  686. mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom);
  687. return err;
  688. }
  689. static int
  690. mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
  691. struct rtnl_link_stats64 *stats)
  692. {
  693. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  694. struct mlxsw_sp_port_pcpu_stats *p;
  695. u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
  696. u32 tx_dropped = 0;
  697. unsigned int start;
  698. int i;
  699. for_each_possible_cpu(i) {
  700. p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
  701. do {
  702. start = u64_stats_fetch_begin(&p->syncp);
  703. rx_packets = p->rx_packets;
  704. rx_bytes = p->rx_bytes;
  705. tx_packets = p->tx_packets;
  706. tx_bytes = p->tx_bytes;
  707. } while (u64_stats_fetch_retry(&p->syncp, start));
  708. stats->rx_packets += rx_packets;
  709. stats->rx_bytes += rx_bytes;
  710. stats->tx_packets += tx_packets;
  711. stats->tx_bytes += tx_bytes;
  712. /* tx_dropped is u32, updated without syncp protection. */
  713. tx_dropped += p->tx_dropped;
  714. }
  715. stats->tx_dropped = tx_dropped;
  716. return 0;
  717. }
  718. static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
  719. {
  720. switch (attr_id) {
  721. case IFLA_OFFLOAD_XSTATS_CPU_HIT:
  722. return true;
  723. }
  724. return false;
  725. }
  726. static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
  727. void *sp)
  728. {
  729. switch (attr_id) {
  730. case IFLA_OFFLOAD_XSTATS_CPU_HIT:
  731. return mlxsw_sp_port_get_sw_stats64(dev, sp);
  732. }
  733. return -EINVAL;
  734. }
  735. int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
  736. int prio, char *ppcnt_pl)
  737. {
  738. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  739. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  740. mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
  741. return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
  742. }
  743. static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
  744. struct rtnl_link_stats64 *stats)
  745. {
  746. char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
  747. int err;
  748. err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
  749. 0, ppcnt_pl);
  750. if (err)
  751. goto out;
  752. stats->tx_packets =
  753. mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
  754. stats->rx_packets =
  755. mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
  756. stats->tx_bytes =
  757. mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
  758. stats->rx_bytes =
  759. mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
  760. stats->multicast =
  761. mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
  762. stats->rx_crc_errors =
  763. mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
  764. stats->rx_frame_errors =
  765. mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
  766. stats->rx_length_errors = (
  767. mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
  768. mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
  769. mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
  770. stats->rx_errors = (stats->rx_crc_errors +
  771. stats->rx_frame_errors + stats->rx_length_errors);
  772. out:
  773. return err;
  774. }
  775. static void
  776. mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
  777. struct mlxsw_sp_port_xstats *xstats)
  778. {
  779. char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
  780. int err, i;
  781. err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
  782. ppcnt_pl);
  783. if (!err)
  784. xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
  785. for (i = 0; i < TC_MAX_QUEUE; i++) {
  786. err = mlxsw_sp_port_get_stats_raw(dev,
  787. MLXSW_REG_PPCNT_TC_CONG_CNT,
  788. i, ppcnt_pl);
  789. if (err)
  790. goto tc_cnt;
  791. xstats->wred_drop[i] =
  792. mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
  793. xstats->tc_ecn[i] = mlxsw_reg_ppcnt_ecn_marked_tc_get(ppcnt_pl);
  794. tc_cnt:
  795. err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
  796. i, ppcnt_pl);
  797. if (err)
  798. continue;
  799. xstats->backlog[i] =
  800. mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
  801. xstats->tail_drop[i] =
  802. mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
  803. }
  804. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  805. err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
  806. i, ppcnt_pl);
  807. if (err)
  808. continue;
  809. xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
  810. xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
  811. }
  812. }
  813. static void update_stats_cache(struct work_struct *work)
  814. {
  815. struct mlxsw_sp_port *mlxsw_sp_port =
  816. container_of(work, struct mlxsw_sp_port,
  817. periodic_hw_stats.update_dw.work);
  818. if (!netif_carrier_ok(mlxsw_sp_port->dev))
  819. /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as
  820. * necessary when port goes down.
  821. */
  822. goto out;
  823. mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
  824. &mlxsw_sp_port->periodic_hw_stats.stats);
  825. mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
  826. &mlxsw_sp_port->periodic_hw_stats.xstats);
  827. out:
  828. mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
  829. MLXSW_HW_STATS_UPDATE_TIME);
  830. }
  831. /* Return the stats from a cache that is updated periodically,
  832. * as this function might get called in an atomic context.
  833. */
  834. static void
  835. mlxsw_sp_port_get_stats64(struct net_device *dev,
  836. struct rtnl_link_stats64 *stats)
  837. {
  838. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  839. memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
  840. }
  841. static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
  842. u16 vid_begin, u16 vid_end,
  843. bool is_member, bool untagged)
  844. {
  845. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  846. char *spvm_pl;
  847. int err;
  848. spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
  849. if (!spvm_pl)
  850. return -ENOMEM;
  851. mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
  852. vid_end, is_member, untagged);
  853. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
  854. kfree(spvm_pl);
  855. return err;
  856. }
  857. int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
  858. u16 vid_end, bool is_member, bool untagged)
  859. {
  860. u16 vid, vid_e;
  861. int err;
  862. for (vid = vid_begin; vid <= vid_end;
  863. vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
  864. vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
  865. vid_end);
  866. err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
  867. is_member, untagged);
  868. if (err)
  869. return err;
  870. }
  871. return 0;
  872. }
  873. static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
  874. bool flush_default)
  875. {
  876. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
  877. list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
  878. &mlxsw_sp_port->vlans_list, list) {
  879. if (!flush_default &&
  880. mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
  881. continue;
  882. mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
  883. }
  884. }
  885. static void
  886. mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
  887. {
  888. if (mlxsw_sp_port_vlan->bridge_port)
  889. mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
  890. else if (mlxsw_sp_port_vlan->fid)
  891. mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
  892. }
  893. struct mlxsw_sp_port_vlan *
  894. mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
  895. {
  896. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  897. bool untagged = vid == MLXSW_SP_DEFAULT_VID;
  898. int err;
  899. mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
  900. if (mlxsw_sp_port_vlan)
  901. return ERR_PTR(-EEXIST);
  902. err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
  903. if (err)
  904. return ERR_PTR(err);
  905. mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
  906. if (!mlxsw_sp_port_vlan) {
  907. err = -ENOMEM;
  908. goto err_port_vlan_alloc;
  909. }
  910. mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
  911. mlxsw_sp_port_vlan->vid = vid;
  912. list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
  913. return mlxsw_sp_port_vlan;
  914. err_port_vlan_alloc:
  915. mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
  916. return ERR_PTR(err);
  917. }
  918. void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
  919. {
  920. struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
  921. u16 vid = mlxsw_sp_port_vlan->vid;
  922. mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
  923. list_del(&mlxsw_sp_port_vlan->list);
  924. kfree(mlxsw_sp_port_vlan);
  925. mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
  926. }
  927. static int mlxsw_sp_port_add_vid(struct net_device *dev,
  928. __be16 __always_unused proto, u16 vid)
  929. {
  930. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  931. /* VLAN 0 is added to HW filter when device goes up, but it is
  932. * reserved in our case, so simply return.
  933. */
  934. if (!vid)
  935. return 0;
  936. return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
  937. }
  938. int mlxsw_sp_port_kill_vid(struct net_device *dev,
  939. __be16 __always_unused proto, u16 vid)
  940. {
  941. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  942. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  943. /* VLAN 0 is removed from HW filter when device goes down, but
  944. * it is reserved in our case, so simply return.
  945. */
  946. if (!vid)
  947. return 0;
  948. mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
  949. if (!mlxsw_sp_port_vlan)
  950. return 0;
  951. mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
  952. return 0;
  953. }
  954. static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
  955. struct flow_block_offload *f)
  956. {
  957. switch (f->binder_type) {
  958. case FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS:
  959. return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, true);
  960. case FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS:
  961. return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, false);
  962. case FLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP:
  963. return mlxsw_sp_setup_tc_block_qevent_early_drop(mlxsw_sp_port, f);
  964. case FLOW_BLOCK_BINDER_TYPE_RED_MARK:
  965. return mlxsw_sp_setup_tc_block_qevent_mark(mlxsw_sp_port, f);
  966. default:
  967. return -EOPNOTSUPP;
  968. }
  969. }
  970. static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
  971. void *type_data)
  972. {
  973. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  974. switch (type) {
  975. case TC_SETUP_BLOCK:
  976. return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
  977. case TC_SETUP_QDISC_RED:
  978. return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
  979. case TC_SETUP_QDISC_PRIO:
  980. return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
  981. case TC_SETUP_QDISC_ETS:
  982. return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data);
  983. case TC_SETUP_QDISC_TBF:
  984. return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data);
  985. case TC_SETUP_QDISC_FIFO:
  986. return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data);
  987. default:
  988. return -EOPNOTSUPP;
  989. }
  990. }
  991. static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
  992. {
  993. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  994. if (!enable) {
  995. if (mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->ing_flow_block) ||
  996. mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->eg_flow_block)) {
  997. netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
  998. return -EINVAL;
  999. }
  1000. mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->ing_flow_block);
  1001. mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->eg_flow_block);
  1002. } else {
  1003. mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->ing_flow_block);
  1004. mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->eg_flow_block);
  1005. }
  1006. return 0;
  1007. }
  1008. static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable)
  1009. {
  1010. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1011. char pplr_pl[MLXSW_REG_PPLR_LEN];
  1012. int err;
  1013. if (netif_running(dev))
  1014. mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
  1015. mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable);
  1016. err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
  1017. pplr_pl);
  1018. if (netif_running(dev))
  1019. mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
  1020. return err;
  1021. }
  1022. typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
  1023. static int mlxsw_sp_handle_feature(struct net_device *dev,
  1024. netdev_features_t wanted_features,
  1025. netdev_features_t feature,
  1026. mlxsw_sp_feature_handler feature_handler)
  1027. {
  1028. netdev_features_t changes = wanted_features ^ dev->features;
  1029. bool enable = !!(wanted_features & feature);
  1030. int err;
  1031. if (!(changes & feature))
  1032. return 0;
  1033. err = feature_handler(dev, enable);
  1034. if (err) {
  1035. netdev_err(dev, "%s feature %pNF failed, err %d\n",
  1036. enable ? "Enable" : "Disable", &feature, err);
  1037. return err;
  1038. }
  1039. if (enable)
  1040. dev->features |= feature;
  1041. else
  1042. dev->features &= ~feature;
  1043. return 0;
  1044. }
  1045. static int mlxsw_sp_set_features(struct net_device *dev,
  1046. netdev_features_t features)
  1047. {
  1048. netdev_features_t oper_features = dev->features;
  1049. int err = 0;
  1050. err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
  1051. mlxsw_sp_feature_hw_tc);
  1052. err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK,
  1053. mlxsw_sp_feature_loopback);
  1054. if (err) {
  1055. dev->features = oper_features;
  1056. return -EINVAL;
  1057. }
  1058. return 0;
  1059. }
  1060. static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
  1061. struct ifreq *ifr)
  1062. {
  1063. struct hwtstamp_config config;
  1064. int err;
  1065. if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
  1066. return -EFAULT;
  1067. err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
  1068. &config);
  1069. if (err)
  1070. return err;
  1071. if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
  1072. return -EFAULT;
  1073. return 0;
  1074. }
  1075. static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
  1076. struct ifreq *ifr)
  1077. {
  1078. struct hwtstamp_config config;
  1079. int err;
  1080. err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
  1081. &config);
  1082. if (err)
  1083. return err;
  1084. if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
  1085. return -EFAULT;
  1086. return 0;
  1087. }
  1088. static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port)
  1089. {
  1090. struct hwtstamp_config config = {0};
  1091. mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config);
  1092. }
  1093. static int
  1094. mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1095. {
  1096. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  1097. switch (cmd) {
  1098. case SIOCSHWTSTAMP:
  1099. return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr);
  1100. case SIOCGHWTSTAMP:
  1101. return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr);
  1102. default:
  1103. return -EOPNOTSUPP;
  1104. }
  1105. }
  1106. static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
  1107. .ndo_open = mlxsw_sp_port_open,
  1108. .ndo_stop = mlxsw_sp_port_stop,
  1109. .ndo_start_xmit = mlxsw_sp_port_xmit,
  1110. .ndo_setup_tc = mlxsw_sp_setup_tc,
  1111. .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
  1112. .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
  1113. .ndo_change_mtu = mlxsw_sp_port_change_mtu,
  1114. .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
  1115. .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
  1116. .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
  1117. .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
  1118. .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
  1119. .ndo_set_features = mlxsw_sp_set_features,
  1120. .ndo_eth_ioctl = mlxsw_sp_port_ioctl,
  1121. };
  1122. static int
  1123. mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port)
  1124. {
  1125. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1126. u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
  1127. const struct mlxsw_sp_port_type_speed_ops *ops;
  1128. char ptys_pl[MLXSW_REG_PTYS_LEN];
  1129. u32 eth_proto_cap_masked;
  1130. int err;
  1131. ops = mlxsw_sp->port_type_speed_ops;
  1132. /* Set advertised speeds to speeds supported by both the driver
  1133. * and the device.
  1134. */
  1135. ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
  1136. 0, false);
  1137. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
  1138. if (err)
  1139. return err;
  1140. ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, &eth_proto_cap,
  1141. &eth_proto_admin, &eth_proto_oper);
  1142. eth_proto_cap_masked = ops->ptys_proto_cap_masked_get(eth_proto_cap);
  1143. ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
  1144. eth_proto_cap_masked,
  1145. mlxsw_sp_port->link.autoneg);
  1146. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
  1147. }
  1148. int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed)
  1149. {
  1150. const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops;
  1151. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1152. char ptys_pl[MLXSW_REG_PTYS_LEN];
  1153. u32 eth_proto_oper;
  1154. int err;
  1155. port_type_speed_ops = mlxsw_sp->port_type_speed_ops;
  1156. port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl,
  1157. mlxsw_sp_port->local_port, 0,
  1158. false);
  1159. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
  1160. if (err)
  1161. return err;
  1162. port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL,
  1163. &eth_proto_oper);
  1164. *speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper);
  1165. return 0;
  1166. }
  1167. int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
  1168. enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
  1169. bool dwrr, u8 dwrr_weight)
  1170. {
  1171. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1172. char qeec_pl[MLXSW_REG_QEEC_LEN];
  1173. mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
  1174. next_index);
  1175. mlxsw_reg_qeec_de_set(qeec_pl, true);
  1176. mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
  1177. mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
  1178. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
  1179. }
  1180. int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
  1181. enum mlxsw_reg_qeec_hr hr, u8 index,
  1182. u8 next_index, u32 maxrate, u8 burst_size)
  1183. {
  1184. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1185. char qeec_pl[MLXSW_REG_QEEC_LEN];
  1186. mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
  1187. next_index);
  1188. mlxsw_reg_qeec_mase_set(qeec_pl, true);
  1189. mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
  1190. mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size);
  1191. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
  1192. }
  1193. static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
  1194. enum mlxsw_reg_qeec_hr hr, u8 index,
  1195. u8 next_index, u32 minrate)
  1196. {
  1197. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1198. char qeec_pl[MLXSW_REG_QEEC_LEN];
  1199. mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
  1200. next_index);
  1201. mlxsw_reg_qeec_mise_set(qeec_pl, true);
  1202. mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
  1203. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
  1204. }
  1205. int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
  1206. u8 switch_prio, u8 tclass)
  1207. {
  1208. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1209. char qtct_pl[MLXSW_REG_QTCT_LEN];
  1210. mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
  1211. tclass);
  1212. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
  1213. }
  1214. static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
  1215. {
  1216. int err, i;
  1217. /* Setup the elements hierarcy, so that each TC is linked to
  1218. * one subgroup, which are all member in the same group.
  1219. */
  1220. err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
  1221. MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0);
  1222. if (err)
  1223. return err;
  1224. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  1225. err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
  1226. MLXSW_REG_QEEC_HR_SUBGROUP, i,
  1227. 0, false, 0);
  1228. if (err)
  1229. return err;
  1230. }
  1231. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  1232. err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
  1233. MLXSW_REG_QEEC_HR_TC, i, i,
  1234. false, 0);
  1235. if (err)
  1236. return err;
  1237. err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
  1238. MLXSW_REG_QEEC_HR_TC,
  1239. i + 8, i,
  1240. true, 100);
  1241. if (err)
  1242. return err;
  1243. }
  1244. /* Make sure the max shaper is disabled in all hierarchies that support
  1245. * it. Note that this disables ptps (PTP shaper), but that is intended
  1246. * for the initial configuration.
  1247. */
  1248. err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
  1249. MLXSW_REG_QEEC_HR_PORT, 0, 0,
  1250. MLXSW_REG_QEEC_MAS_DIS, 0);
  1251. if (err)
  1252. return err;
  1253. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  1254. err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
  1255. MLXSW_REG_QEEC_HR_SUBGROUP,
  1256. i, 0,
  1257. MLXSW_REG_QEEC_MAS_DIS, 0);
  1258. if (err)
  1259. return err;
  1260. }
  1261. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  1262. err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
  1263. MLXSW_REG_QEEC_HR_TC,
  1264. i, i,
  1265. MLXSW_REG_QEEC_MAS_DIS, 0);
  1266. if (err)
  1267. return err;
  1268. err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
  1269. MLXSW_REG_QEEC_HR_TC,
  1270. i + 8, i,
  1271. MLXSW_REG_QEEC_MAS_DIS, 0);
  1272. if (err)
  1273. return err;
  1274. }
  1275. /* Configure the min shaper for multicast TCs. */
  1276. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  1277. err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
  1278. MLXSW_REG_QEEC_HR_TC,
  1279. i + 8, i,
  1280. MLXSW_REG_QEEC_MIS_MIN);
  1281. if (err)
  1282. return err;
  1283. }
  1284. /* Map all priorities to traffic class 0. */
  1285. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
  1286. err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
  1287. if (err)
  1288. return err;
  1289. }
  1290. return 0;
  1291. }
  1292. static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
  1293. bool enable)
  1294. {
  1295. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1296. char qtctm_pl[MLXSW_REG_QTCTM_LEN];
  1297. mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
  1298. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
  1299. }
  1300. static int mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port *mlxsw_sp_port)
  1301. {
  1302. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1303. u8 slot_index = mlxsw_sp_port->mapping.slot_index;
  1304. u8 module = mlxsw_sp_port->mapping.module;
  1305. u64 overheat_counter;
  1306. int err;
  1307. err = mlxsw_env_module_overheat_counter_get(mlxsw_sp->core, slot_index,
  1308. module, &overheat_counter);
  1309. if (err)
  1310. return err;
  1311. mlxsw_sp_port->module_overheat_initial_val = overheat_counter;
  1312. return 0;
  1313. }
  1314. int
  1315. mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port *mlxsw_sp_port,
  1316. bool is_8021ad_tagged,
  1317. bool is_8021q_tagged)
  1318. {
  1319. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  1320. char spvc_pl[MLXSW_REG_SPVC_LEN];
  1321. mlxsw_reg_spvc_pack(spvc_pl, mlxsw_sp_port->local_port,
  1322. is_8021ad_tagged, is_8021q_tagged);
  1323. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvc), spvc_pl);
  1324. }
  1325. static int mlxsw_sp_port_label_info_get(struct mlxsw_sp *mlxsw_sp,
  1326. u16 local_port, u8 *port_number,
  1327. u8 *split_port_subnumber,
  1328. u8 *slot_index)
  1329. {
  1330. char pllp_pl[MLXSW_REG_PLLP_LEN];
  1331. int err;
  1332. mlxsw_reg_pllp_pack(pllp_pl, local_port);
  1333. err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl);
  1334. if (err)
  1335. return err;
  1336. mlxsw_reg_pllp_unpack(pllp_pl, port_number,
  1337. split_port_subnumber, slot_index);
  1338. return 0;
  1339. }
  1340. static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u16 local_port,
  1341. bool split,
  1342. struct mlxsw_sp_port_mapping *port_mapping)
  1343. {
  1344. struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
  1345. struct mlxsw_sp_port *mlxsw_sp_port;
  1346. u32 lanes = port_mapping->width;
  1347. u8 split_port_subnumber;
  1348. struct net_device *dev;
  1349. u8 port_number;
  1350. u8 slot_index;
  1351. bool splittable;
  1352. int err;
  1353. err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, port_mapping);
  1354. if (err) {
  1355. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
  1356. local_port);
  1357. return err;
  1358. }
  1359. err = mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 0);
  1360. if (err) {
  1361. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
  1362. local_port);
  1363. goto err_port_swid_set;
  1364. }
  1365. err = mlxsw_sp_port_label_info_get(mlxsw_sp, local_port, &port_number,
  1366. &split_port_subnumber, &slot_index);
  1367. if (err) {
  1368. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get port label information\n",
  1369. local_port);
  1370. goto err_port_label_info_get;
  1371. }
  1372. splittable = lanes > 1 && !split;
  1373. err = mlxsw_core_port_init(mlxsw_sp->core, local_port, slot_index,
  1374. port_number, split, split_port_subnumber,
  1375. splittable, lanes, mlxsw_sp->base_mac,
  1376. sizeof(mlxsw_sp->base_mac));
  1377. if (err) {
  1378. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
  1379. local_port);
  1380. goto err_core_port_init;
  1381. }
  1382. dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
  1383. if (!dev) {
  1384. err = -ENOMEM;
  1385. goto err_alloc_etherdev;
  1386. }
  1387. SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
  1388. dev_net_set(dev, mlxsw_sp_net(mlxsw_sp));
  1389. mlxsw_sp_port = netdev_priv(dev);
  1390. mlxsw_core_port_netdev_link(mlxsw_sp->core, local_port,
  1391. mlxsw_sp_port, dev);
  1392. mlxsw_sp_port->dev = dev;
  1393. mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
  1394. mlxsw_sp_port->local_port = local_port;
  1395. mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
  1396. mlxsw_sp_port->split = split;
  1397. mlxsw_sp_port->mapping = *port_mapping;
  1398. mlxsw_sp_port->link.autoneg = 1;
  1399. INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
  1400. mlxsw_sp_port->pcpu_stats =
  1401. netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
  1402. if (!mlxsw_sp_port->pcpu_stats) {
  1403. err = -ENOMEM;
  1404. goto err_alloc_stats;
  1405. }
  1406. INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
  1407. &update_stats_cache);
  1408. dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
  1409. dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
  1410. err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
  1411. if (err) {
  1412. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
  1413. mlxsw_sp_port->local_port);
  1414. goto err_dev_addr_init;
  1415. }
  1416. netif_carrier_off(dev);
  1417. dev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_FILTER |
  1418. NETIF_F_HW_TC;
  1419. dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK;
  1420. dev->lltx = true;
  1421. dev->netns_local = true;
  1422. dev->min_mtu = ETH_MIN_MTU;
  1423. dev->max_mtu = MLXSW_PORT_MAX_MTU - MLXSW_PORT_ETH_FRAME_HDR;
  1424. /* Each packet needs to have a Tx header (metadata) on top all other
  1425. * headers.
  1426. */
  1427. dev->needed_headroom = MLXSW_TXHDR_LEN;
  1428. err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
  1429. if (err) {
  1430. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
  1431. mlxsw_sp_port->local_port);
  1432. goto err_port_system_port_mapping_set;
  1433. }
  1434. err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port);
  1435. if (err) {
  1436. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
  1437. mlxsw_sp_port->local_port);
  1438. goto err_port_speed_by_width_set;
  1439. }
  1440. err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port,
  1441. &mlxsw_sp_port->max_speed);
  1442. if (err) {
  1443. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n",
  1444. mlxsw_sp_port->local_port);
  1445. goto err_max_speed_get;
  1446. }
  1447. err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
  1448. if (err) {
  1449. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
  1450. mlxsw_sp_port->local_port);
  1451. goto err_port_mtu_set;
  1452. }
  1453. err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
  1454. if (err)
  1455. goto err_port_admin_status_set;
  1456. err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
  1457. if (err) {
  1458. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
  1459. mlxsw_sp_port->local_port);
  1460. goto err_port_buffers_init;
  1461. }
  1462. err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
  1463. if (err) {
  1464. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
  1465. mlxsw_sp_port->local_port);
  1466. goto err_port_ets_init;
  1467. }
  1468. err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
  1469. if (err) {
  1470. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
  1471. mlxsw_sp_port->local_port);
  1472. goto err_port_tc_mc_mode;
  1473. }
  1474. /* ETS and buffers must be initialized before DCB. */
  1475. err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
  1476. if (err) {
  1477. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
  1478. mlxsw_sp_port->local_port);
  1479. goto err_port_dcb_init;
  1480. }
  1481. err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
  1482. if (err) {
  1483. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
  1484. mlxsw_sp_port->local_port);
  1485. goto err_port_fids_init;
  1486. }
  1487. err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
  1488. if (err) {
  1489. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
  1490. mlxsw_sp_port->local_port);
  1491. goto err_port_qdiscs_init;
  1492. }
  1493. err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false,
  1494. false);
  1495. if (err) {
  1496. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
  1497. mlxsw_sp_port->local_port);
  1498. goto err_port_vlan_clear;
  1499. }
  1500. err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
  1501. if (err) {
  1502. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
  1503. mlxsw_sp_port->local_port);
  1504. goto err_port_nve_init;
  1505. }
  1506. err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID,
  1507. ETH_P_8021Q);
  1508. if (err) {
  1509. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
  1510. mlxsw_sp_port->local_port);
  1511. goto err_port_pvid_set;
  1512. }
  1513. mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
  1514. MLXSW_SP_DEFAULT_VID);
  1515. if (IS_ERR(mlxsw_sp_port_vlan)) {
  1516. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
  1517. mlxsw_sp_port->local_port);
  1518. err = PTR_ERR(mlxsw_sp_port_vlan);
  1519. goto err_port_vlan_create;
  1520. }
  1521. mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
  1522. /* Set SPVC.et0=true and SPVC.et1=false to make the local port to treat
  1523. * only packets with 802.1q header as tagged packets.
  1524. */
  1525. err = mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, false, true);
  1526. if (err) {
  1527. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set default VLAN classification\n",
  1528. local_port);
  1529. goto err_port_vlan_classification_set;
  1530. }
  1531. INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw,
  1532. mlxsw_sp->ptp_ops->shaper_work);
  1533. mlxsw_sp->ports[local_port] = mlxsw_sp_port;
  1534. err = mlxsw_sp_port_overheat_init_val_set(mlxsw_sp_port);
  1535. if (err) {
  1536. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set overheat initial value\n",
  1537. mlxsw_sp_port->local_port);
  1538. goto err_port_overheat_init_val_set;
  1539. }
  1540. err = register_netdev(dev);
  1541. if (err) {
  1542. dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
  1543. mlxsw_sp_port->local_port);
  1544. goto err_register_netdev;
  1545. }
  1546. mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
  1547. return 0;
  1548. err_register_netdev:
  1549. err_port_overheat_init_val_set:
  1550. mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true);
  1551. err_port_vlan_classification_set:
  1552. mlxsw_sp->ports[local_port] = NULL;
  1553. mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
  1554. err_port_vlan_create:
  1555. err_port_pvid_set:
  1556. mlxsw_sp_port_nve_fini(mlxsw_sp_port);
  1557. err_port_nve_init:
  1558. err_port_vlan_clear:
  1559. mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
  1560. err_port_qdiscs_init:
  1561. mlxsw_sp_port_fids_fini(mlxsw_sp_port);
  1562. err_port_fids_init:
  1563. mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
  1564. err_port_dcb_init:
  1565. mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
  1566. err_port_tc_mc_mode:
  1567. err_port_ets_init:
  1568. mlxsw_sp_port_buffers_fini(mlxsw_sp_port);
  1569. err_port_buffers_init:
  1570. err_port_admin_status_set:
  1571. err_port_mtu_set:
  1572. err_max_speed_get:
  1573. err_port_speed_by_width_set:
  1574. err_port_system_port_mapping_set:
  1575. err_dev_addr_init:
  1576. free_percpu(mlxsw_sp_port->pcpu_stats);
  1577. err_alloc_stats:
  1578. free_netdev(dev);
  1579. err_alloc_etherdev:
  1580. mlxsw_core_port_fini(mlxsw_sp->core, local_port);
  1581. err_core_port_init:
  1582. err_port_label_info_get:
  1583. mlxsw_sp_port_swid_set(mlxsw_sp, local_port,
  1584. MLXSW_PORT_SWID_DISABLED_PORT);
  1585. err_port_swid_set:
  1586. mlxsw_sp_port_module_unmap(mlxsw_sp, local_port,
  1587. port_mapping->slot_index,
  1588. port_mapping->module);
  1589. return err;
  1590. }
  1591. static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u16 local_port)
  1592. {
  1593. struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
  1594. u8 slot_index = mlxsw_sp_port->mapping.slot_index;
  1595. u8 module = mlxsw_sp_port->mapping.module;
  1596. cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
  1597. cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw);
  1598. unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
  1599. mlxsw_sp_port_ptp_clear(mlxsw_sp_port);
  1600. mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true);
  1601. mlxsw_sp->ports[local_port] = NULL;
  1602. mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
  1603. mlxsw_sp_port_nve_fini(mlxsw_sp_port);
  1604. mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
  1605. mlxsw_sp_port_fids_fini(mlxsw_sp_port);
  1606. mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
  1607. mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
  1608. mlxsw_sp_port_buffers_fini(mlxsw_sp_port);
  1609. free_percpu(mlxsw_sp_port->pcpu_stats);
  1610. WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
  1611. free_netdev(mlxsw_sp_port->dev);
  1612. mlxsw_core_port_fini(mlxsw_sp->core, local_port);
  1613. mlxsw_sp_port_swid_set(mlxsw_sp, local_port,
  1614. MLXSW_PORT_SWID_DISABLED_PORT);
  1615. mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, slot_index, module);
  1616. }
  1617. static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
  1618. {
  1619. struct mlxsw_sp_port *mlxsw_sp_port;
  1620. int err;
  1621. mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL);
  1622. if (!mlxsw_sp_port)
  1623. return -ENOMEM;
  1624. mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
  1625. mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT;
  1626. err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
  1627. mlxsw_sp_port,
  1628. mlxsw_sp->base_mac,
  1629. sizeof(mlxsw_sp->base_mac));
  1630. if (err) {
  1631. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
  1632. goto err_core_cpu_port_init;
  1633. }
  1634. mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
  1635. return 0;
  1636. err_core_cpu_port_init:
  1637. kfree(mlxsw_sp_port);
  1638. return err;
  1639. }
  1640. static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
  1641. {
  1642. struct mlxsw_sp_port *mlxsw_sp_port =
  1643. mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
  1644. mlxsw_core_cpu_port_fini(mlxsw_sp->core);
  1645. mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
  1646. kfree(mlxsw_sp_port);
  1647. }
  1648. static bool mlxsw_sp_local_port_valid(u16 local_port)
  1649. {
  1650. return local_port != MLXSW_PORT_CPU_PORT;
  1651. }
  1652. static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u16 local_port)
  1653. {
  1654. if (!mlxsw_sp_local_port_valid(local_port))
  1655. return false;
  1656. return mlxsw_sp->ports[local_port] != NULL;
  1657. }
  1658. static int mlxsw_sp_port_mapping_event_set(struct mlxsw_sp *mlxsw_sp,
  1659. u16 local_port, bool enable)
  1660. {
  1661. char pmecr_pl[MLXSW_REG_PMECR_LEN];
  1662. mlxsw_reg_pmecr_pack(pmecr_pl, local_port,
  1663. enable ? MLXSW_REG_PMECR_E_GENERATE_EVENT :
  1664. MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT);
  1665. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmecr), pmecr_pl);
  1666. }
  1667. struct mlxsw_sp_port_mapping_event {
  1668. struct list_head list;
  1669. char pmlp_pl[MLXSW_REG_PMLP_LEN];
  1670. };
  1671. static void mlxsw_sp_port_mapping_events_work(struct work_struct *work)
  1672. {
  1673. struct mlxsw_sp_port_mapping_event *event, *next_event;
  1674. struct mlxsw_sp_port_mapping_events *events;
  1675. struct mlxsw_sp_port_mapping port_mapping;
  1676. struct mlxsw_sp *mlxsw_sp;
  1677. struct devlink *devlink;
  1678. LIST_HEAD(event_queue);
  1679. u16 local_port;
  1680. int err;
  1681. events = container_of(work, struct mlxsw_sp_port_mapping_events, work);
  1682. mlxsw_sp = container_of(events, struct mlxsw_sp, port_mapping_events);
  1683. devlink = priv_to_devlink(mlxsw_sp->core);
  1684. spin_lock_bh(&events->queue_lock);
  1685. list_splice_init(&events->queue, &event_queue);
  1686. spin_unlock_bh(&events->queue_lock);
  1687. list_for_each_entry_safe(event, next_event, &event_queue, list) {
  1688. local_port = mlxsw_reg_pmlp_local_port_get(event->pmlp_pl);
  1689. err = mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port,
  1690. event->pmlp_pl, &port_mapping);
  1691. if (err)
  1692. goto out;
  1693. if (WARN_ON_ONCE(!port_mapping.width))
  1694. goto out;
  1695. devl_lock(devlink);
  1696. if (!mlxsw_sp_port_created(mlxsw_sp, local_port))
  1697. mlxsw_sp_port_create(mlxsw_sp, local_port,
  1698. false, &port_mapping);
  1699. else
  1700. WARN_ON_ONCE(1);
  1701. devl_unlock(devlink);
  1702. mlxsw_sp->port_mapping[local_port] = port_mapping;
  1703. out:
  1704. kfree(event);
  1705. }
  1706. }
  1707. static void
  1708. mlxsw_sp_port_mapping_listener_func(const struct mlxsw_reg_info *reg,
  1709. char *pmlp_pl, void *priv)
  1710. {
  1711. struct mlxsw_sp_port_mapping_events *events;
  1712. struct mlxsw_sp_port_mapping_event *event;
  1713. struct mlxsw_sp *mlxsw_sp = priv;
  1714. u16 local_port;
  1715. local_port = mlxsw_reg_pmlp_local_port_get(pmlp_pl);
  1716. if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port)))
  1717. return;
  1718. events = &mlxsw_sp->port_mapping_events;
  1719. event = kmalloc(sizeof(*event), GFP_ATOMIC);
  1720. if (!event)
  1721. return;
  1722. memcpy(event->pmlp_pl, pmlp_pl, sizeof(event->pmlp_pl));
  1723. spin_lock(&events->queue_lock);
  1724. list_add_tail(&event->list, &events->queue);
  1725. spin_unlock(&events->queue_lock);
  1726. mlxsw_core_schedule_work(&events->work);
  1727. }
  1728. static void
  1729. __mlxsw_sp_port_mapping_events_cancel(struct mlxsw_sp *mlxsw_sp)
  1730. {
  1731. struct mlxsw_sp_port_mapping_event *event, *next_event;
  1732. struct mlxsw_sp_port_mapping_events *events;
  1733. events = &mlxsw_sp->port_mapping_events;
  1734. /* Caller needs to make sure that no new event is going to appear. */
  1735. cancel_work_sync(&events->work);
  1736. list_for_each_entry_safe(event, next_event, &events->queue, list) {
  1737. list_del(&event->list);
  1738. kfree(event);
  1739. }
  1740. }
  1741. static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
  1742. {
  1743. unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
  1744. int i;
  1745. for (i = 1; i < max_ports; i++)
  1746. mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false);
  1747. /* Make sure all scheduled events are processed */
  1748. __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp);
  1749. for (i = 1; i < max_ports; i++)
  1750. if (mlxsw_sp_port_created(mlxsw_sp, i))
  1751. mlxsw_sp_port_remove(mlxsw_sp, i);
  1752. mlxsw_sp_cpu_port_remove(mlxsw_sp);
  1753. kfree(mlxsw_sp->ports);
  1754. mlxsw_sp->ports = NULL;
  1755. }
  1756. static void
  1757. mlxsw_sp_ports_remove_selected(struct mlxsw_core *mlxsw_core,
  1758. bool (*selector)(void *priv, u16 local_port),
  1759. void *priv)
  1760. {
  1761. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  1762. unsigned int max_ports = mlxsw_core_max_ports(mlxsw_core);
  1763. int i;
  1764. for (i = 1; i < max_ports; i++)
  1765. if (mlxsw_sp_port_created(mlxsw_sp, i) && selector(priv, i))
  1766. mlxsw_sp_port_remove(mlxsw_sp, i);
  1767. }
  1768. static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
  1769. {
  1770. unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
  1771. struct mlxsw_sp_port_mapping_events *events;
  1772. struct mlxsw_sp_port_mapping *port_mapping;
  1773. size_t alloc_size;
  1774. int i;
  1775. int err;
  1776. alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
  1777. mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
  1778. if (!mlxsw_sp->ports)
  1779. return -ENOMEM;
  1780. events = &mlxsw_sp->port_mapping_events;
  1781. INIT_LIST_HEAD(&events->queue);
  1782. spin_lock_init(&events->queue_lock);
  1783. INIT_WORK(&events->work, mlxsw_sp_port_mapping_events_work);
  1784. for (i = 1; i < max_ports; i++) {
  1785. err = mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, true);
  1786. if (err)
  1787. goto err_event_enable;
  1788. }
  1789. err = mlxsw_sp_cpu_port_create(mlxsw_sp);
  1790. if (err)
  1791. goto err_cpu_port_create;
  1792. for (i = 1; i < max_ports; i++) {
  1793. port_mapping = &mlxsw_sp->port_mapping[i];
  1794. if (!port_mapping->width)
  1795. continue;
  1796. err = mlxsw_sp_port_create(mlxsw_sp, i, false, port_mapping);
  1797. if (err)
  1798. goto err_port_create;
  1799. }
  1800. return 0;
  1801. err_port_create:
  1802. for (i--; i >= 1; i--)
  1803. if (mlxsw_sp_port_created(mlxsw_sp, i))
  1804. mlxsw_sp_port_remove(mlxsw_sp, i);
  1805. i = max_ports;
  1806. mlxsw_sp_cpu_port_remove(mlxsw_sp);
  1807. err_cpu_port_create:
  1808. err_event_enable:
  1809. for (i--; i >= 1; i--)
  1810. mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false);
  1811. /* Make sure all scheduled events are processed */
  1812. __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp);
  1813. kfree(mlxsw_sp->ports);
  1814. mlxsw_sp->ports = NULL;
  1815. return err;
  1816. }
  1817. static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp)
  1818. {
  1819. unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
  1820. struct mlxsw_sp_port_mapping *port_mapping;
  1821. int i;
  1822. int err;
  1823. mlxsw_sp->port_mapping = kcalloc(max_ports,
  1824. sizeof(struct mlxsw_sp_port_mapping),
  1825. GFP_KERNEL);
  1826. if (!mlxsw_sp->port_mapping)
  1827. return -ENOMEM;
  1828. for (i = 1; i < max_ports; i++) {
  1829. port_mapping = &mlxsw_sp->port_mapping[i];
  1830. err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, port_mapping);
  1831. if (err)
  1832. goto err_port_module_info_get;
  1833. }
  1834. return 0;
  1835. err_port_module_info_get:
  1836. kfree(mlxsw_sp->port_mapping);
  1837. return err;
  1838. }
  1839. static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp)
  1840. {
  1841. kfree(mlxsw_sp->port_mapping);
  1842. }
  1843. static int
  1844. mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp,
  1845. struct mlxsw_sp_port_mapping *port_mapping,
  1846. unsigned int count, const char *pmtdb_pl)
  1847. {
  1848. struct mlxsw_sp_port_mapping split_port_mapping;
  1849. int err, i;
  1850. split_port_mapping = *port_mapping;
  1851. split_port_mapping.width /= count;
  1852. for (i = 0; i < count; i++) {
  1853. u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
  1854. if (!mlxsw_sp_local_port_valid(s_local_port))
  1855. continue;
  1856. err = mlxsw_sp_port_create(mlxsw_sp, s_local_port,
  1857. true, &split_port_mapping);
  1858. if (err)
  1859. goto err_port_create;
  1860. split_port_mapping.lane += split_port_mapping.width;
  1861. }
  1862. return 0;
  1863. err_port_create:
  1864. for (i--; i >= 0; i--) {
  1865. u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
  1866. if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
  1867. mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
  1868. }
  1869. return err;
  1870. }
  1871. static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
  1872. unsigned int count,
  1873. const char *pmtdb_pl)
  1874. {
  1875. struct mlxsw_sp_port_mapping *port_mapping;
  1876. int i;
  1877. /* Go over original unsplit ports in the gap and recreate them. */
  1878. for (i = 0; i < count; i++) {
  1879. u16 local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
  1880. port_mapping = &mlxsw_sp->port_mapping[local_port];
  1881. if (!port_mapping->width || !mlxsw_sp_local_port_valid(local_port))
  1882. continue;
  1883. mlxsw_sp_port_create(mlxsw_sp, local_port,
  1884. false, port_mapping);
  1885. }
  1886. }
  1887. static struct mlxsw_sp_port *
  1888. mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u16 local_port)
  1889. {
  1890. if (mlxsw_sp->ports && mlxsw_sp->ports[local_port])
  1891. return mlxsw_sp->ports[local_port];
  1892. return NULL;
  1893. }
  1894. static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u16 local_port,
  1895. unsigned int count,
  1896. struct netlink_ext_ack *extack)
  1897. {
  1898. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  1899. struct mlxsw_sp_port_mapping port_mapping;
  1900. struct mlxsw_sp_port *mlxsw_sp_port;
  1901. enum mlxsw_reg_pmtdb_status status;
  1902. char pmtdb_pl[MLXSW_REG_PMTDB_LEN];
  1903. int i;
  1904. int err;
  1905. mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
  1906. if (!mlxsw_sp_port) {
  1907. dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
  1908. local_port);
  1909. NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
  1910. return -EINVAL;
  1911. }
  1912. if (mlxsw_sp_port->split) {
  1913. NL_SET_ERR_MSG_MOD(extack, "Port is already split");
  1914. return -EINVAL;
  1915. }
  1916. mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index,
  1917. mlxsw_sp_port->mapping.module,
  1918. mlxsw_sp_port->mapping.module_width / count,
  1919. count);
  1920. err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl);
  1921. if (err) {
  1922. NL_SET_ERR_MSG_MOD(extack, "Failed to query split info");
  1923. return err;
  1924. }
  1925. status = mlxsw_reg_pmtdb_status_get(pmtdb_pl);
  1926. if (status != MLXSW_REG_PMTDB_STATUS_SUCCESS) {
  1927. NL_SET_ERR_MSG_MOD(extack, "Unsupported split configuration");
  1928. return -EINVAL;
  1929. }
  1930. port_mapping = mlxsw_sp_port->mapping;
  1931. for (i = 0; i < count; i++) {
  1932. u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
  1933. if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
  1934. mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
  1935. }
  1936. err = mlxsw_sp_port_split_create(mlxsw_sp, &port_mapping,
  1937. count, pmtdb_pl);
  1938. if (err) {
  1939. dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
  1940. goto err_port_split_create;
  1941. }
  1942. return 0;
  1943. err_port_split_create:
  1944. mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl);
  1945. return err;
  1946. }
  1947. static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u16 local_port,
  1948. struct netlink_ext_ack *extack)
  1949. {
  1950. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  1951. struct mlxsw_sp_port *mlxsw_sp_port;
  1952. char pmtdb_pl[MLXSW_REG_PMTDB_LEN];
  1953. unsigned int count;
  1954. int i;
  1955. int err;
  1956. mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
  1957. if (!mlxsw_sp_port) {
  1958. dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
  1959. local_port);
  1960. NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
  1961. return -EINVAL;
  1962. }
  1963. if (!mlxsw_sp_port->split) {
  1964. NL_SET_ERR_MSG_MOD(extack, "Port was not split");
  1965. return -EINVAL;
  1966. }
  1967. count = mlxsw_sp_port->mapping.module_width /
  1968. mlxsw_sp_port->mapping.width;
  1969. mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index,
  1970. mlxsw_sp_port->mapping.module,
  1971. mlxsw_sp_port->mapping.module_width / count,
  1972. count);
  1973. err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl);
  1974. if (err) {
  1975. NL_SET_ERR_MSG_MOD(extack, "Failed to query split info");
  1976. return err;
  1977. }
  1978. for (i = 0; i < count; i++) {
  1979. u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
  1980. if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
  1981. mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
  1982. }
  1983. mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl);
  1984. return 0;
  1985. }
  1986. static void
  1987. mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port)
  1988. {
  1989. int i;
  1990. for (i = 0; i < TC_MAX_QUEUE; i++)
  1991. mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0;
  1992. }
  1993. static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
  1994. char *pude_pl, void *priv)
  1995. {
  1996. struct mlxsw_sp *mlxsw_sp = priv;
  1997. struct mlxsw_sp_port *mlxsw_sp_port;
  1998. enum mlxsw_reg_pude_oper_status status;
  1999. u16 local_port;
  2000. local_port = mlxsw_reg_pude_local_port_get(pude_pl);
  2001. if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port)))
  2002. return;
  2003. mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2004. if (!mlxsw_sp_port)
  2005. return;
  2006. status = mlxsw_reg_pude_oper_status_get(pude_pl);
  2007. if (status == MLXSW_PORT_OPER_STATUS_UP) {
  2008. netdev_info(mlxsw_sp_port->dev, "link up\n");
  2009. netif_carrier_on(mlxsw_sp_port->dev);
  2010. mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0);
  2011. } else {
  2012. netdev_info(mlxsw_sp_port->dev, "link down\n");
  2013. netif_carrier_off(mlxsw_sp_port->dev);
  2014. mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port);
  2015. }
  2016. }
  2017. static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
  2018. char *mtpptr_pl, bool ingress)
  2019. {
  2020. u16 local_port;
  2021. u8 num_rec;
  2022. int i;
  2023. local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl);
  2024. num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl);
  2025. for (i = 0; i < num_rec; i++) {
  2026. u8 domain_number;
  2027. u8 message_type;
  2028. u16 sequence_id;
  2029. u64 timestamp;
  2030. mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type,
  2031. &domain_number, &sequence_id,
  2032. &timestamp);
  2033. mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
  2034. message_type, domain_number,
  2035. sequence_id, timestamp);
  2036. }
  2037. }
  2038. static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg,
  2039. char *mtpptr_pl, void *priv)
  2040. {
  2041. struct mlxsw_sp *mlxsw_sp = priv;
  2042. mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
  2043. }
  2044. static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg,
  2045. char *mtpptr_pl, void *priv)
  2046. {
  2047. struct mlxsw_sp *mlxsw_sp = priv;
  2048. mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
  2049. }
  2050. void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
  2051. u16 local_port, void *priv)
  2052. {
  2053. struct mlxsw_sp *mlxsw_sp = priv;
  2054. struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
  2055. struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
  2056. if (unlikely(!mlxsw_sp_port)) {
  2057. dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
  2058. local_port);
  2059. return;
  2060. }
  2061. skb->dev = mlxsw_sp_port->dev;
  2062. pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
  2063. u64_stats_update_begin(&pcpu_stats->syncp);
  2064. pcpu_stats->rx_packets++;
  2065. pcpu_stats->rx_bytes += skb->len;
  2066. u64_stats_update_end(&pcpu_stats->syncp);
  2067. skb->protocol = eth_type_trans(skb, skb->dev);
  2068. netif_receive_skb(skb);
  2069. }
  2070. static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u16 local_port,
  2071. void *priv)
  2072. {
  2073. skb->offload_fwd_mark = 1;
  2074. return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
  2075. }
  2076. static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
  2077. u16 local_port, void *priv)
  2078. {
  2079. skb->offload_l3_fwd_mark = 1;
  2080. skb->offload_fwd_mark = 1;
  2081. return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
  2082. }
  2083. void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
  2084. u16 local_port)
  2085. {
  2086. mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
  2087. }
  2088. #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
  2089. MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
  2090. _is_ctrl, SP_##_trap_group, DISCARD)
  2091. #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
  2092. MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
  2093. _is_ctrl, SP_##_trap_group, DISCARD)
  2094. #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
  2095. MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \
  2096. _is_ctrl, SP_##_trap_group, DISCARD)
  2097. #define MLXSW_SP_EVENTL(_func, _trap_id) \
  2098. MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
  2099. static const struct mlxsw_listener mlxsw_sp_listener[] = {
  2100. /* Events */
  2101. MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
  2102. /* L2 traps */
  2103. MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false),
  2104. /* L3 traps */
  2105. MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
  2106. false),
  2107. MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
  2108. MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
  2109. false),
  2110. MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD,
  2111. ROUTER_EXP, false),
  2112. MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD,
  2113. ROUTER_EXP, false),
  2114. MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD,
  2115. ROUTER_EXP, false),
  2116. MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD,
  2117. ROUTER_EXP, false),
  2118. MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_LINK_LOCAL, FORWARD,
  2119. ROUTER_EXP, false),
  2120. /* Multicast Router Traps */
  2121. MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
  2122. MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
  2123. /* NVE traps */
  2124. MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, NEIGH_DISCOVERY, false),
  2125. };
  2126. static const struct mlxsw_listener mlxsw_sp1_listener[] = {
  2127. /* Events */
  2128. MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0),
  2129. MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0),
  2130. };
  2131. static const struct mlxsw_listener mlxsw_sp2_listener[] = {
  2132. /* Events */
  2133. MLXSW_SP_EVENTL(mlxsw_sp_port_mapping_listener_func, PMLPE),
  2134. };
  2135. static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
  2136. {
  2137. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  2138. char qpcr_pl[MLXSW_REG_QPCR_LEN];
  2139. enum mlxsw_reg_qpcr_ir_units ir_units;
  2140. int max_cpu_policers;
  2141. bool is_bytes;
  2142. u8 burst_size;
  2143. u32 rate;
  2144. int i, err;
  2145. if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
  2146. return -EIO;
  2147. max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
  2148. ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
  2149. for (i = 0; i < max_cpu_policers; i++) {
  2150. is_bytes = false;
  2151. switch (i) {
  2152. case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
  2153. case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
  2154. case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:
  2155. rate = 1024;
  2156. burst_size = 7;
  2157. break;
  2158. default:
  2159. continue;
  2160. }
  2161. __set_bit(i, mlxsw_sp->trap->policers_usage);
  2162. mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
  2163. burst_size);
  2164. err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
  2165. if (err)
  2166. return err;
  2167. }
  2168. return 0;
  2169. }
  2170. static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
  2171. {
  2172. char htgt_pl[MLXSW_REG_HTGT_LEN];
  2173. enum mlxsw_reg_htgt_trap_group i;
  2174. int max_cpu_policers;
  2175. int max_trap_groups;
  2176. u8 priority, tc;
  2177. u16 policer_id;
  2178. int err;
  2179. if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
  2180. return -EIO;
  2181. max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
  2182. max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
  2183. for (i = 0; i < max_trap_groups; i++) {
  2184. policer_id = i;
  2185. switch (i) {
  2186. case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
  2187. case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
  2188. case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:
  2189. priority = 1;
  2190. tc = 1;
  2191. break;
  2192. case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
  2193. priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
  2194. tc = MLXSW_REG_HTGT_DEFAULT_TC;
  2195. policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
  2196. break;
  2197. default:
  2198. continue;
  2199. }
  2200. if (max_cpu_policers <= policer_id &&
  2201. policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
  2202. return -EIO;
  2203. mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
  2204. err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
  2205. if (err)
  2206. return err;
  2207. }
  2208. return 0;
  2209. }
  2210. static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
  2211. {
  2212. struct mlxsw_sp_trap *trap;
  2213. u64 max_policers;
  2214. int err;
  2215. if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS))
  2216. return -EIO;
  2217. max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS);
  2218. trap = kzalloc(struct_size(trap, policers_usage,
  2219. BITS_TO_LONGS(max_policers)), GFP_KERNEL);
  2220. if (!trap)
  2221. return -ENOMEM;
  2222. trap->max_policers = max_policers;
  2223. mlxsw_sp->trap = trap;
  2224. err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
  2225. if (err)
  2226. goto err_cpu_policers_set;
  2227. err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
  2228. if (err)
  2229. goto err_trap_groups_set;
  2230. err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp_listener,
  2231. ARRAY_SIZE(mlxsw_sp_listener),
  2232. mlxsw_sp);
  2233. if (err)
  2234. goto err_traps_register;
  2235. err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp->listeners,
  2236. mlxsw_sp->listeners_count, mlxsw_sp);
  2237. if (err)
  2238. goto err_extra_traps_init;
  2239. return 0;
  2240. err_extra_traps_init:
  2241. mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener,
  2242. ARRAY_SIZE(mlxsw_sp_listener),
  2243. mlxsw_sp);
  2244. err_traps_register:
  2245. err_trap_groups_set:
  2246. err_cpu_policers_set:
  2247. kfree(trap);
  2248. return err;
  2249. }
  2250. static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
  2251. {
  2252. mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp->listeners,
  2253. mlxsw_sp->listeners_count,
  2254. mlxsw_sp);
  2255. mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener,
  2256. ARRAY_SIZE(mlxsw_sp_listener), mlxsw_sp);
  2257. kfree(mlxsw_sp->trap);
  2258. }
  2259. static int mlxsw_sp_lag_pgt_init(struct mlxsw_sp *mlxsw_sp)
  2260. {
  2261. char sgcr_pl[MLXSW_REG_SGCR_LEN];
  2262. int err;
  2263. if (mlxsw_core_lag_mode(mlxsw_sp->core) !=
  2264. MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW)
  2265. return 0;
  2266. /* In DDD mode, which we by default use, each LAG entry is 8 PGT
  2267. * entries. The LAG table address needs to be 8-aligned, but that ought
  2268. * to be the case, since the LAG table is allocated first.
  2269. */
  2270. err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, &mlxsw_sp->lag_pgt_base,
  2271. mlxsw_sp->max_lag * 8);
  2272. if (err)
  2273. return err;
  2274. if (WARN_ON_ONCE(mlxsw_sp->lag_pgt_base % 8)) {
  2275. err = -EINVAL;
  2276. goto err_mid_alloc_range;
  2277. }
  2278. mlxsw_reg_sgcr_pack(sgcr_pl, mlxsw_sp->lag_pgt_base);
  2279. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sgcr), sgcr_pl);
  2280. if (err)
  2281. goto err_mid_alloc_range;
  2282. return 0;
  2283. err_mid_alloc_range:
  2284. mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base,
  2285. mlxsw_sp->max_lag * 8);
  2286. return err;
  2287. }
  2288. static void mlxsw_sp_lag_pgt_fini(struct mlxsw_sp *mlxsw_sp)
  2289. {
  2290. if (mlxsw_core_lag_mode(mlxsw_sp->core) !=
  2291. MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW)
  2292. return;
  2293. mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base,
  2294. mlxsw_sp->max_lag * 8);
  2295. }
  2296. #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe
  2297. struct mlxsw_sp_lag {
  2298. struct net_device *dev;
  2299. refcount_t ref_count;
  2300. u16 lag_id;
  2301. };
  2302. static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
  2303. {
  2304. char slcr_pl[MLXSW_REG_SLCR_LEN];
  2305. u32 seed;
  2306. int err;
  2307. seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
  2308. MLXSW_SP_LAG_SEED_INIT);
  2309. mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
  2310. MLXSW_REG_SLCR_LAG_HASH_DMAC |
  2311. MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
  2312. MLXSW_REG_SLCR_LAG_HASH_VLANID |
  2313. MLXSW_REG_SLCR_LAG_HASH_SIP |
  2314. MLXSW_REG_SLCR_LAG_HASH_DIP |
  2315. MLXSW_REG_SLCR_LAG_HASH_SPORT |
  2316. MLXSW_REG_SLCR_LAG_HASH_DPORT |
  2317. MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
  2318. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
  2319. if (err)
  2320. return err;
  2321. err = mlxsw_core_max_lag(mlxsw_sp->core, &mlxsw_sp->max_lag);
  2322. if (err)
  2323. return err;
  2324. if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
  2325. return -EIO;
  2326. err = mlxsw_sp_lag_pgt_init(mlxsw_sp);
  2327. if (err)
  2328. return err;
  2329. mlxsw_sp->lags = kcalloc(mlxsw_sp->max_lag, sizeof(struct mlxsw_sp_lag),
  2330. GFP_KERNEL);
  2331. if (!mlxsw_sp->lags) {
  2332. err = -ENOMEM;
  2333. goto err_kcalloc;
  2334. }
  2335. return 0;
  2336. err_kcalloc:
  2337. mlxsw_sp_lag_pgt_fini(mlxsw_sp);
  2338. return err;
  2339. }
  2340. static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
  2341. {
  2342. mlxsw_sp_lag_pgt_fini(mlxsw_sp);
  2343. kfree(mlxsw_sp->lags);
  2344. }
  2345. static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = {
  2346. .clock_init = mlxsw_sp1_ptp_clock_init,
  2347. .clock_fini = mlxsw_sp1_ptp_clock_fini,
  2348. .init = mlxsw_sp1_ptp_init,
  2349. .fini = mlxsw_sp1_ptp_fini,
  2350. .receive = mlxsw_sp1_ptp_receive,
  2351. .transmitted = mlxsw_sp1_ptp_transmitted,
  2352. .hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get,
  2353. .hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set,
  2354. .shaper_work = mlxsw_sp1_ptp_shaper_work,
  2355. #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK)
  2356. .get_ts_info = mlxsw_sp1_ptp_get_ts_info,
  2357. #endif
  2358. .get_stats_count = mlxsw_sp1_get_stats_count,
  2359. .get_stats_strings = mlxsw_sp1_get_stats_strings,
  2360. .get_stats = mlxsw_sp1_get_stats,
  2361. .txhdr_construct = mlxsw_sp_ptp_txhdr_construct,
  2362. };
  2363. static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = {
  2364. .clock_init = mlxsw_sp2_ptp_clock_init,
  2365. .clock_fini = mlxsw_sp2_ptp_clock_fini,
  2366. .init = mlxsw_sp2_ptp_init,
  2367. .fini = mlxsw_sp2_ptp_fini,
  2368. .receive = mlxsw_sp2_ptp_receive,
  2369. .transmitted = mlxsw_sp2_ptp_transmitted,
  2370. .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get,
  2371. .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set,
  2372. .shaper_work = mlxsw_sp2_ptp_shaper_work,
  2373. #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK)
  2374. .get_ts_info = mlxsw_sp2_ptp_get_ts_info,
  2375. #endif
  2376. .get_stats_count = mlxsw_sp2_get_stats_count,
  2377. .get_stats_strings = mlxsw_sp2_get_stats_strings,
  2378. .get_stats = mlxsw_sp2_get_stats,
  2379. .txhdr_construct = mlxsw_sp2_ptp_txhdr_construct,
  2380. };
  2381. static const struct mlxsw_sp_ptp_ops mlxsw_sp4_ptp_ops = {
  2382. .clock_init = mlxsw_sp2_ptp_clock_init,
  2383. .clock_fini = mlxsw_sp2_ptp_clock_fini,
  2384. .init = mlxsw_sp2_ptp_init,
  2385. .fini = mlxsw_sp2_ptp_fini,
  2386. .receive = mlxsw_sp2_ptp_receive,
  2387. .transmitted = mlxsw_sp2_ptp_transmitted,
  2388. .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get,
  2389. .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set,
  2390. .shaper_work = mlxsw_sp2_ptp_shaper_work,
  2391. #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK)
  2392. .get_ts_info = mlxsw_sp2_ptp_get_ts_info,
  2393. #endif
  2394. .get_stats_count = mlxsw_sp2_get_stats_count,
  2395. .get_stats_strings = mlxsw_sp2_get_stats_strings,
  2396. .get_stats = mlxsw_sp2_get_stats,
  2397. .txhdr_construct = mlxsw_sp_ptp_txhdr_construct,
  2398. };
  2399. struct mlxsw_sp_sample_trigger_node {
  2400. struct mlxsw_sp_sample_trigger trigger;
  2401. struct mlxsw_sp_sample_params params;
  2402. struct rhash_head ht_node;
  2403. struct rcu_head rcu;
  2404. refcount_t refcount;
  2405. };
  2406. static const struct rhashtable_params mlxsw_sp_sample_trigger_ht_params = {
  2407. .key_offset = offsetof(struct mlxsw_sp_sample_trigger_node, trigger),
  2408. .head_offset = offsetof(struct mlxsw_sp_sample_trigger_node, ht_node),
  2409. .key_len = sizeof(struct mlxsw_sp_sample_trigger),
  2410. .automatic_shrinking = true,
  2411. };
  2412. static void
  2413. mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger *key,
  2414. const struct mlxsw_sp_sample_trigger *trigger)
  2415. {
  2416. memset(key, 0, sizeof(*key));
  2417. key->type = trigger->type;
  2418. key->local_port = trigger->local_port;
  2419. }
  2420. /* RCU read lock must be held */
  2421. struct mlxsw_sp_sample_params *
  2422. mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp *mlxsw_sp,
  2423. const struct mlxsw_sp_sample_trigger *trigger)
  2424. {
  2425. struct mlxsw_sp_sample_trigger_node *trigger_node;
  2426. struct mlxsw_sp_sample_trigger key;
  2427. mlxsw_sp_sample_trigger_key_init(&key, trigger);
  2428. trigger_node = rhashtable_lookup(&mlxsw_sp->sample_trigger_ht, &key,
  2429. mlxsw_sp_sample_trigger_ht_params);
  2430. if (!trigger_node)
  2431. return NULL;
  2432. return &trigger_node->params;
  2433. }
  2434. static int
  2435. mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp *mlxsw_sp,
  2436. const struct mlxsw_sp_sample_trigger *trigger,
  2437. const struct mlxsw_sp_sample_params *params)
  2438. {
  2439. struct mlxsw_sp_sample_trigger_node *trigger_node;
  2440. int err;
  2441. trigger_node = kzalloc(sizeof(*trigger_node), GFP_KERNEL);
  2442. if (!trigger_node)
  2443. return -ENOMEM;
  2444. trigger_node->trigger = *trigger;
  2445. trigger_node->params = *params;
  2446. refcount_set(&trigger_node->refcount, 1);
  2447. err = rhashtable_insert_fast(&mlxsw_sp->sample_trigger_ht,
  2448. &trigger_node->ht_node,
  2449. mlxsw_sp_sample_trigger_ht_params);
  2450. if (err)
  2451. goto err_rhashtable_insert;
  2452. return 0;
  2453. err_rhashtable_insert:
  2454. kfree(trigger_node);
  2455. return err;
  2456. }
  2457. static void
  2458. mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp *mlxsw_sp,
  2459. struct mlxsw_sp_sample_trigger_node *trigger_node)
  2460. {
  2461. rhashtable_remove_fast(&mlxsw_sp->sample_trigger_ht,
  2462. &trigger_node->ht_node,
  2463. mlxsw_sp_sample_trigger_ht_params);
  2464. kfree_rcu(trigger_node, rcu);
  2465. }
  2466. int
  2467. mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp *mlxsw_sp,
  2468. const struct mlxsw_sp_sample_trigger *trigger,
  2469. const struct mlxsw_sp_sample_params *params,
  2470. struct netlink_ext_ack *extack)
  2471. {
  2472. struct mlxsw_sp_sample_trigger_node *trigger_node;
  2473. struct mlxsw_sp_sample_trigger key;
  2474. ASSERT_RTNL();
  2475. mlxsw_sp_sample_trigger_key_init(&key, trigger);
  2476. trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht,
  2477. &key,
  2478. mlxsw_sp_sample_trigger_ht_params);
  2479. if (!trigger_node)
  2480. return mlxsw_sp_sample_trigger_node_init(mlxsw_sp, &key,
  2481. params);
  2482. if (trigger_node->trigger.local_port) {
  2483. NL_SET_ERR_MSG_MOD(extack, "Sampling already enabled on port");
  2484. return -EINVAL;
  2485. }
  2486. if (trigger_node->params.psample_group != params->psample_group ||
  2487. trigger_node->params.truncate != params->truncate ||
  2488. trigger_node->params.rate != params->rate ||
  2489. trigger_node->params.trunc_size != params->trunc_size) {
  2490. NL_SET_ERR_MSG_MOD(extack, "Sampling parameters do not match for an existing sampling trigger");
  2491. return -EINVAL;
  2492. }
  2493. refcount_inc(&trigger_node->refcount);
  2494. return 0;
  2495. }
  2496. void
  2497. mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp *mlxsw_sp,
  2498. const struct mlxsw_sp_sample_trigger *trigger)
  2499. {
  2500. struct mlxsw_sp_sample_trigger_node *trigger_node;
  2501. struct mlxsw_sp_sample_trigger key;
  2502. ASSERT_RTNL();
  2503. mlxsw_sp_sample_trigger_key_init(&key, trigger);
  2504. trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht,
  2505. &key,
  2506. mlxsw_sp_sample_trigger_ht_params);
  2507. if (!trigger_node)
  2508. return;
  2509. if (!refcount_dec_and_test(&trigger_node->refcount))
  2510. return;
  2511. mlxsw_sp_sample_trigger_node_fini(mlxsw_sp, trigger_node);
  2512. }
  2513. static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
  2514. unsigned long event, void *ptr);
  2515. #define MLXSW_SP_DEFAULT_PARSING_DEPTH 96
  2516. #define MLXSW_SP_INCREASED_PARSING_DEPTH 128
  2517. #define MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT 4789
  2518. static void mlxsw_sp_parsing_init(struct mlxsw_sp *mlxsw_sp)
  2519. {
  2520. refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 0);
  2521. mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH;
  2522. mlxsw_sp->parsing.vxlan_udp_dport = MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT;
  2523. mutex_init(&mlxsw_sp->parsing.lock);
  2524. }
  2525. static void mlxsw_sp_parsing_fini(struct mlxsw_sp *mlxsw_sp)
  2526. {
  2527. mutex_destroy(&mlxsw_sp->parsing.lock);
  2528. WARN_ON_ONCE(refcount_read(&mlxsw_sp->parsing.parsing_depth_ref));
  2529. }
  2530. struct mlxsw_sp_ipv6_addr_node {
  2531. struct in6_addr key;
  2532. struct rhash_head ht_node;
  2533. u32 kvdl_index;
  2534. refcount_t refcount;
  2535. };
  2536. static const struct rhashtable_params mlxsw_sp_ipv6_addr_ht_params = {
  2537. .key_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, key),
  2538. .head_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, ht_node),
  2539. .key_len = sizeof(struct in6_addr),
  2540. .automatic_shrinking = true,
  2541. };
  2542. static int
  2543. mlxsw_sp_ipv6_addr_init(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6,
  2544. u32 *p_kvdl_index)
  2545. {
  2546. struct mlxsw_sp_ipv6_addr_node *node;
  2547. char rips_pl[MLXSW_REG_RIPS_LEN];
  2548. int err;
  2549. err = mlxsw_sp_kvdl_alloc(mlxsw_sp,
  2550. MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
  2551. p_kvdl_index);
  2552. if (err)
  2553. return err;
  2554. mlxsw_reg_rips_pack(rips_pl, *p_kvdl_index, addr6);
  2555. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rips), rips_pl);
  2556. if (err)
  2557. goto err_rips_write;
  2558. node = kzalloc(sizeof(*node), GFP_KERNEL);
  2559. if (!node) {
  2560. err = -ENOMEM;
  2561. goto err_node_alloc;
  2562. }
  2563. node->key = *addr6;
  2564. node->kvdl_index = *p_kvdl_index;
  2565. refcount_set(&node->refcount, 1);
  2566. err = rhashtable_insert_fast(&mlxsw_sp->ipv6_addr_ht,
  2567. &node->ht_node,
  2568. mlxsw_sp_ipv6_addr_ht_params);
  2569. if (err)
  2570. goto err_rhashtable_insert;
  2571. return 0;
  2572. err_rhashtable_insert:
  2573. kfree(node);
  2574. err_node_alloc:
  2575. err_rips_write:
  2576. mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
  2577. *p_kvdl_index);
  2578. return err;
  2579. }
  2580. static void mlxsw_sp_ipv6_addr_fini(struct mlxsw_sp *mlxsw_sp,
  2581. struct mlxsw_sp_ipv6_addr_node *node)
  2582. {
  2583. u32 kvdl_index = node->kvdl_index;
  2584. rhashtable_remove_fast(&mlxsw_sp->ipv6_addr_ht, &node->ht_node,
  2585. mlxsw_sp_ipv6_addr_ht_params);
  2586. kfree(node);
  2587. mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
  2588. kvdl_index);
  2589. }
  2590. int mlxsw_sp_ipv6_addr_kvdl_index_get(struct mlxsw_sp *mlxsw_sp,
  2591. const struct in6_addr *addr6,
  2592. u32 *p_kvdl_index)
  2593. {
  2594. struct mlxsw_sp_ipv6_addr_node *node;
  2595. int err = 0;
  2596. mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock);
  2597. node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6,
  2598. mlxsw_sp_ipv6_addr_ht_params);
  2599. if (node) {
  2600. refcount_inc(&node->refcount);
  2601. *p_kvdl_index = node->kvdl_index;
  2602. goto out_unlock;
  2603. }
  2604. err = mlxsw_sp_ipv6_addr_init(mlxsw_sp, addr6, p_kvdl_index);
  2605. out_unlock:
  2606. mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock);
  2607. return err;
  2608. }
  2609. void
  2610. mlxsw_sp_ipv6_addr_put(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6)
  2611. {
  2612. struct mlxsw_sp_ipv6_addr_node *node;
  2613. mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock);
  2614. node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6,
  2615. mlxsw_sp_ipv6_addr_ht_params);
  2616. if (WARN_ON(!node))
  2617. goto out_unlock;
  2618. if (!refcount_dec_and_test(&node->refcount))
  2619. goto out_unlock;
  2620. mlxsw_sp_ipv6_addr_fini(mlxsw_sp, node);
  2621. out_unlock:
  2622. mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock);
  2623. }
  2624. static int mlxsw_sp_ipv6_addr_ht_init(struct mlxsw_sp *mlxsw_sp)
  2625. {
  2626. int err;
  2627. err = rhashtable_init(&mlxsw_sp->ipv6_addr_ht,
  2628. &mlxsw_sp_ipv6_addr_ht_params);
  2629. if (err)
  2630. return err;
  2631. mutex_init(&mlxsw_sp->ipv6_addr_ht_lock);
  2632. return 0;
  2633. }
  2634. static void mlxsw_sp_ipv6_addr_ht_fini(struct mlxsw_sp *mlxsw_sp)
  2635. {
  2636. mutex_destroy(&mlxsw_sp->ipv6_addr_ht_lock);
  2637. rhashtable_destroy(&mlxsw_sp->ipv6_addr_ht);
  2638. }
  2639. static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
  2640. const struct mlxsw_bus_info *mlxsw_bus_info,
  2641. struct netlink_ext_ack *extack)
  2642. {
  2643. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  2644. int err;
  2645. mlxsw_sp->core = mlxsw_core;
  2646. mlxsw_sp->bus_info = mlxsw_bus_info;
  2647. mlxsw_sp_parsing_init(mlxsw_sp);
  2648. err = mlxsw_sp_base_mac_get(mlxsw_sp);
  2649. if (err) {
  2650. dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
  2651. return err;
  2652. }
  2653. err = mlxsw_sp_kvdl_init(mlxsw_sp);
  2654. if (err) {
  2655. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
  2656. return err;
  2657. }
  2658. err = mlxsw_sp_pgt_init(mlxsw_sp);
  2659. if (err) {
  2660. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PGT\n");
  2661. goto err_pgt_init;
  2662. }
  2663. /* Initialize before FIDs so that the LAG table is at the start of PGT
  2664. * and 8-aligned without overallocation.
  2665. */
  2666. err = mlxsw_sp_lag_init(mlxsw_sp);
  2667. if (err) {
  2668. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
  2669. goto err_lag_init;
  2670. }
  2671. err = mlxsw_sp->fid_core_ops->init(mlxsw_sp);
  2672. if (err) {
  2673. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
  2674. goto err_fid_core_init;
  2675. }
  2676. err = mlxsw_sp_policers_init(mlxsw_sp);
  2677. if (err) {
  2678. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n");
  2679. goto err_policers_init;
  2680. }
  2681. err = mlxsw_sp_traps_init(mlxsw_sp);
  2682. if (err) {
  2683. dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
  2684. goto err_traps_init;
  2685. }
  2686. err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
  2687. if (err) {
  2688. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
  2689. goto err_devlink_traps_init;
  2690. }
  2691. err = mlxsw_sp_buffers_init(mlxsw_sp);
  2692. if (err) {
  2693. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
  2694. goto err_buffers_init;
  2695. }
  2696. /* Initialize SPAN before router and switchdev, so that those components
  2697. * can call mlxsw_sp_span_respin().
  2698. */
  2699. err = mlxsw_sp_span_init(mlxsw_sp);
  2700. if (err) {
  2701. dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
  2702. goto err_span_init;
  2703. }
  2704. err = mlxsw_sp_switchdev_init(mlxsw_sp);
  2705. if (err) {
  2706. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
  2707. goto err_switchdev_init;
  2708. }
  2709. err = mlxsw_sp_counter_pool_init(mlxsw_sp);
  2710. if (err) {
  2711. dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
  2712. goto err_counter_pool_init;
  2713. }
  2714. err = mlxsw_sp_afa_init(mlxsw_sp);
  2715. if (err) {
  2716. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
  2717. goto err_afa_init;
  2718. }
  2719. err = mlxsw_sp_ipv6_addr_ht_init(mlxsw_sp);
  2720. if (err) {
  2721. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize hash table for IPv6 addresses\n");
  2722. goto err_ipv6_addr_ht_init;
  2723. }
  2724. err = mlxsw_sp_nve_init(mlxsw_sp);
  2725. if (err) {
  2726. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
  2727. goto err_nve_init;
  2728. }
  2729. err = mlxsw_sp_port_range_init(mlxsw_sp);
  2730. if (err) {
  2731. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize port ranges\n");
  2732. goto err_port_range_init;
  2733. }
  2734. err = mlxsw_sp_acl_init(mlxsw_sp);
  2735. if (err) {
  2736. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
  2737. goto err_acl_init;
  2738. }
  2739. err = mlxsw_sp_router_init(mlxsw_sp, extack);
  2740. if (err) {
  2741. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
  2742. goto err_router_init;
  2743. }
  2744. if (mlxsw_sp->bus_info->read_clock_capable) {
  2745. /* NULL is a valid return value from clock_init */
  2746. mlxsw_sp->clock =
  2747. mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
  2748. mlxsw_sp->bus_info->dev);
  2749. if (IS_ERR(mlxsw_sp->clock)) {
  2750. err = PTR_ERR(mlxsw_sp->clock);
  2751. dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
  2752. goto err_ptp_clock_init;
  2753. }
  2754. }
  2755. if (mlxsw_sp->clock) {
  2756. /* NULL is a valid return value from ptp_ops->init */
  2757. mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
  2758. if (IS_ERR(mlxsw_sp->ptp_state)) {
  2759. err = PTR_ERR(mlxsw_sp->ptp_state);
  2760. dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
  2761. goto err_ptp_init;
  2762. }
  2763. }
  2764. /* Initialize netdevice notifier after SPAN is initialized, so that the
  2765. * event handler can call SPAN respin.
  2766. */
  2767. mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
  2768. err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
  2769. &mlxsw_sp->netdevice_nb);
  2770. if (err) {
  2771. dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
  2772. goto err_netdev_notifier;
  2773. }
  2774. err = mlxsw_sp_dpipe_init(mlxsw_sp);
  2775. if (err) {
  2776. dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
  2777. goto err_dpipe_init;
  2778. }
  2779. err = mlxsw_sp_port_module_info_init(mlxsw_sp);
  2780. if (err) {
  2781. dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n");
  2782. goto err_port_module_info_init;
  2783. }
  2784. err = rhashtable_init(&mlxsw_sp->sample_trigger_ht,
  2785. &mlxsw_sp_sample_trigger_ht_params);
  2786. if (err) {
  2787. dev_err(mlxsw_sp->bus_info->dev, "Failed to init sampling trigger hashtable\n");
  2788. goto err_sample_trigger_init;
  2789. }
  2790. err = mlxsw_sp_ports_create(mlxsw_sp);
  2791. if (err) {
  2792. dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
  2793. goto err_ports_create;
  2794. }
  2795. return 0;
  2796. err_ports_create:
  2797. rhashtable_destroy(&mlxsw_sp->sample_trigger_ht);
  2798. err_sample_trigger_init:
  2799. mlxsw_sp_port_module_info_fini(mlxsw_sp);
  2800. err_port_module_info_init:
  2801. mlxsw_sp_dpipe_fini(mlxsw_sp);
  2802. err_dpipe_init:
  2803. unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
  2804. &mlxsw_sp->netdevice_nb);
  2805. err_netdev_notifier:
  2806. if (mlxsw_sp->clock)
  2807. mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
  2808. err_ptp_init:
  2809. if (mlxsw_sp->clock)
  2810. mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
  2811. err_ptp_clock_init:
  2812. mlxsw_sp_router_fini(mlxsw_sp);
  2813. err_router_init:
  2814. mlxsw_sp_acl_fini(mlxsw_sp);
  2815. err_acl_init:
  2816. mlxsw_sp_port_range_fini(mlxsw_sp);
  2817. err_port_range_init:
  2818. mlxsw_sp_nve_fini(mlxsw_sp);
  2819. err_nve_init:
  2820. mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp);
  2821. err_ipv6_addr_ht_init:
  2822. mlxsw_sp_afa_fini(mlxsw_sp);
  2823. err_afa_init:
  2824. mlxsw_sp_counter_pool_fini(mlxsw_sp);
  2825. err_counter_pool_init:
  2826. mlxsw_sp_switchdev_fini(mlxsw_sp);
  2827. err_switchdev_init:
  2828. mlxsw_sp_span_fini(mlxsw_sp);
  2829. err_span_init:
  2830. mlxsw_sp_buffers_fini(mlxsw_sp);
  2831. err_buffers_init:
  2832. mlxsw_sp_devlink_traps_fini(mlxsw_sp);
  2833. err_devlink_traps_init:
  2834. mlxsw_sp_traps_fini(mlxsw_sp);
  2835. err_traps_init:
  2836. mlxsw_sp_policers_fini(mlxsw_sp);
  2837. err_policers_init:
  2838. mlxsw_sp->fid_core_ops->fini(mlxsw_sp);
  2839. err_fid_core_init:
  2840. mlxsw_sp_lag_fini(mlxsw_sp);
  2841. err_lag_init:
  2842. mlxsw_sp_pgt_fini(mlxsw_sp);
  2843. err_pgt_init:
  2844. mlxsw_sp_kvdl_fini(mlxsw_sp);
  2845. mlxsw_sp_parsing_fini(mlxsw_sp);
  2846. return err;
  2847. }
  2848. static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
  2849. const struct mlxsw_bus_info *mlxsw_bus_info,
  2850. struct netlink_ext_ack *extack)
  2851. {
  2852. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  2853. mlxsw_sp->switchdev_ops = &mlxsw_sp1_switchdev_ops;
  2854. mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
  2855. mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
  2856. mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
  2857. mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
  2858. mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops;
  2859. mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
  2860. mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
  2861. mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
  2862. mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
  2863. mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops;
  2864. mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
  2865. mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
  2866. mlxsw_sp->span_ops = &mlxsw_sp1_span_ops;
  2867. mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops;
  2868. mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops;
  2869. mlxsw_sp->mall_ops = &mlxsw_sp1_mall_ops;
  2870. mlxsw_sp->router_ops = &mlxsw_sp1_router_ops;
  2871. mlxsw_sp->listeners = mlxsw_sp1_listener;
  2872. mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
  2873. mlxsw_sp->fid_core_ops = &mlxsw_sp1_fid_core_ops;
  2874. mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1;
  2875. mlxsw_sp->pgt_smpe_index_valid = true;
  2876. return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
  2877. }
  2878. static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
  2879. const struct mlxsw_bus_info *mlxsw_bus_info,
  2880. struct netlink_ext_ack *extack)
  2881. {
  2882. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  2883. mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
  2884. mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
  2885. mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
  2886. mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
  2887. mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
  2888. mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
  2889. mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
  2890. mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops;
  2891. mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
  2892. mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
  2893. mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
  2894. mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops;
  2895. mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
  2896. mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
  2897. mlxsw_sp->span_ops = &mlxsw_sp2_span_ops;
  2898. mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
  2899. mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
  2900. mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
  2901. mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
  2902. mlxsw_sp->listeners = mlxsw_sp2_listener;
  2903. mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
  2904. mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops;
  2905. mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2;
  2906. mlxsw_sp->pgt_smpe_index_valid = false;
  2907. return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
  2908. }
  2909. static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core,
  2910. const struct mlxsw_bus_info *mlxsw_bus_info,
  2911. struct netlink_ext_ack *extack)
  2912. {
  2913. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  2914. mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
  2915. mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
  2916. mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
  2917. mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
  2918. mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
  2919. mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
  2920. mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
  2921. mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops;
  2922. mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
  2923. mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
  2924. mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
  2925. mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops;
  2926. mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
  2927. mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
  2928. mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
  2929. mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
  2930. mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
  2931. mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
  2932. mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
  2933. mlxsw_sp->listeners = mlxsw_sp2_listener;
  2934. mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
  2935. mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops;
  2936. mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3;
  2937. mlxsw_sp->pgt_smpe_index_valid = false;
  2938. return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
  2939. }
  2940. static int mlxsw_sp4_init(struct mlxsw_core *mlxsw_core,
  2941. const struct mlxsw_bus_info *mlxsw_bus_info,
  2942. struct netlink_ext_ack *extack)
  2943. {
  2944. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  2945. mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
  2946. mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
  2947. mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
  2948. mlxsw_sp->afk_ops = &mlxsw_sp4_afk_ops;
  2949. mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
  2950. mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
  2951. mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
  2952. mlxsw_sp->acl_bf_ops = &mlxsw_sp4_acl_bf_ops;
  2953. mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
  2954. mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
  2955. mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
  2956. mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops;
  2957. mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
  2958. mlxsw_sp->ptp_ops = &mlxsw_sp4_ptp_ops;
  2959. mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
  2960. mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
  2961. mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
  2962. mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
  2963. mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
  2964. mlxsw_sp->listeners = mlxsw_sp2_listener;
  2965. mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
  2966. mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops;
  2967. mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4;
  2968. mlxsw_sp->pgt_smpe_index_valid = false;
  2969. return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
  2970. }
  2971. static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
  2972. {
  2973. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  2974. mlxsw_sp_ports_remove(mlxsw_sp);
  2975. rhashtable_destroy(&mlxsw_sp->sample_trigger_ht);
  2976. mlxsw_sp_port_module_info_fini(mlxsw_sp);
  2977. mlxsw_sp_dpipe_fini(mlxsw_sp);
  2978. unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
  2979. &mlxsw_sp->netdevice_nb);
  2980. if (mlxsw_sp->clock) {
  2981. mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
  2982. mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
  2983. }
  2984. mlxsw_sp_router_fini(mlxsw_sp);
  2985. mlxsw_sp_acl_fini(mlxsw_sp);
  2986. mlxsw_sp_port_range_fini(mlxsw_sp);
  2987. mlxsw_sp_nve_fini(mlxsw_sp);
  2988. mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp);
  2989. mlxsw_sp_afa_fini(mlxsw_sp);
  2990. mlxsw_sp_counter_pool_fini(mlxsw_sp);
  2991. mlxsw_sp_switchdev_fini(mlxsw_sp);
  2992. mlxsw_sp_span_fini(mlxsw_sp);
  2993. mlxsw_sp_buffers_fini(mlxsw_sp);
  2994. mlxsw_sp_devlink_traps_fini(mlxsw_sp);
  2995. mlxsw_sp_traps_fini(mlxsw_sp);
  2996. mlxsw_sp_policers_fini(mlxsw_sp);
  2997. mlxsw_sp->fid_core_ops->fini(mlxsw_sp);
  2998. mlxsw_sp_lag_fini(mlxsw_sp);
  2999. mlxsw_sp_pgt_fini(mlxsw_sp);
  3000. mlxsw_sp_kvdl_fini(mlxsw_sp);
  3001. mlxsw_sp_parsing_fini(mlxsw_sp);
  3002. }
  3003. static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
  3004. .used_flood_mode = 1,
  3005. .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,
  3006. .used_max_ib_mc = 1,
  3007. .max_ib_mc = 0,
  3008. .used_max_pkey = 1,
  3009. .max_pkey = 0,
  3010. .used_ubridge = 1,
  3011. .ubridge = 1,
  3012. .used_kvd_sizes = 1,
  3013. .kvd_hash_single_parts = 59,
  3014. .kvd_hash_double_parts = 41,
  3015. .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
  3016. .swid_config = {
  3017. {
  3018. .used_type = 1,
  3019. .type = MLXSW_PORT_SWID_TYPE_ETH,
  3020. }
  3021. },
  3022. };
  3023. static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
  3024. .used_flood_mode = 1,
  3025. .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,
  3026. .used_max_ib_mc = 1,
  3027. .max_ib_mc = 0,
  3028. .used_max_pkey = 1,
  3029. .max_pkey = 0,
  3030. .used_ubridge = 1,
  3031. .ubridge = 1,
  3032. .swid_config = {
  3033. {
  3034. .used_type = 1,
  3035. .type = MLXSW_PORT_SWID_TYPE_ETH,
  3036. }
  3037. },
  3038. .used_cqe_time_stamp_type = 1,
  3039. .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
  3040. .lag_mode_prefer_sw = true,
  3041. .flood_mode_prefer_cff = true,
  3042. };
  3043. /* Reduce number of LAGs from full capacity (256) to the maximum supported LAGs
  3044. * in Spectrum-2/3, to avoid regression in number of free entries in the PGT
  3045. * table.
  3046. */
  3047. #define MLXSW_SP4_CONFIG_PROFILE_MAX_LAG 128
  3048. static const struct mlxsw_config_profile mlxsw_sp4_config_profile = {
  3049. .used_max_lag = 1,
  3050. .max_lag = MLXSW_SP4_CONFIG_PROFILE_MAX_LAG,
  3051. .used_flood_mode = 1,
  3052. .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,
  3053. .used_max_ib_mc = 1,
  3054. .max_ib_mc = 0,
  3055. .used_max_pkey = 1,
  3056. .max_pkey = 0,
  3057. .used_ubridge = 1,
  3058. .ubridge = 1,
  3059. .swid_config = {
  3060. {
  3061. .used_type = 1,
  3062. .type = MLXSW_PORT_SWID_TYPE_ETH,
  3063. }
  3064. },
  3065. .used_cqe_time_stamp_type = 1,
  3066. .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
  3067. .lag_mode_prefer_sw = true,
  3068. .flood_mode_prefer_cff = true,
  3069. };
  3070. static void
  3071. mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
  3072. struct devlink_resource_size_params *kvd_size_params,
  3073. struct devlink_resource_size_params *linear_size_params,
  3074. struct devlink_resource_size_params *hash_double_size_params,
  3075. struct devlink_resource_size_params *hash_single_size_params)
  3076. {
  3077. u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
  3078. KVD_SINGLE_MIN_SIZE);
  3079. u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
  3080. KVD_DOUBLE_MIN_SIZE);
  3081. u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
  3082. u32 linear_size_min = 0;
  3083. devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
  3084. MLXSW_SP_KVD_GRANULARITY,
  3085. DEVLINK_RESOURCE_UNIT_ENTRY);
  3086. devlink_resource_size_params_init(linear_size_params, linear_size_min,
  3087. kvd_size - single_size_min -
  3088. double_size_min,
  3089. MLXSW_SP_KVD_GRANULARITY,
  3090. DEVLINK_RESOURCE_UNIT_ENTRY);
  3091. devlink_resource_size_params_init(hash_double_size_params,
  3092. double_size_min,
  3093. kvd_size - single_size_min -
  3094. linear_size_min,
  3095. MLXSW_SP_KVD_GRANULARITY,
  3096. DEVLINK_RESOURCE_UNIT_ENTRY);
  3097. devlink_resource_size_params_init(hash_single_size_params,
  3098. single_size_min,
  3099. kvd_size - double_size_min -
  3100. linear_size_min,
  3101. MLXSW_SP_KVD_GRANULARITY,
  3102. DEVLINK_RESOURCE_UNIT_ENTRY);
  3103. }
  3104. static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
  3105. {
  3106. struct devlink *devlink = priv_to_devlink(mlxsw_core);
  3107. struct devlink_resource_size_params hash_single_size_params;
  3108. struct devlink_resource_size_params hash_double_size_params;
  3109. struct devlink_resource_size_params linear_size_params;
  3110. struct devlink_resource_size_params kvd_size_params;
  3111. u32 kvd_size, single_size, double_size, linear_size;
  3112. const struct mlxsw_config_profile *profile;
  3113. int err;
  3114. profile = &mlxsw_sp1_config_profile;
  3115. if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
  3116. return -EIO;
  3117. mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
  3118. &linear_size_params,
  3119. &hash_double_size_params,
  3120. &hash_single_size_params);
  3121. kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
  3122. err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
  3123. kvd_size, MLXSW_SP_RESOURCE_KVD,
  3124. DEVLINK_RESOURCE_ID_PARENT_TOP,
  3125. &kvd_size_params);
  3126. if (err)
  3127. return err;
  3128. linear_size = profile->kvd_linear_size;
  3129. err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
  3130. linear_size,
  3131. MLXSW_SP_RESOURCE_KVD_LINEAR,
  3132. MLXSW_SP_RESOURCE_KVD,
  3133. &linear_size_params);
  3134. if (err)
  3135. return err;
  3136. err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
  3137. if (err)
  3138. return err;
  3139. double_size = kvd_size - linear_size;
  3140. double_size *= profile->kvd_hash_double_parts;
  3141. double_size /= profile->kvd_hash_double_parts +
  3142. profile->kvd_hash_single_parts;
  3143. double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
  3144. err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
  3145. double_size,
  3146. MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
  3147. MLXSW_SP_RESOURCE_KVD,
  3148. &hash_double_size_params);
  3149. if (err)
  3150. return err;
  3151. single_size = kvd_size - double_size - linear_size;
  3152. err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
  3153. single_size,
  3154. MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
  3155. MLXSW_SP_RESOURCE_KVD,
  3156. &hash_single_size_params);
  3157. if (err)
  3158. return err;
  3159. return 0;
  3160. }
  3161. static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core)
  3162. {
  3163. struct devlink *devlink = priv_to_devlink(mlxsw_core);
  3164. struct devlink_resource_size_params kvd_size_params;
  3165. u32 kvd_size;
  3166. if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
  3167. return -EIO;
  3168. kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
  3169. devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size,
  3170. MLXSW_SP_KVD_GRANULARITY,
  3171. DEVLINK_RESOURCE_UNIT_ENTRY);
  3172. return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
  3173. kvd_size, MLXSW_SP_RESOURCE_KVD,
  3174. DEVLINK_RESOURCE_ID_PARENT_TOP,
  3175. &kvd_size_params);
  3176. }
  3177. static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core)
  3178. {
  3179. struct devlink *devlink = priv_to_devlink(mlxsw_core);
  3180. struct devlink_resource_size_params span_size_params;
  3181. u32 max_span;
  3182. if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN))
  3183. return -EIO;
  3184. max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN);
  3185. devlink_resource_size_params_init(&span_size_params, max_span, max_span,
  3186. 1, DEVLINK_RESOURCE_UNIT_ENTRY);
  3187. return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN,
  3188. max_span, MLXSW_SP_RESOURCE_SPAN,
  3189. DEVLINK_RESOURCE_ID_PARENT_TOP,
  3190. &span_size_params);
  3191. }
  3192. static int
  3193. mlxsw_sp_resources_rif_mac_profile_register(struct mlxsw_core *mlxsw_core)
  3194. {
  3195. struct devlink *devlink = priv_to_devlink(mlxsw_core);
  3196. struct devlink_resource_size_params size_params;
  3197. u8 max_rif_mac_profiles;
  3198. if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIF_MAC_PROFILES))
  3199. max_rif_mac_profiles = 1;
  3200. else
  3201. max_rif_mac_profiles = MLXSW_CORE_RES_GET(mlxsw_core,
  3202. MAX_RIF_MAC_PROFILES);
  3203. devlink_resource_size_params_init(&size_params, max_rif_mac_profiles,
  3204. max_rif_mac_profiles, 1,
  3205. DEVLINK_RESOURCE_UNIT_ENTRY);
  3206. return devl_resource_register(devlink,
  3207. "rif_mac_profiles",
  3208. max_rif_mac_profiles,
  3209. MLXSW_SP_RESOURCE_RIF_MAC_PROFILES,
  3210. DEVLINK_RESOURCE_ID_PARENT_TOP,
  3211. &size_params);
  3212. }
  3213. static int mlxsw_sp_resources_rifs_register(struct mlxsw_core *mlxsw_core)
  3214. {
  3215. struct devlink *devlink = priv_to_devlink(mlxsw_core);
  3216. struct devlink_resource_size_params size_params;
  3217. u64 max_rifs;
  3218. if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIFS))
  3219. return -EIO;
  3220. max_rifs = MLXSW_CORE_RES_GET(mlxsw_core, MAX_RIFS);
  3221. devlink_resource_size_params_init(&size_params, max_rifs, max_rifs,
  3222. 1, DEVLINK_RESOURCE_UNIT_ENTRY);
  3223. return devl_resource_register(devlink, "rifs", max_rifs,
  3224. MLXSW_SP_RESOURCE_RIFS,
  3225. DEVLINK_RESOURCE_ID_PARENT_TOP,
  3226. &size_params);
  3227. }
  3228. static int
  3229. mlxsw_sp_resources_port_range_register(struct mlxsw_core *mlxsw_core)
  3230. {
  3231. struct devlink *devlink = priv_to_devlink(mlxsw_core);
  3232. struct devlink_resource_size_params size_params;
  3233. u64 max;
  3234. if (!MLXSW_CORE_RES_VALID(mlxsw_core, ACL_MAX_L4_PORT_RANGE))
  3235. return -EIO;
  3236. max = MLXSW_CORE_RES_GET(mlxsw_core, ACL_MAX_L4_PORT_RANGE);
  3237. devlink_resource_size_params_init(&size_params, max, max, 1,
  3238. DEVLINK_RESOURCE_UNIT_ENTRY);
  3239. return devl_resource_register(devlink, "port_range_registers", max,
  3240. MLXSW_SP_RESOURCE_PORT_RANGE_REGISTERS,
  3241. DEVLINK_RESOURCE_ID_PARENT_TOP,
  3242. &size_params);
  3243. }
  3244. static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
  3245. {
  3246. int err;
  3247. err = mlxsw_sp1_resources_kvd_register(mlxsw_core);
  3248. if (err)
  3249. return err;
  3250. err = mlxsw_sp_resources_span_register(mlxsw_core);
  3251. if (err)
  3252. goto err_resources_span_register;
  3253. err = mlxsw_sp_counter_resources_register(mlxsw_core);
  3254. if (err)
  3255. goto err_resources_counter_register;
  3256. err = mlxsw_sp_policer_resources_register(mlxsw_core);
  3257. if (err)
  3258. goto err_policer_resources_register;
  3259. err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core);
  3260. if (err)
  3261. goto err_resources_rif_mac_profile_register;
  3262. err = mlxsw_sp_resources_rifs_register(mlxsw_core);
  3263. if (err)
  3264. goto err_resources_rifs_register;
  3265. err = mlxsw_sp_resources_port_range_register(mlxsw_core);
  3266. if (err)
  3267. goto err_resources_port_range_register;
  3268. return 0;
  3269. err_resources_port_range_register:
  3270. err_resources_rifs_register:
  3271. err_resources_rif_mac_profile_register:
  3272. err_policer_resources_register:
  3273. err_resources_counter_register:
  3274. err_resources_span_register:
  3275. devl_resources_unregister(priv_to_devlink(mlxsw_core));
  3276. return err;
  3277. }
  3278. static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
  3279. {
  3280. int err;
  3281. err = mlxsw_sp2_resources_kvd_register(mlxsw_core);
  3282. if (err)
  3283. return err;
  3284. err = mlxsw_sp_resources_span_register(mlxsw_core);
  3285. if (err)
  3286. goto err_resources_span_register;
  3287. err = mlxsw_sp_counter_resources_register(mlxsw_core);
  3288. if (err)
  3289. goto err_resources_counter_register;
  3290. err = mlxsw_sp_policer_resources_register(mlxsw_core);
  3291. if (err)
  3292. goto err_policer_resources_register;
  3293. err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core);
  3294. if (err)
  3295. goto err_resources_rif_mac_profile_register;
  3296. err = mlxsw_sp_resources_rifs_register(mlxsw_core);
  3297. if (err)
  3298. goto err_resources_rifs_register;
  3299. err = mlxsw_sp_resources_port_range_register(mlxsw_core);
  3300. if (err)
  3301. goto err_resources_port_range_register;
  3302. return 0;
  3303. err_resources_port_range_register:
  3304. err_resources_rifs_register:
  3305. err_resources_rif_mac_profile_register:
  3306. err_policer_resources_register:
  3307. err_resources_counter_register:
  3308. err_resources_span_register:
  3309. devl_resources_unregister(priv_to_devlink(mlxsw_core));
  3310. return err;
  3311. }
  3312. static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
  3313. const struct mlxsw_config_profile *profile,
  3314. u64 *p_single_size, u64 *p_double_size,
  3315. u64 *p_linear_size)
  3316. {
  3317. struct devlink *devlink = priv_to_devlink(mlxsw_core);
  3318. u32 double_size;
  3319. int err;
  3320. if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
  3321. !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
  3322. return -EIO;
  3323. /* The hash part is what left of the kvd without the
  3324. * linear part. It is split to the single size and
  3325. * double size by the parts ratio from the profile.
  3326. * Both sizes must be a multiplications of the
  3327. * granularity from the profile. In case the user
  3328. * provided the sizes they are obtained via devlink.
  3329. */
  3330. err = devl_resource_size_get(devlink,
  3331. MLXSW_SP_RESOURCE_KVD_LINEAR,
  3332. p_linear_size);
  3333. if (err)
  3334. *p_linear_size = profile->kvd_linear_size;
  3335. err = devl_resource_size_get(devlink,
  3336. MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
  3337. p_double_size);
  3338. if (err) {
  3339. double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
  3340. *p_linear_size;
  3341. double_size *= profile->kvd_hash_double_parts;
  3342. double_size /= profile->kvd_hash_double_parts +
  3343. profile->kvd_hash_single_parts;
  3344. *p_double_size = rounddown(double_size,
  3345. MLXSW_SP_KVD_GRANULARITY);
  3346. }
  3347. err = devl_resource_size_get(devlink,
  3348. MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
  3349. p_single_size);
  3350. if (err)
  3351. *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
  3352. *p_double_size - *p_linear_size;
  3353. /* Check results are legal. */
  3354. if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
  3355. *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
  3356. MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
  3357. return -EIO;
  3358. return 0;
  3359. }
  3360. static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core,
  3361. struct sk_buff *skb, u16 local_port)
  3362. {
  3363. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  3364. skb_pull(skb, MLXSW_TXHDR_LEN);
  3365. mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
  3366. }
  3367. static struct mlxsw_driver mlxsw_sp1_driver = {
  3368. .kind = mlxsw_sp1_driver_name,
  3369. .priv_size = sizeof(struct mlxsw_sp),
  3370. .fw_req_rev = &mlxsw_sp1_fw_rev,
  3371. .fw_filename = MLXSW_SP1_FW_FILENAME,
  3372. .init = mlxsw_sp1_init,
  3373. .fini = mlxsw_sp_fini,
  3374. .port_split = mlxsw_sp_port_split,
  3375. .port_unsplit = mlxsw_sp_port_unsplit,
  3376. .sb_pool_get = mlxsw_sp_sb_pool_get,
  3377. .sb_pool_set = mlxsw_sp_sb_pool_set,
  3378. .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
  3379. .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
  3380. .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
  3381. .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
  3382. .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
  3383. .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
  3384. .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
  3385. .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
  3386. .trap_init = mlxsw_sp_trap_init,
  3387. .trap_fini = mlxsw_sp_trap_fini,
  3388. .trap_action_set = mlxsw_sp_trap_action_set,
  3389. .trap_group_init = mlxsw_sp_trap_group_init,
  3390. .trap_group_set = mlxsw_sp_trap_group_set,
  3391. .trap_policer_init = mlxsw_sp_trap_policer_init,
  3392. .trap_policer_fini = mlxsw_sp_trap_policer_fini,
  3393. .trap_policer_set = mlxsw_sp_trap_policer_set,
  3394. .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
  3395. .txhdr_construct = mlxsw_sp_txhdr_construct,
  3396. .resources_register = mlxsw_sp1_resources_register,
  3397. .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
  3398. .ptp_transmitted = mlxsw_sp_ptp_transmitted,
  3399. .txhdr_len = MLXSW_TXHDR_LEN,
  3400. .profile = &mlxsw_sp1_config_profile,
  3401. .sdq_supports_cqe_v2 = false,
  3402. };
  3403. static struct mlxsw_driver mlxsw_sp2_driver = {
  3404. .kind = mlxsw_sp2_driver_name,
  3405. .priv_size = sizeof(struct mlxsw_sp),
  3406. .fw_req_rev = &mlxsw_sp2_fw_rev,
  3407. .fw_filename = MLXSW_SP2_FW_FILENAME,
  3408. .init = mlxsw_sp2_init,
  3409. .fini = mlxsw_sp_fini,
  3410. .port_split = mlxsw_sp_port_split,
  3411. .port_unsplit = mlxsw_sp_port_unsplit,
  3412. .ports_remove_selected = mlxsw_sp_ports_remove_selected,
  3413. .sb_pool_get = mlxsw_sp_sb_pool_get,
  3414. .sb_pool_set = mlxsw_sp_sb_pool_set,
  3415. .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
  3416. .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
  3417. .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
  3418. .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
  3419. .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
  3420. .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
  3421. .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
  3422. .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
  3423. .trap_init = mlxsw_sp_trap_init,
  3424. .trap_fini = mlxsw_sp_trap_fini,
  3425. .trap_action_set = mlxsw_sp_trap_action_set,
  3426. .trap_group_init = mlxsw_sp_trap_group_init,
  3427. .trap_group_set = mlxsw_sp_trap_group_set,
  3428. .trap_policer_init = mlxsw_sp_trap_policer_init,
  3429. .trap_policer_fini = mlxsw_sp_trap_policer_fini,
  3430. .trap_policer_set = mlxsw_sp_trap_policer_set,
  3431. .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
  3432. .txhdr_construct = mlxsw_sp_txhdr_construct,
  3433. .resources_register = mlxsw_sp2_resources_register,
  3434. .ptp_transmitted = mlxsw_sp_ptp_transmitted,
  3435. .txhdr_len = MLXSW_TXHDR_LEN,
  3436. .profile = &mlxsw_sp2_config_profile,
  3437. .sdq_supports_cqe_v2 = true,
  3438. };
  3439. static struct mlxsw_driver mlxsw_sp3_driver = {
  3440. .kind = mlxsw_sp3_driver_name,
  3441. .priv_size = sizeof(struct mlxsw_sp),
  3442. .fw_req_rev = &mlxsw_sp3_fw_rev,
  3443. .fw_filename = MLXSW_SP3_FW_FILENAME,
  3444. .init = mlxsw_sp3_init,
  3445. .fini = mlxsw_sp_fini,
  3446. .port_split = mlxsw_sp_port_split,
  3447. .port_unsplit = mlxsw_sp_port_unsplit,
  3448. .ports_remove_selected = mlxsw_sp_ports_remove_selected,
  3449. .sb_pool_get = mlxsw_sp_sb_pool_get,
  3450. .sb_pool_set = mlxsw_sp_sb_pool_set,
  3451. .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
  3452. .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
  3453. .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
  3454. .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
  3455. .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
  3456. .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
  3457. .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
  3458. .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
  3459. .trap_init = mlxsw_sp_trap_init,
  3460. .trap_fini = mlxsw_sp_trap_fini,
  3461. .trap_action_set = mlxsw_sp_trap_action_set,
  3462. .trap_group_init = mlxsw_sp_trap_group_init,
  3463. .trap_group_set = mlxsw_sp_trap_group_set,
  3464. .trap_policer_init = mlxsw_sp_trap_policer_init,
  3465. .trap_policer_fini = mlxsw_sp_trap_policer_fini,
  3466. .trap_policer_set = mlxsw_sp_trap_policer_set,
  3467. .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
  3468. .txhdr_construct = mlxsw_sp_txhdr_construct,
  3469. .resources_register = mlxsw_sp2_resources_register,
  3470. .ptp_transmitted = mlxsw_sp_ptp_transmitted,
  3471. .txhdr_len = MLXSW_TXHDR_LEN,
  3472. .profile = &mlxsw_sp2_config_profile,
  3473. .sdq_supports_cqe_v2 = true,
  3474. };
  3475. static struct mlxsw_driver mlxsw_sp4_driver = {
  3476. .kind = mlxsw_sp4_driver_name,
  3477. .priv_size = sizeof(struct mlxsw_sp),
  3478. .init = mlxsw_sp4_init,
  3479. .fini = mlxsw_sp_fini,
  3480. .port_split = mlxsw_sp_port_split,
  3481. .port_unsplit = mlxsw_sp_port_unsplit,
  3482. .ports_remove_selected = mlxsw_sp_ports_remove_selected,
  3483. .sb_pool_get = mlxsw_sp_sb_pool_get,
  3484. .sb_pool_set = mlxsw_sp_sb_pool_set,
  3485. .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
  3486. .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
  3487. .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
  3488. .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
  3489. .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
  3490. .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
  3491. .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
  3492. .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
  3493. .trap_init = mlxsw_sp_trap_init,
  3494. .trap_fini = mlxsw_sp_trap_fini,
  3495. .trap_action_set = mlxsw_sp_trap_action_set,
  3496. .trap_group_init = mlxsw_sp_trap_group_init,
  3497. .trap_group_set = mlxsw_sp_trap_group_set,
  3498. .trap_policer_init = mlxsw_sp_trap_policer_init,
  3499. .trap_policer_fini = mlxsw_sp_trap_policer_fini,
  3500. .trap_policer_set = mlxsw_sp_trap_policer_set,
  3501. .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get,
  3502. .txhdr_construct = mlxsw_sp_txhdr_construct,
  3503. .resources_register = mlxsw_sp2_resources_register,
  3504. .ptp_transmitted = mlxsw_sp_ptp_transmitted,
  3505. .txhdr_len = MLXSW_TXHDR_LEN,
  3506. .profile = &mlxsw_sp4_config_profile,
  3507. .sdq_supports_cqe_v2 = true,
  3508. };
  3509. bool mlxsw_sp_port_dev_check(const struct net_device *dev)
  3510. {
  3511. return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
  3512. }
  3513. static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev,
  3514. struct netdev_nested_priv *priv)
  3515. {
  3516. int ret = 0;
  3517. if (mlxsw_sp_port_dev_check(lower_dev)) {
  3518. priv->data = (void *)netdev_priv(lower_dev);
  3519. ret = 1;
  3520. }
  3521. return ret;
  3522. }
  3523. struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
  3524. {
  3525. struct netdev_nested_priv priv = {
  3526. .data = NULL,
  3527. };
  3528. if (mlxsw_sp_port_dev_check(dev))
  3529. return netdev_priv(dev);
  3530. netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &priv);
  3531. return (struct mlxsw_sp_port *)priv.data;
  3532. }
  3533. struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
  3534. {
  3535. struct mlxsw_sp_port *mlxsw_sp_port;
  3536. mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
  3537. return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
  3538. }
  3539. struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
  3540. {
  3541. struct netdev_nested_priv priv = {
  3542. .data = NULL,
  3543. };
  3544. if (mlxsw_sp_port_dev_check(dev))
  3545. return netdev_priv(dev);
  3546. netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
  3547. &priv);
  3548. return (struct mlxsw_sp_port *)priv.data;
  3549. }
  3550. int mlxsw_sp_parsing_depth_inc(struct mlxsw_sp *mlxsw_sp)
  3551. {
  3552. char mprs_pl[MLXSW_REG_MPRS_LEN];
  3553. int err = 0;
  3554. mutex_lock(&mlxsw_sp->parsing.lock);
  3555. if (refcount_inc_not_zero(&mlxsw_sp->parsing.parsing_depth_ref))
  3556. goto out_unlock;
  3557. mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_INCREASED_PARSING_DEPTH,
  3558. mlxsw_sp->parsing.vxlan_udp_dport);
  3559. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
  3560. if (err)
  3561. goto out_unlock;
  3562. mlxsw_sp->parsing.parsing_depth = MLXSW_SP_INCREASED_PARSING_DEPTH;
  3563. refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 1);
  3564. out_unlock:
  3565. mutex_unlock(&mlxsw_sp->parsing.lock);
  3566. return err;
  3567. }
  3568. void mlxsw_sp_parsing_depth_dec(struct mlxsw_sp *mlxsw_sp)
  3569. {
  3570. char mprs_pl[MLXSW_REG_MPRS_LEN];
  3571. mutex_lock(&mlxsw_sp->parsing.lock);
  3572. if (!refcount_dec_and_test(&mlxsw_sp->parsing.parsing_depth_ref))
  3573. goto out_unlock;
  3574. mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_DEFAULT_PARSING_DEPTH,
  3575. mlxsw_sp->parsing.vxlan_udp_dport);
  3576. mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
  3577. mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH;
  3578. out_unlock:
  3579. mutex_unlock(&mlxsw_sp->parsing.lock);
  3580. }
  3581. int mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp *mlxsw_sp,
  3582. __be16 udp_dport)
  3583. {
  3584. char mprs_pl[MLXSW_REG_MPRS_LEN];
  3585. int err;
  3586. mutex_lock(&mlxsw_sp->parsing.lock);
  3587. mlxsw_reg_mprs_pack(mprs_pl, mlxsw_sp->parsing.parsing_depth,
  3588. be16_to_cpu(udp_dport));
  3589. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
  3590. if (err)
  3591. goto out_unlock;
  3592. mlxsw_sp->parsing.vxlan_udp_dport = be16_to_cpu(udp_dport);
  3593. out_unlock:
  3594. mutex_unlock(&mlxsw_sp->parsing.lock);
  3595. return err;
  3596. }
  3597. static void
  3598. mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
  3599. struct net_device *lag_dev)
  3600. {
  3601. struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
  3602. struct net_device *upper_dev;
  3603. struct list_head *iter;
  3604. if (netif_is_bridge_port(lag_dev))
  3605. mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
  3606. netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
  3607. if (!netif_is_bridge_port(upper_dev))
  3608. continue;
  3609. br_dev = netdev_master_upper_dev_get(upper_dev);
  3610. mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
  3611. }
  3612. }
  3613. static struct mlxsw_sp_lag *
  3614. mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev,
  3615. struct netlink_ext_ack *extack)
  3616. {
  3617. char sldr_pl[MLXSW_REG_SLDR_LEN];
  3618. struct mlxsw_sp_lag *lag;
  3619. u16 lag_id;
  3620. int i, err;
  3621. for (i = 0; i < mlxsw_sp->max_lag; i++) {
  3622. if (!mlxsw_sp->lags[i].dev)
  3623. break;
  3624. }
  3625. if (i == mlxsw_sp->max_lag) {
  3626. NL_SET_ERR_MSG_MOD(extack,
  3627. "Exceeded number of supported LAG devices");
  3628. return ERR_PTR(-EBUSY);
  3629. }
  3630. lag_id = i;
  3631. mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
  3632. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
  3633. if (err)
  3634. return ERR_PTR(err);
  3635. lag = &mlxsw_sp->lags[lag_id];
  3636. lag->lag_id = lag_id;
  3637. lag->dev = lag_dev;
  3638. refcount_set(&lag->ref_count, 1);
  3639. return lag;
  3640. }
  3641. static int
  3642. mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_lag *lag)
  3643. {
  3644. char sldr_pl[MLXSW_REG_SLDR_LEN];
  3645. lag->dev = NULL;
  3646. mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag->lag_id);
  3647. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
  3648. }
  3649. static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
  3650. u16 lag_id, u8 port_index)
  3651. {
  3652. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3653. char slcor_pl[MLXSW_REG_SLCOR_LEN];
  3654. mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
  3655. lag_id, port_index);
  3656. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
  3657. }
  3658. static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
  3659. u16 lag_id)
  3660. {
  3661. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3662. char slcor_pl[MLXSW_REG_SLCOR_LEN];
  3663. mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
  3664. lag_id);
  3665. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
  3666. }
  3667. static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
  3668. u16 lag_id)
  3669. {
  3670. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3671. char slcor_pl[MLXSW_REG_SLCOR_LEN];
  3672. mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
  3673. lag_id);
  3674. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
  3675. }
  3676. static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
  3677. u16 lag_id)
  3678. {
  3679. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3680. char slcor_pl[MLXSW_REG_SLCOR_LEN];
  3681. mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
  3682. lag_id);
  3683. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
  3684. }
  3685. static struct mlxsw_sp_lag *
  3686. mlxsw_sp_lag_find(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev)
  3687. {
  3688. int i;
  3689. for (i = 0; i < mlxsw_sp->max_lag; i++) {
  3690. if (!mlxsw_sp->lags[i].dev)
  3691. continue;
  3692. if (mlxsw_sp->lags[i].dev == lag_dev)
  3693. return &mlxsw_sp->lags[i];
  3694. }
  3695. return NULL;
  3696. }
  3697. static struct mlxsw_sp_lag *
  3698. mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev,
  3699. struct netlink_ext_ack *extack)
  3700. {
  3701. struct mlxsw_sp_lag *lag;
  3702. lag = mlxsw_sp_lag_find(mlxsw_sp, lag_dev);
  3703. if (lag) {
  3704. refcount_inc(&lag->ref_count);
  3705. return lag;
  3706. }
  3707. return mlxsw_sp_lag_create(mlxsw_sp, lag_dev, extack);
  3708. }
  3709. static void
  3710. mlxsw_sp_lag_put(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_lag *lag)
  3711. {
  3712. if (!refcount_dec_and_test(&lag->ref_count))
  3713. return;
  3714. mlxsw_sp_lag_destroy(mlxsw_sp, lag);
  3715. }
  3716. static bool
  3717. mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
  3718. struct net_device *lag_dev,
  3719. struct netdev_lag_upper_info *lag_upper_info,
  3720. struct netlink_ext_ack *extack)
  3721. {
  3722. if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
  3723. NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
  3724. return false;
  3725. }
  3726. return true;
  3727. }
  3728. static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
  3729. u16 lag_id, u8 *p_port_index)
  3730. {
  3731. u64 max_lag_members;
  3732. int i;
  3733. max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
  3734. MAX_LAG_MEMBERS);
  3735. for (i = 0; i < max_lag_members; i++) {
  3736. if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
  3737. *p_port_index = i;
  3738. return 0;
  3739. }
  3740. }
  3741. return -EBUSY;
  3742. }
  3743. static int mlxsw_sp_lag_uppers_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
  3744. struct net_device *lag_dev,
  3745. struct netlink_ext_ack *extack)
  3746. {
  3747. struct net_device *upper_dev;
  3748. struct net_device *master;
  3749. struct list_head *iter;
  3750. int done = 0;
  3751. int err;
  3752. master = netdev_master_upper_dev_get(lag_dev);
  3753. if (master && netif_is_bridge_master(master)) {
  3754. err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, lag_dev, master,
  3755. extack);
  3756. if (err)
  3757. return err;
  3758. }
  3759. netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
  3760. if (!is_vlan_dev(upper_dev))
  3761. continue;
  3762. master = netdev_master_upper_dev_get(upper_dev);
  3763. if (master && netif_is_bridge_master(master)) {
  3764. err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
  3765. upper_dev, master,
  3766. extack);
  3767. if (err)
  3768. goto err_port_bridge_join;
  3769. }
  3770. ++done;
  3771. }
  3772. return 0;
  3773. err_port_bridge_join:
  3774. netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
  3775. if (!is_vlan_dev(upper_dev))
  3776. continue;
  3777. master = netdev_master_upper_dev_get(upper_dev);
  3778. if (!master || !netif_is_bridge_master(master))
  3779. continue;
  3780. if (!done--)
  3781. break;
  3782. mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, master);
  3783. }
  3784. master = netdev_master_upper_dev_get(lag_dev);
  3785. if (master && netif_is_bridge_master(master))
  3786. mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, master);
  3787. return err;
  3788. }
  3789. static void
  3790. mlxsw_sp_lag_uppers_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port,
  3791. struct net_device *lag_dev)
  3792. {
  3793. struct net_device *upper_dev;
  3794. struct net_device *master;
  3795. struct list_head *iter;
  3796. netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
  3797. if (!is_vlan_dev(upper_dev))
  3798. continue;
  3799. master = netdev_master_upper_dev_get(upper_dev);
  3800. if (!master)
  3801. continue;
  3802. mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, master);
  3803. }
  3804. master = netdev_master_upper_dev_get(lag_dev);
  3805. if (master)
  3806. mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, master);
  3807. }
  3808. static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
  3809. struct net_device *lag_dev,
  3810. struct netlink_ext_ack *extack)
  3811. {
  3812. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3813. struct mlxsw_sp_lag *lag;
  3814. u16 lag_id;
  3815. u8 port_index;
  3816. int err;
  3817. lag = mlxsw_sp_lag_get(mlxsw_sp, lag_dev, extack);
  3818. if (IS_ERR(lag))
  3819. return PTR_ERR(lag);
  3820. lag_id = lag->lag_id;
  3821. err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
  3822. if (err)
  3823. return err;
  3824. err = mlxsw_sp_lag_uppers_bridge_join(mlxsw_sp_port, lag_dev,
  3825. extack);
  3826. if (err)
  3827. goto err_lag_uppers_bridge_join;
  3828. err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
  3829. if (err)
  3830. goto err_col_port_add;
  3831. mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
  3832. mlxsw_sp_port->local_port);
  3833. mlxsw_sp_port->lag_id = lag_id;
  3834. mlxsw_sp_port->lagged = 1;
  3835. err = mlxsw_sp_fid_port_join_lag(mlxsw_sp_port);
  3836. if (err)
  3837. goto err_fid_port_join_lag;
  3838. /* Port is no longer usable as a router interface */
  3839. if (mlxsw_sp_port->default_vlan->fid)
  3840. mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
  3841. /* Join a router interface configured on the LAG, if exists */
  3842. err = mlxsw_sp_router_port_join_lag(mlxsw_sp_port, lag_dev,
  3843. extack);
  3844. if (err)
  3845. goto err_router_join;
  3846. err = mlxsw_sp_netdevice_enslavement_replay(mlxsw_sp, lag_dev, extack);
  3847. if (err)
  3848. goto err_replay;
  3849. return 0;
  3850. err_replay:
  3851. mlxsw_sp_router_port_leave_lag(mlxsw_sp_port, lag_dev);
  3852. err_router_join:
  3853. mlxsw_sp_fid_port_leave_lag(mlxsw_sp_port);
  3854. err_fid_port_join_lag:
  3855. mlxsw_sp_port->lagged = 0;
  3856. mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
  3857. mlxsw_sp_port->local_port);
  3858. mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
  3859. err_col_port_add:
  3860. mlxsw_sp_lag_uppers_bridge_leave(mlxsw_sp_port, lag_dev);
  3861. err_lag_uppers_bridge_join:
  3862. mlxsw_sp_lag_put(mlxsw_sp, lag);
  3863. return err;
  3864. }
  3865. static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
  3866. struct net_device *lag_dev)
  3867. {
  3868. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3869. u16 lag_id = mlxsw_sp_port->lag_id;
  3870. struct mlxsw_sp_lag *lag;
  3871. if (!mlxsw_sp_port->lagged)
  3872. return;
  3873. lag = &mlxsw_sp->lags[lag_id];
  3874. mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
  3875. /* Any VLANs configured on the port are no longer valid */
  3876. mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
  3877. mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
  3878. /* Make the LAG and its directly linked uppers leave bridges they
  3879. * are memeber in
  3880. */
  3881. mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
  3882. mlxsw_sp_fid_port_leave_lag(mlxsw_sp_port);
  3883. mlxsw_sp_lag_put(mlxsw_sp, lag);
  3884. mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
  3885. mlxsw_sp_port->local_port);
  3886. mlxsw_sp_port->lagged = 0;
  3887. /* Make sure untagged frames are allowed to ingress */
  3888. mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID,
  3889. ETH_P_8021Q);
  3890. }
  3891. static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
  3892. u16 lag_id)
  3893. {
  3894. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3895. char sldr_pl[MLXSW_REG_SLDR_LEN];
  3896. mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
  3897. mlxsw_sp_port->local_port);
  3898. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
  3899. }
  3900. static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
  3901. u16 lag_id)
  3902. {
  3903. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3904. char sldr_pl[MLXSW_REG_SLDR_LEN];
  3905. mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
  3906. mlxsw_sp_port->local_port);
  3907. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
  3908. }
  3909. static int
  3910. mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
  3911. {
  3912. int err;
  3913. err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
  3914. mlxsw_sp_port->lag_id);
  3915. if (err)
  3916. return err;
  3917. err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
  3918. if (err)
  3919. goto err_dist_port_add;
  3920. return 0;
  3921. err_dist_port_add:
  3922. mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
  3923. return err;
  3924. }
  3925. static int
  3926. mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
  3927. {
  3928. int err;
  3929. err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
  3930. mlxsw_sp_port->lag_id);
  3931. if (err)
  3932. return err;
  3933. err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
  3934. mlxsw_sp_port->lag_id);
  3935. if (err)
  3936. goto err_col_port_disable;
  3937. return 0;
  3938. err_col_port_disable:
  3939. mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
  3940. return err;
  3941. }
  3942. static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
  3943. struct netdev_lag_lower_state_info *info)
  3944. {
  3945. if (info->tx_enabled)
  3946. return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
  3947. else
  3948. return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
  3949. }
  3950. static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
  3951. bool enable)
  3952. {
  3953. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  3954. enum mlxsw_reg_spms_state spms_state;
  3955. char *spms_pl;
  3956. u16 vid;
  3957. int err;
  3958. spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
  3959. MLXSW_REG_SPMS_STATE_DISCARDING;
  3960. spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
  3961. if (!spms_pl)
  3962. return -ENOMEM;
  3963. mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
  3964. for (vid = 0; vid < VLAN_N_VID; vid++)
  3965. mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
  3966. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
  3967. kfree(spms_pl);
  3968. return err;
  3969. }
  3970. static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
  3971. {
  3972. u16 vid = 1;
  3973. int err;
  3974. err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
  3975. if (err)
  3976. return err;
  3977. err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
  3978. if (err)
  3979. goto err_port_stp_set;
  3980. err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
  3981. true, false);
  3982. if (err)
  3983. goto err_port_vlan_set;
  3984. for (; vid <= VLAN_N_VID - 1; vid++) {
  3985. err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
  3986. vid, false);
  3987. if (err)
  3988. goto err_vid_learning_set;
  3989. }
  3990. return 0;
  3991. err_vid_learning_set:
  3992. for (vid--; vid >= 1; vid--)
  3993. mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
  3994. err_port_vlan_set:
  3995. mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
  3996. err_port_stp_set:
  3997. mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
  3998. return err;
  3999. }
  4000. static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
  4001. {
  4002. u16 vid;
  4003. for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
  4004. mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
  4005. vid, true);
  4006. mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
  4007. false, false);
  4008. mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
  4009. mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
  4010. }
  4011. static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
  4012. {
  4013. unsigned int num_vxlans = 0;
  4014. struct net_device *dev;
  4015. struct list_head *iter;
  4016. netdev_for_each_lower_dev(br_dev, dev, iter) {
  4017. if (netif_is_vxlan(dev))
  4018. num_vxlans++;
  4019. }
  4020. return num_vxlans > 1;
  4021. }
  4022. static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
  4023. {
  4024. DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
  4025. struct net_device *dev;
  4026. struct list_head *iter;
  4027. netdev_for_each_lower_dev(br_dev, dev, iter) {
  4028. u16 pvid;
  4029. int err;
  4030. if (!netif_is_vxlan(dev))
  4031. continue;
  4032. err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
  4033. if (err || !pvid)
  4034. continue;
  4035. if (test_and_set_bit(pvid, vlans))
  4036. return false;
  4037. }
  4038. return true;
  4039. }
  4040. static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
  4041. struct netlink_ext_ack *extack)
  4042. {
  4043. if (br_multicast_enabled(br_dev)) {
  4044. NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
  4045. return false;
  4046. }
  4047. if (!br_vlan_enabled(br_dev) &&
  4048. mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
  4049. NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
  4050. return false;
  4051. }
  4052. if (br_vlan_enabled(br_dev) &&
  4053. !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
  4054. NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
  4055. return false;
  4056. }
  4057. return true;
  4058. }
  4059. static bool mlxsw_sp_netdev_is_master(struct net_device *upper_dev,
  4060. struct net_device *dev)
  4061. {
  4062. return upper_dev == netdev_master_upper_dev_get(dev);
  4063. }
  4064. static int __mlxsw_sp_netdevice_event(struct mlxsw_sp *mlxsw_sp,
  4065. unsigned long event, void *ptr,
  4066. bool process_foreign);
  4067. static int mlxsw_sp_netdevice_validate_uppers(struct mlxsw_sp *mlxsw_sp,
  4068. struct net_device *dev,
  4069. struct netlink_ext_ack *extack)
  4070. {
  4071. struct net_device *upper_dev;
  4072. struct list_head *iter;
  4073. int err;
  4074. netdev_for_each_upper_dev_rcu(dev, upper_dev, iter) {
  4075. struct netdev_notifier_changeupper_info info = {
  4076. .info = {
  4077. .dev = dev,
  4078. .extack = extack,
  4079. },
  4080. .master = mlxsw_sp_netdev_is_master(upper_dev, dev),
  4081. .upper_dev = upper_dev,
  4082. .linking = true,
  4083. /* upper_info is relevant for LAG devices. But we would
  4084. * only need this if LAG were a valid upper above
  4085. * another upper (e.g. a bridge that is a member of a
  4086. * LAG), and that is never a valid configuration. So we
  4087. * can keep this as NULL.
  4088. */
  4089. .upper_info = NULL,
  4090. };
  4091. err = __mlxsw_sp_netdevice_event(mlxsw_sp,
  4092. NETDEV_PRECHANGEUPPER,
  4093. &info, true);
  4094. if (err)
  4095. return err;
  4096. err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp, upper_dev,
  4097. extack);
  4098. if (err)
  4099. return err;
  4100. }
  4101. return 0;
  4102. }
  4103. static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
  4104. struct net_device *dev,
  4105. unsigned long event, void *ptr,
  4106. bool replay_deslavement)
  4107. {
  4108. struct netdev_notifier_changeupper_info *info;
  4109. struct mlxsw_sp_port *mlxsw_sp_port;
  4110. struct netlink_ext_ack *extack;
  4111. struct net_device *upper_dev;
  4112. struct mlxsw_sp *mlxsw_sp;
  4113. int err = 0;
  4114. u16 proto;
  4115. mlxsw_sp_port = netdev_priv(dev);
  4116. mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  4117. info = ptr;
  4118. extack = netdev_notifier_info_to_extack(&info->info);
  4119. switch (event) {
  4120. case NETDEV_PRECHANGEUPPER:
  4121. upper_dev = info->upper_dev;
  4122. if (!is_vlan_dev(upper_dev) &&
  4123. !netif_is_lag_master(upper_dev) &&
  4124. !netif_is_bridge_master(upper_dev) &&
  4125. !netif_is_ovs_master(upper_dev) &&
  4126. !netif_is_macvlan(upper_dev) &&
  4127. !netif_is_l3_master(upper_dev)) {
  4128. NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
  4129. return -EINVAL;
  4130. }
  4131. if (!info->linking)
  4132. break;
  4133. if (netif_is_bridge_master(upper_dev) &&
  4134. !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
  4135. mlxsw_sp_bridge_has_vxlan(upper_dev) &&
  4136. !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
  4137. return -EOPNOTSUPP;
  4138. if (netdev_has_any_upper_dev(upper_dev) &&
  4139. (!netif_is_bridge_master(upper_dev) ||
  4140. !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
  4141. upper_dev))) {
  4142. err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp,
  4143. upper_dev,
  4144. extack);
  4145. if (err)
  4146. return err;
  4147. }
  4148. if (netif_is_lag_master(upper_dev) &&
  4149. !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
  4150. info->upper_info, extack))
  4151. return -EINVAL;
  4152. if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
  4153. NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
  4154. return -EINVAL;
  4155. }
  4156. if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
  4157. !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
  4158. NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
  4159. return -EINVAL;
  4160. }
  4161. if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
  4162. NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
  4163. return -EINVAL;
  4164. }
  4165. if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
  4166. NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
  4167. return -EINVAL;
  4168. }
  4169. if (netif_is_bridge_master(upper_dev)) {
  4170. br_vlan_get_proto(upper_dev, &proto);
  4171. if (br_vlan_enabled(upper_dev) &&
  4172. proto != ETH_P_8021Q && proto != ETH_P_8021AD) {
  4173. NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a bridge with unknown VLAN protocol is not supported");
  4174. return -EOPNOTSUPP;
  4175. }
  4176. if (vlan_uses_dev(lower_dev) &&
  4177. br_vlan_enabled(upper_dev) &&
  4178. proto == ETH_P_8021AD) {
  4179. NL_SET_ERR_MSG_MOD(extack, "Enslaving a port that already has a VLAN upper to an 802.1ad bridge is not supported");
  4180. return -EOPNOTSUPP;
  4181. }
  4182. }
  4183. if (netif_is_bridge_port(lower_dev) && is_vlan_dev(upper_dev)) {
  4184. struct net_device *br_dev = netdev_master_upper_dev_get(lower_dev);
  4185. if (br_vlan_enabled(br_dev)) {
  4186. br_vlan_get_proto(br_dev, &proto);
  4187. if (proto == ETH_P_8021AD) {
  4188. NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a port enslaved to an 802.1ad bridge");
  4189. return -EOPNOTSUPP;
  4190. }
  4191. }
  4192. }
  4193. if (is_vlan_dev(upper_dev) &&
  4194. ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) {
  4195. NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol");
  4196. return -EOPNOTSUPP;
  4197. }
  4198. if (is_vlan_dev(upper_dev) && mlxsw_sp_port->security) {
  4199. NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a locked port");
  4200. return -EOPNOTSUPP;
  4201. }
  4202. break;
  4203. case NETDEV_CHANGEUPPER:
  4204. upper_dev = info->upper_dev;
  4205. if (netif_is_bridge_master(upper_dev)) {
  4206. if (info->linking) {
  4207. err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
  4208. lower_dev,
  4209. upper_dev,
  4210. extack);
  4211. } else {
  4212. mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
  4213. lower_dev,
  4214. upper_dev);
  4215. if (!replay_deslavement)
  4216. break;
  4217. mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp,
  4218. lower_dev);
  4219. }
  4220. } else if (netif_is_lag_master(upper_dev)) {
  4221. if (info->linking) {
  4222. err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
  4223. upper_dev, extack);
  4224. } else {
  4225. mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
  4226. mlxsw_sp_port_lag_leave(mlxsw_sp_port,
  4227. upper_dev);
  4228. mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp,
  4229. dev);
  4230. }
  4231. } else if (netif_is_ovs_master(upper_dev)) {
  4232. if (info->linking)
  4233. err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
  4234. else
  4235. mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
  4236. } else if (netif_is_macvlan(upper_dev)) {
  4237. if (!info->linking)
  4238. mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
  4239. } else if (is_vlan_dev(upper_dev)) {
  4240. struct net_device *br_dev;
  4241. if (!netif_is_bridge_port(upper_dev))
  4242. break;
  4243. if (info->linking)
  4244. break;
  4245. br_dev = netdev_master_upper_dev_get(upper_dev);
  4246. mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
  4247. br_dev);
  4248. }
  4249. break;
  4250. }
  4251. return err;
  4252. }
  4253. static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
  4254. unsigned long event, void *ptr)
  4255. {
  4256. struct netdev_notifier_changelowerstate_info *info;
  4257. struct mlxsw_sp_port *mlxsw_sp_port;
  4258. int err;
  4259. mlxsw_sp_port = netdev_priv(dev);
  4260. info = ptr;
  4261. switch (event) {
  4262. case NETDEV_CHANGELOWERSTATE:
  4263. if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
  4264. err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
  4265. info->lower_state_info);
  4266. if (err)
  4267. netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
  4268. }
  4269. break;
  4270. }
  4271. return 0;
  4272. }
  4273. static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
  4274. struct net_device *port_dev,
  4275. unsigned long event, void *ptr,
  4276. bool replay_deslavement)
  4277. {
  4278. switch (event) {
  4279. case NETDEV_PRECHANGEUPPER:
  4280. case NETDEV_CHANGEUPPER:
  4281. return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
  4282. event, ptr,
  4283. replay_deslavement);
  4284. case NETDEV_CHANGELOWERSTATE:
  4285. return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
  4286. ptr);
  4287. }
  4288. return 0;
  4289. }
  4290. /* Called for LAG or its upper VLAN after the per-LAG-lower processing was done,
  4291. * to do any per-LAG / per-LAG-upper processing.
  4292. */
  4293. static int mlxsw_sp_netdevice_post_lag_event(struct net_device *dev,
  4294. unsigned long event,
  4295. void *ptr)
  4296. {
  4297. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(dev);
  4298. struct netdev_notifier_changeupper_info *info = ptr;
  4299. if (!mlxsw_sp)
  4300. return 0;
  4301. switch (event) {
  4302. case NETDEV_CHANGEUPPER:
  4303. if (info->linking)
  4304. break;
  4305. if (netif_is_bridge_master(info->upper_dev))
  4306. mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, dev);
  4307. break;
  4308. }
  4309. return 0;
  4310. }
  4311. static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
  4312. unsigned long event, void *ptr)
  4313. {
  4314. struct net_device *dev;
  4315. struct list_head *iter;
  4316. int ret;
  4317. netdev_for_each_lower_dev(lag_dev, dev, iter) {
  4318. if (mlxsw_sp_port_dev_check(dev)) {
  4319. ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
  4320. ptr, false);
  4321. if (ret)
  4322. return ret;
  4323. }
  4324. }
  4325. return mlxsw_sp_netdevice_post_lag_event(lag_dev, event, ptr);
  4326. }
  4327. static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
  4328. struct net_device *dev,
  4329. unsigned long event, void *ptr,
  4330. u16 vid, bool replay_deslavement)
  4331. {
  4332. struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
  4333. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  4334. struct netdev_notifier_changeupper_info *info = ptr;
  4335. struct netlink_ext_ack *extack;
  4336. struct net_device *upper_dev;
  4337. int err = 0;
  4338. extack = netdev_notifier_info_to_extack(&info->info);
  4339. switch (event) {
  4340. case NETDEV_PRECHANGEUPPER:
  4341. upper_dev = info->upper_dev;
  4342. if (!netif_is_bridge_master(upper_dev) &&
  4343. !netif_is_macvlan(upper_dev) &&
  4344. !netif_is_l3_master(upper_dev)) {
  4345. NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
  4346. return -EINVAL;
  4347. }
  4348. if (!info->linking)
  4349. break;
  4350. if (netif_is_bridge_master(upper_dev) &&
  4351. !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
  4352. mlxsw_sp_bridge_has_vxlan(upper_dev) &&
  4353. !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
  4354. return -EOPNOTSUPP;
  4355. if (netdev_has_any_upper_dev(upper_dev) &&
  4356. (!netif_is_bridge_master(upper_dev) ||
  4357. !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
  4358. upper_dev))) {
  4359. err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp,
  4360. upper_dev,
  4361. extack);
  4362. if (err)
  4363. return err;
  4364. }
  4365. break;
  4366. case NETDEV_CHANGEUPPER:
  4367. upper_dev = info->upper_dev;
  4368. if (netif_is_bridge_master(upper_dev)) {
  4369. if (info->linking) {
  4370. err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
  4371. vlan_dev,
  4372. upper_dev,
  4373. extack);
  4374. } else {
  4375. mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
  4376. vlan_dev,
  4377. upper_dev);
  4378. if (!replay_deslavement)
  4379. break;
  4380. mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp,
  4381. vlan_dev);
  4382. }
  4383. } else if (netif_is_macvlan(upper_dev)) {
  4384. if (!info->linking)
  4385. mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
  4386. }
  4387. break;
  4388. }
  4389. return err;
  4390. }
  4391. static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
  4392. struct net_device *lag_dev,
  4393. unsigned long event,
  4394. void *ptr, u16 vid)
  4395. {
  4396. struct net_device *dev;
  4397. struct list_head *iter;
  4398. int ret;
  4399. netdev_for_each_lower_dev(lag_dev, dev, iter) {
  4400. if (mlxsw_sp_port_dev_check(dev)) {
  4401. ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
  4402. event, ptr,
  4403. vid, false);
  4404. if (ret)
  4405. return ret;
  4406. }
  4407. }
  4408. return mlxsw_sp_netdevice_post_lag_event(vlan_dev, event, ptr);
  4409. }
  4410. static int mlxsw_sp_netdevice_bridge_vlan_event(struct mlxsw_sp *mlxsw_sp,
  4411. struct net_device *vlan_dev,
  4412. struct net_device *br_dev,
  4413. unsigned long event, void *ptr,
  4414. u16 vid, bool process_foreign)
  4415. {
  4416. struct netdev_notifier_changeupper_info *info = ptr;
  4417. struct netlink_ext_ack *extack;
  4418. struct net_device *upper_dev;
  4419. if (!process_foreign && !mlxsw_sp_lower_get(vlan_dev))
  4420. return 0;
  4421. extack = netdev_notifier_info_to_extack(&info->info);
  4422. switch (event) {
  4423. case NETDEV_PRECHANGEUPPER:
  4424. upper_dev = info->upper_dev;
  4425. if (!netif_is_macvlan(upper_dev) &&
  4426. !netif_is_l3_master(upper_dev)) {
  4427. NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
  4428. return -EOPNOTSUPP;
  4429. }
  4430. break;
  4431. case NETDEV_CHANGEUPPER:
  4432. upper_dev = info->upper_dev;
  4433. if (info->linking)
  4434. break;
  4435. if (netif_is_macvlan(upper_dev))
  4436. mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
  4437. break;
  4438. }
  4439. return 0;
  4440. }
  4441. static int mlxsw_sp_netdevice_vlan_event(struct mlxsw_sp *mlxsw_sp,
  4442. struct net_device *vlan_dev,
  4443. unsigned long event, void *ptr,
  4444. bool process_foreign)
  4445. {
  4446. struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
  4447. u16 vid = vlan_dev_vlan_id(vlan_dev);
  4448. if (mlxsw_sp_port_dev_check(real_dev))
  4449. return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
  4450. event, ptr, vid,
  4451. true);
  4452. else if (netif_is_lag_master(real_dev))
  4453. return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
  4454. real_dev, event,
  4455. ptr, vid);
  4456. else if (netif_is_bridge_master(real_dev))
  4457. return mlxsw_sp_netdevice_bridge_vlan_event(mlxsw_sp, vlan_dev,
  4458. real_dev, event,
  4459. ptr, vid,
  4460. process_foreign);
  4461. return 0;
  4462. }
  4463. static int mlxsw_sp_netdevice_bridge_event(struct mlxsw_sp *mlxsw_sp,
  4464. struct net_device *br_dev,
  4465. unsigned long event, void *ptr,
  4466. bool process_foreign)
  4467. {
  4468. struct netdev_notifier_changeupper_info *info = ptr;
  4469. struct netlink_ext_ack *extack;
  4470. struct net_device *upper_dev;
  4471. u16 proto;
  4472. if (!process_foreign && !mlxsw_sp_lower_get(br_dev))
  4473. return 0;
  4474. extack = netdev_notifier_info_to_extack(&info->info);
  4475. switch (event) {
  4476. case NETDEV_PRECHANGEUPPER:
  4477. upper_dev = info->upper_dev;
  4478. if (!is_vlan_dev(upper_dev) &&
  4479. !netif_is_macvlan(upper_dev) &&
  4480. !netif_is_l3_master(upper_dev)) {
  4481. NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
  4482. return -EOPNOTSUPP;
  4483. }
  4484. if (!info->linking)
  4485. break;
  4486. if (br_vlan_enabled(br_dev)) {
  4487. br_vlan_get_proto(br_dev, &proto);
  4488. if (proto == ETH_P_8021AD) {
  4489. NL_SET_ERR_MSG_MOD(extack, "Upper devices are not supported on top of an 802.1ad bridge");
  4490. return -EOPNOTSUPP;
  4491. }
  4492. }
  4493. if (is_vlan_dev(upper_dev) &&
  4494. ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) {
  4495. NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol");
  4496. return -EOPNOTSUPP;
  4497. }
  4498. break;
  4499. case NETDEV_CHANGEUPPER:
  4500. upper_dev = info->upper_dev;
  4501. if (info->linking)
  4502. break;
  4503. if (is_vlan_dev(upper_dev))
  4504. mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
  4505. if (netif_is_macvlan(upper_dev))
  4506. mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
  4507. break;
  4508. }
  4509. return 0;
  4510. }
  4511. static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
  4512. unsigned long event, void *ptr)
  4513. {
  4514. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
  4515. struct netdev_notifier_changeupper_info *info = ptr;
  4516. struct netlink_ext_ack *extack;
  4517. struct net_device *upper_dev;
  4518. if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
  4519. return 0;
  4520. extack = netdev_notifier_info_to_extack(&info->info);
  4521. upper_dev = info->upper_dev;
  4522. if (!netif_is_l3_master(upper_dev)) {
  4523. NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
  4524. return -EOPNOTSUPP;
  4525. }
  4526. return 0;
  4527. }
  4528. static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
  4529. struct net_device *dev,
  4530. unsigned long event, void *ptr)
  4531. {
  4532. struct netdev_notifier_changeupper_info *cu_info;
  4533. struct netdev_notifier_info *info = ptr;
  4534. struct netlink_ext_ack *extack;
  4535. struct net_device *upper_dev;
  4536. extack = netdev_notifier_info_to_extack(info);
  4537. switch (event) {
  4538. case NETDEV_CHANGEUPPER:
  4539. cu_info = container_of(info,
  4540. struct netdev_notifier_changeupper_info,
  4541. info);
  4542. upper_dev = cu_info->upper_dev;
  4543. if (!netif_is_bridge_master(upper_dev))
  4544. return 0;
  4545. if (!mlxsw_sp_lower_get(upper_dev))
  4546. return 0;
  4547. if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
  4548. return -EOPNOTSUPP;
  4549. if (cu_info->linking) {
  4550. if (!netif_running(dev))
  4551. return 0;
  4552. /* When the bridge is VLAN-aware, the VNI of the VxLAN
  4553. * device needs to be mapped to a VLAN, but at this
  4554. * point no VLANs are configured on the VxLAN device
  4555. */
  4556. if (br_vlan_enabled(upper_dev))
  4557. return 0;
  4558. return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
  4559. dev, 0, extack);
  4560. } else {
  4561. /* VLANs were already flushed, which triggered the
  4562. * necessary cleanup
  4563. */
  4564. if (br_vlan_enabled(upper_dev))
  4565. return 0;
  4566. mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
  4567. }
  4568. break;
  4569. case NETDEV_PRE_UP:
  4570. upper_dev = netdev_master_upper_dev_get(dev);
  4571. if (!upper_dev)
  4572. return 0;
  4573. if (!netif_is_bridge_master(upper_dev))
  4574. return 0;
  4575. if (!mlxsw_sp_lower_get(upper_dev))
  4576. return 0;
  4577. return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
  4578. extack);
  4579. case NETDEV_DOWN:
  4580. upper_dev = netdev_master_upper_dev_get(dev);
  4581. if (!upper_dev)
  4582. return 0;
  4583. if (!netif_is_bridge_master(upper_dev))
  4584. return 0;
  4585. if (!mlxsw_sp_lower_get(upper_dev))
  4586. return 0;
  4587. mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
  4588. break;
  4589. }
  4590. return 0;
  4591. }
  4592. static int __mlxsw_sp_netdevice_event(struct mlxsw_sp *mlxsw_sp,
  4593. unsigned long event, void *ptr,
  4594. bool process_foreign)
  4595. {
  4596. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  4597. struct mlxsw_sp_span_entry *span_entry;
  4598. int err = 0;
  4599. if (event == NETDEV_UNREGISTER) {
  4600. span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
  4601. if (span_entry)
  4602. mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
  4603. }
  4604. if (netif_is_vxlan(dev))
  4605. err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
  4606. else if (mlxsw_sp_port_dev_check(dev))
  4607. err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr, true);
  4608. else if (netif_is_lag_master(dev))
  4609. err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
  4610. else if (is_vlan_dev(dev))
  4611. err = mlxsw_sp_netdevice_vlan_event(mlxsw_sp, dev, event, ptr,
  4612. process_foreign);
  4613. else if (netif_is_bridge_master(dev))
  4614. err = mlxsw_sp_netdevice_bridge_event(mlxsw_sp, dev, event, ptr,
  4615. process_foreign);
  4616. else if (netif_is_macvlan(dev))
  4617. err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
  4618. return err;
  4619. }
  4620. static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
  4621. unsigned long event, void *ptr)
  4622. {
  4623. struct mlxsw_sp *mlxsw_sp;
  4624. int err;
  4625. mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
  4626. mlxsw_sp_span_respin(mlxsw_sp);
  4627. err = __mlxsw_sp_netdevice_event(mlxsw_sp, event, ptr, false);
  4628. return notifier_from_errno(err);
  4629. }
  4630. static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
  4631. {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
  4632. {0, },
  4633. };
  4634. static struct pci_driver mlxsw_sp1_pci_driver = {
  4635. .name = mlxsw_sp1_driver_name,
  4636. .id_table = mlxsw_sp1_pci_id_table,
  4637. };
  4638. static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
  4639. {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
  4640. {0, },
  4641. };
  4642. static struct pci_driver mlxsw_sp2_pci_driver = {
  4643. .name = mlxsw_sp2_driver_name,
  4644. .id_table = mlxsw_sp2_pci_id_table,
  4645. };
  4646. static const struct pci_device_id mlxsw_sp3_pci_id_table[] = {
  4647. {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0},
  4648. {0, },
  4649. };
  4650. static struct pci_driver mlxsw_sp3_pci_driver = {
  4651. .name = mlxsw_sp3_driver_name,
  4652. .id_table = mlxsw_sp3_pci_id_table,
  4653. };
  4654. static const struct pci_device_id mlxsw_sp4_pci_id_table[] = {
  4655. {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM4), 0},
  4656. {0, },
  4657. };
  4658. static struct pci_driver mlxsw_sp4_pci_driver = {
  4659. .name = mlxsw_sp4_driver_name,
  4660. .id_table = mlxsw_sp4_pci_id_table,
  4661. };
  4662. static int __init mlxsw_sp_module_init(void)
  4663. {
  4664. int err;
  4665. err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
  4666. if (err)
  4667. return err;
  4668. err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
  4669. if (err)
  4670. goto err_sp2_core_driver_register;
  4671. err = mlxsw_core_driver_register(&mlxsw_sp3_driver);
  4672. if (err)
  4673. goto err_sp3_core_driver_register;
  4674. err = mlxsw_core_driver_register(&mlxsw_sp4_driver);
  4675. if (err)
  4676. goto err_sp4_core_driver_register;
  4677. err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
  4678. if (err)
  4679. goto err_sp1_pci_driver_register;
  4680. err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
  4681. if (err)
  4682. goto err_sp2_pci_driver_register;
  4683. err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver);
  4684. if (err)
  4685. goto err_sp3_pci_driver_register;
  4686. err = mlxsw_pci_driver_register(&mlxsw_sp4_pci_driver);
  4687. if (err)
  4688. goto err_sp4_pci_driver_register;
  4689. return 0;
  4690. err_sp4_pci_driver_register:
  4691. mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
  4692. err_sp3_pci_driver_register:
  4693. mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
  4694. err_sp2_pci_driver_register:
  4695. mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
  4696. err_sp1_pci_driver_register:
  4697. mlxsw_core_driver_unregister(&mlxsw_sp4_driver);
  4698. err_sp4_core_driver_register:
  4699. mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
  4700. err_sp3_core_driver_register:
  4701. mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
  4702. err_sp2_core_driver_register:
  4703. mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
  4704. return err;
  4705. }
  4706. static void __exit mlxsw_sp_module_exit(void)
  4707. {
  4708. mlxsw_pci_driver_unregister(&mlxsw_sp4_pci_driver);
  4709. mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
  4710. mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
  4711. mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
  4712. mlxsw_core_driver_unregister(&mlxsw_sp4_driver);
  4713. mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
  4714. mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
  4715. mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
  4716. }
  4717. module_init(mlxsw_sp_module_init);
  4718. module_exit(mlxsw_sp_module_exit);
  4719. MODULE_LICENSE("Dual BSD/GPL");
  4720. MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
  4721. MODULE_DESCRIPTION("Mellanox Spectrum driver");
  4722. MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
  4723. MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
  4724. MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table);
  4725. MODULE_DEVICE_TABLE(pci, mlxsw_sp4_pci_id_table);
  4726. MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);
  4727. MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME);
  4728. MODULE_FIRMWARE(MLXSW_SP3_FW_FILENAME);
  4729. MODULE_FIRMWARE(MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME);