lan743x_main.c 110 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /* Copyright (C) 2018 Microchip Technology Inc. */
  3. #include <linux/module.h>
  4. #include <linux/pci.h>
  5. #include <linux/netdevice.h>
  6. #include <linux/etherdevice.h>
  7. #include <linux/crc32.h>
  8. #include <linux/microchipphy.h>
  9. #include <linux/net_tstamp.h>
  10. #include <linux/of_mdio.h>
  11. #include <linux/of_net.h>
  12. #include <linux/phy.h>
  13. #include <linux/phy_fixed.h>
  14. #include <linux/rtnetlink.h>
  15. #include <linux/iopoll.h>
  16. #include <linux/crc16.h>
  17. #include <linux/phylink.h>
  18. #include "lan743x_main.h"
  19. #include "lan743x_ethtool.h"
  20. #define MMD_ACCESS_ADDRESS 0
  21. #define MMD_ACCESS_WRITE 1
  22. #define MMD_ACCESS_READ 2
  23. #define MMD_ACCESS_READ_INC 3
  24. #define PCS_POWER_STATE_DOWN 0x6
  25. #define PCS_POWER_STATE_UP 0x4
  26. #define RFE_RD_FIFO_TH_3_DWORDS 0x3
  27. static void pci11x1x_strap_get_status(struct lan743x_adapter *adapter)
  28. {
  29. u32 chip_rev;
  30. u32 cfg_load;
  31. u32 hw_cfg;
  32. u32 strap;
  33. int ret;
  34. /* Timeout = 100 (i.e. 1 sec (10 msce * 100)) */
  35. ret = lan743x_hs_syslock_acquire(adapter, 100);
  36. if (ret < 0) {
  37. netif_err(adapter, drv, adapter->netdev,
  38. "Sys Lock acquire failed ret:%d\n", ret);
  39. return;
  40. }
  41. cfg_load = lan743x_csr_read(adapter, ETH_SYS_CONFIG_LOAD_STARTED_REG);
  42. lan743x_hs_syslock_release(adapter);
  43. hw_cfg = lan743x_csr_read(adapter, HW_CFG);
  44. if (cfg_load & GEN_SYS_LOAD_STARTED_REG_ETH_ ||
  45. hw_cfg & HW_CFG_RST_PROTECT_) {
  46. strap = lan743x_csr_read(adapter, STRAP_READ);
  47. if (strap & STRAP_READ_SGMII_EN_)
  48. adapter->is_sgmii_en = true;
  49. else
  50. adapter->is_sgmii_en = false;
  51. } else {
  52. chip_rev = lan743x_csr_read(adapter, FPGA_REV);
  53. if (chip_rev) {
  54. if (chip_rev & FPGA_SGMII_OP)
  55. adapter->is_sgmii_en = true;
  56. else
  57. adapter->is_sgmii_en = false;
  58. } else {
  59. adapter->is_sgmii_en = false;
  60. }
  61. }
  62. netif_dbg(adapter, drv, adapter->netdev,
  63. "SGMII I/F %sable\n", adapter->is_sgmii_en ? "En" : "Dis");
  64. }
  65. static bool is_pci11x1x_chip(struct lan743x_adapter *adapter)
  66. {
  67. struct lan743x_csr *csr = &adapter->csr;
  68. u32 id_rev = csr->id_rev;
  69. if (((id_rev & 0xFFFF0000) == ID_REV_ID_A011_) ||
  70. ((id_rev & 0xFFFF0000) == ID_REV_ID_A041_)) {
  71. return true;
  72. }
  73. return false;
  74. }
  75. static void lan743x_pci_cleanup(struct lan743x_adapter *adapter)
  76. {
  77. pci_release_selected_regions(adapter->pdev,
  78. pci_select_bars(adapter->pdev,
  79. IORESOURCE_MEM));
  80. pci_disable_device(adapter->pdev);
  81. }
  82. static int lan743x_pci_init(struct lan743x_adapter *adapter,
  83. struct pci_dev *pdev)
  84. {
  85. unsigned long bars = 0;
  86. int ret;
  87. adapter->pdev = pdev;
  88. ret = pci_enable_device_mem(pdev);
  89. if (ret)
  90. goto return_error;
  91. netif_info(adapter, probe, adapter->netdev,
  92. "PCI: Vendor ID = 0x%04X, Device ID = 0x%04X\n",
  93. pdev->vendor, pdev->device);
  94. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  95. if (!test_bit(0, &bars))
  96. goto disable_device;
  97. ret = pci_request_selected_regions(pdev, bars, DRIVER_NAME);
  98. if (ret)
  99. goto disable_device;
  100. pci_set_master(pdev);
  101. return 0;
  102. disable_device:
  103. pci_disable_device(adapter->pdev);
  104. return_error:
  105. return ret;
  106. }
  107. u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset)
  108. {
  109. return ioread32(&adapter->csr.csr_address[offset]);
  110. }
  111. void lan743x_csr_write(struct lan743x_adapter *adapter, int offset,
  112. u32 data)
  113. {
  114. iowrite32(data, &adapter->csr.csr_address[offset]);
  115. }
  116. #define LAN743X_CSR_READ_OP(offset) lan743x_csr_read(adapter, offset)
  117. static int lan743x_csr_light_reset(struct lan743x_adapter *adapter)
  118. {
  119. u32 data;
  120. data = lan743x_csr_read(adapter, HW_CFG);
  121. data |= HW_CFG_LRST_;
  122. lan743x_csr_write(adapter, HW_CFG, data);
  123. return readx_poll_timeout(LAN743X_CSR_READ_OP, HW_CFG, data,
  124. !(data & HW_CFG_LRST_), 100000, 10000000);
  125. }
  126. static int lan743x_csr_wait_for_bit_atomic(struct lan743x_adapter *adapter,
  127. int offset, u32 bit_mask,
  128. int target_value, int udelay_min,
  129. int udelay_max, int count)
  130. {
  131. u32 data;
  132. return readx_poll_timeout_atomic(LAN743X_CSR_READ_OP, offset, data,
  133. target_value == !!(data & bit_mask),
  134. udelay_max, udelay_min * count);
  135. }
  136. static int lan743x_csr_wait_for_bit(struct lan743x_adapter *adapter,
  137. int offset, u32 bit_mask,
  138. int target_value, int usleep_min,
  139. int usleep_max, int count)
  140. {
  141. u32 data;
  142. return readx_poll_timeout(LAN743X_CSR_READ_OP, offset, data,
  143. target_value == !!(data & bit_mask),
  144. usleep_max, usleep_min * count);
  145. }
  146. static int lan743x_csr_init(struct lan743x_adapter *adapter)
  147. {
  148. struct lan743x_csr *csr = &adapter->csr;
  149. resource_size_t bar_start, bar_length;
  150. bar_start = pci_resource_start(adapter->pdev, 0);
  151. bar_length = pci_resource_len(adapter->pdev, 0);
  152. csr->csr_address = devm_ioremap(&adapter->pdev->dev,
  153. bar_start, bar_length);
  154. if (!csr->csr_address)
  155. return -ENOMEM;
  156. csr->id_rev = lan743x_csr_read(adapter, ID_REV);
  157. csr->fpga_rev = lan743x_csr_read(adapter, FPGA_REV);
  158. netif_info(adapter, probe, adapter->netdev,
  159. "ID_REV = 0x%08X, FPGA_REV = %d.%d\n",
  160. csr->id_rev, FPGA_REV_GET_MAJOR_(csr->fpga_rev),
  161. FPGA_REV_GET_MINOR_(csr->fpga_rev));
  162. if (!ID_REV_IS_VALID_CHIP_ID_(csr->id_rev))
  163. return -ENODEV;
  164. csr->flags = LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR;
  165. switch (csr->id_rev & ID_REV_CHIP_REV_MASK_) {
  166. case ID_REV_CHIP_REV_A0_:
  167. csr->flags |= LAN743X_CSR_FLAG_IS_A0;
  168. csr->flags &= ~LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR;
  169. break;
  170. case ID_REV_CHIP_REV_B0_:
  171. csr->flags |= LAN743X_CSR_FLAG_IS_B0;
  172. break;
  173. }
  174. return lan743x_csr_light_reset(adapter);
  175. }
  176. static void lan743x_intr_software_isr(struct lan743x_adapter *adapter)
  177. {
  178. struct lan743x_intr *intr = &adapter->intr;
  179. /* disable the interrupt to prevent repeated re-triggering */
  180. lan743x_csr_write(adapter, INT_EN_CLR, INT_BIT_SW_GP_);
  181. intr->software_isr_flag = true;
  182. wake_up(&intr->software_isr_wq);
  183. }
  184. static void lan743x_tx_isr(void *context, u32 int_sts, u32 flags)
  185. {
  186. struct lan743x_tx *tx = context;
  187. struct lan743x_adapter *adapter = tx->adapter;
  188. bool enable_flag = true;
  189. lan743x_csr_read(adapter, INT_EN_SET);
  190. if (flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR) {
  191. lan743x_csr_write(adapter, INT_EN_CLR,
  192. INT_BIT_DMA_TX_(tx->channel_number));
  193. }
  194. if (int_sts & INT_BIT_DMA_TX_(tx->channel_number)) {
  195. u32 ioc_bit = DMAC_INT_BIT_TX_IOC_(tx->channel_number);
  196. u32 dmac_int_sts;
  197. u32 dmac_int_en;
  198. if (flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ)
  199. dmac_int_sts = lan743x_csr_read(adapter, DMAC_INT_STS);
  200. else
  201. dmac_int_sts = ioc_bit;
  202. if (flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK)
  203. dmac_int_en = lan743x_csr_read(adapter,
  204. DMAC_INT_EN_SET);
  205. else
  206. dmac_int_en = ioc_bit;
  207. dmac_int_en &= ioc_bit;
  208. dmac_int_sts &= dmac_int_en;
  209. if (dmac_int_sts & ioc_bit) {
  210. napi_schedule(&tx->napi);
  211. enable_flag = false;/* poll func will enable later */
  212. }
  213. }
  214. if (enable_flag)
  215. /* enable isr */
  216. lan743x_csr_write(adapter, INT_EN_SET,
  217. INT_BIT_DMA_TX_(tx->channel_number));
  218. }
  219. static void lan743x_rx_isr(void *context, u32 int_sts, u32 flags)
  220. {
  221. struct lan743x_rx *rx = context;
  222. struct lan743x_adapter *adapter = rx->adapter;
  223. bool enable_flag = true;
  224. if (flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR) {
  225. lan743x_csr_write(adapter, INT_EN_CLR,
  226. INT_BIT_DMA_RX_(rx->channel_number));
  227. }
  228. if (int_sts & INT_BIT_DMA_RX_(rx->channel_number)) {
  229. u32 rx_frame_bit = DMAC_INT_BIT_RXFRM_(rx->channel_number);
  230. u32 dmac_int_sts;
  231. u32 dmac_int_en;
  232. if (flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ)
  233. dmac_int_sts = lan743x_csr_read(adapter, DMAC_INT_STS);
  234. else
  235. dmac_int_sts = rx_frame_bit;
  236. if (flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK)
  237. dmac_int_en = lan743x_csr_read(adapter,
  238. DMAC_INT_EN_SET);
  239. else
  240. dmac_int_en = rx_frame_bit;
  241. dmac_int_en &= rx_frame_bit;
  242. dmac_int_sts &= dmac_int_en;
  243. if (dmac_int_sts & rx_frame_bit) {
  244. napi_schedule(&rx->napi);
  245. enable_flag = false;/* poll funct will enable later */
  246. }
  247. }
  248. if (enable_flag) {
  249. /* enable isr */
  250. lan743x_csr_write(adapter, INT_EN_SET,
  251. INT_BIT_DMA_RX_(rx->channel_number));
  252. }
  253. }
  254. static void lan743x_intr_shared_isr(void *context, u32 int_sts, u32 flags)
  255. {
  256. struct lan743x_adapter *adapter = context;
  257. unsigned int channel;
  258. if (int_sts & INT_BIT_ALL_RX_) {
  259. for (channel = 0; channel < LAN743X_USED_RX_CHANNELS;
  260. channel++) {
  261. u32 int_bit = INT_BIT_DMA_RX_(channel);
  262. if (int_sts & int_bit) {
  263. lan743x_rx_isr(&adapter->rx[channel],
  264. int_bit, flags);
  265. int_sts &= ~int_bit;
  266. }
  267. }
  268. }
  269. if (int_sts & INT_BIT_ALL_TX_) {
  270. for (channel = 0; channel < adapter->used_tx_channels;
  271. channel++) {
  272. u32 int_bit = INT_BIT_DMA_TX_(channel);
  273. if (int_sts & int_bit) {
  274. lan743x_tx_isr(&adapter->tx[channel],
  275. int_bit, flags);
  276. int_sts &= ~int_bit;
  277. }
  278. }
  279. }
  280. if (int_sts & INT_BIT_ALL_OTHER_) {
  281. if (int_sts & INT_BIT_SW_GP_) {
  282. lan743x_intr_software_isr(adapter);
  283. int_sts &= ~INT_BIT_SW_GP_;
  284. }
  285. if (int_sts & INT_BIT_1588_) {
  286. lan743x_ptp_isr(adapter);
  287. int_sts &= ~INT_BIT_1588_;
  288. }
  289. }
  290. if (int_sts)
  291. lan743x_csr_write(adapter, INT_EN_CLR, int_sts);
  292. }
  293. static irqreturn_t lan743x_intr_entry_isr(int irq, void *ptr)
  294. {
  295. struct lan743x_vector *vector = ptr;
  296. struct lan743x_adapter *adapter = vector->adapter;
  297. irqreturn_t result = IRQ_NONE;
  298. u32 int_enables;
  299. u32 int_sts;
  300. if (vector->flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ) {
  301. int_sts = lan743x_csr_read(adapter, INT_STS);
  302. } else if (vector->flags &
  303. (LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C |
  304. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C)) {
  305. int_sts = lan743x_csr_read(adapter, INT_STS_R2C);
  306. } else {
  307. /* use mask as implied status */
  308. int_sts = vector->int_mask | INT_BIT_MAS_;
  309. }
  310. if (!(int_sts & INT_BIT_MAS_))
  311. goto irq_done;
  312. if (vector->flags & LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR)
  313. /* disable vector interrupt */
  314. lan743x_csr_write(adapter,
  315. INT_VEC_EN_CLR,
  316. INT_VEC_EN_(vector->vector_index));
  317. if (vector->flags & LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR)
  318. /* disable master interrupt */
  319. lan743x_csr_write(adapter, INT_EN_CLR, INT_BIT_MAS_);
  320. if (vector->flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK) {
  321. int_enables = lan743x_csr_read(adapter, INT_EN_SET);
  322. } else {
  323. /* use vector mask as implied enable mask */
  324. int_enables = vector->int_mask;
  325. }
  326. int_sts &= int_enables;
  327. int_sts &= vector->int_mask;
  328. if (int_sts) {
  329. if (vector->handler) {
  330. vector->handler(vector->context,
  331. int_sts, vector->flags);
  332. } else {
  333. /* disable interrupts on this vector */
  334. lan743x_csr_write(adapter, INT_EN_CLR,
  335. vector->int_mask);
  336. }
  337. result = IRQ_HANDLED;
  338. }
  339. if (vector->flags & LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET)
  340. /* enable master interrupt */
  341. lan743x_csr_write(adapter, INT_EN_SET, INT_BIT_MAS_);
  342. if (vector->flags & LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET)
  343. /* enable vector interrupt */
  344. lan743x_csr_write(adapter,
  345. INT_VEC_EN_SET,
  346. INT_VEC_EN_(vector->vector_index));
  347. irq_done:
  348. return result;
  349. }
  350. static int lan743x_intr_test_isr(struct lan743x_adapter *adapter)
  351. {
  352. struct lan743x_intr *intr = &adapter->intr;
  353. int ret;
  354. intr->software_isr_flag = false;
  355. /* enable and activate test interrupt */
  356. lan743x_csr_write(adapter, INT_EN_SET, INT_BIT_SW_GP_);
  357. lan743x_csr_write(adapter, INT_SET, INT_BIT_SW_GP_);
  358. ret = wait_event_timeout(intr->software_isr_wq,
  359. intr->software_isr_flag,
  360. msecs_to_jiffies(200));
  361. /* disable test interrupt */
  362. lan743x_csr_write(adapter, INT_EN_CLR, INT_BIT_SW_GP_);
  363. return ret > 0 ? 0 : -ENODEV;
  364. }
  365. static int lan743x_intr_register_isr(struct lan743x_adapter *adapter,
  366. int vector_index, u32 flags,
  367. u32 int_mask,
  368. lan743x_vector_handler handler,
  369. void *context)
  370. {
  371. struct lan743x_vector *vector = &adapter->intr.vector_list
  372. [vector_index];
  373. int ret;
  374. vector->adapter = adapter;
  375. vector->flags = flags;
  376. vector->vector_index = vector_index;
  377. vector->int_mask = int_mask;
  378. vector->handler = handler;
  379. vector->context = context;
  380. ret = request_irq(vector->irq,
  381. lan743x_intr_entry_isr,
  382. (flags & LAN743X_VECTOR_FLAG_IRQ_SHARED) ?
  383. IRQF_SHARED : 0, DRIVER_NAME, vector);
  384. if (ret) {
  385. vector->handler = NULL;
  386. vector->context = NULL;
  387. vector->int_mask = 0;
  388. vector->flags = 0;
  389. }
  390. return ret;
  391. }
  392. static void lan743x_intr_unregister_isr(struct lan743x_adapter *adapter,
  393. int vector_index)
  394. {
  395. struct lan743x_vector *vector = &adapter->intr.vector_list
  396. [vector_index];
  397. free_irq(vector->irq, vector);
  398. vector->handler = NULL;
  399. vector->context = NULL;
  400. vector->int_mask = 0;
  401. vector->flags = 0;
  402. }
  403. static u32 lan743x_intr_get_vector_flags(struct lan743x_adapter *adapter,
  404. u32 int_mask)
  405. {
  406. int index;
  407. for (index = 0; index < adapter->max_vector_count; index++) {
  408. if (adapter->intr.vector_list[index].int_mask & int_mask)
  409. return adapter->intr.vector_list[index].flags;
  410. }
  411. return 0;
  412. }
  413. static void lan743x_intr_close(struct lan743x_adapter *adapter)
  414. {
  415. struct lan743x_intr *intr = &adapter->intr;
  416. int index = 0;
  417. lan743x_csr_write(adapter, INT_EN_CLR, INT_BIT_MAS_);
  418. if (adapter->is_pci11x1x)
  419. lan743x_csr_write(adapter, INT_VEC_EN_CLR, 0x0000FFFF);
  420. else
  421. lan743x_csr_write(adapter, INT_VEC_EN_CLR, 0x000000FF);
  422. for (index = 0; index < intr->number_of_vectors; index++) {
  423. if (intr->flags & INTR_FLAG_IRQ_REQUESTED(index)) {
  424. lan743x_intr_unregister_isr(adapter, index);
  425. intr->flags &= ~INTR_FLAG_IRQ_REQUESTED(index);
  426. }
  427. }
  428. if (intr->flags & INTR_FLAG_MSI_ENABLED) {
  429. pci_disable_msi(adapter->pdev);
  430. intr->flags &= ~INTR_FLAG_MSI_ENABLED;
  431. }
  432. if (intr->flags & INTR_FLAG_MSIX_ENABLED) {
  433. pci_disable_msix(adapter->pdev);
  434. intr->flags &= ~INTR_FLAG_MSIX_ENABLED;
  435. }
  436. }
  437. static int lan743x_intr_open(struct lan743x_adapter *adapter)
  438. {
  439. struct msix_entry msix_entries[PCI11X1X_MAX_VECTOR_COUNT];
  440. struct lan743x_intr *intr = &adapter->intr;
  441. unsigned int used_tx_channels;
  442. u32 int_vec_en_auto_clr = 0;
  443. u8 max_vector_count;
  444. u32 int_vec_map0 = 0;
  445. u32 int_vec_map1 = 0;
  446. int ret = -ENODEV;
  447. int index = 0;
  448. u32 flags = 0;
  449. intr->number_of_vectors = 0;
  450. /* Try to set up MSIX interrupts */
  451. max_vector_count = adapter->max_vector_count;
  452. memset(&msix_entries[0], 0,
  453. sizeof(struct msix_entry) * max_vector_count);
  454. for (index = 0; index < max_vector_count; index++)
  455. msix_entries[index].entry = index;
  456. used_tx_channels = adapter->used_tx_channels;
  457. ret = pci_enable_msix_range(adapter->pdev,
  458. msix_entries, 1,
  459. 1 + used_tx_channels +
  460. LAN743X_USED_RX_CHANNELS);
  461. if (ret > 0) {
  462. intr->flags |= INTR_FLAG_MSIX_ENABLED;
  463. intr->number_of_vectors = ret;
  464. intr->using_vectors = true;
  465. for (index = 0; index < intr->number_of_vectors; index++)
  466. intr->vector_list[index].irq = msix_entries
  467. [index].vector;
  468. netif_info(adapter, ifup, adapter->netdev,
  469. "using MSIX interrupts, number of vectors = %d\n",
  470. intr->number_of_vectors);
  471. }
  472. /* If MSIX failed try to setup using MSI interrupts */
  473. if (!intr->number_of_vectors) {
  474. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0)) {
  475. if (!pci_enable_msi(adapter->pdev)) {
  476. intr->flags |= INTR_FLAG_MSI_ENABLED;
  477. intr->number_of_vectors = 1;
  478. intr->using_vectors = true;
  479. intr->vector_list[0].irq =
  480. adapter->pdev->irq;
  481. netif_info(adapter, ifup, adapter->netdev,
  482. "using MSI interrupts, number of vectors = %d\n",
  483. intr->number_of_vectors);
  484. }
  485. }
  486. }
  487. /* If MSIX, and MSI failed, setup using legacy interrupt */
  488. if (!intr->number_of_vectors) {
  489. intr->number_of_vectors = 1;
  490. intr->using_vectors = false;
  491. intr->vector_list[0].irq = intr->irq;
  492. netif_info(adapter, ifup, adapter->netdev,
  493. "using legacy interrupts\n");
  494. }
  495. /* At this point we must have at least one irq */
  496. lan743x_csr_write(adapter, INT_VEC_EN_CLR, 0xFFFFFFFF);
  497. /* map all interrupts to vector 0 */
  498. lan743x_csr_write(adapter, INT_VEC_MAP0, 0x00000000);
  499. lan743x_csr_write(adapter, INT_VEC_MAP1, 0x00000000);
  500. lan743x_csr_write(adapter, INT_VEC_MAP2, 0x00000000);
  501. flags = LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ |
  502. LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C |
  503. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK |
  504. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR;
  505. if (intr->using_vectors) {
  506. flags |= LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR |
  507. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET;
  508. } else {
  509. flags |= LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR |
  510. LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET |
  511. LAN743X_VECTOR_FLAG_IRQ_SHARED;
  512. }
  513. if (adapter->csr.flags & LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR) {
  514. flags &= ~LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ;
  515. flags &= ~LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C;
  516. flags &= ~LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR;
  517. flags &= ~LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK;
  518. flags |= LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C;
  519. flags |= LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C;
  520. }
  521. init_waitqueue_head(&intr->software_isr_wq);
  522. ret = lan743x_intr_register_isr(adapter, 0, flags,
  523. INT_BIT_ALL_RX_ | INT_BIT_ALL_TX_ |
  524. INT_BIT_ALL_OTHER_,
  525. lan743x_intr_shared_isr, adapter);
  526. if (ret)
  527. goto clean_up;
  528. intr->flags |= INTR_FLAG_IRQ_REQUESTED(0);
  529. if (intr->using_vectors)
  530. lan743x_csr_write(adapter, INT_VEC_EN_SET,
  531. INT_VEC_EN_(0));
  532. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0)) {
  533. lan743x_csr_write(adapter, INT_MOD_CFG0, LAN743X_INT_MOD);
  534. lan743x_csr_write(adapter, INT_MOD_CFG1, LAN743X_INT_MOD);
  535. lan743x_csr_write(adapter, INT_MOD_CFG2, LAN743X_INT_MOD);
  536. lan743x_csr_write(adapter, INT_MOD_CFG3, LAN743X_INT_MOD);
  537. lan743x_csr_write(adapter, INT_MOD_CFG4, LAN743X_INT_MOD);
  538. lan743x_csr_write(adapter, INT_MOD_CFG5, LAN743X_INT_MOD);
  539. lan743x_csr_write(adapter, INT_MOD_CFG6, LAN743X_INT_MOD);
  540. lan743x_csr_write(adapter, INT_MOD_CFG7, LAN743X_INT_MOD);
  541. if (adapter->is_pci11x1x) {
  542. lan743x_csr_write(adapter, INT_MOD_CFG8, LAN743X_INT_MOD);
  543. lan743x_csr_write(adapter, INT_MOD_CFG9, LAN743X_INT_MOD);
  544. lan743x_csr_write(adapter, INT_MOD_MAP0, 0x00007654);
  545. lan743x_csr_write(adapter, INT_MOD_MAP1, 0x00003210);
  546. } else {
  547. lan743x_csr_write(adapter, INT_MOD_MAP0, 0x00005432);
  548. lan743x_csr_write(adapter, INT_MOD_MAP1, 0x00000001);
  549. }
  550. lan743x_csr_write(adapter, INT_MOD_MAP2, 0x00FFFFFF);
  551. }
  552. /* enable interrupts */
  553. lan743x_csr_write(adapter, INT_EN_SET, INT_BIT_MAS_);
  554. ret = lan743x_intr_test_isr(adapter);
  555. if (ret)
  556. goto clean_up;
  557. if (intr->number_of_vectors > 1) {
  558. int number_of_tx_vectors = intr->number_of_vectors - 1;
  559. if (number_of_tx_vectors > used_tx_channels)
  560. number_of_tx_vectors = used_tx_channels;
  561. flags = LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ |
  562. LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C |
  563. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK |
  564. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR |
  565. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR |
  566. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET;
  567. if (adapter->csr.flags &
  568. LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR) {
  569. flags = LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET |
  570. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET |
  571. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR |
  572. LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR;
  573. }
  574. for (index = 0; index < number_of_tx_vectors; index++) {
  575. u32 int_bit = INT_BIT_DMA_TX_(index);
  576. int vector = index + 1;
  577. /* map TX interrupt to vector */
  578. int_vec_map1 |= INT_VEC_MAP1_TX_VEC_(index, vector);
  579. lan743x_csr_write(adapter, INT_VEC_MAP1, int_vec_map1);
  580. /* Remove TX interrupt from shared mask */
  581. intr->vector_list[0].int_mask &= ~int_bit;
  582. ret = lan743x_intr_register_isr(adapter, vector, flags,
  583. int_bit, lan743x_tx_isr,
  584. &adapter->tx[index]);
  585. if (ret)
  586. goto clean_up;
  587. intr->flags |= INTR_FLAG_IRQ_REQUESTED(vector);
  588. if (!(flags &
  589. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET))
  590. lan743x_csr_write(adapter, INT_VEC_EN_SET,
  591. INT_VEC_EN_(vector));
  592. }
  593. }
  594. if ((intr->number_of_vectors - used_tx_channels) > 1) {
  595. int number_of_rx_vectors = intr->number_of_vectors -
  596. used_tx_channels - 1;
  597. if (number_of_rx_vectors > LAN743X_USED_RX_CHANNELS)
  598. number_of_rx_vectors = LAN743X_USED_RX_CHANNELS;
  599. flags = LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ |
  600. LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C |
  601. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK |
  602. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR |
  603. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR |
  604. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET;
  605. if (adapter->csr.flags &
  606. LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR) {
  607. flags = LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR |
  608. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET |
  609. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET |
  610. LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR |
  611. LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR;
  612. }
  613. for (index = 0; index < number_of_rx_vectors; index++) {
  614. int vector = index + 1 + used_tx_channels;
  615. u32 int_bit = INT_BIT_DMA_RX_(index);
  616. /* map RX interrupt to vector */
  617. int_vec_map0 |= INT_VEC_MAP0_RX_VEC_(index, vector);
  618. lan743x_csr_write(adapter, INT_VEC_MAP0, int_vec_map0);
  619. if (flags &
  620. LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR) {
  621. int_vec_en_auto_clr |= INT_VEC_EN_(vector);
  622. lan743x_csr_write(adapter, INT_VEC_EN_AUTO_CLR,
  623. int_vec_en_auto_clr);
  624. }
  625. /* Remove RX interrupt from shared mask */
  626. intr->vector_list[0].int_mask &= ~int_bit;
  627. ret = lan743x_intr_register_isr(adapter, vector, flags,
  628. int_bit, lan743x_rx_isr,
  629. &adapter->rx[index]);
  630. if (ret)
  631. goto clean_up;
  632. intr->flags |= INTR_FLAG_IRQ_REQUESTED(vector);
  633. lan743x_csr_write(adapter, INT_VEC_EN_SET,
  634. INT_VEC_EN_(vector));
  635. }
  636. }
  637. return 0;
  638. clean_up:
  639. lan743x_intr_close(adapter);
  640. return ret;
  641. }
  642. static int lan743x_dp_write(struct lan743x_adapter *adapter,
  643. u32 select, u32 addr, u32 length, u32 *buf)
  644. {
  645. u32 dp_sel;
  646. int i;
  647. if (lan743x_csr_wait_for_bit_atomic(adapter, DP_SEL, DP_SEL_DPRDY_,
  648. 1, 40, 100, 100))
  649. return -EIO;
  650. dp_sel = lan743x_csr_read(adapter, DP_SEL);
  651. dp_sel &= ~DP_SEL_MASK_;
  652. dp_sel |= select;
  653. lan743x_csr_write(adapter, DP_SEL, dp_sel);
  654. for (i = 0; i < length; i++) {
  655. lan743x_csr_write(adapter, DP_ADDR, addr + i);
  656. lan743x_csr_write(adapter, DP_DATA_0, buf[i]);
  657. lan743x_csr_write(adapter, DP_CMD, DP_CMD_WRITE_);
  658. if (lan743x_csr_wait_for_bit_atomic(adapter, DP_SEL,
  659. DP_SEL_DPRDY_,
  660. 1, 40, 100, 100))
  661. return -EIO;
  662. }
  663. return 0;
  664. }
  665. static u32 lan743x_mac_mii_access(u16 id, u16 index, int read)
  666. {
  667. u32 ret;
  668. ret = (id << MAC_MII_ACC_PHY_ADDR_SHIFT_) &
  669. MAC_MII_ACC_PHY_ADDR_MASK_;
  670. ret |= (index << MAC_MII_ACC_MIIRINDA_SHIFT_) &
  671. MAC_MII_ACC_MIIRINDA_MASK_;
  672. if (read)
  673. ret |= MAC_MII_ACC_MII_READ_;
  674. else
  675. ret |= MAC_MII_ACC_MII_WRITE_;
  676. ret |= MAC_MII_ACC_MII_BUSY_;
  677. return ret;
  678. }
  679. static int lan743x_mac_mii_wait_till_not_busy(struct lan743x_adapter *adapter)
  680. {
  681. u32 data;
  682. return readx_poll_timeout(LAN743X_CSR_READ_OP, MAC_MII_ACC, data,
  683. !(data & MAC_MII_ACC_MII_BUSY_), 0, 1000000);
  684. }
  685. static int lan743x_mdiobus_read_c22(struct mii_bus *bus, int phy_id, int index)
  686. {
  687. struct lan743x_adapter *adapter = bus->priv;
  688. u32 val, mii_access;
  689. int ret;
  690. /* confirm MII not busy */
  691. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  692. if (ret < 0)
  693. return ret;
  694. /* set the address, index & direction (read from PHY) */
  695. mii_access = lan743x_mac_mii_access(phy_id, index, MAC_MII_READ);
  696. lan743x_csr_write(adapter, MAC_MII_ACC, mii_access);
  697. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  698. if (ret < 0)
  699. return ret;
  700. val = lan743x_csr_read(adapter, MAC_MII_DATA);
  701. return (int)(val & 0xFFFF);
  702. }
  703. static int lan743x_mdiobus_write_c22(struct mii_bus *bus,
  704. int phy_id, int index, u16 regval)
  705. {
  706. struct lan743x_adapter *adapter = bus->priv;
  707. u32 val, mii_access;
  708. int ret;
  709. /* confirm MII not busy */
  710. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  711. if (ret < 0)
  712. return ret;
  713. val = (u32)regval;
  714. lan743x_csr_write(adapter, MAC_MII_DATA, val);
  715. /* set the address, index & direction (write to PHY) */
  716. mii_access = lan743x_mac_mii_access(phy_id, index, MAC_MII_WRITE);
  717. lan743x_csr_write(adapter, MAC_MII_ACC, mii_access);
  718. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  719. return ret;
  720. }
  721. static u32 lan743x_mac_mmd_access(int id, int dev_addr, int op)
  722. {
  723. u32 ret;
  724. ret = (id << MAC_MII_ACC_PHY_ADDR_SHIFT_) &
  725. MAC_MII_ACC_PHY_ADDR_MASK_;
  726. ret |= (dev_addr << MAC_MII_ACC_MIIMMD_SHIFT_) &
  727. MAC_MII_ACC_MIIMMD_MASK_;
  728. if (op == MMD_ACCESS_WRITE)
  729. ret |= MAC_MII_ACC_MIICMD_WRITE_;
  730. else if (op == MMD_ACCESS_READ)
  731. ret |= MAC_MII_ACC_MIICMD_READ_;
  732. else if (op == MMD_ACCESS_READ_INC)
  733. ret |= MAC_MII_ACC_MIICMD_READ_INC_;
  734. else
  735. ret |= MAC_MII_ACC_MIICMD_ADDR_;
  736. ret |= (MAC_MII_ACC_MII_BUSY_ | MAC_MII_ACC_MIICL45_);
  737. return ret;
  738. }
  739. static int lan743x_mdiobus_read_c45(struct mii_bus *bus, int phy_id,
  740. int dev_addr, int index)
  741. {
  742. struct lan743x_adapter *adapter = bus->priv;
  743. u32 mmd_access;
  744. int ret;
  745. /* confirm MII not busy */
  746. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  747. if (ret < 0)
  748. return ret;
  749. /* Load Register Address */
  750. lan743x_csr_write(adapter, MAC_MII_DATA, index);
  751. mmd_access = lan743x_mac_mmd_access(phy_id, dev_addr,
  752. MMD_ACCESS_ADDRESS);
  753. lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access);
  754. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  755. if (ret < 0)
  756. return ret;
  757. /* Read Data */
  758. mmd_access = lan743x_mac_mmd_access(phy_id, dev_addr,
  759. MMD_ACCESS_READ);
  760. lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access);
  761. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  762. if (ret < 0)
  763. return ret;
  764. ret = lan743x_csr_read(adapter, MAC_MII_DATA);
  765. return (int)(ret & 0xFFFF);
  766. }
  767. static int lan743x_mdiobus_write_c45(struct mii_bus *bus, int phy_id,
  768. int dev_addr, int index, u16 regval)
  769. {
  770. struct lan743x_adapter *adapter = bus->priv;
  771. u32 mmd_access;
  772. int ret;
  773. /* confirm MII not busy */
  774. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  775. if (ret < 0)
  776. return ret;
  777. /* Load Register Address */
  778. lan743x_csr_write(adapter, MAC_MII_DATA, (u32)index);
  779. mmd_access = lan743x_mac_mmd_access(phy_id, dev_addr,
  780. MMD_ACCESS_ADDRESS);
  781. lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access);
  782. ret = lan743x_mac_mii_wait_till_not_busy(adapter);
  783. if (ret < 0)
  784. return ret;
  785. /* Write Data */
  786. lan743x_csr_write(adapter, MAC_MII_DATA, (u32)regval);
  787. mmd_access = lan743x_mac_mmd_access(phy_id, dev_addr,
  788. MMD_ACCESS_WRITE);
  789. lan743x_csr_write(adapter, MAC_MII_ACC, mmd_access);
  790. return lan743x_mac_mii_wait_till_not_busy(adapter);
  791. }
  792. static int lan743x_sgmii_wait_till_not_busy(struct lan743x_adapter *adapter)
  793. {
  794. u32 data;
  795. int ret;
  796. ret = readx_poll_timeout(LAN743X_CSR_READ_OP, SGMII_ACC, data,
  797. !(data & SGMII_ACC_SGMII_BZY_), 100, 1000000);
  798. if (ret < 0)
  799. netif_err(adapter, drv, adapter->netdev,
  800. "%s: error %d sgmii wait timeout\n", __func__, ret);
  801. return ret;
  802. }
  803. int lan743x_sgmii_read(struct lan743x_adapter *adapter, u8 mmd, u16 addr)
  804. {
  805. u32 mmd_access;
  806. int ret;
  807. u32 val;
  808. if (mmd > 31) {
  809. netif_err(adapter, probe, adapter->netdev,
  810. "%s mmd should <= 31\n", __func__);
  811. return -EINVAL;
  812. }
  813. mutex_lock(&adapter->sgmii_rw_lock);
  814. /* Load Register Address */
  815. mmd_access = mmd << SGMII_ACC_SGMII_MMD_SHIFT_;
  816. mmd_access |= (addr | SGMII_ACC_SGMII_BZY_);
  817. lan743x_csr_write(adapter, SGMII_ACC, mmd_access);
  818. ret = lan743x_sgmii_wait_till_not_busy(adapter);
  819. if (ret < 0)
  820. goto sgmii_unlock;
  821. val = lan743x_csr_read(adapter, SGMII_DATA);
  822. ret = (int)(val & SGMII_DATA_MASK_);
  823. sgmii_unlock:
  824. mutex_unlock(&adapter->sgmii_rw_lock);
  825. return ret;
  826. }
  827. static int lan743x_sgmii_write(struct lan743x_adapter *adapter,
  828. u8 mmd, u16 addr, u16 val)
  829. {
  830. u32 mmd_access;
  831. int ret;
  832. if (mmd > 31) {
  833. netif_err(adapter, probe, adapter->netdev,
  834. "%s mmd should <= 31\n", __func__);
  835. return -EINVAL;
  836. }
  837. mutex_lock(&adapter->sgmii_rw_lock);
  838. /* Load Register Data */
  839. lan743x_csr_write(adapter, SGMII_DATA, (u32)(val & SGMII_DATA_MASK_));
  840. /* Load Register Address */
  841. mmd_access = mmd << SGMII_ACC_SGMII_MMD_SHIFT_;
  842. mmd_access |= (addr | SGMII_ACC_SGMII_BZY_ | SGMII_ACC_SGMII_WR_);
  843. lan743x_csr_write(adapter, SGMII_ACC, mmd_access);
  844. ret = lan743x_sgmii_wait_till_not_busy(adapter);
  845. mutex_unlock(&adapter->sgmii_rw_lock);
  846. return ret;
  847. }
  848. static int lan743x_get_lsd(int speed, int duplex, u8 mss)
  849. {
  850. int lsd;
  851. switch (speed) {
  852. case SPEED_2500:
  853. if (mss == MASTER_SLAVE_STATE_SLAVE)
  854. lsd = LINK_2500_SLAVE;
  855. else
  856. lsd = LINK_2500_MASTER;
  857. break;
  858. case SPEED_1000:
  859. if (mss == MASTER_SLAVE_STATE_SLAVE)
  860. lsd = LINK_1000_SLAVE;
  861. else
  862. lsd = LINK_1000_MASTER;
  863. break;
  864. case SPEED_100:
  865. if (duplex == DUPLEX_FULL)
  866. lsd = LINK_100FD;
  867. else
  868. lsd = LINK_100HD;
  869. break;
  870. case SPEED_10:
  871. if (duplex == DUPLEX_FULL)
  872. lsd = LINK_10FD;
  873. else
  874. lsd = LINK_10HD;
  875. break;
  876. default:
  877. lsd = -EINVAL;
  878. }
  879. return lsd;
  880. }
  881. static int lan743x_sgmii_mpll_set(struct lan743x_adapter *adapter,
  882. u16 baud)
  883. {
  884. int mpllctrl0;
  885. int mpllctrl1;
  886. int miscctrl1;
  887. int ret;
  888. mpllctrl0 = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2,
  889. VR_MII_GEN2_4_MPLL_CTRL0);
  890. if (mpllctrl0 < 0)
  891. return mpllctrl0;
  892. mpllctrl0 &= ~VR_MII_MPLL_CTRL0_USE_REFCLK_PAD_;
  893. if (baud == VR_MII_BAUD_RATE_1P25GBPS) {
  894. mpllctrl1 = VR_MII_MPLL_MULTIPLIER_100;
  895. /* mpll_baud_clk/4 */
  896. miscctrl1 = 0xA;
  897. } else {
  898. mpllctrl1 = VR_MII_MPLL_MULTIPLIER_125;
  899. /* mpll_baud_clk/2 */
  900. miscctrl1 = 0x5;
  901. }
  902. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2,
  903. VR_MII_GEN2_4_MPLL_CTRL0, mpllctrl0);
  904. if (ret < 0)
  905. return ret;
  906. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2,
  907. VR_MII_GEN2_4_MPLL_CTRL1, mpllctrl1);
  908. if (ret < 0)
  909. return ret;
  910. return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2,
  911. VR_MII_GEN2_4_MISC_CTRL1, miscctrl1);
  912. }
  913. static int lan743x_sgmii_2_5G_mode_set(struct lan743x_adapter *adapter,
  914. bool enable)
  915. {
  916. if (enable)
  917. return lan743x_sgmii_mpll_set(adapter,
  918. VR_MII_BAUD_RATE_3P125GBPS);
  919. else
  920. return lan743x_sgmii_mpll_set(adapter,
  921. VR_MII_BAUD_RATE_1P25GBPS);
  922. }
  923. static int lan743x_serdes_clock_and_aneg_update(struct lan743x_adapter *adapter)
  924. {
  925. enum lan743x_sgmii_lsd lsd = adapter->sgmii_lsd;
  926. int mii_ctrl;
  927. int dgt_ctrl;
  928. int an_ctrl;
  929. int ret;
  930. if (lsd == LINK_2500_MASTER || lsd == LINK_2500_SLAVE)
  931. /* Switch to 2.5 Gbps */
  932. ret = lan743x_sgmii_2_5G_mode_set(adapter, true);
  933. else
  934. /* Switch to 10/100/1000 Mbps clock */
  935. ret = lan743x_sgmii_2_5G_mode_set(adapter, false);
  936. if (ret < 0)
  937. return ret;
  938. /* Enable SGMII Auto NEG */
  939. mii_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, MII_BMCR);
  940. if (mii_ctrl < 0)
  941. return mii_ctrl;
  942. an_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, VR_MII_AN_CTRL);
  943. if (an_ctrl < 0)
  944. return an_ctrl;
  945. dgt_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2,
  946. VR_MII_DIG_CTRL1);
  947. if (dgt_ctrl < 0)
  948. return dgt_ctrl;
  949. if (lsd == LINK_2500_MASTER || lsd == LINK_2500_SLAVE) {
  950. mii_ctrl &= ~(BMCR_ANENABLE | BMCR_ANRESTART | BMCR_SPEED100);
  951. mii_ctrl |= BMCR_SPEED1000;
  952. dgt_ctrl |= VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_;
  953. dgt_ctrl &= ~VR_MII_DIG_CTRL1_MAC_AUTO_SW_;
  954. /* In order for Auto-Negotiation to operate properly at
  955. * 2.5 Gbps the 1.6ms link timer values must be adjusted
  956. * The VR_MII_LINK_TIMER_CTRL Register must be set to
  957. * 16'h7A1 and The CL37_TMR_OVR_RIDE bit of the
  958. * VR_MII_DIG_CTRL1 Register set to 1
  959. */
  960. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2,
  961. VR_MII_LINK_TIMER_CTRL, 0x7A1);
  962. if (ret < 0)
  963. return ret;
  964. } else {
  965. mii_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  966. an_ctrl &= ~VR_MII_AN_CTRL_SGMII_LINK_STS_;
  967. dgt_ctrl &= ~VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_;
  968. dgt_ctrl |= VR_MII_DIG_CTRL1_MAC_AUTO_SW_;
  969. }
  970. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMCR,
  971. mii_ctrl);
  972. if (ret < 0)
  973. return ret;
  974. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2,
  975. VR_MII_DIG_CTRL1, dgt_ctrl);
  976. if (ret < 0)
  977. return ret;
  978. return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2,
  979. VR_MII_AN_CTRL, an_ctrl);
  980. }
  981. static int lan743x_pcs_seq_state(struct lan743x_adapter *adapter, u8 state)
  982. {
  983. u8 wait_cnt = 0;
  984. u32 dig_sts;
  985. do {
  986. dig_sts = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2,
  987. VR_MII_DIG_STS);
  988. if (((dig_sts & VR_MII_DIG_STS_PSEQ_STATE_MASK_) >>
  989. VR_MII_DIG_STS_PSEQ_STATE_POS_) == state)
  990. break;
  991. usleep_range(1000, 2000);
  992. } while (wait_cnt++ < 10);
  993. if (wait_cnt >= 10)
  994. return -ETIMEDOUT;
  995. return 0;
  996. }
  997. static int lan743x_pcs_power_reset(struct lan743x_adapter *adapter)
  998. {
  999. int mii_ctl;
  1000. int ret;
  1001. /* SGMII/1000/2500BASE-X PCS power down */
  1002. mii_ctl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, MII_BMCR);
  1003. if (mii_ctl < 0)
  1004. return mii_ctl;
  1005. mii_ctl |= BMCR_PDOWN;
  1006. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMCR, mii_ctl);
  1007. if (ret < 0)
  1008. return ret;
  1009. ret = lan743x_pcs_seq_state(adapter, PCS_POWER_STATE_DOWN);
  1010. if (ret < 0)
  1011. return ret;
  1012. /* SGMII/1000/2500BASE-X PCS power up */
  1013. mii_ctl &= ~BMCR_PDOWN;
  1014. ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMCR, mii_ctl);
  1015. if (ret < 0)
  1016. return ret;
  1017. return lan743x_pcs_seq_state(adapter, PCS_POWER_STATE_UP);
  1018. }
  1019. static void lan743x_mac_set_address(struct lan743x_adapter *adapter,
  1020. u8 *addr)
  1021. {
  1022. u32 addr_lo, addr_hi;
  1023. addr_lo = addr[0] |
  1024. addr[1] << 8 |
  1025. addr[2] << 16 |
  1026. addr[3] << 24;
  1027. addr_hi = addr[4] |
  1028. addr[5] << 8;
  1029. lan743x_csr_write(adapter, MAC_RX_ADDRL, addr_lo);
  1030. lan743x_csr_write(adapter, MAC_RX_ADDRH, addr_hi);
  1031. ether_addr_copy(adapter->mac_address, addr);
  1032. netif_info(adapter, drv, adapter->netdev,
  1033. "MAC address set to %pM\n", addr);
  1034. }
  1035. static int lan743x_mac_init(struct lan743x_adapter *adapter)
  1036. {
  1037. bool mac_address_valid = true;
  1038. struct net_device *netdev;
  1039. u32 mac_addr_hi = 0;
  1040. u32 mac_addr_lo = 0;
  1041. u32 data;
  1042. netdev = adapter->netdev;
  1043. /* disable auto duplex, and speed detection. Phylib does that */
  1044. data = lan743x_csr_read(adapter, MAC_CR);
  1045. data &= ~(MAC_CR_ADD_ | MAC_CR_ASD_);
  1046. data |= MAC_CR_CNTR_RST_;
  1047. lan743x_csr_write(adapter, MAC_CR, data);
  1048. if (!is_valid_ether_addr(adapter->mac_address)) {
  1049. mac_addr_hi = lan743x_csr_read(adapter, MAC_RX_ADDRH);
  1050. mac_addr_lo = lan743x_csr_read(adapter, MAC_RX_ADDRL);
  1051. adapter->mac_address[0] = mac_addr_lo & 0xFF;
  1052. adapter->mac_address[1] = (mac_addr_lo >> 8) & 0xFF;
  1053. adapter->mac_address[2] = (mac_addr_lo >> 16) & 0xFF;
  1054. adapter->mac_address[3] = (mac_addr_lo >> 24) & 0xFF;
  1055. adapter->mac_address[4] = mac_addr_hi & 0xFF;
  1056. adapter->mac_address[5] = (mac_addr_hi >> 8) & 0xFF;
  1057. if (((mac_addr_hi & 0x0000FFFF) == 0x0000FFFF) &&
  1058. mac_addr_lo == 0xFFFFFFFF) {
  1059. mac_address_valid = false;
  1060. } else if (!is_valid_ether_addr(adapter->mac_address)) {
  1061. mac_address_valid = false;
  1062. }
  1063. if (!mac_address_valid)
  1064. eth_random_addr(adapter->mac_address);
  1065. }
  1066. lan743x_mac_set_address(adapter, adapter->mac_address);
  1067. eth_hw_addr_set(netdev, adapter->mac_address);
  1068. return 0;
  1069. }
  1070. static int lan743x_mac_open(struct lan743x_adapter *adapter)
  1071. {
  1072. u32 temp;
  1073. temp = lan743x_csr_read(adapter, MAC_RX);
  1074. lan743x_csr_write(adapter, MAC_RX, temp | MAC_RX_RXEN_);
  1075. temp = lan743x_csr_read(adapter, MAC_TX);
  1076. lan743x_csr_write(adapter, MAC_TX, temp | MAC_TX_TXEN_);
  1077. return 0;
  1078. }
  1079. static void lan743x_mac_close(struct lan743x_adapter *adapter)
  1080. {
  1081. u32 temp;
  1082. temp = lan743x_csr_read(adapter, MAC_TX);
  1083. temp &= ~MAC_TX_TXEN_;
  1084. lan743x_csr_write(adapter, MAC_TX, temp);
  1085. lan743x_csr_wait_for_bit(adapter, MAC_TX, MAC_TX_TXD_,
  1086. 1, 1000, 20000, 100);
  1087. temp = lan743x_csr_read(adapter, MAC_RX);
  1088. temp &= ~MAC_RX_RXEN_;
  1089. lan743x_csr_write(adapter, MAC_RX, temp);
  1090. lan743x_csr_wait_for_bit(adapter, MAC_RX, MAC_RX_RXD_,
  1091. 1, 1000, 20000, 100);
  1092. }
  1093. void lan743x_mac_flow_ctrl_set_enables(struct lan743x_adapter *adapter,
  1094. bool tx_enable, bool rx_enable)
  1095. {
  1096. u32 flow_setting = 0;
  1097. /* set maximum pause time because when fifo space frees
  1098. * up a zero value pause frame will be sent to release the pause
  1099. */
  1100. flow_setting = MAC_FLOW_CR_FCPT_MASK_;
  1101. if (tx_enable)
  1102. flow_setting |= MAC_FLOW_CR_TX_FCEN_;
  1103. if (rx_enable)
  1104. flow_setting |= MAC_FLOW_CR_RX_FCEN_;
  1105. lan743x_csr_write(adapter, MAC_FLOW, flow_setting);
  1106. }
  1107. static int lan743x_mac_set_mtu(struct lan743x_adapter *adapter, int new_mtu)
  1108. {
  1109. int enabled = 0;
  1110. u32 mac_rx = 0;
  1111. mac_rx = lan743x_csr_read(adapter, MAC_RX);
  1112. if (mac_rx & MAC_RX_RXEN_) {
  1113. enabled = 1;
  1114. if (mac_rx & MAC_RX_RXD_) {
  1115. lan743x_csr_write(adapter, MAC_RX, mac_rx);
  1116. mac_rx &= ~MAC_RX_RXD_;
  1117. }
  1118. mac_rx &= ~MAC_RX_RXEN_;
  1119. lan743x_csr_write(adapter, MAC_RX, mac_rx);
  1120. lan743x_csr_wait_for_bit(adapter, MAC_RX, MAC_RX_RXD_,
  1121. 1, 1000, 20000, 100);
  1122. lan743x_csr_write(adapter, MAC_RX, mac_rx | MAC_RX_RXD_);
  1123. }
  1124. mac_rx &= ~(MAC_RX_MAX_SIZE_MASK_);
  1125. mac_rx |= (((new_mtu + ETH_HLEN + ETH_FCS_LEN)
  1126. << MAC_RX_MAX_SIZE_SHIFT_) & MAC_RX_MAX_SIZE_MASK_);
  1127. lan743x_csr_write(adapter, MAC_RX, mac_rx);
  1128. if (enabled) {
  1129. mac_rx |= MAC_RX_RXEN_;
  1130. lan743x_csr_write(adapter, MAC_RX, mac_rx);
  1131. }
  1132. return 0;
  1133. }
  1134. /* PHY */
  1135. static int lan743x_hw_reset_phy(struct lan743x_adapter *adapter)
  1136. {
  1137. u32 data;
  1138. /* Only called with in probe, and before mdiobus_register */
  1139. data = lan743x_csr_read(adapter, PMT_CTL);
  1140. data |= PMT_CTL_ETH_PHY_RST_;
  1141. lan743x_csr_write(adapter, PMT_CTL, data);
  1142. return readx_poll_timeout(LAN743X_CSR_READ_OP, PMT_CTL, data,
  1143. (!(data & PMT_CTL_ETH_PHY_RST_) &&
  1144. (data & PMT_CTL_READY_)),
  1145. 50000, 1000000);
  1146. }
  1147. static void lan743x_phy_interface_select(struct lan743x_adapter *adapter)
  1148. {
  1149. u32 id_rev;
  1150. u32 data;
  1151. data = lan743x_csr_read(adapter, MAC_CR);
  1152. id_rev = adapter->csr.id_rev & ID_REV_ID_MASK_;
  1153. if (adapter->is_pci11x1x && adapter->is_sgmii_en)
  1154. adapter->phy_interface = PHY_INTERFACE_MODE_SGMII;
  1155. else if (id_rev == ID_REV_ID_LAN7430_)
  1156. adapter->phy_interface = PHY_INTERFACE_MODE_GMII;
  1157. else if ((id_rev == ID_REV_ID_LAN7431_) && (data & MAC_CR_MII_EN_))
  1158. adapter->phy_interface = PHY_INTERFACE_MODE_MII;
  1159. else
  1160. adapter->phy_interface = PHY_INTERFACE_MODE_RGMII;
  1161. netif_dbg(adapter, drv, adapter->netdev,
  1162. "selected phy interface: 0x%X\n", adapter->phy_interface);
  1163. }
  1164. static void lan743x_rfe_open(struct lan743x_adapter *adapter)
  1165. {
  1166. lan743x_csr_write(adapter, RFE_RSS_CFG,
  1167. RFE_RSS_CFG_UDP_IPV6_EX_ |
  1168. RFE_RSS_CFG_TCP_IPV6_EX_ |
  1169. RFE_RSS_CFG_IPV6_EX_ |
  1170. RFE_RSS_CFG_UDP_IPV6_ |
  1171. RFE_RSS_CFG_TCP_IPV6_ |
  1172. RFE_RSS_CFG_IPV6_ |
  1173. RFE_RSS_CFG_UDP_IPV4_ |
  1174. RFE_RSS_CFG_TCP_IPV4_ |
  1175. RFE_RSS_CFG_IPV4_ |
  1176. RFE_RSS_CFG_VALID_HASH_BITS_ |
  1177. RFE_RSS_CFG_RSS_QUEUE_ENABLE_ |
  1178. RFE_RSS_CFG_RSS_HASH_STORE_ |
  1179. RFE_RSS_CFG_RSS_ENABLE_);
  1180. }
  1181. static void lan743x_rfe_update_mac_address(struct lan743x_adapter *adapter)
  1182. {
  1183. u8 *mac_addr;
  1184. u32 mac_addr_hi = 0;
  1185. u32 mac_addr_lo = 0;
  1186. /* Add mac address to perfect Filter */
  1187. mac_addr = adapter->mac_address;
  1188. mac_addr_lo = ((((u32)(mac_addr[0])) << 0) |
  1189. (((u32)(mac_addr[1])) << 8) |
  1190. (((u32)(mac_addr[2])) << 16) |
  1191. (((u32)(mac_addr[3])) << 24));
  1192. mac_addr_hi = ((((u32)(mac_addr[4])) << 0) |
  1193. (((u32)(mac_addr[5])) << 8));
  1194. lan743x_csr_write(adapter, RFE_ADDR_FILT_LO(0), mac_addr_lo);
  1195. lan743x_csr_write(adapter, RFE_ADDR_FILT_HI(0),
  1196. mac_addr_hi | RFE_ADDR_FILT_HI_VALID_);
  1197. }
  1198. static void lan743x_rfe_set_multicast(struct lan743x_adapter *adapter)
  1199. {
  1200. struct net_device *netdev = adapter->netdev;
  1201. u32 hash_table[DP_SEL_VHF_HASH_LEN];
  1202. u32 rfctl;
  1203. u32 data;
  1204. rfctl = lan743x_csr_read(adapter, RFE_CTL);
  1205. rfctl &= ~(RFE_CTL_AU_ | RFE_CTL_AM_ |
  1206. RFE_CTL_DA_PERFECT_ | RFE_CTL_MCAST_HASH_);
  1207. rfctl |= RFE_CTL_AB_;
  1208. if (netdev->flags & IFF_PROMISC) {
  1209. rfctl |= RFE_CTL_AM_ | RFE_CTL_AU_;
  1210. } else {
  1211. if (netdev->flags & IFF_ALLMULTI)
  1212. rfctl |= RFE_CTL_AM_;
  1213. }
  1214. if (netdev->features & NETIF_F_RXCSUM)
  1215. rfctl |= RFE_CTL_IP_COE_ | RFE_CTL_TCP_UDP_COE_;
  1216. memset(hash_table, 0, DP_SEL_VHF_HASH_LEN * sizeof(u32));
  1217. if (netdev_mc_count(netdev)) {
  1218. struct netdev_hw_addr *ha;
  1219. int i;
  1220. rfctl |= RFE_CTL_DA_PERFECT_;
  1221. i = 1;
  1222. netdev_for_each_mc_addr(ha, netdev) {
  1223. /* set first 32 into Perfect Filter */
  1224. if (i < 33) {
  1225. lan743x_csr_write(adapter,
  1226. RFE_ADDR_FILT_HI(i), 0);
  1227. data = ha->addr[3];
  1228. data = ha->addr[2] | (data << 8);
  1229. data = ha->addr[1] | (data << 8);
  1230. data = ha->addr[0] | (data << 8);
  1231. lan743x_csr_write(adapter,
  1232. RFE_ADDR_FILT_LO(i), data);
  1233. data = ha->addr[5];
  1234. data = ha->addr[4] | (data << 8);
  1235. data |= RFE_ADDR_FILT_HI_VALID_;
  1236. lan743x_csr_write(adapter,
  1237. RFE_ADDR_FILT_HI(i), data);
  1238. } else {
  1239. u32 bitnum = (ether_crc(ETH_ALEN, ha->addr) >>
  1240. 23) & 0x1FF;
  1241. hash_table[bitnum / 32] |= (1 << (bitnum % 32));
  1242. rfctl |= RFE_CTL_MCAST_HASH_;
  1243. }
  1244. i++;
  1245. }
  1246. }
  1247. lan743x_dp_write(adapter, DP_SEL_RFE_RAM,
  1248. DP_SEL_VHF_VLAN_LEN,
  1249. DP_SEL_VHF_HASH_LEN, hash_table);
  1250. lan743x_csr_write(adapter, RFE_CTL, rfctl);
  1251. }
  1252. static int lan743x_dmac_init(struct lan743x_adapter *adapter)
  1253. {
  1254. u32 data = 0;
  1255. lan743x_csr_write(adapter, DMAC_CMD, DMAC_CMD_SWR_);
  1256. lan743x_csr_wait_for_bit(adapter, DMAC_CMD, DMAC_CMD_SWR_,
  1257. 0, 1000, 20000, 100);
  1258. switch (DEFAULT_DMA_DESCRIPTOR_SPACING) {
  1259. case DMA_DESCRIPTOR_SPACING_16:
  1260. data = DMAC_CFG_MAX_DSPACE_16_;
  1261. break;
  1262. case DMA_DESCRIPTOR_SPACING_32:
  1263. data = DMAC_CFG_MAX_DSPACE_32_;
  1264. break;
  1265. case DMA_DESCRIPTOR_SPACING_64:
  1266. data = DMAC_CFG_MAX_DSPACE_64_;
  1267. break;
  1268. case DMA_DESCRIPTOR_SPACING_128:
  1269. data = DMAC_CFG_MAX_DSPACE_128_;
  1270. break;
  1271. default:
  1272. return -EPERM;
  1273. }
  1274. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0))
  1275. data |= DMAC_CFG_COAL_EN_;
  1276. data |= DMAC_CFG_CH_ARB_SEL_RX_HIGH_;
  1277. data |= DMAC_CFG_MAX_READ_REQ_SET_(6);
  1278. lan743x_csr_write(adapter, DMAC_CFG, data);
  1279. data = DMAC_COAL_CFG_TIMER_LIMIT_SET_(1);
  1280. data |= DMAC_COAL_CFG_TIMER_TX_START_;
  1281. data |= DMAC_COAL_CFG_FLUSH_INTS_;
  1282. data |= DMAC_COAL_CFG_INT_EXIT_COAL_;
  1283. data |= DMAC_COAL_CFG_CSR_EXIT_COAL_;
  1284. data |= DMAC_COAL_CFG_TX_THRES_SET_(0x0A);
  1285. data |= DMAC_COAL_CFG_RX_THRES_SET_(0x0C);
  1286. lan743x_csr_write(adapter, DMAC_COAL_CFG, data);
  1287. data = DMAC_OBFF_TX_THRES_SET_(0x08);
  1288. data |= DMAC_OBFF_RX_THRES_SET_(0x0A);
  1289. lan743x_csr_write(adapter, DMAC_OBFF_CFG, data);
  1290. return 0;
  1291. }
  1292. static int lan743x_dmac_tx_get_state(struct lan743x_adapter *adapter,
  1293. int tx_channel)
  1294. {
  1295. u32 dmac_cmd = 0;
  1296. dmac_cmd = lan743x_csr_read(adapter, DMAC_CMD);
  1297. return DMAC_CHANNEL_STATE_SET((dmac_cmd &
  1298. DMAC_CMD_START_T_(tx_channel)),
  1299. (dmac_cmd &
  1300. DMAC_CMD_STOP_T_(tx_channel)));
  1301. }
  1302. static int lan743x_dmac_tx_wait_till_stopped(struct lan743x_adapter *adapter,
  1303. int tx_channel)
  1304. {
  1305. int timeout = 100;
  1306. int result = 0;
  1307. while (timeout &&
  1308. ((result = lan743x_dmac_tx_get_state(adapter, tx_channel)) ==
  1309. DMAC_CHANNEL_STATE_STOP_PENDING)) {
  1310. usleep_range(1000, 20000);
  1311. timeout--;
  1312. }
  1313. if (result == DMAC_CHANNEL_STATE_STOP_PENDING)
  1314. result = -ENODEV;
  1315. return result;
  1316. }
  1317. static int lan743x_dmac_rx_get_state(struct lan743x_adapter *adapter,
  1318. int rx_channel)
  1319. {
  1320. u32 dmac_cmd = 0;
  1321. dmac_cmd = lan743x_csr_read(adapter, DMAC_CMD);
  1322. return DMAC_CHANNEL_STATE_SET((dmac_cmd &
  1323. DMAC_CMD_START_R_(rx_channel)),
  1324. (dmac_cmd &
  1325. DMAC_CMD_STOP_R_(rx_channel)));
  1326. }
  1327. static int lan743x_dmac_rx_wait_till_stopped(struct lan743x_adapter *adapter,
  1328. int rx_channel)
  1329. {
  1330. int timeout = 100;
  1331. int result = 0;
  1332. while (timeout &&
  1333. ((result = lan743x_dmac_rx_get_state(adapter, rx_channel)) ==
  1334. DMAC_CHANNEL_STATE_STOP_PENDING)) {
  1335. usleep_range(1000, 20000);
  1336. timeout--;
  1337. }
  1338. if (result == DMAC_CHANNEL_STATE_STOP_PENDING)
  1339. result = -ENODEV;
  1340. return result;
  1341. }
  1342. static void lan743x_tx_release_desc(struct lan743x_tx *tx,
  1343. int descriptor_index, bool cleanup)
  1344. {
  1345. struct lan743x_tx_buffer_info *buffer_info = NULL;
  1346. struct lan743x_tx_descriptor *descriptor = NULL;
  1347. u32 descriptor_type = 0;
  1348. bool ignore_sync;
  1349. descriptor = &tx->ring_cpu_ptr[descriptor_index];
  1350. buffer_info = &tx->buffer_info[descriptor_index];
  1351. if (!(buffer_info->flags & TX_BUFFER_INFO_FLAG_ACTIVE))
  1352. goto done;
  1353. descriptor_type = le32_to_cpu(descriptor->data0) &
  1354. TX_DESC_DATA0_DTYPE_MASK_;
  1355. if (descriptor_type == TX_DESC_DATA0_DTYPE_DATA_)
  1356. goto clean_up_data_descriptor;
  1357. else
  1358. goto clear_active;
  1359. clean_up_data_descriptor:
  1360. if (buffer_info->dma_ptr) {
  1361. if (buffer_info->flags &
  1362. TX_BUFFER_INFO_FLAG_SKB_FRAGMENT) {
  1363. dma_unmap_page(&tx->adapter->pdev->dev,
  1364. buffer_info->dma_ptr,
  1365. buffer_info->buffer_length,
  1366. DMA_TO_DEVICE);
  1367. } else {
  1368. dma_unmap_single(&tx->adapter->pdev->dev,
  1369. buffer_info->dma_ptr,
  1370. buffer_info->buffer_length,
  1371. DMA_TO_DEVICE);
  1372. }
  1373. buffer_info->dma_ptr = 0;
  1374. buffer_info->buffer_length = 0;
  1375. }
  1376. if (!buffer_info->skb)
  1377. goto clear_active;
  1378. if (!(buffer_info->flags & TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED)) {
  1379. dev_kfree_skb_any(buffer_info->skb);
  1380. goto clear_skb;
  1381. }
  1382. if (cleanup) {
  1383. lan743x_ptp_unrequest_tx_timestamp(tx->adapter);
  1384. dev_kfree_skb_any(buffer_info->skb);
  1385. } else {
  1386. ignore_sync = (buffer_info->flags &
  1387. TX_BUFFER_INFO_FLAG_IGNORE_SYNC) != 0;
  1388. lan743x_ptp_tx_timestamp_skb(tx->adapter,
  1389. buffer_info->skb, ignore_sync);
  1390. }
  1391. clear_skb:
  1392. buffer_info->skb = NULL;
  1393. clear_active:
  1394. buffer_info->flags &= ~TX_BUFFER_INFO_FLAG_ACTIVE;
  1395. done:
  1396. memset(buffer_info, 0, sizeof(*buffer_info));
  1397. memset(descriptor, 0, sizeof(*descriptor));
  1398. }
  1399. static int lan743x_tx_next_index(struct lan743x_tx *tx, int index)
  1400. {
  1401. return ((++index) % tx->ring_size);
  1402. }
  1403. static void lan743x_tx_release_completed_descriptors(struct lan743x_tx *tx)
  1404. {
  1405. while (le32_to_cpu(*tx->head_cpu_ptr) != (tx->last_head)) {
  1406. lan743x_tx_release_desc(tx, tx->last_head, false);
  1407. tx->last_head = lan743x_tx_next_index(tx, tx->last_head);
  1408. }
  1409. }
  1410. static void lan743x_tx_release_all_descriptors(struct lan743x_tx *tx)
  1411. {
  1412. u32 original_head = 0;
  1413. original_head = tx->last_head;
  1414. do {
  1415. lan743x_tx_release_desc(tx, tx->last_head, true);
  1416. tx->last_head = lan743x_tx_next_index(tx, tx->last_head);
  1417. } while (tx->last_head != original_head);
  1418. memset(tx->ring_cpu_ptr, 0,
  1419. sizeof(*tx->ring_cpu_ptr) * (tx->ring_size));
  1420. memset(tx->buffer_info, 0,
  1421. sizeof(*tx->buffer_info) * (tx->ring_size));
  1422. }
  1423. static int lan743x_tx_get_desc_cnt(struct lan743x_tx *tx,
  1424. struct sk_buff *skb)
  1425. {
  1426. int result = 1; /* 1 for the main skb buffer */
  1427. int nr_frags = 0;
  1428. if (skb_is_gso(skb))
  1429. result++; /* requires an extension descriptor */
  1430. nr_frags = skb_shinfo(skb)->nr_frags;
  1431. result += nr_frags; /* 1 for each fragment buffer */
  1432. return result;
  1433. }
  1434. static int lan743x_tx_get_avail_desc(struct lan743x_tx *tx)
  1435. {
  1436. int last_head = tx->last_head;
  1437. int last_tail = tx->last_tail;
  1438. if (last_tail >= last_head)
  1439. return tx->ring_size - last_tail + last_head - 1;
  1440. else
  1441. return last_head - last_tail - 1;
  1442. }
  1443. static void lan743x_rx_cfg_b_tstamp_config(struct lan743x_adapter *adapter,
  1444. int rx_ts_config)
  1445. {
  1446. int channel_number;
  1447. int index;
  1448. u32 data;
  1449. for (index = 0; index < LAN743X_USED_RX_CHANNELS; index++) {
  1450. channel_number = adapter->rx[index].channel_number;
  1451. data = lan743x_csr_read(adapter, RX_CFG_B(channel_number));
  1452. data &= RX_CFG_B_TS_MASK_;
  1453. data |= rx_ts_config;
  1454. lan743x_csr_write(adapter, RX_CFG_B(channel_number),
  1455. data);
  1456. }
  1457. }
  1458. int lan743x_rx_set_tstamp_mode(struct lan743x_adapter *adapter,
  1459. int rx_filter)
  1460. {
  1461. u32 data;
  1462. switch (rx_filter) {
  1463. case HWTSTAMP_FILTER_PTP_V2_EVENT:
  1464. lan743x_rx_cfg_b_tstamp_config(adapter,
  1465. RX_CFG_B_TS_DESCR_EN_);
  1466. data = lan743x_csr_read(adapter, PTP_RX_TS_CFG);
  1467. data |= PTP_RX_TS_CFG_EVENT_MSGS_;
  1468. lan743x_csr_write(adapter, PTP_RX_TS_CFG, data);
  1469. break;
  1470. case HWTSTAMP_FILTER_NONE:
  1471. lan743x_rx_cfg_b_tstamp_config(adapter,
  1472. RX_CFG_B_TS_NONE_);
  1473. break;
  1474. case HWTSTAMP_FILTER_ALL:
  1475. lan743x_rx_cfg_b_tstamp_config(adapter,
  1476. RX_CFG_B_TS_ALL_RX_);
  1477. break;
  1478. default:
  1479. return -ERANGE;
  1480. }
  1481. return 0;
  1482. }
  1483. void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx,
  1484. bool enable_timestamping,
  1485. bool enable_onestep_sync)
  1486. {
  1487. if (enable_timestamping)
  1488. tx->ts_flags |= TX_TS_FLAG_TIMESTAMPING_ENABLED;
  1489. else
  1490. tx->ts_flags &= ~TX_TS_FLAG_TIMESTAMPING_ENABLED;
  1491. if (enable_onestep_sync)
  1492. tx->ts_flags |= TX_TS_FLAG_ONE_STEP_SYNC;
  1493. else
  1494. tx->ts_flags &= ~TX_TS_FLAG_ONE_STEP_SYNC;
  1495. }
  1496. static int lan743x_tx_frame_start(struct lan743x_tx *tx,
  1497. unsigned char *first_buffer,
  1498. unsigned int first_buffer_length,
  1499. unsigned int frame_length,
  1500. bool time_stamp,
  1501. bool check_sum)
  1502. {
  1503. /* called only from within lan743x_tx_xmit_frame.
  1504. * assuming tx->ring_lock has already been acquired.
  1505. */
  1506. struct lan743x_tx_descriptor *tx_descriptor = NULL;
  1507. struct lan743x_tx_buffer_info *buffer_info = NULL;
  1508. struct lan743x_adapter *adapter = tx->adapter;
  1509. struct device *dev = &adapter->pdev->dev;
  1510. dma_addr_t dma_ptr;
  1511. tx->frame_flags |= TX_FRAME_FLAG_IN_PROGRESS;
  1512. tx->frame_first = tx->last_tail;
  1513. tx->frame_tail = tx->frame_first;
  1514. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_tail];
  1515. buffer_info = &tx->buffer_info[tx->frame_tail];
  1516. dma_ptr = dma_map_single(dev, first_buffer, first_buffer_length,
  1517. DMA_TO_DEVICE);
  1518. if (dma_mapping_error(dev, dma_ptr))
  1519. return -ENOMEM;
  1520. tx_descriptor->data1 = cpu_to_le32(DMA_ADDR_LOW32(dma_ptr));
  1521. tx_descriptor->data2 = cpu_to_le32(DMA_ADDR_HIGH32(dma_ptr));
  1522. tx_descriptor->data3 = cpu_to_le32((frame_length << 16) &
  1523. TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_);
  1524. buffer_info->skb = NULL;
  1525. buffer_info->dma_ptr = dma_ptr;
  1526. buffer_info->buffer_length = first_buffer_length;
  1527. buffer_info->flags |= TX_BUFFER_INFO_FLAG_ACTIVE;
  1528. tx->frame_data0 = (first_buffer_length &
  1529. TX_DESC_DATA0_BUF_LENGTH_MASK_) |
  1530. TX_DESC_DATA0_DTYPE_DATA_ |
  1531. TX_DESC_DATA0_FS_ |
  1532. TX_DESC_DATA0_FCS_;
  1533. if (time_stamp)
  1534. tx->frame_data0 |= TX_DESC_DATA0_TSE_;
  1535. if (check_sum)
  1536. tx->frame_data0 |= TX_DESC_DATA0_ICE_ |
  1537. TX_DESC_DATA0_IPE_ |
  1538. TX_DESC_DATA0_TPE_;
  1539. /* data0 will be programmed in one of other frame assembler functions */
  1540. return 0;
  1541. }
  1542. static void lan743x_tx_frame_add_lso(struct lan743x_tx *tx,
  1543. unsigned int frame_length,
  1544. int nr_frags)
  1545. {
  1546. /* called only from within lan743x_tx_xmit_frame.
  1547. * assuming tx->ring_lock has already been acquired.
  1548. */
  1549. struct lan743x_tx_descriptor *tx_descriptor = NULL;
  1550. struct lan743x_tx_buffer_info *buffer_info = NULL;
  1551. /* wrap up previous descriptor */
  1552. tx->frame_data0 |= TX_DESC_DATA0_EXT_;
  1553. if (nr_frags <= 0) {
  1554. tx->frame_data0 |= TX_DESC_DATA0_LS_;
  1555. tx->frame_data0 |= TX_DESC_DATA0_IOC_;
  1556. tx->frame_last = tx->frame_first;
  1557. }
  1558. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_tail];
  1559. tx_descriptor->data0 = cpu_to_le32(tx->frame_data0);
  1560. /* move to next descriptor */
  1561. tx->frame_tail = lan743x_tx_next_index(tx, tx->frame_tail);
  1562. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_tail];
  1563. buffer_info = &tx->buffer_info[tx->frame_tail];
  1564. /* add extension descriptor */
  1565. tx_descriptor->data1 = 0;
  1566. tx_descriptor->data2 = 0;
  1567. tx_descriptor->data3 = 0;
  1568. buffer_info->skb = NULL;
  1569. buffer_info->dma_ptr = 0;
  1570. buffer_info->buffer_length = 0;
  1571. buffer_info->flags |= TX_BUFFER_INFO_FLAG_ACTIVE;
  1572. tx->frame_data0 = (frame_length & TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_) |
  1573. TX_DESC_DATA0_DTYPE_EXT_ |
  1574. TX_DESC_DATA0_EXT_LSO_;
  1575. /* data0 will be programmed in one of other frame assembler functions */
  1576. }
  1577. static int lan743x_tx_frame_add_fragment(struct lan743x_tx *tx,
  1578. const skb_frag_t *fragment,
  1579. unsigned int frame_length)
  1580. {
  1581. /* called only from within lan743x_tx_xmit_frame
  1582. * assuming tx->ring_lock has already been acquired
  1583. */
  1584. struct lan743x_tx_descriptor *tx_descriptor = NULL;
  1585. struct lan743x_tx_buffer_info *buffer_info = NULL;
  1586. struct lan743x_adapter *adapter = tx->adapter;
  1587. struct device *dev = &adapter->pdev->dev;
  1588. unsigned int fragment_length = 0;
  1589. dma_addr_t dma_ptr;
  1590. fragment_length = skb_frag_size(fragment);
  1591. if (!fragment_length)
  1592. return 0;
  1593. /* wrap up previous descriptor */
  1594. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_tail];
  1595. tx_descriptor->data0 = cpu_to_le32(tx->frame_data0);
  1596. /* move to next descriptor */
  1597. tx->frame_tail = lan743x_tx_next_index(tx, tx->frame_tail);
  1598. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_tail];
  1599. buffer_info = &tx->buffer_info[tx->frame_tail];
  1600. dma_ptr = skb_frag_dma_map(dev, fragment,
  1601. 0, fragment_length,
  1602. DMA_TO_DEVICE);
  1603. if (dma_mapping_error(dev, dma_ptr)) {
  1604. int desc_index;
  1605. /* cleanup all previously setup descriptors */
  1606. desc_index = tx->frame_first;
  1607. while (desc_index != tx->frame_tail) {
  1608. lan743x_tx_release_desc(tx, desc_index, true);
  1609. desc_index = lan743x_tx_next_index(tx, desc_index);
  1610. }
  1611. dma_wmb();
  1612. tx->frame_flags &= ~TX_FRAME_FLAG_IN_PROGRESS;
  1613. tx->frame_first = 0;
  1614. tx->frame_data0 = 0;
  1615. tx->frame_tail = 0;
  1616. tx->frame_last = 0;
  1617. return -ENOMEM;
  1618. }
  1619. tx_descriptor->data1 = cpu_to_le32(DMA_ADDR_LOW32(dma_ptr));
  1620. tx_descriptor->data2 = cpu_to_le32(DMA_ADDR_HIGH32(dma_ptr));
  1621. tx_descriptor->data3 = cpu_to_le32((frame_length << 16) &
  1622. TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_);
  1623. buffer_info->skb = NULL;
  1624. buffer_info->dma_ptr = dma_ptr;
  1625. buffer_info->buffer_length = fragment_length;
  1626. buffer_info->flags |= TX_BUFFER_INFO_FLAG_ACTIVE;
  1627. buffer_info->flags |= TX_BUFFER_INFO_FLAG_SKB_FRAGMENT;
  1628. tx->frame_data0 = (fragment_length & TX_DESC_DATA0_BUF_LENGTH_MASK_) |
  1629. TX_DESC_DATA0_DTYPE_DATA_ |
  1630. TX_DESC_DATA0_FCS_;
  1631. /* data0 will be programmed in one of other frame assembler functions */
  1632. return 0;
  1633. }
  1634. static void lan743x_tx_frame_end(struct lan743x_tx *tx,
  1635. struct sk_buff *skb,
  1636. bool time_stamp,
  1637. bool ignore_sync)
  1638. {
  1639. /* called only from within lan743x_tx_xmit_frame
  1640. * assuming tx->ring_lock has already been acquired
  1641. */
  1642. struct lan743x_tx_descriptor *tx_descriptor = NULL;
  1643. struct lan743x_tx_buffer_info *buffer_info = NULL;
  1644. struct lan743x_adapter *adapter = tx->adapter;
  1645. u32 tx_tail_flags = 0;
  1646. /* wrap up previous descriptor */
  1647. if ((tx->frame_data0 & TX_DESC_DATA0_DTYPE_MASK_) ==
  1648. TX_DESC_DATA0_DTYPE_DATA_) {
  1649. tx->frame_data0 |= TX_DESC_DATA0_LS_;
  1650. tx->frame_data0 |= TX_DESC_DATA0_IOC_;
  1651. tx->frame_last = tx->frame_tail;
  1652. }
  1653. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_last];
  1654. buffer_info = &tx->buffer_info[tx->frame_last];
  1655. buffer_info->skb = skb;
  1656. if (time_stamp)
  1657. buffer_info->flags |= TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED;
  1658. if (ignore_sync)
  1659. buffer_info->flags |= TX_BUFFER_INFO_FLAG_IGNORE_SYNC;
  1660. tx_descriptor = &tx->ring_cpu_ptr[tx->frame_tail];
  1661. tx_descriptor->data0 = cpu_to_le32(tx->frame_data0);
  1662. tx->frame_tail = lan743x_tx_next_index(tx, tx->frame_tail);
  1663. tx->last_tail = tx->frame_tail;
  1664. dma_wmb();
  1665. if (tx->vector_flags & LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET)
  1666. tx_tail_flags |= TX_TAIL_SET_TOP_INT_VEC_EN_;
  1667. if (tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET)
  1668. tx_tail_flags |= TX_TAIL_SET_DMAC_INT_EN_ |
  1669. TX_TAIL_SET_TOP_INT_EN_;
  1670. lan743x_csr_write(adapter, TX_TAIL(tx->channel_number),
  1671. tx_tail_flags | tx->frame_tail);
  1672. tx->frame_flags &= ~TX_FRAME_FLAG_IN_PROGRESS;
  1673. }
  1674. static netdev_tx_t lan743x_tx_xmit_frame(struct lan743x_tx *tx,
  1675. struct sk_buff *skb)
  1676. {
  1677. int required_number_of_descriptors = 0;
  1678. unsigned int start_frame_length = 0;
  1679. netdev_tx_t retval = NETDEV_TX_OK;
  1680. unsigned int frame_length = 0;
  1681. unsigned int head_length = 0;
  1682. unsigned long irq_flags = 0;
  1683. bool do_timestamp = false;
  1684. bool ignore_sync = false;
  1685. struct netdev_queue *txq;
  1686. int nr_frags = 0;
  1687. bool gso = false;
  1688. int j;
  1689. required_number_of_descriptors = lan743x_tx_get_desc_cnt(tx, skb);
  1690. spin_lock_irqsave(&tx->ring_lock, irq_flags);
  1691. if (required_number_of_descriptors >
  1692. lan743x_tx_get_avail_desc(tx)) {
  1693. if (required_number_of_descriptors > (tx->ring_size - 1)) {
  1694. dev_kfree_skb_irq(skb);
  1695. } else {
  1696. /* save how many descriptors we needed to restart the queue */
  1697. tx->rqd_descriptors = required_number_of_descriptors;
  1698. retval = NETDEV_TX_BUSY;
  1699. txq = netdev_get_tx_queue(tx->adapter->netdev,
  1700. tx->channel_number);
  1701. netif_tx_stop_queue(txq);
  1702. }
  1703. goto unlock;
  1704. }
  1705. /* space available, transmit skb */
  1706. if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
  1707. (tx->ts_flags & TX_TS_FLAG_TIMESTAMPING_ENABLED) &&
  1708. (lan743x_ptp_request_tx_timestamp(tx->adapter))) {
  1709. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  1710. do_timestamp = true;
  1711. if (tx->ts_flags & TX_TS_FLAG_ONE_STEP_SYNC)
  1712. ignore_sync = true;
  1713. }
  1714. head_length = skb_headlen(skb);
  1715. frame_length = skb_pagelen(skb);
  1716. nr_frags = skb_shinfo(skb)->nr_frags;
  1717. start_frame_length = frame_length;
  1718. gso = skb_is_gso(skb);
  1719. if (gso) {
  1720. start_frame_length = max(skb_shinfo(skb)->gso_size,
  1721. (unsigned short)8);
  1722. }
  1723. if (lan743x_tx_frame_start(tx,
  1724. skb->data, head_length,
  1725. start_frame_length,
  1726. do_timestamp,
  1727. skb->ip_summed == CHECKSUM_PARTIAL)) {
  1728. dev_kfree_skb_irq(skb);
  1729. goto unlock;
  1730. }
  1731. tx->frame_count++;
  1732. if (gso)
  1733. lan743x_tx_frame_add_lso(tx, frame_length, nr_frags);
  1734. if (nr_frags <= 0)
  1735. goto finish;
  1736. for (j = 0; j < nr_frags; j++) {
  1737. const skb_frag_t *frag = &(skb_shinfo(skb)->frags[j]);
  1738. if (lan743x_tx_frame_add_fragment(tx, frag, frame_length)) {
  1739. /* upon error no need to call
  1740. * lan743x_tx_frame_end
  1741. * frame assembler clean up was performed inside
  1742. * lan743x_tx_frame_add_fragment
  1743. */
  1744. dev_kfree_skb_irq(skb);
  1745. goto unlock;
  1746. }
  1747. }
  1748. finish:
  1749. lan743x_tx_frame_end(tx, skb, do_timestamp, ignore_sync);
  1750. unlock:
  1751. spin_unlock_irqrestore(&tx->ring_lock, irq_flags);
  1752. return retval;
  1753. }
  1754. static int lan743x_tx_napi_poll(struct napi_struct *napi, int weight)
  1755. {
  1756. struct lan743x_tx *tx = container_of(napi, struct lan743x_tx, napi);
  1757. struct lan743x_adapter *adapter = tx->adapter;
  1758. unsigned long irq_flags = 0;
  1759. struct netdev_queue *txq;
  1760. u32 ioc_bit = 0;
  1761. ioc_bit = DMAC_INT_BIT_TX_IOC_(tx->channel_number);
  1762. lan743x_csr_read(adapter, DMAC_INT_STS);
  1763. if (tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C)
  1764. lan743x_csr_write(adapter, DMAC_INT_STS, ioc_bit);
  1765. spin_lock_irqsave(&tx->ring_lock, irq_flags);
  1766. /* clean up tx ring */
  1767. lan743x_tx_release_completed_descriptors(tx);
  1768. txq = netdev_get_tx_queue(adapter->netdev, tx->channel_number);
  1769. if (netif_tx_queue_stopped(txq)) {
  1770. if (tx->rqd_descriptors) {
  1771. if (tx->rqd_descriptors <=
  1772. lan743x_tx_get_avail_desc(tx)) {
  1773. tx->rqd_descriptors = 0;
  1774. netif_tx_wake_queue(txq);
  1775. }
  1776. } else {
  1777. netif_tx_wake_queue(txq);
  1778. }
  1779. }
  1780. spin_unlock_irqrestore(&tx->ring_lock, irq_flags);
  1781. if (!napi_complete(napi))
  1782. goto done;
  1783. /* enable isr */
  1784. lan743x_csr_write(adapter, INT_EN_SET,
  1785. INT_BIT_DMA_TX_(tx->channel_number));
  1786. lan743x_csr_read(adapter, INT_STS);
  1787. done:
  1788. return 0;
  1789. }
  1790. static void lan743x_tx_ring_cleanup(struct lan743x_tx *tx)
  1791. {
  1792. if (tx->head_cpu_ptr) {
  1793. dma_free_coherent(&tx->adapter->pdev->dev,
  1794. sizeof(*tx->head_cpu_ptr), tx->head_cpu_ptr,
  1795. tx->head_dma_ptr);
  1796. tx->head_cpu_ptr = NULL;
  1797. tx->head_dma_ptr = 0;
  1798. }
  1799. kfree(tx->buffer_info);
  1800. tx->buffer_info = NULL;
  1801. if (tx->ring_cpu_ptr) {
  1802. dma_free_coherent(&tx->adapter->pdev->dev,
  1803. tx->ring_allocation_size, tx->ring_cpu_ptr,
  1804. tx->ring_dma_ptr);
  1805. tx->ring_allocation_size = 0;
  1806. tx->ring_cpu_ptr = NULL;
  1807. tx->ring_dma_ptr = 0;
  1808. }
  1809. tx->ring_size = 0;
  1810. }
  1811. static int lan743x_tx_ring_init(struct lan743x_tx *tx)
  1812. {
  1813. size_t ring_allocation_size = 0;
  1814. void *cpu_ptr = NULL;
  1815. dma_addr_t dma_ptr;
  1816. int ret = -ENOMEM;
  1817. tx->ring_size = LAN743X_TX_RING_SIZE;
  1818. if (tx->ring_size & ~TX_CFG_B_TX_RING_LEN_MASK_) {
  1819. ret = -EINVAL;
  1820. goto cleanup;
  1821. }
  1822. if (dma_set_mask_and_coherent(&tx->adapter->pdev->dev,
  1823. DMA_BIT_MASK(64))) {
  1824. dev_warn(&tx->adapter->pdev->dev,
  1825. "lan743x_: No suitable DMA available\n");
  1826. ret = -ENOMEM;
  1827. goto cleanup;
  1828. }
  1829. ring_allocation_size = ALIGN(tx->ring_size *
  1830. sizeof(struct lan743x_tx_descriptor),
  1831. PAGE_SIZE);
  1832. dma_ptr = 0;
  1833. cpu_ptr = dma_alloc_coherent(&tx->adapter->pdev->dev,
  1834. ring_allocation_size, &dma_ptr, GFP_KERNEL);
  1835. if (!cpu_ptr) {
  1836. ret = -ENOMEM;
  1837. goto cleanup;
  1838. }
  1839. tx->ring_allocation_size = ring_allocation_size;
  1840. tx->ring_cpu_ptr = (struct lan743x_tx_descriptor *)cpu_ptr;
  1841. tx->ring_dma_ptr = dma_ptr;
  1842. cpu_ptr = kcalloc(tx->ring_size, sizeof(*tx->buffer_info), GFP_KERNEL);
  1843. if (!cpu_ptr) {
  1844. ret = -ENOMEM;
  1845. goto cleanup;
  1846. }
  1847. tx->buffer_info = (struct lan743x_tx_buffer_info *)cpu_ptr;
  1848. dma_ptr = 0;
  1849. cpu_ptr = dma_alloc_coherent(&tx->adapter->pdev->dev,
  1850. sizeof(*tx->head_cpu_ptr), &dma_ptr,
  1851. GFP_KERNEL);
  1852. if (!cpu_ptr) {
  1853. ret = -ENOMEM;
  1854. goto cleanup;
  1855. }
  1856. tx->head_cpu_ptr = cpu_ptr;
  1857. tx->head_dma_ptr = dma_ptr;
  1858. if (tx->head_dma_ptr & 0x3) {
  1859. ret = -ENOMEM;
  1860. goto cleanup;
  1861. }
  1862. return 0;
  1863. cleanup:
  1864. lan743x_tx_ring_cleanup(tx);
  1865. return ret;
  1866. }
  1867. static void lan743x_tx_close(struct lan743x_tx *tx)
  1868. {
  1869. struct lan743x_adapter *adapter = tx->adapter;
  1870. lan743x_csr_write(adapter,
  1871. DMAC_CMD,
  1872. DMAC_CMD_STOP_T_(tx->channel_number));
  1873. lan743x_dmac_tx_wait_till_stopped(adapter, tx->channel_number);
  1874. lan743x_csr_write(adapter,
  1875. DMAC_INT_EN_CLR,
  1876. DMAC_INT_BIT_TX_IOC_(tx->channel_number));
  1877. lan743x_csr_write(adapter, INT_EN_CLR,
  1878. INT_BIT_DMA_TX_(tx->channel_number));
  1879. napi_disable(&tx->napi);
  1880. netif_napi_del(&tx->napi);
  1881. lan743x_csr_write(adapter, FCT_TX_CTL,
  1882. FCT_TX_CTL_DIS_(tx->channel_number));
  1883. lan743x_csr_wait_for_bit(adapter, FCT_TX_CTL,
  1884. FCT_TX_CTL_EN_(tx->channel_number),
  1885. 0, 1000, 20000, 100);
  1886. lan743x_tx_release_all_descriptors(tx);
  1887. tx->rqd_descriptors = 0;
  1888. lan743x_tx_ring_cleanup(tx);
  1889. }
  1890. static int lan743x_tx_open(struct lan743x_tx *tx)
  1891. {
  1892. struct lan743x_adapter *adapter = NULL;
  1893. u32 data = 0;
  1894. int ret;
  1895. adapter = tx->adapter;
  1896. ret = lan743x_tx_ring_init(tx);
  1897. if (ret)
  1898. return ret;
  1899. /* initialize fifo */
  1900. lan743x_csr_write(adapter, FCT_TX_CTL,
  1901. FCT_TX_CTL_RESET_(tx->channel_number));
  1902. lan743x_csr_wait_for_bit(adapter, FCT_TX_CTL,
  1903. FCT_TX_CTL_RESET_(tx->channel_number),
  1904. 0, 1000, 20000, 100);
  1905. /* enable fifo */
  1906. lan743x_csr_write(adapter, FCT_TX_CTL,
  1907. FCT_TX_CTL_EN_(tx->channel_number));
  1908. /* reset tx channel */
  1909. lan743x_csr_write(adapter, DMAC_CMD,
  1910. DMAC_CMD_TX_SWR_(tx->channel_number));
  1911. lan743x_csr_wait_for_bit(adapter, DMAC_CMD,
  1912. DMAC_CMD_TX_SWR_(tx->channel_number),
  1913. 0, 1000, 20000, 100);
  1914. /* Write TX_BASE_ADDR */
  1915. lan743x_csr_write(adapter,
  1916. TX_BASE_ADDRH(tx->channel_number),
  1917. DMA_ADDR_HIGH32(tx->ring_dma_ptr));
  1918. lan743x_csr_write(adapter,
  1919. TX_BASE_ADDRL(tx->channel_number),
  1920. DMA_ADDR_LOW32(tx->ring_dma_ptr));
  1921. /* Write TX_CFG_B */
  1922. data = lan743x_csr_read(adapter, TX_CFG_B(tx->channel_number));
  1923. data &= ~TX_CFG_B_TX_RING_LEN_MASK_;
  1924. data |= ((tx->ring_size) & TX_CFG_B_TX_RING_LEN_MASK_);
  1925. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0))
  1926. data |= TX_CFG_B_TDMABL_512_;
  1927. lan743x_csr_write(adapter, TX_CFG_B(tx->channel_number), data);
  1928. /* Write TX_CFG_A */
  1929. data = TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ | TX_CFG_A_TX_HP_WB_EN_;
  1930. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0)) {
  1931. data |= TX_CFG_A_TX_HP_WB_ON_INT_TMR_;
  1932. data |= TX_CFG_A_TX_PF_THRES_SET_(0x10);
  1933. data |= TX_CFG_A_TX_PF_PRI_THRES_SET_(0x04);
  1934. data |= TX_CFG_A_TX_HP_WB_THRES_SET_(0x07);
  1935. }
  1936. lan743x_csr_write(adapter, TX_CFG_A(tx->channel_number), data);
  1937. /* Write TX_HEAD_WRITEBACK_ADDR */
  1938. lan743x_csr_write(adapter,
  1939. TX_HEAD_WRITEBACK_ADDRH(tx->channel_number),
  1940. DMA_ADDR_HIGH32(tx->head_dma_ptr));
  1941. lan743x_csr_write(adapter,
  1942. TX_HEAD_WRITEBACK_ADDRL(tx->channel_number),
  1943. DMA_ADDR_LOW32(tx->head_dma_ptr));
  1944. /* set last head */
  1945. tx->last_head = lan743x_csr_read(adapter, TX_HEAD(tx->channel_number));
  1946. /* write TX_TAIL */
  1947. tx->last_tail = 0;
  1948. lan743x_csr_write(adapter, TX_TAIL(tx->channel_number),
  1949. (u32)(tx->last_tail));
  1950. tx->vector_flags = lan743x_intr_get_vector_flags(adapter,
  1951. INT_BIT_DMA_TX_
  1952. (tx->channel_number));
  1953. netif_napi_add_tx_weight(adapter->netdev,
  1954. &tx->napi, lan743x_tx_napi_poll,
  1955. NAPI_POLL_WEIGHT);
  1956. napi_enable(&tx->napi);
  1957. data = 0;
  1958. if (tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR)
  1959. data |= TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_;
  1960. if (tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR)
  1961. data |= TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_;
  1962. if (tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C)
  1963. data |= TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_;
  1964. if (tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C)
  1965. data |= TX_CFG_C_TX_INT_EN_R2C_;
  1966. lan743x_csr_write(adapter, TX_CFG_C(tx->channel_number), data);
  1967. if (!(tx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET))
  1968. lan743x_csr_write(adapter, INT_EN_SET,
  1969. INT_BIT_DMA_TX_(tx->channel_number));
  1970. lan743x_csr_write(adapter, DMAC_INT_EN_SET,
  1971. DMAC_INT_BIT_TX_IOC_(tx->channel_number));
  1972. /* start dmac channel */
  1973. lan743x_csr_write(adapter, DMAC_CMD,
  1974. DMAC_CMD_START_T_(tx->channel_number));
  1975. return 0;
  1976. }
  1977. static int lan743x_rx_next_index(struct lan743x_rx *rx, int index)
  1978. {
  1979. return ((++index) % rx->ring_size);
  1980. }
  1981. static void lan743x_rx_update_tail(struct lan743x_rx *rx, int index)
  1982. {
  1983. /* update the tail once per 8 descriptors */
  1984. if ((index & 7) == 7)
  1985. lan743x_csr_write(rx->adapter, RX_TAIL(rx->channel_number),
  1986. index);
  1987. }
  1988. static int lan743x_rx_init_ring_element(struct lan743x_rx *rx, int index,
  1989. gfp_t gfp)
  1990. {
  1991. struct net_device *netdev = rx->adapter->netdev;
  1992. struct device *dev = &rx->adapter->pdev->dev;
  1993. struct lan743x_rx_buffer_info *buffer_info;
  1994. unsigned int buffer_length, used_length;
  1995. struct lan743x_rx_descriptor *descriptor;
  1996. struct sk_buff *skb;
  1997. dma_addr_t dma_ptr;
  1998. buffer_length = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + RX_HEAD_PADDING;
  1999. descriptor = &rx->ring_cpu_ptr[index];
  2000. buffer_info = &rx->buffer_info[index];
  2001. skb = __netdev_alloc_skb(netdev, buffer_length, gfp);
  2002. if (!skb)
  2003. return -ENOMEM;
  2004. dma_ptr = dma_map_single(dev, skb->data, buffer_length, DMA_FROM_DEVICE);
  2005. if (dma_mapping_error(dev, dma_ptr)) {
  2006. dev_kfree_skb_any(skb);
  2007. return -ENOMEM;
  2008. }
  2009. if (buffer_info->dma_ptr) {
  2010. /* sync used area of buffer only */
  2011. if (le32_to_cpu(descriptor->data0) & RX_DESC_DATA0_LS_)
  2012. /* frame length is valid only if LS bit is set.
  2013. * it's a safe upper bound for the used area in this
  2014. * buffer.
  2015. */
  2016. used_length = min(RX_DESC_DATA0_FRAME_LENGTH_GET_
  2017. (le32_to_cpu(descriptor->data0)),
  2018. buffer_info->buffer_length);
  2019. else
  2020. used_length = buffer_info->buffer_length;
  2021. dma_sync_single_for_cpu(dev, buffer_info->dma_ptr,
  2022. used_length,
  2023. DMA_FROM_DEVICE);
  2024. dma_unmap_single_attrs(dev, buffer_info->dma_ptr,
  2025. buffer_info->buffer_length,
  2026. DMA_FROM_DEVICE,
  2027. DMA_ATTR_SKIP_CPU_SYNC);
  2028. }
  2029. buffer_info->skb = skb;
  2030. buffer_info->dma_ptr = dma_ptr;
  2031. buffer_info->buffer_length = buffer_length;
  2032. descriptor->data1 = cpu_to_le32(DMA_ADDR_LOW32(buffer_info->dma_ptr));
  2033. descriptor->data2 = cpu_to_le32(DMA_ADDR_HIGH32(buffer_info->dma_ptr));
  2034. descriptor->data3 = 0;
  2035. descriptor->data0 = cpu_to_le32((RX_DESC_DATA0_OWN_ |
  2036. (buffer_length & RX_DESC_DATA0_BUF_LENGTH_MASK_)));
  2037. lan743x_rx_update_tail(rx, index);
  2038. return 0;
  2039. }
  2040. static void lan743x_rx_reuse_ring_element(struct lan743x_rx *rx, int index)
  2041. {
  2042. struct lan743x_rx_buffer_info *buffer_info;
  2043. struct lan743x_rx_descriptor *descriptor;
  2044. descriptor = &rx->ring_cpu_ptr[index];
  2045. buffer_info = &rx->buffer_info[index];
  2046. descriptor->data1 = cpu_to_le32(DMA_ADDR_LOW32(buffer_info->dma_ptr));
  2047. descriptor->data2 = cpu_to_le32(DMA_ADDR_HIGH32(buffer_info->dma_ptr));
  2048. descriptor->data3 = 0;
  2049. descriptor->data0 = cpu_to_le32((RX_DESC_DATA0_OWN_ |
  2050. ((buffer_info->buffer_length) &
  2051. RX_DESC_DATA0_BUF_LENGTH_MASK_)));
  2052. lan743x_rx_update_tail(rx, index);
  2053. }
  2054. static void lan743x_rx_release_ring_element(struct lan743x_rx *rx, int index)
  2055. {
  2056. struct lan743x_rx_buffer_info *buffer_info;
  2057. struct lan743x_rx_descriptor *descriptor;
  2058. descriptor = &rx->ring_cpu_ptr[index];
  2059. buffer_info = &rx->buffer_info[index];
  2060. memset(descriptor, 0, sizeof(*descriptor));
  2061. if (buffer_info->dma_ptr) {
  2062. dma_unmap_single(&rx->adapter->pdev->dev,
  2063. buffer_info->dma_ptr,
  2064. buffer_info->buffer_length,
  2065. DMA_FROM_DEVICE);
  2066. buffer_info->dma_ptr = 0;
  2067. }
  2068. if (buffer_info->skb) {
  2069. dev_kfree_skb(buffer_info->skb);
  2070. buffer_info->skb = NULL;
  2071. }
  2072. memset(buffer_info, 0, sizeof(*buffer_info));
  2073. }
  2074. static struct sk_buff *
  2075. lan743x_rx_trim_skb(struct sk_buff *skb, int frame_length)
  2076. {
  2077. if (skb_linearize(skb)) {
  2078. dev_kfree_skb_irq(skb);
  2079. return NULL;
  2080. }
  2081. frame_length = max_t(int, 0, frame_length - ETH_FCS_LEN);
  2082. if (skb->len > frame_length) {
  2083. skb->tail -= skb->len - frame_length;
  2084. skb->len = frame_length;
  2085. }
  2086. return skb;
  2087. }
  2088. static int lan743x_rx_process_buffer(struct lan743x_rx *rx)
  2089. {
  2090. int current_head_index = le32_to_cpu(*rx->head_cpu_ptr);
  2091. struct lan743x_rx_descriptor *descriptor, *desc_ext;
  2092. struct net_device *netdev = rx->adapter->netdev;
  2093. int result = RX_PROCESS_RESULT_NOTHING_TO_DO;
  2094. struct lan743x_rx_buffer_info *buffer_info;
  2095. int frame_length, buffer_length;
  2096. bool is_ice, is_tce, is_icsm;
  2097. int extension_index = -1;
  2098. bool is_last, is_first;
  2099. struct sk_buff *skb;
  2100. if (current_head_index < 0 || current_head_index >= rx->ring_size)
  2101. goto done;
  2102. if (rx->last_head < 0 || rx->last_head >= rx->ring_size)
  2103. goto done;
  2104. if (rx->last_head == current_head_index)
  2105. goto done;
  2106. descriptor = &rx->ring_cpu_ptr[rx->last_head];
  2107. if (le32_to_cpu(descriptor->data0) & RX_DESC_DATA0_OWN_)
  2108. goto done;
  2109. buffer_info = &rx->buffer_info[rx->last_head];
  2110. is_last = le32_to_cpu(descriptor->data0) & RX_DESC_DATA0_LS_;
  2111. is_first = le32_to_cpu(descriptor->data0) & RX_DESC_DATA0_FS_;
  2112. if (is_last && le32_to_cpu(descriptor->data0) & RX_DESC_DATA0_EXT_) {
  2113. /* extension is expected to follow */
  2114. int index = lan743x_rx_next_index(rx, rx->last_head);
  2115. if (index == current_head_index)
  2116. /* extension not yet available */
  2117. goto done;
  2118. desc_ext = &rx->ring_cpu_ptr[index];
  2119. if (le32_to_cpu(desc_ext->data0) & RX_DESC_DATA0_OWN_)
  2120. /* extension not yet available */
  2121. goto done;
  2122. if (!(le32_to_cpu(desc_ext->data0) & RX_DESC_DATA0_EXT_))
  2123. goto move_forward;
  2124. extension_index = index;
  2125. }
  2126. /* Only the last buffer in a multi-buffer frame contains the total frame
  2127. * length. The chip occasionally sends more buffers than strictly
  2128. * required to reach the total frame length.
  2129. * Handle this by adding all buffers to the skb in their entirety.
  2130. * Once the real frame length is known, trim the skb.
  2131. */
  2132. frame_length =
  2133. RX_DESC_DATA0_FRAME_LENGTH_GET_(le32_to_cpu(descriptor->data0));
  2134. buffer_length = buffer_info->buffer_length;
  2135. is_ice = le32_to_cpu(descriptor->data1) & RX_DESC_DATA1_STATUS_ICE_;
  2136. is_tce = le32_to_cpu(descriptor->data1) & RX_DESC_DATA1_STATUS_TCE_;
  2137. is_icsm = le32_to_cpu(descriptor->data1) & RX_DESC_DATA1_STATUS_ICSM_;
  2138. netdev_dbg(netdev, "%s%schunk: %d/%d",
  2139. is_first ? "first " : " ",
  2140. is_last ? "last " : " ",
  2141. frame_length, buffer_length);
  2142. /* save existing skb, allocate new skb and map to dma */
  2143. skb = buffer_info->skb;
  2144. if (lan743x_rx_init_ring_element(rx, rx->last_head,
  2145. GFP_ATOMIC | GFP_DMA)) {
  2146. /* failed to allocate next skb.
  2147. * Memory is very low.
  2148. * Drop this packet and reuse buffer.
  2149. */
  2150. lan743x_rx_reuse_ring_element(rx, rx->last_head);
  2151. /* drop packet that was being assembled */
  2152. dev_kfree_skb_irq(rx->skb_head);
  2153. rx->skb_head = NULL;
  2154. goto process_extension;
  2155. }
  2156. /* add buffers to skb via skb->frag_list */
  2157. if (is_first) {
  2158. skb_reserve(skb, RX_HEAD_PADDING);
  2159. skb_put(skb, buffer_length - RX_HEAD_PADDING);
  2160. if (rx->skb_head)
  2161. dev_kfree_skb_irq(rx->skb_head);
  2162. rx->skb_head = skb;
  2163. } else if (rx->skb_head) {
  2164. skb_put(skb, buffer_length);
  2165. if (skb_shinfo(rx->skb_head)->frag_list)
  2166. rx->skb_tail->next = skb;
  2167. else
  2168. skb_shinfo(rx->skb_head)->frag_list = skb;
  2169. rx->skb_tail = skb;
  2170. rx->skb_head->len += skb->len;
  2171. rx->skb_head->data_len += skb->len;
  2172. rx->skb_head->truesize += skb->truesize;
  2173. } else {
  2174. /* packet to assemble has already been dropped because one or
  2175. * more of its buffers could not be allocated
  2176. */
  2177. netdev_dbg(netdev, "drop buffer intended for dropped packet");
  2178. dev_kfree_skb_irq(skb);
  2179. }
  2180. process_extension:
  2181. if (extension_index >= 0) {
  2182. u32 ts_sec;
  2183. u32 ts_nsec;
  2184. ts_sec = le32_to_cpu(desc_ext->data1);
  2185. ts_nsec = (le32_to_cpu(desc_ext->data2) &
  2186. RX_DESC_DATA2_TS_NS_MASK_);
  2187. if (rx->skb_head)
  2188. skb_hwtstamps(rx->skb_head)->hwtstamp =
  2189. ktime_set(ts_sec, ts_nsec);
  2190. lan743x_rx_reuse_ring_element(rx, extension_index);
  2191. rx->last_head = extension_index;
  2192. netdev_dbg(netdev, "process extension");
  2193. }
  2194. if (is_last && rx->skb_head)
  2195. rx->skb_head = lan743x_rx_trim_skb(rx->skb_head, frame_length);
  2196. if (is_last && rx->skb_head) {
  2197. rx->skb_head->protocol = eth_type_trans(rx->skb_head,
  2198. rx->adapter->netdev);
  2199. if (rx->adapter->netdev->features & NETIF_F_RXCSUM) {
  2200. if (!is_ice && !is_tce && !is_icsm)
  2201. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2202. }
  2203. netdev_dbg(netdev, "sending %d byte frame to OS",
  2204. rx->skb_head->len);
  2205. napi_gro_receive(&rx->napi, rx->skb_head);
  2206. rx->skb_head = NULL;
  2207. }
  2208. move_forward:
  2209. /* push tail and head forward */
  2210. rx->last_tail = rx->last_head;
  2211. rx->last_head = lan743x_rx_next_index(rx, rx->last_head);
  2212. result = RX_PROCESS_RESULT_BUFFER_RECEIVED;
  2213. done:
  2214. return result;
  2215. }
  2216. static int lan743x_rx_napi_poll(struct napi_struct *napi, int weight)
  2217. {
  2218. struct lan743x_rx *rx = container_of(napi, struct lan743x_rx, napi);
  2219. struct lan743x_adapter *adapter = rx->adapter;
  2220. int result = RX_PROCESS_RESULT_NOTHING_TO_DO;
  2221. u32 rx_tail_flags = 0;
  2222. int count;
  2223. if (rx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C) {
  2224. /* clear int status bit before reading packet */
  2225. lan743x_csr_write(adapter, DMAC_INT_STS,
  2226. DMAC_INT_BIT_RXFRM_(rx->channel_number));
  2227. }
  2228. for (count = 0; count < weight; count++) {
  2229. result = lan743x_rx_process_buffer(rx);
  2230. if (result == RX_PROCESS_RESULT_NOTHING_TO_DO)
  2231. break;
  2232. }
  2233. rx->frame_count += count;
  2234. if (count == weight || result == RX_PROCESS_RESULT_BUFFER_RECEIVED)
  2235. return weight;
  2236. if (!napi_complete_done(napi, count))
  2237. return count;
  2238. /* re-arm interrupts, must write to rx tail on some chip variants */
  2239. if (rx->vector_flags & LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET)
  2240. rx_tail_flags |= RX_TAIL_SET_TOP_INT_VEC_EN_;
  2241. if (rx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET) {
  2242. rx_tail_flags |= RX_TAIL_SET_TOP_INT_EN_;
  2243. } else {
  2244. lan743x_csr_write(adapter, INT_EN_SET,
  2245. INT_BIT_DMA_RX_(rx->channel_number));
  2246. }
  2247. if (rx_tail_flags)
  2248. lan743x_csr_write(adapter, RX_TAIL(rx->channel_number),
  2249. rx_tail_flags | rx->last_tail);
  2250. return count;
  2251. }
  2252. static void lan743x_rx_ring_cleanup(struct lan743x_rx *rx)
  2253. {
  2254. if (rx->buffer_info && rx->ring_cpu_ptr) {
  2255. int index;
  2256. for (index = 0; index < rx->ring_size; index++)
  2257. lan743x_rx_release_ring_element(rx, index);
  2258. }
  2259. if (rx->head_cpu_ptr) {
  2260. dma_free_coherent(&rx->adapter->pdev->dev,
  2261. sizeof(*rx->head_cpu_ptr), rx->head_cpu_ptr,
  2262. rx->head_dma_ptr);
  2263. rx->head_cpu_ptr = NULL;
  2264. rx->head_dma_ptr = 0;
  2265. }
  2266. kfree(rx->buffer_info);
  2267. rx->buffer_info = NULL;
  2268. if (rx->ring_cpu_ptr) {
  2269. dma_free_coherent(&rx->adapter->pdev->dev,
  2270. rx->ring_allocation_size, rx->ring_cpu_ptr,
  2271. rx->ring_dma_ptr);
  2272. rx->ring_allocation_size = 0;
  2273. rx->ring_cpu_ptr = NULL;
  2274. rx->ring_dma_ptr = 0;
  2275. }
  2276. rx->ring_size = 0;
  2277. rx->last_head = 0;
  2278. }
  2279. static int lan743x_rx_ring_init(struct lan743x_rx *rx)
  2280. {
  2281. size_t ring_allocation_size = 0;
  2282. dma_addr_t dma_ptr = 0;
  2283. void *cpu_ptr = NULL;
  2284. int ret = -ENOMEM;
  2285. int index = 0;
  2286. rx->ring_size = LAN743X_RX_RING_SIZE;
  2287. if (rx->ring_size <= 1) {
  2288. ret = -EINVAL;
  2289. goto cleanup;
  2290. }
  2291. if (rx->ring_size & ~RX_CFG_B_RX_RING_LEN_MASK_) {
  2292. ret = -EINVAL;
  2293. goto cleanup;
  2294. }
  2295. if (dma_set_mask_and_coherent(&rx->adapter->pdev->dev,
  2296. DMA_BIT_MASK(64))) {
  2297. dev_warn(&rx->adapter->pdev->dev,
  2298. "lan743x_: No suitable DMA available\n");
  2299. ret = -ENOMEM;
  2300. goto cleanup;
  2301. }
  2302. ring_allocation_size = ALIGN(rx->ring_size *
  2303. sizeof(struct lan743x_rx_descriptor),
  2304. PAGE_SIZE);
  2305. dma_ptr = 0;
  2306. cpu_ptr = dma_alloc_coherent(&rx->adapter->pdev->dev,
  2307. ring_allocation_size, &dma_ptr, GFP_KERNEL);
  2308. if (!cpu_ptr) {
  2309. ret = -ENOMEM;
  2310. goto cleanup;
  2311. }
  2312. rx->ring_allocation_size = ring_allocation_size;
  2313. rx->ring_cpu_ptr = (struct lan743x_rx_descriptor *)cpu_ptr;
  2314. rx->ring_dma_ptr = dma_ptr;
  2315. cpu_ptr = kcalloc(rx->ring_size, sizeof(*rx->buffer_info),
  2316. GFP_KERNEL);
  2317. if (!cpu_ptr) {
  2318. ret = -ENOMEM;
  2319. goto cleanup;
  2320. }
  2321. rx->buffer_info = (struct lan743x_rx_buffer_info *)cpu_ptr;
  2322. dma_ptr = 0;
  2323. cpu_ptr = dma_alloc_coherent(&rx->adapter->pdev->dev,
  2324. sizeof(*rx->head_cpu_ptr), &dma_ptr,
  2325. GFP_KERNEL);
  2326. if (!cpu_ptr) {
  2327. ret = -ENOMEM;
  2328. goto cleanup;
  2329. }
  2330. rx->head_cpu_ptr = cpu_ptr;
  2331. rx->head_dma_ptr = dma_ptr;
  2332. if (rx->head_dma_ptr & 0x3) {
  2333. ret = -ENOMEM;
  2334. goto cleanup;
  2335. }
  2336. rx->last_head = 0;
  2337. for (index = 0; index < rx->ring_size; index++) {
  2338. ret = lan743x_rx_init_ring_element(rx, index, GFP_KERNEL);
  2339. if (ret)
  2340. goto cleanup;
  2341. }
  2342. return 0;
  2343. cleanup:
  2344. netif_warn(rx->adapter, ifup, rx->adapter->netdev,
  2345. "Error allocating memory for LAN743x\n");
  2346. lan743x_rx_ring_cleanup(rx);
  2347. return ret;
  2348. }
  2349. static void lan743x_rx_close(struct lan743x_rx *rx)
  2350. {
  2351. struct lan743x_adapter *adapter = rx->adapter;
  2352. lan743x_csr_write(adapter, FCT_RX_CTL,
  2353. FCT_RX_CTL_DIS_(rx->channel_number));
  2354. lan743x_csr_wait_for_bit(adapter, FCT_RX_CTL,
  2355. FCT_RX_CTL_EN_(rx->channel_number),
  2356. 0, 1000, 20000, 100);
  2357. lan743x_csr_write(adapter, DMAC_CMD,
  2358. DMAC_CMD_STOP_R_(rx->channel_number));
  2359. lan743x_dmac_rx_wait_till_stopped(adapter, rx->channel_number);
  2360. lan743x_csr_write(adapter, DMAC_INT_EN_CLR,
  2361. DMAC_INT_BIT_RXFRM_(rx->channel_number));
  2362. lan743x_csr_write(adapter, INT_EN_CLR,
  2363. INT_BIT_DMA_RX_(rx->channel_number));
  2364. napi_disable(&rx->napi);
  2365. netif_napi_del(&rx->napi);
  2366. lan743x_rx_ring_cleanup(rx);
  2367. }
  2368. static int lan743x_rx_open(struct lan743x_rx *rx)
  2369. {
  2370. struct lan743x_adapter *adapter = rx->adapter;
  2371. u32 data = 0;
  2372. int ret;
  2373. rx->frame_count = 0;
  2374. ret = lan743x_rx_ring_init(rx);
  2375. if (ret)
  2376. goto return_error;
  2377. netif_napi_add(adapter->netdev, &rx->napi, lan743x_rx_napi_poll);
  2378. lan743x_csr_write(adapter, DMAC_CMD,
  2379. DMAC_CMD_RX_SWR_(rx->channel_number));
  2380. lan743x_csr_wait_for_bit(adapter, DMAC_CMD,
  2381. DMAC_CMD_RX_SWR_(rx->channel_number),
  2382. 0, 1000, 20000, 100);
  2383. /* set ring base address */
  2384. lan743x_csr_write(adapter,
  2385. RX_BASE_ADDRH(rx->channel_number),
  2386. DMA_ADDR_HIGH32(rx->ring_dma_ptr));
  2387. lan743x_csr_write(adapter,
  2388. RX_BASE_ADDRL(rx->channel_number),
  2389. DMA_ADDR_LOW32(rx->ring_dma_ptr));
  2390. /* set rx write back address */
  2391. lan743x_csr_write(adapter,
  2392. RX_HEAD_WRITEBACK_ADDRH(rx->channel_number),
  2393. DMA_ADDR_HIGH32(rx->head_dma_ptr));
  2394. lan743x_csr_write(adapter,
  2395. RX_HEAD_WRITEBACK_ADDRL(rx->channel_number),
  2396. DMA_ADDR_LOW32(rx->head_dma_ptr));
  2397. data = RX_CFG_A_RX_HP_WB_EN_;
  2398. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0)) {
  2399. data |= (RX_CFG_A_RX_WB_ON_INT_TMR_ |
  2400. RX_CFG_A_RX_WB_THRES_SET_(0x7) |
  2401. RX_CFG_A_RX_PF_THRES_SET_(16) |
  2402. RX_CFG_A_RX_PF_PRI_THRES_SET_(4));
  2403. }
  2404. /* set RX_CFG_A */
  2405. lan743x_csr_write(adapter,
  2406. RX_CFG_A(rx->channel_number), data);
  2407. /* set RX_CFG_B */
  2408. data = lan743x_csr_read(adapter, RX_CFG_B(rx->channel_number));
  2409. data &= ~RX_CFG_B_RX_PAD_MASK_;
  2410. if (!RX_HEAD_PADDING)
  2411. data |= RX_CFG_B_RX_PAD_0_;
  2412. else
  2413. data |= RX_CFG_B_RX_PAD_2_;
  2414. data &= ~RX_CFG_B_RX_RING_LEN_MASK_;
  2415. data |= ((rx->ring_size) & RX_CFG_B_RX_RING_LEN_MASK_);
  2416. if (!(adapter->csr.flags & LAN743X_CSR_FLAG_IS_A0))
  2417. data |= RX_CFG_B_RDMABL_512_;
  2418. lan743x_csr_write(adapter, RX_CFG_B(rx->channel_number), data);
  2419. rx->vector_flags = lan743x_intr_get_vector_flags(adapter,
  2420. INT_BIT_DMA_RX_
  2421. (rx->channel_number));
  2422. /* set RX_CFG_C */
  2423. data = 0;
  2424. if (rx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR)
  2425. data |= RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_;
  2426. if (rx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR)
  2427. data |= RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_;
  2428. if (rx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C)
  2429. data |= RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_;
  2430. if (rx->vector_flags & LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C)
  2431. data |= RX_CFG_C_RX_INT_EN_R2C_;
  2432. lan743x_csr_write(adapter, RX_CFG_C(rx->channel_number), data);
  2433. rx->last_tail = ((u32)(rx->ring_size - 1));
  2434. lan743x_csr_write(adapter, RX_TAIL(rx->channel_number),
  2435. rx->last_tail);
  2436. rx->last_head = lan743x_csr_read(adapter, RX_HEAD(rx->channel_number));
  2437. if (rx->last_head) {
  2438. ret = -EIO;
  2439. goto napi_delete;
  2440. }
  2441. napi_enable(&rx->napi);
  2442. lan743x_csr_write(adapter, INT_EN_SET,
  2443. INT_BIT_DMA_RX_(rx->channel_number));
  2444. lan743x_csr_write(adapter, DMAC_INT_STS,
  2445. DMAC_INT_BIT_RXFRM_(rx->channel_number));
  2446. lan743x_csr_write(adapter, DMAC_INT_EN_SET,
  2447. DMAC_INT_BIT_RXFRM_(rx->channel_number));
  2448. lan743x_csr_write(adapter, DMAC_CMD,
  2449. DMAC_CMD_START_R_(rx->channel_number));
  2450. /* initialize fifo */
  2451. lan743x_csr_write(adapter, FCT_RX_CTL,
  2452. FCT_RX_CTL_RESET_(rx->channel_number));
  2453. lan743x_csr_wait_for_bit(adapter, FCT_RX_CTL,
  2454. FCT_RX_CTL_RESET_(rx->channel_number),
  2455. 0, 1000, 20000, 100);
  2456. lan743x_csr_write(adapter, FCT_FLOW(rx->channel_number),
  2457. FCT_FLOW_CTL_REQ_EN_ |
  2458. FCT_FLOW_CTL_ON_THRESHOLD_SET_(0x2A) |
  2459. FCT_FLOW_CTL_OFF_THRESHOLD_SET_(0xA));
  2460. /* enable fifo */
  2461. lan743x_csr_write(adapter, FCT_RX_CTL,
  2462. FCT_RX_CTL_EN_(rx->channel_number));
  2463. return 0;
  2464. napi_delete:
  2465. netif_napi_del(&rx->napi);
  2466. lan743x_rx_ring_cleanup(rx);
  2467. return_error:
  2468. return ret;
  2469. }
  2470. static int lan743x_phylink_sgmii_config(struct lan743x_adapter *adapter)
  2471. {
  2472. u32 sgmii_ctl;
  2473. int ret;
  2474. ret = lan743x_get_lsd(SPEED_1000, DUPLEX_FULL,
  2475. MASTER_SLAVE_STATE_MASTER);
  2476. if (ret < 0) {
  2477. netif_err(adapter, drv, adapter->netdev,
  2478. "error %d link-speed-duplex(LSD) invalid\n", ret);
  2479. return ret;
  2480. }
  2481. adapter->sgmii_lsd = ret;
  2482. netif_dbg(adapter, drv, adapter->netdev,
  2483. "Link Speed Duplex (lsd) : 0x%X\n", adapter->sgmii_lsd);
  2484. /* LINK_STATUS_SOURCE from the External PHY via SGMII */
  2485. sgmii_ctl = lan743x_csr_read(adapter, SGMII_CTL);
  2486. sgmii_ctl &= ~SGMII_CTL_LINK_STATUS_SOURCE_;
  2487. lan743x_csr_write(adapter, SGMII_CTL, sgmii_ctl);
  2488. ret = lan743x_serdes_clock_and_aneg_update(adapter);
  2489. if (ret < 0) {
  2490. netif_err(adapter, drv, adapter->netdev,
  2491. "error %d sgmii aneg update failed\n", ret);
  2492. return ret;
  2493. }
  2494. return lan743x_pcs_power_reset(adapter);
  2495. }
  2496. static int lan743x_phylink_1000basex_config(struct lan743x_adapter *adapter)
  2497. {
  2498. u32 sgmii_ctl;
  2499. int ret;
  2500. ret = lan743x_get_lsd(SPEED_1000, DUPLEX_FULL,
  2501. MASTER_SLAVE_STATE_MASTER);
  2502. if (ret < 0) {
  2503. netif_err(adapter, drv, adapter->netdev,
  2504. "error %d link-speed-duplex(LSD) invalid\n", ret);
  2505. return ret;
  2506. }
  2507. adapter->sgmii_lsd = ret;
  2508. netif_dbg(adapter, drv, adapter->netdev,
  2509. "Link Speed Duplex (lsd) : 0x%X\n", adapter->sgmii_lsd);
  2510. /* LINK_STATUS_SOURCE from 1000BASE-X PCS link status */
  2511. sgmii_ctl = lan743x_csr_read(adapter, SGMII_CTL);
  2512. sgmii_ctl |= SGMII_CTL_LINK_STATUS_SOURCE_;
  2513. lan743x_csr_write(adapter, SGMII_CTL, sgmii_ctl);
  2514. ret = lan743x_serdes_clock_and_aneg_update(adapter);
  2515. if (ret < 0) {
  2516. netif_err(adapter, drv, adapter->netdev,
  2517. "error %d 1000basex aneg update failed\n", ret);
  2518. return ret;
  2519. }
  2520. return lan743x_pcs_power_reset(adapter);
  2521. }
  2522. static int lan743x_phylink_2500basex_config(struct lan743x_adapter *adapter)
  2523. {
  2524. u32 sgmii_ctl;
  2525. int ret;
  2526. ret = lan743x_get_lsd(SPEED_2500, DUPLEX_FULL,
  2527. MASTER_SLAVE_STATE_MASTER);
  2528. if (ret < 0) {
  2529. netif_err(adapter, drv, adapter->netdev,
  2530. "error %d link-speed-duplex(LSD) invalid\n", ret);
  2531. return ret;
  2532. }
  2533. adapter->sgmii_lsd = ret;
  2534. netif_dbg(adapter, drv, adapter->netdev,
  2535. "Link Speed Duplex (lsd) : 0x%X\n", adapter->sgmii_lsd);
  2536. /* LINK_STATUS_SOURCE from 2500BASE-X PCS link status */
  2537. sgmii_ctl = lan743x_csr_read(adapter, SGMII_CTL);
  2538. sgmii_ctl |= SGMII_CTL_LINK_STATUS_SOURCE_;
  2539. lan743x_csr_write(adapter, SGMII_CTL, sgmii_ctl);
  2540. ret = lan743x_serdes_clock_and_aneg_update(adapter);
  2541. if (ret < 0) {
  2542. netif_err(adapter, drv, adapter->netdev,
  2543. "error %d 2500basex aneg update failed\n", ret);
  2544. return ret;
  2545. }
  2546. return lan743x_pcs_power_reset(adapter);
  2547. }
  2548. void lan743x_mac_eee_enable(struct lan743x_adapter *adapter, bool enable)
  2549. {
  2550. u32 mac_cr;
  2551. mac_cr = lan743x_csr_read(adapter, MAC_CR);
  2552. if (enable)
  2553. mac_cr |= MAC_CR_EEE_EN_;
  2554. else
  2555. mac_cr &= ~MAC_CR_EEE_EN_;
  2556. lan743x_csr_write(adapter, MAC_CR, mac_cr);
  2557. }
  2558. static void lan743x_phylink_mac_config(struct phylink_config *config,
  2559. unsigned int link_an_mode,
  2560. const struct phylink_link_state *state)
  2561. {
  2562. struct net_device *netdev = to_net_dev(config->dev);
  2563. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2564. int ret;
  2565. switch (state->interface) {
  2566. case PHY_INTERFACE_MODE_2500BASEX:
  2567. ret = lan743x_phylink_2500basex_config(adapter);
  2568. if (ret < 0)
  2569. netif_err(adapter, drv, adapter->netdev,
  2570. "2500BASEX config failed. Error %d\n", ret);
  2571. else
  2572. netif_dbg(adapter, drv, adapter->netdev,
  2573. "2500BASEX mode selected and configured\n");
  2574. break;
  2575. case PHY_INTERFACE_MODE_1000BASEX:
  2576. ret = lan743x_phylink_1000basex_config(adapter);
  2577. if (ret < 0)
  2578. netif_err(adapter, drv, adapter->netdev,
  2579. "1000BASEX config failed. Error %d\n", ret);
  2580. else
  2581. netif_dbg(adapter, drv, adapter->netdev,
  2582. "1000BASEX mode selected and configured\n");
  2583. break;
  2584. case PHY_INTERFACE_MODE_SGMII:
  2585. ret = lan743x_phylink_sgmii_config(adapter);
  2586. if (ret < 0)
  2587. netif_err(adapter, drv, adapter->netdev,
  2588. "SGMII config failed. Error %d\n", ret);
  2589. else
  2590. netif_dbg(adapter, drv, adapter->netdev,
  2591. "SGMII mode selected and configured\n");
  2592. break;
  2593. default:
  2594. netif_dbg(adapter, drv, adapter->netdev,
  2595. "RGMII/GMII/MII(0x%X) mode enable\n",
  2596. state->interface);
  2597. break;
  2598. }
  2599. }
  2600. static void lan743x_phylink_mac_link_down(struct phylink_config *config,
  2601. unsigned int link_an_mode,
  2602. phy_interface_t interface)
  2603. {
  2604. struct net_device *netdev = to_net_dev(config->dev);
  2605. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2606. netif_tx_stop_all_queues(to_net_dev(config->dev));
  2607. lan743x_mac_eee_enable(adapter, false);
  2608. }
  2609. static void lan743x_phylink_mac_link_up(struct phylink_config *config,
  2610. struct phy_device *phydev,
  2611. unsigned int link_an_mode,
  2612. phy_interface_t interface,
  2613. int speed, int duplex,
  2614. bool tx_pause, bool rx_pause)
  2615. {
  2616. struct net_device *netdev = to_net_dev(config->dev);
  2617. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2618. int mac_cr;
  2619. u8 cap;
  2620. mac_cr = lan743x_csr_read(adapter, MAC_CR);
  2621. /* Pre-initialize register bits.
  2622. * Resulting value corresponds to SPEED_10
  2623. */
  2624. mac_cr &= ~(MAC_CR_CFG_H_ | MAC_CR_CFG_L_);
  2625. if (speed == SPEED_2500)
  2626. mac_cr |= MAC_CR_CFG_H_ | MAC_CR_CFG_L_;
  2627. else if (speed == SPEED_1000)
  2628. mac_cr |= MAC_CR_CFG_H_;
  2629. else if (speed == SPEED_100)
  2630. mac_cr |= MAC_CR_CFG_L_;
  2631. lan743x_csr_write(adapter, MAC_CR, mac_cr);
  2632. lan743x_ptp_update_latency(adapter, speed);
  2633. /* Flow Control operation */
  2634. cap = 0;
  2635. if (tx_pause)
  2636. cap |= FLOW_CTRL_TX;
  2637. if (rx_pause)
  2638. cap |= FLOW_CTRL_RX;
  2639. lan743x_mac_flow_ctrl_set_enables(adapter,
  2640. cap & FLOW_CTRL_TX,
  2641. cap & FLOW_CTRL_RX);
  2642. if (phydev)
  2643. lan743x_mac_eee_enable(adapter, phydev->enable_tx_lpi);
  2644. netif_tx_wake_all_queues(netdev);
  2645. }
  2646. static const struct phylink_mac_ops lan743x_phylink_mac_ops = {
  2647. .mac_config = lan743x_phylink_mac_config,
  2648. .mac_link_down = lan743x_phylink_mac_link_down,
  2649. .mac_link_up = lan743x_phylink_mac_link_up,
  2650. };
  2651. static int lan743x_phylink_create(struct lan743x_adapter *adapter)
  2652. {
  2653. struct net_device *netdev = adapter->netdev;
  2654. struct phylink *pl;
  2655. adapter->phylink_config.dev = &netdev->dev;
  2656. adapter->phylink_config.type = PHYLINK_NETDEV;
  2657. adapter->phylink_config.mac_managed_pm = false;
  2658. adapter->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
  2659. MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD;
  2660. lan743x_phy_interface_select(adapter);
  2661. switch (adapter->phy_interface) {
  2662. case PHY_INTERFACE_MODE_SGMII:
  2663. __set_bit(PHY_INTERFACE_MODE_SGMII,
  2664. adapter->phylink_config.supported_interfaces);
  2665. __set_bit(PHY_INTERFACE_MODE_1000BASEX,
  2666. adapter->phylink_config.supported_interfaces);
  2667. __set_bit(PHY_INTERFACE_MODE_2500BASEX,
  2668. adapter->phylink_config.supported_interfaces);
  2669. adapter->phylink_config.mac_capabilities |= MAC_2500FD;
  2670. break;
  2671. case PHY_INTERFACE_MODE_GMII:
  2672. __set_bit(PHY_INTERFACE_MODE_GMII,
  2673. adapter->phylink_config.supported_interfaces);
  2674. break;
  2675. case PHY_INTERFACE_MODE_MII:
  2676. __set_bit(PHY_INTERFACE_MODE_MII,
  2677. adapter->phylink_config.supported_interfaces);
  2678. break;
  2679. default:
  2680. phy_interface_set_rgmii(adapter->phylink_config.supported_interfaces);
  2681. }
  2682. pl = phylink_create(&adapter->phylink_config, NULL,
  2683. adapter->phy_interface, &lan743x_phylink_mac_ops);
  2684. if (IS_ERR(pl)) {
  2685. netdev_err(netdev, "Could not create phylink (%pe)\n", pl);
  2686. return PTR_ERR(pl);
  2687. }
  2688. adapter->phylink = pl;
  2689. netdev_dbg(netdev, "lan743x phylink created");
  2690. return 0;
  2691. }
  2692. static bool lan743x_phy_handle_exists(struct device_node *dn)
  2693. {
  2694. dn = of_parse_phandle(dn, "phy-handle", 0);
  2695. of_node_put(dn);
  2696. return dn != NULL;
  2697. }
  2698. static int lan743x_phylink_connect(struct lan743x_adapter *adapter)
  2699. {
  2700. struct device_node *dn = adapter->pdev->dev.of_node;
  2701. struct net_device *dev = adapter->netdev;
  2702. struct phy_device *phydev;
  2703. int ret;
  2704. if (dn)
  2705. ret = phylink_of_phy_connect(adapter->phylink, dn, 0);
  2706. if (!dn || (ret && !lan743x_phy_handle_exists(dn))) {
  2707. phydev = phy_find_first(adapter->mdiobus);
  2708. if (phydev) {
  2709. /* attach the mac to the phy */
  2710. ret = phylink_connect_phy(adapter->phylink, phydev);
  2711. } else if (((adapter->csr.id_rev & ID_REV_ID_MASK_) ==
  2712. ID_REV_ID_LAN7431_) || adapter->is_pci11x1x) {
  2713. struct phylink_link_state state;
  2714. unsigned long caps;
  2715. caps = adapter->phylink_config.mac_capabilities;
  2716. if (caps & MAC_2500FD) {
  2717. state.speed = SPEED_2500;
  2718. state.duplex = DUPLEX_FULL;
  2719. } else if (caps & MAC_1000FD) {
  2720. state.speed = SPEED_1000;
  2721. state.duplex = DUPLEX_FULL;
  2722. } else {
  2723. state.speed = SPEED_UNKNOWN;
  2724. state.duplex = DUPLEX_UNKNOWN;
  2725. }
  2726. ret = phylink_set_fixed_link(adapter->phylink, &state);
  2727. if (ret) {
  2728. netdev_err(dev, "Could not set fixed link\n");
  2729. return ret;
  2730. }
  2731. } else {
  2732. netdev_err(dev, "no PHY found\n");
  2733. return -ENXIO;
  2734. }
  2735. }
  2736. if (ret) {
  2737. netdev_err(dev, "Could not attach PHY (%d)\n", ret);
  2738. return ret;
  2739. }
  2740. phylink_start(adapter->phylink);
  2741. return 0;
  2742. }
  2743. static void lan743x_phylink_disconnect(struct lan743x_adapter *adapter)
  2744. {
  2745. phylink_stop(adapter->phylink);
  2746. phylink_disconnect_phy(adapter->phylink);
  2747. }
  2748. static int lan743x_netdev_close(struct net_device *netdev)
  2749. {
  2750. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2751. int index;
  2752. for (index = 0; index < adapter->used_tx_channels; index++)
  2753. lan743x_tx_close(&adapter->tx[index]);
  2754. for (index = 0; index < LAN743X_USED_RX_CHANNELS; index++)
  2755. lan743x_rx_close(&adapter->rx[index]);
  2756. lan743x_ptp_close(adapter);
  2757. lan743x_phylink_disconnect(adapter);
  2758. lan743x_mac_close(adapter);
  2759. lan743x_intr_close(adapter);
  2760. return 0;
  2761. }
  2762. static int lan743x_netdev_open(struct net_device *netdev)
  2763. {
  2764. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2765. int index;
  2766. int ret;
  2767. ret = lan743x_intr_open(adapter);
  2768. if (ret)
  2769. goto return_error;
  2770. ret = lan743x_mac_open(adapter);
  2771. if (ret)
  2772. goto close_intr;
  2773. ret = lan743x_phylink_connect(adapter);
  2774. if (ret)
  2775. goto close_mac;
  2776. ret = lan743x_ptp_open(adapter);
  2777. if (ret)
  2778. goto close_mac;
  2779. lan743x_rfe_open(adapter);
  2780. for (index = 0; index < LAN743X_USED_RX_CHANNELS; index++) {
  2781. ret = lan743x_rx_open(&adapter->rx[index]);
  2782. if (ret)
  2783. goto close_rx;
  2784. }
  2785. for (index = 0; index < adapter->used_tx_channels; index++) {
  2786. ret = lan743x_tx_open(&adapter->tx[index]);
  2787. if (ret)
  2788. goto close_tx;
  2789. }
  2790. if (netdev->phydev)
  2791. phy_support_eee(netdev->phydev);
  2792. #ifdef CONFIG_PM
  2793. if (adapter->netdev->phydev) {
  2794. struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
  2795. phy_ethtool_get_wol(netdev->phydev, &wol);
  2796. adapter->phy_wol_supported = wol.supported;
  2797. adapter->phy_wolopts = wol.wolopts;
  2798. }
  2799. #endif
  2800. return 0;
  2801. close_tx:
  2802. for (index = 0; index < adapter->used_tx_channels; index++) {
  2803. if (adapter->tx[index].ring_cpu_ptr)
  2804. lan743x_tx_close(&adapter->tx[index]);
  2805. }
  2806. close_rx:
  2807. for (index = 0; index < LAN743X_USED_RX_CHANNELS; index++) {
  2808. if (adapter->rx[index].ring_cpu_ptr)
  2809. lan743x_rx_close(&adapter->rx[index]);
  2810. }
  2811. lan743x_ptp_close(adapter);
  2812. if (adapter->phylink)
  2813. lan743x_phylink_disconnect(adapter);
  2814. close_mac:
  2815. lan743x_mac_close(adapter);
  2816. close_intr:
  2817. lan743x_intr_close(adapter);
  2818. return_error:
  2819. netif_warn(adapter, ifup, adapter->netdev,
  2820. "Error opening LAN743x\n");
  2821. return ret;
  2822. }
  2823. static netdev_tx_t lan743x_netdev_xmit_frame(struct sk_buff *skb,
  2824. struct net_device *netdev)
  2825. {
  2826. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2827. u8 ch = 0;
  2828. if (adapter->is_pci11x1x)
  2829. ch = skb->queue_mapping % PCI11X1X_USED_TX_CHANNELS;
  2830. return lan743x_tx_xmit_frame(&adapter->tx[ch], skb);
  2831. }
  2832. static int lan743x_netdev_ioctl(struct net_device *netdev,
  2833. struct ifreq *ifr, int cmd)
  2834. {
  2835. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2836. if (!netif_running(netdev))
  2837. return -EINVAL;
  2838. if (cmd == SIOCSHWTSTAMP)
  2839. return lan743x_ptp_ioctl(netdev, ifr, cmd);
  2840. return phylink_mii_ioctl(adapter->phylink, ifr, cmd);
  2841. }
  2842. static void lan743x_netdev_set_multicast(struct net_device *netdev)
  2843. {
  2844. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2845. lan743x_rfe_set_multicast(adapter);
  2846. }
  2847. static int lan743x_netdev_change_mtu(struct net_device *netdev, int new_mtu)
  2848. {
  2849. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2850. int ret = 0;
  2851. ret = lan743x_mac_set_mtu(adapter, new_mtu);
  2852. if (!ret)
  2853. WRITE_ONCE(netdev->mtu, new_mtu);
  2854. return ret;
  2855. }
  2856. static void lan743x_netdev_get_stats64(struct net_device *netdev,
  2857. struct rtnl_link_stats64 *stats)
  2858. {
  2859. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2860. stats->rx_packets = lan743x_csr_read(adapter, STAT_RX_TOTAL_FRAMES);
  2861. stats->tx_packets = lan743x_csr_read(adapter, STAT_TX_TOTAL_FRAMES);
  2862. stats->rx_bytes = lan743x_csr_read(adapter,
  2863. STAT_RX_UNICAST_BYTE_COUNT) +
  2864. lan743x_csr_read(adapter,
  2865. STAT_RX_BROADCAST_BYTE_COUNT) +
  2866. lan743x_csr_read(adapter,
  2867. STAT_RX_MULTICAST_BYTE_COUNT);
  2868. stats->tx_bytes = lan743x_csr_read(adapter,
  2869. STAT_TX_UNICAST_BYTE_COUNT) +
  2870. lan743x_csr_read(adapter,
  2871. STAT_TX_BROADCAST_BYTE_COUNT) +
  2872. lan743x_csr_read(adapter,
  2873. STAT_TX_MULTICAST_BYTE_COUNT);
  2874. stats->rx_errors = lan743x_csr_read(adapter, STAT_RX_FCS_ERRORS) +
  2875. lan743x_csr_read(adapter,
  2876. STAT_RX_ALIGNMENT_ERRORS) +
  2877. lan743x_csr_read(adapter, STAT_RX_JABBER_ERRORS) +
  2878. lan743x_csr_read(adapter,
  2879. STAT_RX_UNDERSIZE_FRAME_ERRORS) +
  2880. lan743x_csr_read(adapter,
  2881. STAT_RX_OVERSIZE_FRAME_ERRORS);
  2882. stats->tx_errors = lan743x_csr_read(adapter, STAT_TX_FCS_ERRORS) +
  2883. lan743x_csr_read(adapter,
  2884. STAT_TX_EXCESS_DEFERRAL_ERRORS) +
  2885. lan743x_csr_read(adapter, STAT_TX_CARRIER_ERRORS);
  2886. stats->rx_dropped = lan743x_csr_read(adapter,
  2887. STAT_RX_DROPPED_FRAMES);
  2888. stats->tx_dropped = lan743x_csr_read(adapter,
  2889. STAT_TX_EXCESSIVE_COLLISION);
  2890. stats->multicast = lan743x_csr_read(adapter,
  2891. STAT_RX_MULTICAST_FRAMES) +
  2892. lan743x_csr_read(adapter,
  2893. STAT_TX_MULTICAST_FRAMES);
  2894. stats->collisions = lan743x_csr_read(adapter,
  2895. STAT_TX_SINGLE_COLLISIONS) +
  2896. lan743x_csr_read(adapter,
  2897. STAT_TX_MULTIPLE_COLLISIONS) +
  2898. lan743x_csr_read(adapter,
  2899. STAT_TX_LATE_COLLISIONS);
  2900. }
  2901. static int lan743x_netdev_set_mac_address(struct net_device *netdev,
  2902. void *addr)
  2903. {
  2904. struct lan743x_adapter *adapter = netdev_priv(netdev);
  2905. struct sockaddr *sock_addr = addr;
  2906. int ret;
  2907. ret = eth_prepare_mac_addr_change(netdev, sock_addr);
  2908. if (ret)
  2909. return ret;
  2910. eth_hw_addr_set(netdev, sock_addr->sa_data);
  2911. lan743x_mac_set_address(adapter, sock_addr->sa_data);
  2912. lan743x_rfe_update_mac_address(adapter);
  2913. return 0;
  2914. }
  2915. static const struct net_device_ops lan743x_netdev_ops = {
  2916. .ndo_open = lan743x_netdev_open,
  2917. .ndo_stop = lan743x_netdev_close,
  2918. .ndo_start_xmit = lan743x_netdev_xmit_frame,
  2919. .ndo_eth_ioctl = lan743x_netdev_ioctl,
  2920. .ndo_set_rx_mode = lan743x_netdev_set_multicast,
  2921. .ndo_change_mtu = lan743x_netdev_change_mtu,
  2922. .ndo_get_stats64 = lan743x_netdev_get_stats64,
  2923. .ndo_set_mac_address = lan743x_netdev_set_mac_address,
  2924. };
  2925. static void lan743x_hardware_cleanup(struct lan743x_adapter *adapter)
  2926. {
  2927. lan743x_csr_write(adapter, INT_EN_CLR, 0xFFFFFFFF);
  2928. }
  2929. static void lan743x_mdiobus_cleanup(struct lan743x_adapter *adapter)
  2930. {
  2931. mdiobus_unregister(adapter->mdiobus);
  2932. }
  2933. static void lan743x_destroy_phylink(struct lan743x_adapter *adapter)
  2934. {
  2935. phylink_destroy(adapter->phylink);
  2936. adapter->phylink = NULL;
  2937. }
  2938. static void lan743x_full_cleanup(struct lan743x_adapter *adapter)
  2939. {
  2940. unregister_netdev(adapter->netdev);
  2941. lan743x_destroy_phylink(adapter);
  2942. lan743x_mdiobus_cleanup(adapter);
  2943. lan743x_hardware_cleanup(adapter);
  2944. lan743x_pci_cleanup(adapter);
  2945. }
  2946. static void pci11x1x_set_rfe_rd_fifo_threshold(struct lan743x_adapter *adapter)
  2947. {
  2948. u16 rev = adapter->csr.id_rev & ID_REV_CHIP_REV_MASK_;
  2949. if (rev == ID_REV_CHIP_REV_PCI11X1X_B0_) {
  2950. u32 misc_ctl;
  2951. misc_ctl = lan743x_csr_read(adapter, MISC_CTL_0);
  2952. misc_ctl &= ~MISC_CTL_0_RFE_READ_FIFO_MASK_;
  2953. misc_ctl |= FIELD_PREP(MISC_CTL_0_RFE_READ_FIFO_MASK_,
  2954. RFE_RD_FIFO_TH_3_DWORDS);
  2955. lan743x_csr_write(adapter, MISC_CTL_0, misc_ctl);
  2956. }
  2957. }
  2958. static int lan743x_hardware_init(struct lan743x_adapter *adapter,
  2959. struct pci_dev *pdev)
  2960. {
  2961. struct lan743x_tx *tx;
  2962. u32 sgmii_ctl;
  2963. int index;
  2964. int ret;
  2965. adapter->is_pci11x1x = is_pci11x1x_chip(adapter);
  2966. if (adapter->is_pci11x1x) {
  2967. adapter->max_tx_channels = PCI11X1X_MAX_TX_CHANNELS;
  2968. adapter->used_tx_channels = PCI11X1X_USED_TX_CHANNELS;
  2969. adapter->max_vector_count = PCI11X1X_MAX_VECTOR_COUNT;
  2970. pci11x1x_strap_get_status(adapter);
  2971. spin_lock_init(&adapter->eth_syslock_spinlock);
  2972. mutex_init(&adapter->sgmii_rw_lock);
  2973. pci11x1x_set_rfe_rd_fifo_threshold(adapter);
  2974. sgmii_ctl = lan743x_csr_read(adapter, SGMII_CTL);
  2975. if (adapter->is_sgmii_en) {
  2976. sgmii_ctl |= SGMII_CTL_SGMII_ENABLE_;
  2977. sgmii_ctl &= ~SGMII_CTL_SGMII_POWER_DN_;
  2978. } else {
  2979. sgmii_ctl &= ~SGMII_CTL_SGMII_ENABLE_;
  2980. sgmii_ctl |= SGMII_CTL_SGMII_POWER_DN_;
  2981. }
  2982. lan743x_csr_write(adapter, SGMII_CTL, sgmii_ctl);
  2983. } else {
  2984. adapter->max_tx_channels = LAN743X_MAX_TX_CHANNELS;
  2985. adapter->used_tx_channels = LAN743X_USED_TX_CHANNELS;
  2986. adapter->max_vector_count = LAN743X_MAX_VECTOR_COUNT;
  2987. }
  2988. adapter->intr.irq = adapter->pdev->irq;
  2989. lan743x_csr_write(adapter, INT_EN_CLR, 0xFFFFFFFF);
  2990. ret = lan743x_gpio_init(adapter);
  2991. if (ret)
  2992. return ret;
  2993. ret = lan743x_mac_init(adapter);
  2994. if (ret)
  2995. return ret;
  2996. ret = lan743x_ptp_init(adapter);
  2997. if (ret)
  2998. return ret;
  2999. lan743x_rfe_update_mac_address(adapter);
  3000. ret = lan743x_dmac_init(adapter);
  3001. if (ret)
  3002. return ret;
  3003. for (index = 0; index < LAN743X_USED_RX_CHANNELS; index++) {
  3004. adapter->rx[index].adapter = adapter;
  3005. adapter->rx[index].channel_number = index;
  3006. }
  3007. for (index = 0; index < adapter->used_tx_channels; index++) {
  3008. tx = &adapter->tx[index];
  3009. tx->adapter = adapter;
  3010. tx->channel_number = index;
  3011. spin_lock_init(&tx->ring_lock);
  3012. }
  3013. return 0;
  3014. }
  3015. static int lan743x_mdiobus_init(struct lan743x_adapter *adapter)
  3016. {
  3017. int ret;
  3018. adapter->mdiobus = devm_mdiobus_alloc(&adapter->pdev->dev);
  3019. if (!(adapter->mdiobus)) {
  3020. ret = -ENOMEM;
  3021. goto return_error;
  3022. }
  3023. adapter->mdiobus->priv = (void *)adapter;
  3024. if (adapter->is_pci11x1x) {
  3025. if (adapter->is_sgmii_en) {
  3026. netif_dbg(adapter, drv, adapter->netdev,
  3027. "SGMII operation\n");
  3028. adapter->mdiobus->read = lan743x_mdiobus_read_c22;
  3029. adapter->mdiobus->write = lan743x_mdiobus_write_c22;
  3030. adapter->mdiobus->read_c45 = lan743x_mdiobus_read_c45;
  3031. adapter->mdiobus->write_c45 = lan743x_mdiobus_write_c45;
  3032. adapter->mdiobus->name = "lan743x-mdiobus-c45";
  3033. netif_dbg(adapter, drv, adapter->netdev,
  3034. "lan743x-mdiobus-c45\n");
  3035. } else {
  3036. netif_dbg(adapter, drv, adapter->netdev,
  3037. "RGMII operation\n");
  3038. // Only C22 support when RGMII I/F
  3039. adapter->mdiobus->read = lan743x_mdiobus_read_c22;
  3040. adapter->mdiobus->write = lan743x_mdiobus_write_c22;
  3041. adapter->mdiobus->name = "lan743x-mdiobus";
  3042. netif_dbg(adapter, drv, adapter->netdev,
  3043. "lan743x-mdiobus\n");
  3044. }
  3045. } else {
  3046. adapter->mdiobus->read = lan743x_mdiobus_read_c22;
  3047. adapter->mdiobus->write = lan743x_mdiobus_write_c22;
  3048. adapter->mdiobus->name = "lan743x-mdiobus";
  3049. netif_dbg(adapter, drv, adapter->netdev, "lan743x-mdiobus\n");
  3050. }
  3051. snprintf(adapter->mdiobus->id, MII_BUS_ID_SIZE,
  3052. "pci-%s", pci_name(adapter->pdev));
  3053. if ((adapter->csr.id_rev & ID_REV_ID_MASK_) == ID_REV_ID_LAN7430_)
  3054. /* LAN7430 uses internal phy at address 1 */
  3055. adapter->mdiobus->phy_mask = ~(u32)BIT(1);
  3056. /* register mdiobus */
  3057. ret = mdiobus_register(adapter->mdiobus);
  3058. if (ret < 0)
  3059. goto return_error;
  3060. return 0;
  3061. return_error:
  3062. return ret;
  3063. }
  3064. /* lan743x_pcidev_probe - Device Initialization Routine
  3065. * @pdev: PCI device information struct
  3066. * @id: entry in lan743x_pci_tbl
  3067. *
  3068. * Returns 0 on success, negative on failure
  3069. *
  3070. * initializes an adapter identified by a pci_dev structure.
  3071. * The OS initialization, configuring of the adapter private structure,
  3072. * and a hardware reset occur.
  3073. **/
  3074. static int lan743x_pcidev_probe(struct pci_dev *pdev,
  3075. const struct pci_device_id *id)
  3076. {
  3077. struct lan743x_adapter *adapter = NULL;
  3078. struct net_device *netdev = NULL;
  3079. int ret = -ENODEV;
  3080. if (id->device == PCI_DEVICE_ID_SMSC_A011 ||
  3081. id->device == PCI_DEVICE_ID_SMSC_A041) {
  3082. netdev = devm_alloc_etherdev_mqs(&pdev->dev,
  3083. sizeof(struct lan743x_adapter),
  3084. PCI11X1X_USED_TX_CHANNELS,
  3085. LAN743X_USED_RX_CHANNELS);
  3086. } else {
  3087. netdev = devm_alloc_etherdev_mqs(&pdev->dev,
  3088. sizeof(struct lan743x_adapter),
  3089. LAN743X_USED_TX_CHANNELS,
  3090. LAN743X_USED_RX_CHANNELS);
  3091. }
  3092. if (!netdev)
  3093. goto return_error;
  3094. SET_NETDEV_DEV(netdev, &pdev->dev);
  3095. pci_set_drvdata(pdev, netdev);
  3096. adapter = netdev_priv(netdev);
  3097. adapter->netdev = netdev;
  3098. adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  3099. NETIF_MSG_LINK | NETIF_MSG_IFUP |
  3100. NETIF_MSG_IFDOWN | NETIF_MSG_TX_QUEUED;
  3101. netdev->max_mtu = LAN743X_MAX_FRAME_SIZE;
  3102. of_get_mac_address(pdev->dev.of_node, adapter->mac_address);
  3103. ret = lan743x_pci_init(adapter, pdev);
  3104. if (ret)
  3105. goto return_error;
  3106. ret = lan743x_csr_init(adapter);
  3107. if (ret)
  3108. goto cleanup_pci;
  3109. ret = lan743x_hw_reset_phy(adapter);
  3110. if (ret)
  3111. goto cleanup_pci;
  3112. ret = lan743x_hardware_init(adapter, pdev);
  3113. if (ret)
  3114. goto cleanup_pci;
  3115. ret = lan743x_mdiobus_init(adapter);
  3116. if (ret)
  3117. goto cleanup_hardware;
  3118. adapter->netdev->netdev_ops = &lan743x_netdev_ops;
  3119. adapter->netdev->ethtool_ops = &lan743x_ethtool_ops;
  3120. adapter->netdev->features = NETIF_F_SG | NETIF_F_TSO |
  3121. NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
  3122. adapter->netdev->hw_features = adapter->netdev->features;
  3123. ret = lan743x_phylink_create(adapter);
  3124. if (ret < 0) {
  3125. netif_err(adapter, probe, netdev,
  3126. "failed to setup phylink (%d)\n", ret);
  3127. goto cleanup_mdiobus;
  3128. }
  3129. ret = register_netdev(adapter->netdev);
  3130. if (ret < 0)
  3131. goto cleanup_phylink;
  3132. return 0;
  3133. cleanup_phylink:
  3134. lan743x_destroy_phylink(adapter);
  3135. cleanup_mdiobus:
  3136. lan743x_mdiobus_cleanup(adapter);
  3137. cleanup_hardware:
  3138. lan743x_hardware_cleanup(adapter);
  3139. cleanup_pci:
  3140. lan743x_pci_cleanup(adapter);
  3141. return_error:
  3142. pr_warn("Initialization failed\n");
  3143. return ret;
  3144. }
  3145. /**
  3146. * lan743x_pcidev_remove - Device Removal Routine
  3147. * @pdev: PCI device information struct
  3148. *
  3149. * this is called by the PCI subsystem to alert the driver
  3150. * that it should release a PCI device. This could be caused by a
  3151. * Hot-Plug event, or because the driver is going to be removed from
  3152. * memory.
  3153. **/
  3154. static void lan743x_pcidev_remove(struct pci_dev *pdev)
  3155. {
  3156. struct net_device *netdev = pci_get_drvdata(pdev);
  3157. struct lan743x_adapter *adapter = netdev_priv(netdev);
  3158. lan743x_full_cleanup(adapter);
  3159. }
  3160. static void lan743x_pcidev_shutdown(struct pci_dev *pdev)
  3161. {
  3162. struct net_device *netdev = pci_get_drvdata(pdev);
  3163. struct lan743x_adapter *adapter = netdev_priv(netdev);
  3164. rtnl_lock();
  3165. netif_device_detach(netdev);
  3166. /* close netdev when netdev is at running state.
  3167. * For instance, it is true when system goes to sleep by pm-suspend
  3168. * However, it is false when system goes to sleep by suspend GUI menu
  3169. */
  3170. if (netif_running(netdev))
  3171. lan743x_netdev_close(netdev);
  3172. rtnl_unlock();
  3173. #ifdef CONFIG_PM
  3174. pci_save_state(pdev);
  3175. #endif
  3176. /* clean up lan743x portion */
  3177. lan743x_hardware_cleanup(adapter);
  3178. }
  3179. #ifdef CONFIG_PM_SLEEP
  3180. static u16 lan743x_pm_wakeframe_crc16(const u8 *buf, int len)
  3181. {
  3182. return bitrev16(crc16(0xFFFF, buf, len));
  3183. }
  3184. static void lan743x_pm_set_wol(struct lan743x_adapter *adapter)
  3185. {
  3186. const u8 ipv4_multicast[3] = { 0x01, 0x00, 0x5E };
  3187. const u8 ipv6_multicast[3] = { 0x33, 0x33 };
  3188. const u8 arp_type[2] = { 0x08, 0x06 };
  3189. int mask_index;
  3190. u32 sopass;
  3191. u32 pmtctl;
  3192. u32 wucsr;
  3193. u32 macrx;
  3194. u16 crc;
  3195. for (mask_index = 0; mask_index < MAC_NUM_OF_WUF_CFG; mask_index++)
  3196. lan743x_csr_write(adapter, MAC_WUF_CFG(mask_index), 0);
  3197. /* clear wake settings */
  3198. pmtctl = lan743x_csr_read(adapter, PMT_CTL);
  3199. pmtctl |= PMT_CTL_WUPS_MASK_ | PMT_CTL_RES_CLR_WKP_MASK_;
  3200. pmtctl &= ~(PMT_CTL_GPIO_WAKEUP_EN_ | PMT_CTL_EEE_WAKEUP_EN_ |
  3201. PMT_CTL_WOL_EN_ | PMT_CTL_MAC_D3_RX_CLK_OVR_ |
  3202. PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ | PMT_CTL_ETH_PHY_WAKE_EN_);
  3203. macrx = lan743x_csr_read(adapter, MAC_RX);
  3204. wucsr = 0;
  3205. mask_index = 0;
  3206. pmtctl |= PMT_CTL_ETH_PHY_D3_COLD_OVR_ | PMT_CTL_ETH_PHY_D3_OVR_;
  3207. if (adapter->phy_wolopts)
  3208. pmtctl |= PMT_CTL_ETH_PHY_WAKE_EN_;
  3209. if (adapter->wolopts & WAKE_MAGIC) {
  3210. wucsr |= MAC_WUCSR_MPEN_;
  3211. macrx |= MAC_RX_RXEN_;
  3212. pmtctl |= PMT_CTL_WOL_EN_ | PMT_CTL_MAC_D3_RX_CLK_OVR_;
  3213. }
  3214. if (adapter->wolopts & WAKE_UCAST) {
  3215. wucsr |= MAC_WUCSR_RFE_WAKE_EN_ | MAC_WUCSR_PFDA_EN_;
  3216. macrx |= MAC_RX_RXEN_;
  3217. pmtctl |= PMT_CTL_WOL_EN_ | PMT_CTL_MAC_D3_RX_CLK_OVR_;
  3218. pmtctl |= PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_;
  3219. }
  3220. if (adapter->wolopts & WAKE_BCAST) {
  3221. wucsr |= MAC_WUCSR_RFE_WAKE_EN_ | MAC_WUCSR_BCST_EN_;
  3222. macrx |= MAC_RX_RXEN_;
  3223. pmtctl |= PMT_CTL_WOL_EN_ | PMT_CTL_MAC_D3_RX_CLK_OVR_;
  3224. pmtctl |= PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_;
  3225. }
  3226. if (adapter->wolopts & WAKE_MCAST) {
  3227. /* IPv4 multicast */
  3228. crc = lan743x_pm_wakeframe_crc16(ipv4_multicast, 3);
  3229. lan743x_csr_write(adapter, MAC_WUF_CFG(mask_index),
  3230. MAC_WUF_CFG_EN_ | MAC_WUF_CFG_TYPE_MCAST_ |
  3231. (0 << MAC_WUF_CFG_OFFSET_SHIFT_) |
  3232. (crc & MAC_WUF_CFG_CRC16_MASK_));
  3233. lan743x_csr_write(adapter, MAC_WUF_MASK0(mask_index), 7);
  3234. lan743x_csr_write(adapter, MAC_WUF_MASK1(mask_index), 0);
  3235. lan743x_csr_write(adapter, MAC_WUF_MASK2(mask_index), 0);
  3236. lan743x_csr_write(adapter, MAC_WUF_MASK3(mask_index), 0);
  3237. mask_index++;
  3238. /* IPv6 multicast */
  3239. crc = lan743x_pm_wakeframe_crc16(ipv6_multicast, 2);
  3240. lan743x_csr_write(adapter, MAC_WUF_CFG(mask_index),
  3241. MAC_WUF_CFG_EN_ | MAC_WUF_CFG_TYPE_MCAST_ |
  3242. (0 << MAC_WUF_CFG_OFFSET_SHIFT_) |
  3243. (crc & MAC_WUF_CFG_CRC16_MASK_));
  3244. lan743x_csr_write(adapter, MAC_WUF_MASK0(mask_index), 3);
  3245. lan743x_csr_write(adapter, MAC_WUF_MASK1(mask_index), 0);
  3246. lan743x_csr_write(adapter, MAC_WUF_MASK2(mask_index), 0);
  3247. lan743x_csr_write(adapter, MAC_WUF_MASK3(mask_index), 0);
  3248. mask_index++;
  3249. wucsr |= MAC_WUCSR_RFE_WAKE_EN_ | MAC_WUCSR_WAKE_EN_;
  3250. macrx |= MAC_RX_RXEN_;
  3251. pmtctl |= PMT_CTL_WOL_EN_ | PMT_CTL_MAC_D3_RX_CLK_OVR_;
  3252. pmtctl |= PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_;
  3253. }
  3254. if (adapter->wolopts & WAKE_ARP) {
  3255. /* set MAC_WUF_CFG & WUF_MASK
  3256. * for packettype (offset 12,13) = ARP (0x0806)
  3257. */
  3258. crc = lan743x_pm_wakeframe_crc16(arp_type, 2);
  3259. lan743x_csr_write(adapter, MAC_WUF_CFG(mask_index),
  3260. MAC_WUF_CFG_EN_ | MAC_WUF_CFG_TYPE_ALL_ |
  3261. (0 << MAC_WUF_CFG_OFFSET_SHIFT_) |
  3262. (crc & MAC_WUF_CFG_CRC16_MASK_));
  3263. lan743x_csr_write(adapter, MAC_WUF_MASK0(mask_index), 0x3000);
  3264. lan743x_csr_write(adapter, MAC_WUF_MASK1(mask_index), 0);
  3265. lan743x_csr_write(adapter, MAC_WUF_MASK2(mask_index), 0);
  3266. lan743x_csr_write(adapter, MAC_WUF_MASK3(mask_index), 0);
  3267. mask_index++;
  3268. wucsr |= MAC_WUCSR_RFE_WAKE_EN_ | MAC_WUCSR_WAKE_EN_;
  3269. macrx |= MAC_RX_RXEN_;
  3270. pmtctl |= PMT_CTL_WOL_EN_ | PMT_CTL_MAC_D3_RX_CLK_OVR_;
  3271. pmtctl |= PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_;
  3272. }
  3273. if (adapter->wolopts & WAKE_MAGICSECURE) {
  3274. sopass = *(u32 *)adapter->sopass;
  3275. lan743x_csr_write(adapter, MAC_MP_SO_LO, sopass);
  3276. sopass = *(u16 *)&adapter->sopass[4];
  3277. lan743x_csr_write(adapter, MAC_MP_SO_HI, sopass);
  3278. wucsr |= MAC_MP_SO_EN_;
  3279. }
  3280. lan743x_csr_write(adapter, MAC_WUCSR, wucsr);
  3281. lan743x_csr_write(adapter, PMT_CTL, pmtctl);
  3282. lan743x_csr_write(adapter, MAC_RX, macrx);
  3283. }
  3284. static int lan743x_pm_suspend(struct device *dev)
  3285. {
  3286. struct pci_dev *pdev = to_pci_dev(dev);
  3287. struct net_device *netdev = pci_get_drvdata(pdev);
  3288. struct lan743x_adapter *adapter = netdev_priv(netdev);
  3289. u32 data;
  3290. lan743x_pcidev_shutdown(pdev);
  3291. /* clear all wakes */
  3292. lan743x_csr_write(adapter, MAC_WUCSR, 0);
  3293. lan743x_csr_write(adapter, MAC_WUCSR2, 0);
  3294. lan743x_csr_write(adapter, MAC_WK_SRC, 0xFFFFFFFF);
  3295. if (adapter->wolopts || adapter->phy_wolopts)
  3296. lan743x_pm_set_wol(adapter);
  3297. if (adapter->is_pci11x1x) {
  3298. /* Save HW_CFG to config again in PM resume */
  3299. data = lan743x_csr_read(adapter, HW_CFG);
  3300. adapter->hw_cfg = data;
  3301. data |= (HW_CFG_RST_PROTECT_PCIE_ |
  3302. HW_CFG_D3_RESET_DIS_ |
  3303. HW_CFG_D3_VAUX_OVR_ |
  3304. HW_CFG_HOT_RESET_DIS_ |
  3305. HW_CFG_RST_PROTECT_);
  3306. lan743x_csr_write(adapter, HW_CFG, data);
  3307. }
  3308. /* Host sets PME_En, put D3hot */
  3309. return pci_prepare_to_sleep(pdev);
  3310. }
  3311. static int lan743x_pm_resume(struct device *dev)
  3312. {
  3313. struct pci_dev *pdev = to_pci_dev(dev);
  3314. struct net_device *netdev = pci_get_drvdata(pdev);
  3315. struct lan743x_adapter *adapter = netdev_priv(netdev);
  3316. u32 data;
  3317. int ret;
  3318. pci_set_power_state(pdev, PCI_D0);
  3319. pci_restore_state(pdev);
  3320. pci_save_state(pdev);
  3321. /* Restore HW_CFG that was saved during pm suspend */
  3322. if (adapter->is_pci11x1x)
  3323. lan743x_csr_write(adapter, HW_CFG, adapter->hw_cfg);
  3324. ret = lan743x_hardware_init(adapter, pdev);
  3325. if (ret) {
  3326. netif_err(adapter, probe, adapter->netdev,
  3327. "lan743x_hardware_init returned %d\n", ret);
  3328. lan743x_pci_cleanup(adapter);
  3329. return ret;
  3330. }
  3331. ret = lan743x_csr_read(adapter, MAC_WK_SRC);
  3332. netif_dbg(adapter, drv, adapter->netdev,
  3333. "Wakeup source : 0x%08X\n", ret);
  3334. /* Clear the wol configuration and status bits. Note that
  3335. * the status bits are "Write One to Clear (W1C)"
  3336. */
  3337. data = MAC_WUCSR_EEE_TX_WAKE_ | MAC_WUCSR_EEE_RX_WAKE_ |
  3338. MAC_WUCSR_RFE_WAKE_FR_ | MAC_WUCSR_PFDA_FR_ | MAC_WUCSR_WUFR_ |
  3339. MAC_WUCSR_MPR_ | MAC_WUCSR_BCAST_FR_;
  3340. lan743x_csr_write(adapter, MAC_WUCSR, data);
  3341. data = MAC_WUCSR2_NS_RCD_ | MAC_WUCSR2_ARP_RCD_ |
  3342. MAC_WUCSR2_IPV6_TCPSYN_RCD_ | MAC_WUCSR2_IPV4_TCPSYN_RCD_;
  3343. lan743x_csr_write(adapter, MAC_WUCSR2, data);
  3344. data = MAC_WK_SRC_ETH_PHY_WK_ | MAC_WK_SRC_IPV6_TCPSYN_RCD_WK_ |
  3345. MAC_WK_SRC_IPV4_TCPSYN_RCD_WK_ | MAC_WK_SRC_EEE_TX_WK_ |
  3346. MAC_WK_SRC_EEE_RX_WK_ | MAC_WK_SRC_RFE_FR_WK_ |
  3347. MAC_WK_SRC_PFDA_FR_WK_ | MAC_WK_SRC_MP_FR_WK_ |
  3348. MAC_WK_SRC_BCAST_FR_WK_ | MAC_WK_SRC_WU_FR_WK_ |
  3349. MAC_WK_SRC_WK_FR_SAVED_;
  3350. lan743x_csr_write(adapter, MAC_WK_SRC, data);
  3351. rtnl_lock();
  3352. /* open netdev when netdev is at running state while resume.
  3353. * For instance, it is true when system wakesup after pm-suspend
  3354. * However, it is false when system wakes up after suspend GUI menu
  3355. */
  3356. if (netif_running(netdev))
  3357. lan743x_netdev_open(netdev);
  3358. netif_device_attach(netdev);
  3359. rtnl_unlock();
  3360. return 0;
  3361. }
  3362. static const struct dev_pm_ops lan743x_pm_ops = {
  3363. SET_SYSTEM_SLEEP_PM_OPS(lan743x_pm_suspend, lan743x_pm_resume)
  3364. };
  3365. #endif /* CONFIG_PM_SLEEP */
  3366. static const struct pci_device_id lan743x_pcidev_tbl[] = {
  3367. { PCI_DEVICE(PCI_VENDOR_ID_SMSC, PCI_DEVICE_ID_SMSC_LAN7430) },
  3368. { PCI_DEVICE(PCI_VENDOR_ID_SMSC, PCI_DEVICE_ID_SMSC_LAN7431) },
  3369. { PCI_DEVICE(PCI_VENDOR_ID_SMSC, PCI_DEVICE_ID_SMSC_A011) },
  3370. { PCI_DEVICE(PCI_VENDOR_ID_SMSC, PCI_DEVICE_ID_SMSC_A041) },
  3371. { 0, }
  3372. };
  3373. MODULE_DEVICE_TABLE(pci, lan743x_pcidev_tbl);
  3374. static struct pci_driver lan743x_pcidev_driver = {
  3375. .name = DRIVER_NAME,
  3376. .id_table = lan743x_pcidev_tbl,
  3377. .probe = lan743x_pcidev_probe,
  3378. .remove = lan743x_pcidev_remove,
  3379. #ifdef CONFIG_PM_SLEEP
  3380. .driver.pm = &lan743x_pm_ops,
  3381. #endif
  3382. .shutdown = lan743x_pcidev_shutdown,
  3383. };
  3384. module_pci_driver(lan743x_pcidev_driver);
  3385. MODULE_AUTHOR(DRIVER_AUTHOR);
  3386. MODULE_DESCRIPTION(DRIVER_DESC);
  3387. MODULE_LICENSE("GPL");