emac.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
  3. */
  4. /* Qualcomm Technologies, Inc. EMAC Gigabit Ethernet Driver */
  5. #include <linux/if_ether.h>
  6. #include <linux/if_vlan.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/of_net.h>
  12. #include <linux/phy.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/acpi.h>
  15. #include "emac.h"
  16. #include "emac-mac.h"
  17. #include "emac-phy.h"
  18. #include "emac-sgmii.h"
  19. #define EMAC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
  20. NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
  21. #define EMAC_RRD_SIZE 4
  22. /* The RRD size if timestamping is enabled: */
  23. #define EMAC_TS_RRD_SIZE 6
  24. #define EMAC_TPD_SIZE 4
  25. #define EMAC_RFD_SIZE 2
  26. #define REG_MAC_RX_STATUS_BIN EMAC_RXMAC_STATC_REG0
  27. #define REG_MAC_RX_STATUS_END EMAC_RXMAC_STATC_REG22
  28. #define REG_MAC_TX_STATUS_BIN EMAC_TXMAC_STATC_REG0
  29. #define REG_MAC_TX_STATUS_END EMAC_TXMAC_STATC_REG24
  30. #define RXQ0_NUM_RFD_PREF_DEF 8
  31. #define TXQ0_NUM_TPD_PREF_DEF 5
  32. #define EMAC_PREAMBLE_DEF 7
  33. #define DMAR_DLY_CNT_DEF 15
  34. #define DMAW_DLY_CNT_DEF 4
  35. #define IMR_NORMAL_MASK (ISR_ERROR | ISR_OVER | ISR_TX_PKT)
  36. #define ISR_TX_PKT (\
  37. TX_PKT_INT |\
  38. TX_PKT_INT1 |\
  39. TX_PKT_INT2 |\
  40. TX_PKT_INT3)
  41. #define ISR_OVER (\
  42. RFD0_UR_INT |\
  43. RFD1_UR_INT |\
  44. RFD2_UR_INT |\
  45. RFD3_UR_INT |\
  46. RFD4_UR_INT |\
  47. RXF_OF_INT |\
  48. TXF_UR_INT)
  49. #define ISR_ERROR (\
  50. DMAR_TO_INT |\
  51. DMAW_TO_INT |\
  52. TXQ_TO_INT)
  53. /* in sync with enum emac_clk_id */
  54. static const char * const emac_clk_name[] = {
  55. "axi_clk", "cfg_ahb_clk", "high_speed_clk", "mdio_clk", "tx_clk",
  56. "rx_clk", "sys_clk"
  57. };
  58. void emac_reg_update32(void __iomem *addr, u32 mask, u32 val)
  59. {
  60. u32 data = readl(addr);
  61. writel(((data & ~mask) | val), addr);
  62. }
  63. /* reinitialize */
  64. int emac_reinit_locked(struct emac_adapter *adpt)
  65. {
  66. int ret;
  67. mutex_lock(&adpt->reset_lock);
  68. emac_mac_down(adpt);
  69. emac_sgmii_reset(adpt);
  70. ret = emac_mac_up(adpt);
  71. mutex_unlock(&adpt->reset_lock);
  72. return ret;
  73. }
  74. /* NAPI */
  75. static int emac_napi_rtx(struct napi_struct *napi, int budget)
  76. {
  77. struct emac_rx_queue *rx_q =
  78. container_of(napi, struct emac_rx_queue, napi);
  79. struct emac_adapter *adpt = netdev_priv(rx_q->netdev);
  80. struct emac_irq *irq = rx_q->irq;
  81. int work_done = 0;
  82. emac_mac_rx_process(adpt, rx_q, &work_done, budget);
  83. if (work_done < budget) {
  84. napi_complete_done(napi, work_done);
  85. irq->mask |= rx_q->intr;
  86. writel(irq->mask, adpt->base + EMAC_INT_MASK);
  87. }
  88. return work_done;
  89. }
  90. /* Transmit the packet */
  91. static netdev_tx_t emac_start_xmit(struct sk_buff *skb,
  92. struct net_device *netdev)
  93. {
  94. struct emac_adapter *adpt = netdev_priv(netdev);
  95. return emac_mac_tx_buf_send(adpt, &adpt->tx_q, skb);
  96. }
  97. static irqreturn_t emac_isr(int _irq, void *data)
  98. {
  99. struct emac_irq *irq = data;
  100. struct emac_adapter *adpt =
  101. container_of(irq, struct emac_adapter, irq);
  102. struct emac_rx_queue *rx_q = &adpt->rx_q;
  103. u32 isr, status;
  104. /* disable the interrupt */
  105. writel(0, adpt->base + EMAC_INT_MASK);
  106. isr = readl_relaxed(adpt->base + EMAC_INT_STATUS);
  107. status = isr & irq->mask;
  108. if (status == 0)
  109. goto exit;
  110. if (status & ISR_ERROR) {
  111. net_err_ratelimited("%s: error interrupt 0x%lx\n",
  112. adpt->netdev->name, status & ISR_ERROR);
  113. /* reset MAC */
  114. schedule_work(&adpt->work_thread);
  115. }
  116. /* Schedule the napi for receive queue with interrupt
  117. * status bit set
  118. */
  119. if (status & rx_q->intr) {
  120. if (napi_schedule_prep(&rx_q->napi)) {
  121. irq->mask &= ~rx_q->intr;
  122. __napi_schedule(&rx_q->napi);
  123. }
  124. }
  125. if (status & TX_PKT_INT)
  126. emac_mac_tx_process(adpt, &adpt->tx_q);
  127. if (status & ISR_OVER)
  128. net_warn_ratelimited("%s: TX/RX overflow interrupt\n",
  129. adpt->netdev->name);
  130. exit:
  131. /* enable the interrupt */
  132. writel(irq->mask, adpt->base + EMAC_INT_MASK);
  133. return IRQ_HANDLED;
  134. }
  135. /* Configure VLAN tag strip/insert feature */
  136. static int emac_set_features(struct net_device *netdev,
  137. netdev_features_t features)
  138. {
  139. netdev_features_t changed = features ^ netdev->features;
  140. struct emac_adapter *adpt = netdev_priv(netdev);
  141. /* We only need to reprogram the hardware if the VLAN tag features
  142. * have changed, and if it's already running.
  143. */
  144. if (!(changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX)))
  145. return 0;
  146. if (!netif_running(netdev))
  147. return 0;
  148. /* emac_mac_mode_config() uses netdev->features to configure the EMAC,
  149. * so make sure it's set first.
  150. */
  151. netdev->features = features;
  152. return emac_reinit_locked(adpt);
  153. }
  154. /* Configure Multicast and Promiscuous modes */
  155. static void emac_rx_mode_set(struct net_device *netdev)
  156. {
  157. struct emac_adapter *adpt = netdev_priv(netdev);
  158. struct netdev_hw_addr *ha;
  159. emac_mac_mode_config(adpt);
  160. /* update multicast address filtering */
  161. emac_mac_multicast_addr_clear(adpt);
  162. netdev_for_each_mc_addr(ha, netdev)
  163. emac_mac_multicast_addr_set(adpt, ha->addr);
  164. }
  165. /* Change the Maximum Transfer Unit (MTU) */
  166. static int emac_change_mtu(struct net_device *netdev, int new_mtu)
  167. {
  168. struct emac_adapter *adpt = netdev_priv(netdev);
  169. netif_dbg(adpt, hw, adpt->netdev,
  170. "changing MTU from %d to %d\n", netdev->mtu,
  171. new_mtu);
  172. WRITE_ONCE(netdev->mtu, new_mtu);
  173. if (netif_running(netdev))
  174. return emac_reinit_locked(adpt);
  175. return 0;
  176. }
  177. /* Called when the network interface is made active */
  178. static int emac_open(struct net_device *netdev)
  179. {
  180. struct emac_adapter *adpt = netdev_priv(netdev);
  181. struct emac_irq *irq = &adpt->irq;
  182. int ret;
  183. ret = request_irq(irq->irq, emac_isr, 0, "emac-core0", irq);
  184. if (ret) {
  185. netdev_err(adpt->netdev, "could not request emac-core0 irq\n");
  186. return ret;
  187. }
  188. /* allocate rx/tx dma buffer & descriptors */
  189. ret = emac_mac_rx_tx_rings_alloc_all(adpt);
  190. if (ret) {
  191. netdev_err(adpt->netdev, "error allocating rx/tx rings\n");
  192. free_irq(irq->irq, irq);
  193. return ret;
  194. }
  195. ret = emac_sgmii_open(adpt);
  196. if (ret) {
  197. emac_mac_rx_tx_rings_free_all(adpt);
  198. free_irq(irq->irq, irq);
  199. return ret;
  200. }
  201. ret = emac_mac_up(adpt);
  202. if (ret) {
  203. emac_mac_rx_tx_rings_free_all(adpt);
  204. free_irq(irq->irq, irq);
  205. emac_sgmii_close(adpt);
  206. return ret;
  207. }
  208. return 0;
  209. }
  210. /* Called when the network interface is disabled */
  211. static int emac_close(struct net_device *netdev)
  212. {
  213. struct emac_adapter *adpt = netdev_priv(netdev);
  214. mutex_lock(&adpt->reset_lock);
  215. emac_sgmii_close(adpt);
  216. emac_mac_down(adpt);
  217. emac_mac_rx_tx_rings_free_all(adpt);
  218. free_irq(adpt->irq.irq, &adpt->irq);
  219. mutex_unlock(&adpt->reset_lock);
  220. return 0;
  221. }
  222. /* Respond to a TX hang */
  223. static void emac_tx_timeout(struct net_device *netdev, unsigned int txqueue)
  224. {
  225. struct emac_adapter *adpt = netdev_priv(netdev);
  226. schedule_work(&adpt->work_thread);
  227. }
  228. /**
  229. * emac_update_hw_stats - read the EMAC stat registers
  230. * @adpt: pointer to adapter struct
  231. *
  232. * Reads the stats registers and write the values to adpt->stats.
  233. *
  234. * adpt->stats.lock must be held while calling this function,
  235. * and while reading from adpt->stats.
  236. */
  237. void emac_update_hw_stats(struct emac_adapter *adpt)
  238. {
  239. struct emac_stats *stats = &adpt->stats;
  240. u64 *stats_itr = &adpt->stats.rx_ok;
  241. void __iomem *base = adpt->base;
  242. unsigned int addr;
  243. addr = REG_MAC_RX_STATUS_BIN;
  244. while (addr <= REG_MAC_RX_STATUS_END) {
  245. *stats_itr += readl_relaxed(base + addr);
  246. stats_itr++;
  247. addr += sizeof(u32);
  248. }
  249. /* additional rx status */
  250. stats->rx_crc_align += readl_relaxed(base + EMAC_RXMAC_STATC_REG23);
  251. stats->rx_jabbers += readl_relaxed(base + EMAC_RXMAC_STATC_REG24);
  252. /* update tx status */
  253. addr = REG_MAC_TX_STATUS_BIN;
  254. stats_itr = &stats->tx_ok;
  255. while (addr <= REG_MAC_TX_STATUS_END) {
  256. *stats_itr += readl_relaxed(base + addr);
  257. stats_itr++;
  258. addr += sizeof(u32);
  259. }
  260. /* additional tx status */
  261. stats->tx_col += readl_relaxed(base + EMAC_TXMAC_STATC_REG25);
  262. }
  263. /* Provide network statistics info for the interface */
  264. static void emac_get_stats64(struct net_device *netdev,
  265. struct rtnl_link_stats64 *net_stats)
  266. {
  267. struct emac_adapter *adpt = netdev_priv(netdev);
  268. struct emac_stats *stats = &adpt->stats;
  269. spin_lock(&stats->lock);
  270. emac_update_hw_stats(adpt);
  271. /* return parsed statistics */
  272. net_stats->rx_packets = stats->rx_ok;
  273. net_stats->tx_packets = stats->tx_ok;
  274. net_stats->rx_bytes = stats->rx_byte_cnt;
  275. net_stats->tx_bytes = stats->tx_byte_cnt;
  276. net_stats->multicast = stats->rx_mcast;
  277. net_stats->collisions = stats->tx_1_col + stats->tx_2_col * 2 +
  278. stats->tx_late_col + stats->tx_abort_col;
  279. net_stats->rx_errors = stats->rx_frag + stats->rx_fcs_err +
  280. stats->rx_len_err + stats->rx_sz_ov +
  281. stats->rx_align_err;
  282. net_stats->rx_fifo_errors = stats->rx_rxf_ov;
  283. net_stats->rx_length_errors = stats->rx_len_err;
  284. net_stats->rx_crc_errors = stats->rx_fcs_err;
  285. net_stats->rx_frame_errors = stats->rx_align_err;
  286. net_stats->rx_over_errors = stats->rx_rxf_ov;
  287. net_stats->rx_missed_errors = stats->rx_rxf_ov;
  288. net_stats->tx_errors = stats->tx_late_col + stats->tx_abort_col +
  289. stats->tx_underrun + stats->tx_trunc;
  290. net_stats->tx_fifo_errors = stats->tx_underrun;
  291. net_stats->tx_aborted_errors = stats->tx_abort_col;
  292. net_stats->tx_window_errors = stats->tx_late_col;
  293. spin_unlock(&stats->lock);
  294. }
  295. static const struct net_device_ops emac_netdev_ops = {
  296. .ndo_open = emac_open,
  297. .ndo_stop = emac_close,
  298. .ndo_validate_addr = eth_validate_addr,
  299. .ndo_start_xmit = emac_start_xmit,
  300. .ndo_set_mac_address = eth_mac_addr,
  301. .ndo_change_mtu = emac_change_mtu,
  302. .ndo_eth_ioctl = phy_do_ioctl_running,
  303. .ndo_tx_timeout = emac_tx_timeout,
  304. .ndo_get_stats64 = emac_get_stats64,
  305. .ndo_set_features = emac_set_features,
  306. .ndo_set_rx_mode = emac_rx_mode_set,
  307. };
  308. /* Watchdog task routine, called to reinitialize the EMAC */
  309. static void emac_work_thread(struct work_struct *work)
  310. {
  311. struct emac_adapter *adpt =
  312. container_of(work, struct emac_adapter, work_thread);
  313. emac_reinit_locked(adpt);
  314. }
  315. /* Initialize various data structures */
  316. static void emac_init_adapter(struct emac_adapter *adpt)
  317. {
  318. u32 reg;
  319. adpt->rrd_size = EMAC_RRD_SIZE;
  320. adpt->tpd_size = EMAC_TPD_SIZE;
  321. adpt->rfd_size = EMAC_RFD_SIZE;
  322. /* descriptors */
  323. adpt->tx_desc_cnt = EMAC_DEF_TX_DESCS;
  324. adpt->rx_desc_cnt = EMAC_DEF_RX_DESCS;
  325. /* dma */
  326. adpt->dma_order = emac_dma_ord_out;
  327. adpt->dmar_block = emac_dma_req_4096;
  328. adpt->dmaw_block = emac_dma_req_128;
  329. adpt->dmar_dly_cnt = DMAR_DLY_CNT_DEF;
  330. adpt->dmaw_dly_cnt = DMAW_DLY_CNT_DEF;
  331. adpt->tpd_burst = TXQ0_NUM_TPD_PREF_DEF;
  332. adpt->rfd_burst = RXQ0_NUM_RFD_PREF_DEF;
  333. /* irq moderator */
  334. reg = ((EMAC_DEF_RX_IRQ_MOD >> 1) << IRQ_MODERATOR2_INIT_SHFT) |
  335. ((EMAC_DEF_TX_IRQ_MOD >> 1) << IRQ_MODERATOR_INIT_SHFT);
  336. adpt->irq_mod = reg;
  337. /* others */
  338. adpt->preamble = EMAC_PREAMBLE_DEF;
  339. /* default to automatic flow control */
  340. adpt->automatic = true;
  341. /* Disable single-pause-frame mode by default */
  342. adpt->single_pause_mode = false;
  343. }
  344. /* Get the clock */
  345. static int emac_clks_get(struct platform_device *pdev,
  346. struct emac_adapter *adpt)
  347. {
  348. unsigned int i;
  349. for (i = 0; i < EMAC_CLK_CNT; i++) {
  350. struct clk *clk = devm_clk_get(&pdev->dev, emac_clk_name[i]);
  351. if (IS_ERR(clk)) {
  352. dev_err(&pdev->dev,
  353. "could not claim clock %s (error=%li)\n",
  354. emac_clk_name[i], PTR_ERR(clk));
  355. return PTR_ERR(clk);
  356. }
  357. adpt->clk[i] = clk;
  358. }
  359. return 0;
  360. }
  361. /* Initialize clocks */
  362. static int emac_clks_phase1_init(struct platform_device *pdev,
  363. struct emac_adapter *adpt)
  364. {
  365. int ret;
  366. /* On ACPI platforms, clocks are controlled by firmware and/or
  367. * ACPI, not by drivers.
  368. */
  369. if (has_acpi_companion(&pdev->dev))
  370. return 0;
  371. ret = emac_clks_get(pdev, adpt);
  372. if (ret)
  373. return ret;
  374. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_AXI]);
  375. if (ret)
  376. return ret;
  377. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_CFG_AHB]);
  378. if (ret)
  379. goto disable_clk_axi;
  380. ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 19200000);
  381. if (ret)
  382. goto disable_clk_cfg_ahb;
  383. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_HIGH_SPEED]);
  384. if (ret)
  385. goto disable_clk_cfg_ahb;
  386. return 0;
  387. disable_clk_cfg_ahb:
  388. clk_disable_unprepare(adpt->clk[EMAC_CLK_CFG_AHB]);
  389. disable_clk_axi:
  390. clk_disable_unprepare(adpt->clk[EMAC_CLK_AXI]);
  391. return ret;
  392. }
  393. /* Enable clocks; needs emac_clks_phase1_init to be called before */
  394. static int emac_clks_phase2_init(struct platform_device *pdev,
  395. struct emac_adapter *adpt)
  396. {
  397. int ret;
  398. if (has_acpi_companion(&pdev->dev))
  399. return 0;
  400. ret = clk_set_rate(adpt->clk[EMAC_CLK_TX], 125000000);
  401. if (ret)
  402. return ret;
  403. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_TX]);
  404. if (ret)
  405. return ret;
  406. ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 125000000);
  407. if (ret)
  408. return ret;
  409. ret = clk_set_rate(adpt->clk[EMAC_CLK_MDIO], 25000000);
  410. if (ret)
  411. return ret;
  412. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_MDIO]);
  413. if (ret)
  414. return ret;
  415. ret = clk_prepare_enable(adpt->clk[EMAC_CLK_RX]);
  416. if (ret)
  417. return ret;
  418. return clk_prepare_enable(adpt->clk[EMAC_CLK_SYS]);
  419. }
  420. static void emac_clks_teardown(struct emac_adapter *adpt)
  421. {
  422. unsigned int i;
  423. for (i = 0; i < EMAC_CLK_CNT; i++)
  424. clk_disable_unprepare(adpt->clk[i]);
  425. }
  426. /* Get the resources */
  427. static int emac_probe_resources(struct platform_device *pdev,
  428. struct emac_adapter *adpt)
  429. {
  430. struct net_device *netdev = adpt->netdev;
  431. int ret = 0;
  432. /* get mac address */
  433. if (device_get_ethdev_address(&pdev->dev, netdev))
  434. eth_hw_addr_random(netdev);
  435. /* Core 0 interrupt */
  436. ret = platform_get_irq(pdev, 0);
  437. if (ret < 0)
  438. return ret;
  439. adpt->irq.irq = ret;
  440. /* base register address */
  441. adpt->base = devm_platform_ioremap_resource(pdev, 0);
  442. if (IS_ERR(adpt->base))
  443. return PTR_ERR(adpt->base);
  444. /* CSR register address */
  445. adpt->csr = devm_platform_ioremap_resource(pdev, 1);
  446. if (IS_ERR(adpt->csr))
  447. return PTR_ERR(adpt->csr);
  448. netdev->base_addr = (unsigned long)adpt->base;
  449. return 0;
  450. }
  451. static const struct of_device_id emac_dt_match[] = {
  452. {
  453. .compatible = "qcom,fsm9900-emac",
  454. },
  455. {}
  456. };
  457. MODULE_DEVICE_TABLE(of, emac_dt_match);
  458. #if IS_ENABLED(CONFIG_ACPI)
  459. static const struct acpi_device_id emac_acpi_match[] = {
  460. {
  461. .id = "QCOM8070",
  462. },
  463. {}
  464. };
  465. MODULE_DEVICE_TABLE(acpi, emac_acpi_match);
  466. #endif
  467. static int emac_probe(struct platform_device *pdev)
  468. {
  469. struct net_device *netdev;
  470. struct emac_adapter *adpt;
  471. struct emac_sgmii *phy;
  472. u16 devid, revid;
  473. u32 reg;
  474. int ret;
  475. /* The TPD buffer address is limited to:
  476. * 1. PTP: 45bits. (Driver doesn't support yet.)
  477. * 2. NON-PTP: 46bits.
  478. */
  479. ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(46));
  480. if (ret) {
  481. dev_err(&pdev->dev, "could not set DMA mask\n");
  482. return ret;
  483. }
  484. netdev = alloc_etherdev(sizeof(struct emac_adapter));
  485. if (!netdev)
  486. return -ENOMEM;
  487. dev_set_drvdata(&pdev->dev, netdev);
  488. SET_NETDEV_DEV(netdev, &pdev->dev);
  489. emac_set_ethtool_ops(netdev);
  490. adpt = netdev_priv(netdev);
  491. adpt->netdev = netdev;
  492. adpt->msg_enable = EMAC_MSG_DEFAULT;
  493. phy = &adpt->phy;
  494. atomic_set(&phy->decode_error_count, 0);
  495. mutex_init(&adpt->reset_lock);
  496. spin_lock_init(&adpt->stats.lock);
  497. adpt->irq.mask = RX_PKT_INT0 | IMR_NORMAL_MASK;
  498. ret = emac_probe_resources(pdev, adpt);
  499. if (ret)
  500. goto err_undo_netdev;
  501. /* initialize clocks */
  502. ret = emac_clks_phase1_init(pdev, adpt);
  503. if (ret) {
  504. dev_err(&pdev->dev, "could not initialize clocks\n");
  505. goto err_undo_netdev;
  506. }
  507. netdev->watchdog_timeo = EMAC_WATCHDOG_TIME;
  508. netdev->irq = adpt->irq.irq;
  509. netdev->netdev_ops = &emac_netdev_ops;
  510. emac_init_adapter(adpt);
  511. /* init external phy */
  512. ret = emac_phy_config(pdev, adpt);
  513. if (ret)
  514. goto err_undo_clocks;
  515. /* init internal sgmii phy */
  516. ret = emac_sgmii_config(pdev, adpt);
  517. if (ret)
  518. goto err_undo_mdiobus;
  519. /* enable clocks */
  520. ret = emac_clks_phase2_init(pdev, adpt);
  521. if (ret) {
  522. dev_err(&pdev->dev, "could not initialize clocks\n");
  523. goto err_undo_mdiobus;
  524. }
  525. /* set hw features */
  526. netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
  527. NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  528. NETIF_F_HW_VLAN_CTAG_TX;
  529. netdev->hw_features = netdev->features;
  530. netdev->vlan_features |= NETIF_F_SG | NETIF_F_HW_CSUM |
  531. NETIF_F_TSO | NETIF_F_TSO6;
  532. /* MTU range: 46 - 9194 */
  533. netdev->min_mtu = EMAC_MIN_ETH_FRAME_SIZE -
  534. (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  535. netdev->max_mtu = EMAC_MAX_ETH_FRAME_SIZE -
  536. (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  537. INIT_WORK(&adpt->work_thread, emac_work_thread);
  538. /* Initialize queues */
  539. emac_mac_rx_tx_ring_init_all(pdev, adpt);
  540. netif_napi_add(netdev, &adpt->rx_q.napi, emac_napi_rtx);
  541. ret = register_netdev(netdev);
  542. if (ret) {
  543. dev_err(&pdev->dev, "could not register net device\n");
  544. goto err_undo_napi;
  545. }
  546. reg = readl_relaxed(adpt->base + EMAC_DMA_MAS_CTRL);
  547. devid = (reg & DEV_ID_NUM_BMSK) >> DEV_ID_NUM_SHFT;
  548. revid = (reg & DEV_REV_NUM_BMSK) >> DEV_REV_NUM_SHFT;
  549. reg = readl_relaxed(adpt->base + EMAC_CORE_HW_VERSION);
  550. netif_info(adpt, probe, netdev,
  551. "hardware id %d.%d, hardware version %d.%d.%d\n",
  552. devid, revid,
  553. (reg & MAJOR_BMSK) >> MAJOR_SHFT,
  554. (reg & MINOR_BMSK) >> MINOR_SHFT,
  555. (reg & STEP_BMSK) >> STEP_SHFT);
  556. return 0;
  557. err_undo_napi:
  558. netif_napi_del(&adpt->rx_q.napi);
  559. err_undo_mdiobus:
  560. put_device(&adpt->phydev->mdio.dev);
  561. mdiobus_unregister(adpt->mii_bus);
  562. err_undo_clocks:
  563. emac_clks_teardown(adpt);
  564. err_undo_netdev:
  565. free_netdev(netdev);
  566. return ret;
  567. }
  568. static void emac_remove(struct platform_device *pdev)
  569. {
  570. struct net_device *netdev = dev_get_drvdata(&pdev->dev);
  571. struct emac_adapter *adpt = netdev_priv(netdev);
  572. netif_carrier_off(netdev);
  573. netif_tx_disable(netdev);
  574. unregister_netdev(netdev);
  575. netif_napi_del(&adpt->rx_q.napi);
  576. free_irq(adpt->irq.irq, &adpt->irq);
  577. cancel_work_sync(&adpt->work_thread);
  578. emac_clks_teardown(adpt);
  579. put_device(&adpt->phydev->mdio.dev);
  580. mdiobus_unregister(adpt->mii_bus);
  581. if (adpt->phy.digital)
  582. iounmap(adpt->phy.digital);
  583. iounmap(adpt->phy.base);
  584. free_netdev(netdev);
  585. }
  586. static void emac_shutdown(struct platform_device *pdev)
  587. {
  588. struct net_device *netdev = dev_get_drvdata(&pdev->dev);
  589. struct emac_adapter *adpt = netdev_priv(netdev);
  590. if (netdev->flags & IFF_UP) {
  591. /* Closing the SGMII turns off its interrupts */
  592. emac_sgmii_close(adpt);
  593. /* Resetting the MAC turns off all DMA and its interrupts */
  594. emac_mac_reset(adpt);
  595. }
  596. }
  597. static struct platform_driver emac_platform_driver = {
  598. .probe = emac_probe,
  599. .remove_new = emac_remove,
  600. .driver = {
  601. .name = "qcom-emac",
  602. .of_match_table = emac_dt_match,
  603. .acpi_match_table = ACPI_PTR(emac_acpi_match),
  604. },
  605. .shutdown = emac_shutdown,
  606. };
  607. module_platform_driver(emac_platform_driver);
  608. MODULE_DESCRIPTION("Qualcomm EMAC Gigabit Ethernet driver");
  609. MODULE_LICENSE("GPL v2");
  610. MODULE_ALIAS("platform:qcom-emac");