ef100_rx.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /****************************************************************************
  3. * Driver for Solarflare network controllers and boards
  4. * Copyright 2005-2019 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include "net_driver.h"
  11. #include "ef100_rx.h"
  12. #include "rx_common.h"
  13. #include "efx.h"
  14. #include "nic_common.h"
  15. #include "mcdi_functions.h"
  16. #include "ef100_regs.h"
  17. #include "ef100_nic.h"
  18. #include "io.h"
  19. /* Get the value of a field in the RX prefix */
  20. #define PREFIX_OFFSET_W(_f) (ESF_GZ_RX_PREFIX_ ## _f ## _LBN / 32)
  21. #define PREFIX_OFFSET_B(_f) (ESF_GZ_RX_PREFIX_ ## _f ## _LBN % 32)
  22. #define PREFIX_WIDTH_MASK(_f) ((1ULL << ESF_GZ_RX_PREFIX_ ## _f ## _WIDTH) - 1)
  23. #define PREFIX_WORD(_p, _f) le32_to_cpu((__force __le32)(_p)[PREFIX_OFFSET_W(_f)])
  24. #define PREFIX_FIELD(_p, _f) ((PREFIX_WORD(_p, _f) >> PREFIX_OFFSET_B(_f)) & \
  25. PREFIX_WIDTH_MASK(_f))
  26. #define ESF_GZ_RX_PREFIX_NT_OR_INNER_L3_CLASS_LBN \
  27. (ESF_GZ_RX_PREFIX_CLASS_LBN + ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_LBN)
  28. #define ESF_GZ_RX_PREFIX_NT_OR_INNER_L3_CLASS_WIDTH \
  29. ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_WIDTH
  30. bool ef100_rx_buf_hash_valid(const u8 *prefix)
  31. {
  32. return PREFIX_FIELD(prefix, RSS_HASH_VALID);
  33. }
  34. static bool ef100_has_fcs_error(struct efx_channel *channel, u32 *prefix)
  35. {
  36. u16 rxclass;
  37. u8 l2status;
  38. rxclass = le16_to_cpu((__force __le16)PREFIX_FIELD(prefix, CLASS));
  39. l2status = PREFIX_FIELD(&rxclass, HCLASS_L2_STATUS);
  40. if (likely(l2status == ESE_GZ_RH_HCLASS_L2_STATUS_OK))
  41. /* Everything is ok */
  42. return false;
  43. if (l2status == ESE_GZ_RH_HCLASS_L2_STATUS_FCS_ERR)
  44. channel->n_rx_eth_crc_err++;
  45. return true;
  46. }
  47. void __ef100_rx_packet(struct efx_channel *channel)
  48. {
  49. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  50. struct efx_rx_buffer *rx_buf = efx_rx_buffer(rx_queue,
  51. channel->rx_pkt_index);
  52. struct efx_nic *efx = channel->efx;
  53. struct ef100_nic_data *nic_data;
  54. u8 *eh = efx_rx_buf_va(rx_buf);
  55. __wsum csum = 0;
  56. u16 ing_port;
  57. u32 *prefix;
  58. prefix = (u32 *)(eh - ESE_GZ_RX_PKT_PREFIX_LEN);
  59. if (channel->type->receive_raw) {
  60. u32 mark = PREFIX_FIELD(prefix, USER_MARK);
  61. if (channel->type->receive_raw(rx_queue, mark))
  62. return; /* packet was consumed */
  63. }
  64. if (ef100_has_fcs_error(channel, prefix) &&
  65. unlikely(!(efx->net_dev->features & NETIF_F_RXALL)))
  66. goto out;
  67. rx_buf->len = le16_to_cpu((__force __le16)PREFIX_FIELD(prefix, LENGTH));
  68. if (rx_buf->len <= sizeof(struct ethhdr)) {
  69. if (net_ratelimit())
  70. netif_err(channel->efx, rx_err, channel->efx->net_dev,
  71. "RX packet too small (%d)\n", rx_buf->len);
  72. ++channel->n_rx_frm_trunc;
  73. goto out;
  74. }
  75. ing_port = le16_to_cpu((__force __le16) PREFIX_FIELD(prefix, INGRESS_MPORT));
  76. nic_data = efx->nic_data;
  77. if (nic_data->have_mport && ing_port != nic_data->base_mport) {
  78. #ifdef CONFIG_SFC_SRIOV
  79. struct efx_rep *efv;
  80. rcu_read_lock();
  81. efv = efx_ef100_find_rep_by_mport(efx, ing_port);
  82. if (efv) {
  83. if (efv->net_dev->flags & IFF_UP)
  84. efx_ef100_rep_rx_packet(efv, rx_buf);
  85. rcu_read_unlock();
  86. /* Representor Rx doesn't care about PF Rx buffer
  87. * ownership, it just makes a copy. So, we are done
  88. * with the Rx buffer from PF point of view and should
  89. * free it.
  90. */
  91. goto free_rx_buffer;
  92. }
  93. rcu_read_unlock();
  94. #endif
  95. if (net_ratelimit())
  96. netif_warn(efx, drv, efx->net_dev,
  97. "Unrecognised ing_port %04x (base %04x), dropping\n",
  98. ing_port, nic_data->base_mport);
  99. channel->n_rx_mport_bad++;
  100. goto free_rx_buffer;
  101. }
  102. if (likely(efx->net_dev->features & NETIF_F_RXCSUM)) {
  103. if (PREFIX_FIELD(prefix, NT_OR_INNER_L3_CLASS) == 1) {
  104. ++channel->n_rx_ip_hdr_chksum_err;
  105. } else {
  106. u16 sum = be16_to_cpu((__force __be16)PREFIX_FIELD(prefix, CSUM_FRAME));
  107. csum = (__force __wsum) sum;
  108. }
  109. }
  110. if (channel->type->receive_skb) {
  111. /* no support for special channels yet, so just discard */
  112. WARN_ON_ONCE(1);
  113. goto free_rx_buffer;
  114. }
  115. efx_rx_packet_gro(channel, rx_buf, channel->rx_pkt_n_frags, eh, csum);
  116. goto out;
  117. free_rx_buffer:
  118. efx_free_rx_buffers(rx_queue, rx_buf, 1);
  119. out:
  120. channel->rx_pkt_n_frags = 0;
  121. }
  122. static void ef100_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index)
  123. {
  124. struct efx_rx_buffer *rx_buf = efx_rx_buffer(rx_queue, index);
  125. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  126. struct efx_nic *efx = rx_queue->efx;
  127. ++rx_queue->rx_packets;
  128. netif_vdbg(efx, rx_status, efx->net_dev,
  129. "RX queue %d received id %x\n",
  130. efx_rx_queue_index(rx_queue), index);
  131. efx_sync_rx_buffer(efx, rx_buf, efx->rx_dma_len);
  132. prefetch(efx_rx_buf_va(rx_buf));
  133. rx_buf->page_offset += efx->rx_prefix_size;
  134. efx_recycle_rx_pages(channel, rx_buf, 1);
  135. efx_rx_flush_packet(channel);
  136. channel->rx_pkt_n_frags = 1;
  137. channel->rx_pkt_index = index;
  138. }
  139. void efx_ef100_ev_rx(struct efx_channel *channel, const efx_qword_t *p_event)
  140. {
  141. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  142. unsigned int n_packets =
  143. EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_NUM_PKT);
  144. int i;
  145. WARN_ON_ONCE(!n_packets);
  146. if (n_packets > 1)
  147. ++channel->n_rx_merge_events;
  148. channel->irq_mod_score += 2 * n_packets;
  149. for (i = 0; i < n_packets; ++i) {
  150. ef100_rx_packet(rx_queue,
  151. rx_queue->removed_count & rx_queue->ptr_mask);
  152. ++rx_queue->removed_count;
  153. }
  154. }
  155. void ef100_rx_write(struct efx_rx_queue *rx_queue)
  156. {
  157. unsigned int notified_count = rx_queue->notified_count;
  158. struct efx_rx_buffer *rx_buf;
  159. unsigned int idx;
  160. efx_qword_t *rxd;
  161. efx_dword_t rxdb;
  162. while (notified_count != rx_queue->added_count) {
  163. idx = notified_count & rx_queue->ptr_mask;
  164. rx_buf = efx_rx_buffer(rx_queue, idx);
  165. rxd = efx_rx_desc(rx_queue, idx);
  166. EFX_POPULATE_QWORD_1(*rxd, ESF_GZ_RX_BUF_ADDR, rx_buf->dma_addr);
  167. ++notified_count;
  168. }
  169. if (notified_count == rx_queue->notified_count)
  170. return;
  171. wmb();
  172. EFX_POPULATE_DWORD_1(rxdb, ERF_GZ_RX_RING_PIDX,
  173. rx_queue->added_count & rx_queue->ptr_mask);
  174. efx_writed_page(rx_queue->efx, &rxdb,
  175. ER_GZ_RX_RING_DOORBELL, efx_rx_queue_index(rx_queue));
  176. if (rx_queue->grant_credits)
  177. wmb();
  178. rx_queue->notified_count = notified_count;
  179. if (rx_queue->grant_credits)
  180. schedule_work(&rx_queue->grant_work);
  181. }