rx_common.c 29 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /****************************************************************************
  3. * Driver for Solarflare network controllers and boards
  4. * Copyright 2018 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include "net_driver.h"
  11. #include <linux/module.h>
  12. #include <linux/iommu.h>
  13. #include <net/rps.h>
  14. #include "efx.h"
  15. #include "nic.h"
  16. #include "rx_common.h"
  17. /* This is the percentage fill level below which new RX descriptors
  18. * will be added to the RX descriptor ring.
  19. */
  20. static unsigned int rx_refill_threshold;
  21. module_param(rx_refill_threshold, uint, 0444);
  22. MODULE_PARM_DESC(rx_refill_threshold,
  23. "RX descriptor ring refill threshold (%)");
  24. /* RX maximum head room required.
  25. *
  26. * This must be at least 1 to prevent overflow, plus one packet-worth
  27. * to allow pipelined receives.
  28. */
  29. #define EFX_RXD_HEAD_ROOM (1 + EFX_RX_MAX_FRAGS)
  30. static void efx_unmap_rx_buffer(struct efx_nic *efx,
  31. struct efx_rx_buffer *rx_buf);
  32. /* Check the RX page recycle ring for a page that can be reused. */
  33. static struct page *efx_reuse_page(struct efx_rx_queue *rx_queue)
  34. {
  35. struct efx_nic *efx = rx_queue->efx;
  36. struct efx_rx_page_state *state;
  37. unsigned int index;
  38. struct page *page;
  39. if (unlikely(!rx_queue->page_ring))
  40. return NULL;
  41. index = rx_queue->page_remove & rx_queue->page_ptr_mask;
  42. page = rx_queue->page_ring[index];
  43. if (page == NULL)
  44. return NULL;
  45. rx_queue->page_ring[index] = NULL;
  46. /* page_remove cannot exceed page_add. */
  47. if (rx_queue->page_remove != rx_queue->page_add)
  48. ++rx_queue->page_remove;
  49. /* If page_count is 1 then we hold the only reference to this page. */
  50. if (page_count(page) == 1) {
  51. ++rx_queue->page_recycle_count;
  52. return page;
  53. } else {
  54. state = page_address(page);
  55. dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
  56. PAGE_SIZE << efx->rx_buffer_order,
  57. DMA_FROM_DEVICE);
  58. put_page(page);
  59. ++rx_queue->page_recycle_failed;
  60. }
  61. return NULL;
  62. }
  63. /* Attempt to recycle the page if there is an RX recycle ring; the page can
  64. * only be added if this is the final RX buffer, to prevent pages being used in
  65. * the descriptor ring and appearing in the recycle ring simultaneously.
  66. */
  67. static void efx_recycle_rx_page(struct efx_channel *channel,
  68. struct efx_rx_buffer *rx_buf)
  69. {
  70. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  71. struct efx_nic *efx = rx_queue->efx;
  72. struct page *page = rx_buf->page;
  73. unsigned int index;
  74. /* Only recycle the page after processing the final buffer. */
  75. if (!(rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE))
  76. return;
  77. index = rx_queue->page_add & rx_queue->page_ptr_mask;
  78. if (rx_queue->page_ring[index] == NULL) {
  79. unsigned int read_index = rx_queue->page_remove &
  80. rx_queue->page_ptr_mask;
  81. /* The next slot in the recycle ring is available, but
  82. * increment page_remove if the read pointer currently
  83. * points here.
  84. */
  85. if (read_index == index)
  86. ++rx_queue->page_remove;
  87. rx_queue->page_ring[index] = page;
  88. ++rx_queue->page_add;
  89. return;
  90. }
  91. ++rx_queue->page_recycle_full;
  92. efx_unmap_rx_buffer(efx, rx_buf);
  93. put_page(rx_buf->page);
  94. }
  95. /* Recycle the pages that are used by buffers that have just been received. */
  96. void efx_siena_recycle_rx_pages(struct efx_channel *channel,
  97. struct efx_rx_buffer *rx_buf,
  98. unsigned int n_frags)
  99. {
  100. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  101. if (unlikely(!rx_queue->page_ring))
  102. return;
  103. do {
  104. efx_recycle_rx_page(channel, rx_buf);
  105. rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
  106. } while (--n_frags);
  107. }
  108. void efx_siena_discard_rx_packet(struct efx_channel *channel,
  109. struct efx_rx_buffer *rx_buf,
  110. unsigned int n_frags)
  111. {
  112. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  113. efx_siena_recycle_rx_pages(channel, rx_buf, n_frags);
  114. efx_siena_free_rx_buffers(rx_queue, rx_buf, n_frags);
  115. }
  116. static void efx_init_rx_recycle_ring(struct efx_rx_queue *rx_queue)
  117. {
  118. unsigned int bufs_in_recycle_ring, page_ring_size;
  119. struct efx_nic *efx = rx_queue->efx;
  120. bufs_in_recycle_ring = efx_rx_recycle_ring_size(efx);
  121. page_ring_size = roundup_pow_of_two(bufs_in_recycle_ring /
  122. efx->rx_bufs_per_page);
  123. rx_queue->page_ring = kcalloc(page_ring_size,
  124. sizeof(*rx_queue->page_ring), GFP_KERNEL);
  125. if (!rx_queue->page_ring)
  126. rx_queue->page_ptr_mask = 0;
  127. else
  128. rx_queue->page_ptr_mask = page_ring_size - 1;
  129. }
  130. static void efx_fini_rx_recycle_ring(struct efx_rx_queue *rx_queue)
  131. {
  132. struct efx_nic *efx = rx_queue->efx;
  133. int i;
  134. if (unlikely(!rx_queue->page_ring))
  135. return;
  136. /* Unmap and release the pages in the recycle ring. Remove the ring. */
  137. for (i = 0; i <= rx_queue->page_ptr_mask; i++) {
  138. struct page *page = rx_queue->page_ring[i];
  139. struct efx_rx_page_state *state;
  140. if (page == NULL)
  141. continue;
  142. state = page_address(page);
  143. dma_unmap_page(&efx->pci_dev->dev, state->dma_addr,
  144. PAGE_SIZE << efx->rx_buffer_order,
  145. DMA_FROM_DEVICE);
  146. put_page(page);
  147. }
  148. kfree(rx_queue->page_ring);
  149. rx_queue->page_ring = NULL;
  150. }
  151. static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue,
  152. struct efx_rx_buffer *rx_buf)
  153. {
  154. /* Release the page reference we hold for the buffer. */
  155. if (rx_buf->page)
  156. put_page(rx_buf->page);
  157. /* If this is the last buffer in a page, unmap and free it. */
  158. if (rx_buf->flags & EFX_RX_BUF_LAST_IN_PAGE) {
  159. efx_unmap_rx_buffer(rx_queue->efx, rx_buf);
  160. efx_siena_free_rx_buffers(rx_queue, rx_buf, 1);
  161. }
  162. rx_buf->page = NULL;
  163. }
  164. int efx_siena_probe_rx_queue(struct efx_rx_queue *rx_queue)
  165. {
  166. struct efx_nic *efx = rx_queue->efx;
  167. unsigned int entries;
  168. int rc;
  169. /* Create the smallest power-of-two aligned ring */
  170. entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE);
  171. EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
  172. rx_queue->ptr_mask = entries - 1;
  173. netif_dbg(efx, probe, efx->net_dev,
  174. "creating RX queue %d size %#x mask %#x\n",
  175. efx_rx_queue_index(rx_queue), efx->rxq_entries,
  176. rx_queue->ptr_mask);
  177. /* Allocate RX buffers */
  178. rx_queue->buffer = kcalloc(entries, sizeof(*rx_queue->buffer),
  179. GFP_KERNEL);
  180. if (!rx_queue->buffer)
  181. return -ENOMEM;
  182. rc = efx_nic_probe_rx(rx_queue);
  183. if (rc) {
  184. kfree(rx_queue->buffer);
  185. rx_queue->buffer = NULL;
  186. }
  187. return rc;
  188. }
  189. void efx_siena_init_rx_queue(struct efx_rx_queue *rx_queue)
  190. {
  191. unsigned int max_fill, trigger, max_trigger;
  192. struct efx_nic *efx = rx_queue->efx;
  193. int rc = 0;
  194. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  195. "initialising RX queue %d\n", efx_rx_queue_index(rx_queue));
  196. /* Initialise ptr fields */
  197. rx_queue->added_count = 0;
  198. rx_queue->notified_count = 0;
  199. rx_queue->removed_count = 0;
  200. rx_queue->min_fill = -1U;
  201. efx_init_rx_recycle_ring(rx_queue);
  202. rx_queue->page_remove = 0;
  203. rx_queue->page_add = rx_queue->page_ptr_mask + 1;
  204. rx_queue->page_recycle_count = 0;
  205. rx_queue->page_recycle_failed = 0;
  206. rx_queue->page_recycle_full = 0;
  207. /* Initialise limit fields */
  208. max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM;
  209. max_trigger =
  210. max_fill - efx->rx_pages_per_batch * efx->rx_bufs_per_page;
  211. if (rx_refill_threshold != 0) {
  212. trigger = max_fill * min(rx_refill_threshold, 100U) / 100U;
  213. if (trigger > max_trigger)
  214. trigger = max_trigger;
  215. } else {
  216. trigger = max_trigger;
  217. }
  218. rx_queue->max_fill = max_fill;
  219. rx_queue->fast_fill_trigger = trigger;
  220. rx_queue->refill_enabled = true;
  221. /* Initialise XDP queue information */
  222. rc = xdp_rxq_info_reg(&rx_queue->xdp_rxq_info, efx->net_dev,
  223. rx_queue->core_index, 0);
  224. if (rc) {
  225. netif_err(efx, rx_err, efx->net_dev,
  226. "Failure to initialise XDP queue information rc=%d\n",
  227. rc);
  228. efx->xdp_rxq_info_failed = true;
  229. } else {
  230. rx_queue->xdp_rxq_info_valid = true;
  231. }
  232. /* Set up RX descriptor ring */
  233. efx_nic_init_rx(rx_queue);
  234. }
  235. void efx_siena_fini_rx_queue(struct efx_rx_queue *rx_queue)
  236. {
  237. struct efx_rx_buffer *rx_buf;
  238. int i;
  239. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  240. "shutting down RX queue %d\n", efx_rx_queue_index(rx_queue));
  241. del_timer_sync(&rx_queue->slow_fill);
  242. /* Release RX buffers from the current read ptr to the write ptr */
  243. if (rx_queue->buffer) {
  244. for (i = rx_queue->removed_count; i < rx_queue->added_count;
  245. i++) {
  246. unsigned int index = i & rx_queue->ptr_mask;
  247. rx_buf = efx_rx_buffer(rx_queue, index);
  248. efx_fini_rx_buffer(rx_queue, rx_buf);
  249. }
  250. }
  251. efx_fini_rx_recycle_ring(rx_queue);
  252. if (rx_queue->xdp_rxq_info_valid)
  253. xdp_rxq_info_unreg(&rx_queue->xdp_rxq_info);
  254. rx_queue->xdp_rxq_info_valid = false;
  255. }
  256. void efx_siena_remove_rx_queue(struct efx_rx_queue *rx_queue)
  257. {
  258. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  259. "destroying RX queue %d\n", efx_rx_queue_index(rx_queue));
  260. efx_nic_remove_rx(rx_queue);
  261. kfree(rx_queue->buffer);
  262. rx_queue->buffer = NULL;
  263. }
  264. /* Unmap a DMA-mapped page. This function is only called for the final RX
  265. * buffer in a page.
  266. */
  267. static void efx_unmap_rx_buffer(struct efx_nic *efx,
  268. struct efx_rx_buffer *rx_buf)
  269. {
  270. struct page *page = rx_buf->page;
  271. if (page) {
  272. struct efx_rx_page_state *state = page_address(page);
  273. dma_unmap_page(&efx->pci_dev->dev,
  274. state->dma_addr,
  275. PAGE_SIZE << efx->rx_buffer_order,
  276. DMA_FROM_DEVICE);
  277. }
  278. }
  279. void efx_siena_free_rx_buffers(struct efx_rx_queue *rx_queue,
  280. struct efx_rx_buffer *rx_buf,
  281. unsigned int num_bufs)
  282. {
  283. do {
  284. if (rx_buf->page) {
  285. put_page(rx_buf->page);
  286. rx_buf->page = NULL;
  287. }
  288. rx_buf = efx_rx_buf_next(rx_queue, rx_buf);
  289. } while (--num_bufs);
  290. }
  291. void efx_siena_rx_slow_fill(struct timer_list *t)
  292. {
  293. struct efx_rx_queue *rx_queue = from_timer(rx_queue, t, slow_fill);
  294. /* Post an event to cause NAPI to run and refill the queue */
  295. efx_nic_generate_fill_event(rx_queue);
  296. ++rx_queue->slow_fill_count;
  297. }
  298. static void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue)
  299. {
  300. mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(10));
  301. }
  302. /* efx_init_rx_buffers - create EFX_RX_BATCH page-based RX buffers
  303. *
  304. * @rx_queue: Efx RX queue
  305. *
  306. * This allocates a batch of pages, maps them for DMA, and populates
  307. * struct efx_rx_buffers for each one. Return a negative error code or
  308. * 0 on success. If a single page can be used for multiple buffers,
  309. * then the page will either be inserted fully, or not at all.
  310. */
  311. static int efx_init_rx_buffers(struct efx_rx_queue *rx_queue, bool atomic)
  312. {
  313. unsigned int page_offset, index, count;
  314. struct efx_nic *efx = rx_queue->efx;
  315. struct efx_rx_page_state *state;
  316. struct efx_rx_buffer *rx_buf;
  317. dma_addr_t dma_addr;
  318. struct page *page;
  319. count = 0;
  320. do {
  321. page = efx_reuse_page(rx_queue);
  322. if (page == NULL) {
  323. page = alloc_pages(__GFP_COMP |
  324. (atomic ? GFP_ATOMIC : GFP_KERNEL),
  325. efx->rx_buffer_order);
  326. if (unlikely(page == NULL))
  327. return -ENOMEM;
  328. dma_addr =
  329. dma_map_page(&efx->pci_dev->dev, page, 0,
  330. PAGE_SIZE << efx->rx_buffer_order,
  331. DMA_FROM_DEVICE);
  332. if (unlikely(dma_mapping_error(&efx->pci_dev->dev,
  333. dma_addr))) {
  334. __free_pages(page, efx->rx_buffer_order);
  335. return -EIO;
  336. }
  337. state = page_address(page);
  338. state->dma_addr = dma_addr;
  339. } else {
  340. state = page_address(page);
  341. dma_addr = state->dma_addr;
  342. }
  343. dma_addr += sizeof(struct efx_rx_page_state);
  344. page_offset = sizeof(struct efx_rx_page_state);
  345. do {
  346. index = rx_queue->added_count & rx_queue->ptr_mask;
  347. rx_buf = efx_rx_buffer(rx_queue, index);
  348. rx_buf->dma_addr = dma_addr + efx->rx_ip_align +
  349. EFX_XDP_HEADROOM;
  350. rx_buf->page = page;
  351. rx_buf->page_offset = page_offset + efx->rx_ip_align +
  352. EFX_XDP_HEADROOM;
  353. rx_buf->len = efx->rx_dma_len;
  354. rx_buf->flags = 0;
  355. ++rx_queue->added_count;
  356. get_page(page);
  357. dma_addr += efx->rx_page_buf_step;
  358. page_offset += efx->rx_page_buf_step;
  359. } while (page_offset + efx->rx_page_buf_step <= PAGE_SIZE);
  360. rx_buf->flags = EFX_RX_BUF_LAST_IN_PAGE;
  361. } while (++count < efx->rx_pages_per_batch);
  362. return 0;
  363. }
  364. void efx_siena_rx_config_page_split(struct efx_nic *efx)
  365. {
  366. efx->rx_page_buf_step = ALIGN(efx->rx_dma_len + efx->rx_ip_align +
  367. EFX_XDP_HEADROOM + EFX_XDP_TAILROOM,
  368. EFX_RX_BUF_ALIGNMENT);
  369. efx->rx_bufs_per_page = efx->rx_buffer_order ? 1 :
  370. ((PAGE_SIZE - sizeof(struct efx_rx_page_state)) /
  371. efx->rx_page_buf_step);
  372. efx->rx_buffer_truesize = (PAGE_SIZE << efx->rx_buffer_order) /
  373. efx->rx_bufs_per_page;
  374. efx->rx_pages_per_batch = DIV_ROUND_UP(EFX_RX_PREFERRED_BATCH,
  375. efx->rx_bufs_per_page);
  376. }
  377. /* efx_siena_fast_push_rx_descriptors - push new RX descriptors quickly
  378. * @rx_queue: RX descriptor queue
  379. *
  380. * This will aim to fill the RX descriptor queue up to
  381. * @rx_queue->@max_fill. If there is insufficient atomic
  382. * memory to do so, a slow fill will be scheduled.
  383. *
  384. * The caller must provide serialisation (none is used here). In practise,
  385. * this means this function must run from the NAPI handler, or be called
  386. * when NAPI is disabled.
  387. */
  388. void efx_siena_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue,
  389. bool atomic)
  390. {
  391. struct efx_nic *efx = rx_queue->efx;
  392. unsigned int fill_level, batch_size;
  393. int space, rc = 0;
  394. if (!rx_queue->refill_enabled)
  395. return;
  396. /* Calculate current fill level, and exit if we don't need to fill */
  397. fill_level = (rx_queue->added_count - rx_queue->removed_count);
  398. EFX_WARN_ON_ONCE_PARANOID(fill_level > rx_queue->efx->rxq_entries);
  399. if (fill_level >= rx_queue->fast_fill_trigger)
  400. goto out;
  401. /* Record minimum fill level */
  402. if (unlikely(fill_level < rx_queue->min_fill)) {
  403. if (fill_level)
  404. rx_queue->min_fill = fill_level;
  405. }
  406. batch_size = efx->rx_pages_per_batch * efx->rx_bufs_per_page;
  407. space = rx_queue->max_fill - fill_level;
  408. EFX_WARN_ON_ONCE_PARANOID(space < batch_size);
  409. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  410. "RX queue %d fast-filling descriptor ring from"
  411. " level %d to level %d\n",
  412. efx_rx_queue_index(rx_queue), fill_level,
  413. rx_queue->max_fill);
  414. do {
  415. rc = efx_init_rx_buffers(rx_queue, atomic);
  416. if (unlikely(rc)) {
  417. /* Ensure that we don't leave the rx queue empty */
  418. efx_schedule_slow_fill(rx_queue);
  419. goto out;
  420. }
  421. } while ((space -= batch_size) >= batch_size);
  422. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  423. "RX queue %d fast-filled descriptor ring "
  424. "to level %d\n", efx_rx_queue_index(rx_queue),
  425. rx_queue->added_count - rx_queue->removed_count);
  426. out:
  427. if (rx_queue->notified_count != rx_queue->added_count)
  428. efx_nic_notify_rx_desc(rx_queue);
  429. }
  430. /* Pass a received packet up through GRO. GRO can handle pages
  431. * regardless of checksum state and skbs with a good checksum.
  432. */
  433. void
  434. efx_siena_rx_packet_gro(struct efx_channel *channel,
  435. struct efx_rx_buffer *rx_buf,
  436. unsigned int n_frags, u8 *eh, __wsum csum)
  437. {
  438. struct napi_struct *napi = &channel->napi_str;
  439. struct efx_nic *efx = channel->efx;
  440. struct sk_buff *skb;
  441. skb = napi_get_frags(napi);
  442. if (unlikely(!skb)) {
  443. struct efx_rx_queue *rx_queue;
  444. rx_queue = efx_channel_get_rx_queue(channel);
  445. efx_siena_free_rx_buffers(rx_queue, rx_buf, n_frags);
  446. return;
  447. }
  448. if (efx->net_dev->features & NETIF_F_RXHASH)
  449. skb_set_hash(skb, efx_rx_buf_hash(efx, eh),
  450. PKT_HASH_TYPE_L3);
  451. if (csum) {
  452. skb->csum = csum;
  453. skb->ip_summed = CHECKSUM_COMPLETE;
  454. } else {
  455. skb->ip_summed = ((rx_buf->flags & EFX_RX_PKT_CSUMMED) ?
  456. CHECKSUM_UNNECESSARY : CHECKSUM_NONE);
  457. }
  458. skb->csum_level = !!(rx_buf->flags & EFX_RX_PKT_CSUM_LEVEL);
  459. for (;;) {
  460. skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
  461. rx_buf->page, rx_buf->page_offset,
  462. rx_buf->len);
  463. rx_buf->page = NULL;
  464. skb->len += rx_buf->len;
  465. if (skb_shinfo(skb)->nr_frags == n_frags)
  466. break;
  467. rx_buf = efx_rx_buf_next(&channel->rx_queue, rx_buf);
  468. }
  469. skb->data_len = skb->len;
  470. skb->truesize += n_frags * efx->rx_buffer_truesize;
  471. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  472. napi_gro_frags(napi);
  473. }
  474. void efx_siena_set_default_rx_indir_table(struct efx_nic *efx,
  475. struct efx_rss_context *ctx)
  476. {
  477. size_t i;
  478. for (i = 0; i < ARRAY_SIZE(ctx->rx_indir_table); i++)
  479. ctx->rx_indir_table[i] =
  480. ethtool_rxfh_indir_default(i, efx->rss_spread);
  481. }
  482. /**
  483. * efx_siena_filter_is_mc_recipient - test whether spec is a multicast recipient
  484. * @spec: Specification to test
  485. *
  486. * Return: %true if the specification is a non-drop RX filter that
  487. * matches a local MAC address I/G bit value of 1 or matches a local
  488. * IPv4 or IPv6 address value in the respective multicast address
  489. * range. Otherwise %false.
  490. */
  491. bool efx_siena_filter_is_mc_recipient(const struct efx_filter_spec *spec)
  492. {
  493. if (!(spec->flags & EFX_FILTER_FLAG_RX) ||
  494. spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP)
  495. return false;
  496. if (spec->match_flags &
  497. (EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_LOC_MAC_IG) &&
  498. is_multicast_ether_addr(spec->loc_mac))
  499. return true;
  500. if ((spec->match_flags &
  501. (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
  502. (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
  503. if (spec->ether_type == htons(ETH_P_IP) &&
  504. ipv4_is_multicast(spec->loc_host[0]))
  505. return true;
  506. if (spec->ether_type == htons(ETH_P_IPV6) &&
  507. ((const u8 *)spec->loc_host)[0] == 0xff)
  508. return true;
  509. }
  510. return false;
  511. }
  512. bool efx_siena_filter_spec_equal(const struct efx_filter_spec *left,
  513. const struct efx_filter_spec *right)
  514. {
  515. if ((left->match_flags ^ right->match_flags) |
  516. ((left->flags ^ right->flags) &
  517. (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
  518. return false;
  519. return memcmp(&left->outer_vid, &right->outer_vid,
  520. sizeof(struct efx_filter_spec) -
  521. offsetof(struct efx_filter_spec, outer_vid)) == 0;
  522. }
  523. u32 efx_siena_filter_spec_hash(const struct efx_filter_spec *spec)
  524. {
  525. BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
  526. return jhash2((const u32 *)&spec->outer_vid,
  527. (sizeof(struct efx_filter_spec) -
  528. offsetof(struct efx_filter_spec, outer_vid)) / 4,
  529. 0);
  530. }
  531. #ifdef CONFIG_RFS_ACCEL
  532. bool efx_siena_rps_check_rule(struct efx_arfs_rule *rule,
  533. unsigned int filter_idx, bool *force)
  534. {
  535. if (rule->filter_id == EFX_ARFS_FILTER_ID_PENDING) {
  536. /* ARFS is currently updating this entry, leave it */
  537. return false;
  538. }
  539. if (rule->filter_id == EFX_ARFS_FILTER_ID_ERROR) {
  540. /* ARFS tried and failed to update this, so it's probably out
  541. * of date. Remove the filter and the ARFS rule entry.
  542. */
  543. rule->filter_id = EFX_ARFS_FILTER_ID_REMOVING;
  544. *force = true;
  545. return true;
  546. } else if (WARN_ON(rule->filter_id != filter_idx)) { /* can't happen */
  547. /* ARFS has moved on, so old filter is not needed. Since we did
  548. * not mark the rule with EFX_ARFS_FILTER_ID_REMOVING, it will
  549. * not be removed by efx_siena_rps_hash_del() subsequently.
  550. */
  551. *force = true;
  552. return true;
  553. }
  554. /* Remove it iff ARFS wants to. */
  555. return true;
  556. }
  557. static
  558. struct hlist_head *efx_rps_hash_bucket(struct efx_nic *efx,
  559. const struct efx_filter_spec *spec)
  560. {
  561. u32 hash = efx_siena_filter_spec_hash(spec);
  562. lockdep_assert_held(&efx->rps_hash_lock);
  563. if (!efx->rps_hash_table)
  564. return NULL;
  565. return &efx->rps_hash_table[hash % EFX_ARFS_HASH_TABLE_SIZE];
  566. }
  567. struct efx_arfs_rule *efx_siena_rps_hash_find(struct efx_nic *efx,
  568. const struct efx_filter_spec *spec)
  569. {
  570. struct efx_arfs_rule *rule;
  571. struct hlist_head *head;
  572. struct hlist_node *node;
  573. head = efx_rps_hash_bucket(efx, spec);
  574. if (!head)
  575. return NULL;
  576. hlist_for_each(node, head) {
  577. rule = container_of(node, struct efx_arfs_rule, node);
  578. if (efx_siena_filter_spec_equal(spec, &rule->spec))
  579. return rule;
  580. }
  581. return NULL;
  582. }
  583. static struct efx_arfs_rule *efx_rps_hash_add(struct efx_nic *efx,
  584. const struct efx_filter_spec *spec,
  585. bool *new)
  586. {
  587. struct efx_arfs_rule *rule;
  588. struct hlist_head *head;
  589. struct hlist_node *node;
  590. head = efx_rps_hash_bucket(efx, spec);
  591. if (!head)
  592. return NULL;
  593. hlist_for_each(node, head) {
  594. rule = container_of(node, struct efx_arfs_rule, node);
  595. if (efx_siena_filter_spec_equal(spec, &rule->spec)) {
  596. *new = false;
  597. return rule;
  598. }
  599. }
  600. rule = kmalloc(sizeof(*rule), GFP_ATOMIC);
  601. *new = true;
  602. if (rule) {
  603. memcpy(&rule->spec, spec, sizeof(rule->spec));
  604. hlist_add_head(&rule->node, head);
  605. }
  606. return rule;
  607. }
  608. void efx_siena_rps_hash_del(struct efx_nic *efx,
  609. const struct efx_filter_spec *spec)
  610. {
  611. struct efx_arfs_rule *rule;
  612. struct hlist_head *head;
  613. struct hlist_node *node;
  614. head = efx_rps_hash_bucket(efx, spec);
  615. if (WARN_ON(!head))
  616. return;
  617. hlist_for_each(node, head) {
  618. rule = container_of(node, struct efx_arfs_rule, node);
  619. if (efx_siena_filter_spec_equal(spec, &rule->spec)) {
  620. /* Someone already reused the entry. We know that if
  621. * this check doesn't fire (i.e. filter_id == REMOVING)
  622. * then the REMOVING mark was put there by our caller,
  623. * because caller is holding a lock on filter table and
  624. * only holders of that lock set REMOVING.
  625. */
  626. if (rule->filter_id != EFX_ARFS_FILTER_ID_REMOVING)
  627. return;
  628. hlist_del(node);
  629. kfree(rule);
  630. return;
  631. }
  632. }
  633. /* We didn't find it. */
  634. WARN_ON(1);
  635. }
  636. #endif
  637. int efx_siena_probe_filters(struct efx_nic *efx)
  638. {
  639. int rc;
  640. mutex_lock(&efx->mac_lock);
  641. down_write(&efx->filter_sem);
  642. rc = efx->type->filter_table_probe(efx);
  643. if (rc)
  644. goto out_unlock;
  645. #ifdef CONFIG_RFS_ACCEL
  646. if (efx->type->offload_features & NETIF_F_NTUPLE) {
  647. struct efx_channel *channel;
  648. int i, success = 1;
  649. efx_for_each_channel(channel, efx) {
  650. channel->rps_flow_id =
  651. kcalloc(efx->type->max_rx_ip_filters,
  652. sizeof(*channel->rps_flow_id),
  653. GFP_KERNEL);
  654. if (!channel->rps_flow_id)
  655. success = 0;
  656. else
  657. for (i = 0;
  658. i < efx->type->max_rx_ip_filters;
  659. ++i)
  660. channel->rps_flow_id[i] =
  661. RPS_FLOW_ID_INVALID;
  662. channel->rfs_expire_index = 0;
  663. channel->rfs_filter_count = 0;
  664. }
  665. if (!success) {
  666. efx_for_each_channel(channel, efx)
  667. kfree(channel->rps_flow_id);
  668. efx->type->filter_table_remove(efx);
  669. rc = -ENOMEM;
  670. goto out_unlock;
  671. }
  672. }
  673. #endif
  674. out_unlock:
  675. up_write(&efx->filter_sem);
  676. mutex_unlock(&efx->mac_lock);
  677. return rc;
  678. }
  679. void efx_siena_remove_filters(struct efx_nic *efx)
  680. {
  681. #ifdef CONFIG_RFS_ACCEL
  682. struct efx_channel *channel;
  683. efx_for_each_channel(channel, efx) {
  684. cancel_delayed_work_sync(&channel->filter_work);
  685. kfree(channel->rps_flow_id);
  686. channel->rps_flow_id = NULL;
  687. }
  688. #endif
  689. down_write(&efx->filter_sem);
  690. efx->type->filter_table_remove(efx);
  691. up_write(&efx->filter_sem);
  692. }
  693. #ifdef CONFIG_RFS_ACCEL
  694. static void efx_filter_rfs_work(struct work_struct *data)
  695. {
  696. struct efx_async_filter_insertion *req = container_of(data, struct efx_async_filter_insertion,
  697. work);
  698. struct efx_nic *efx = netdev_priv(req->net_dev);
  699. struct efx_channel *channel = efx_get_channel(efx, req->rxq_index);
  700. int slot_idx = req - efx->rps_slot;
  701. struct efx_arfs_rule *rule;
  702. u16 arfs_id = 0;
  703. int rc;
  704. rc = efx->type->filter_insert(efx, &req->spec, true);
  705. if (rc >= 0)
  706. /* Discard 'priority' part of EF10+ filter ID (mcdi_filters) */
  707. rc %= efx->type->max_rx_ip_filters;
  708. if (efx->rps_hash_table) {
  709. spin_lock_bh(&efx->rps_hash_lock);
  710. rule = efx_siena_rps_hash_find(efx, &req->spec);
  711. /* The rule might have already gone, if someone else's request
  712. * for the same spec was already worked and then expired before
  713. * we got around to our work. In that case we have nothing
  714. * tying us to an arfs_id, meaning that as soon as the filter
  715. * is considered for expiry it will be removed.
  716. */
  717. if (rule) {
  718. if (rc < 0)
  719. rule->filter_id = EFX_ARFS_FILTER_ID_ERROR;
  720. else
  721. rule->filter_id = rc;
  722. arfs_id = rule->arfs_id;
  723. }
  724. spin_unlock_bh(&efx->rps_hash_lock);
  725. }
  726. if (rc >= 0) {
  727. /* Remember this so we can check whether to expire the filter
  728. * later.
  729. */
  730. mutex_lock(&efx->rps_mutex);
  731. if (channel->rps_flow_id[rc] == RPS_FLOW_ID_INVALID)
  732. channel->rfs_filter_count++;
  733. channel->rps_flow_id[rc] = req->flow_id;
  734. mutex_unlock(&efx->rps_mutex);
  735. if (req->spec.ether_type == htons(ETH_P_IP))
  736. netif_info(efx, rx_status, efx->net_dev,
  737. "steering %s %pI4:%u:%pI4:%u to queue %u [flow %u filter %d id %u]\n",
  738. (req->spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  739. req->spec.rem_host, ntohs(req->spec.rem_port),
  740. req->spec.loc_host, ntohs(req->spec.loc_port),
  741. req->rxq_index, req->flow_id, rc, arfs_id);
  742. else
  743. netif_info(efx, rx_status, efx->net_dev,
  744. "steering %s [%pI6]:%u:[%pI6]:%u to queue %u [flow %u filter %d id %u]\n",
  745. (req->spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  746. req->spec.rem_host, ntohs(req->spec.rem_port),
  747. req->spec.loc_host, ntohs(req->spec.loc_port),
  748. req->rxq_index, req->flow_id, rc, arfs_id);
  749. channel->n_rfs_succeeded++;
  750. } else {
  751. if (req->spec.ether_type == htons(ETH_P_IP))
  752. netif_dbg(efx, rx_status, efx->net_dev,
  753. "failed to steer %s %pI4:%u:%pI4:%u to queue %u [flow %u rc %d id %u]\n",
  754. (req->spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  755. req->spec.rem_host, ntohs(req->spec.rem_port),
  756. req->spec.loc_host, ntohs(req->spec.loc_port),
  757. req->rxq_index, req->flow_id, rc, arfs_id);
  758. else
  759. netif_dbg(efx, rx_status, efx->net_dev,
  760. "failed to steer %s [%pI6]:%u:[%pI6]:%u to queue %u [flow %u rc %d id %u]\n",
  761. (req->spec.ip_proto == IPPROTO_TCP) ? "TCP" : "UDP",
  762. req->spec.rem_host, ntohs(req->spec.rem_port),
  763. req->spec.loc_host, ntohs(req->spec.loc_port),
  764. req->rxq_index, req->flow_id, rc, arfs_id);
  765. channel->n_rfs_failed++;
  766. /* We're overloading the NIC's filter tables, so let's do a
  767. * chunk of extra expiry work.
  768. */
  769. __efx_siena_filter_rfs_expire(channel,
  770. min(channel->rfs_filter_count,
  771. 100u));
  772. }
  773. /* Release references */
  774. clear_bit(slot_idx, &efx->rps_slot_map);
  775. dev_put(req->net_dev);
  776. }
  777. int efx_siena_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
  778. u16 rxq_index, u32 flow_id)
  779. {
  780. struct efx_nic *efx = netdev_priv(net_dev);
  781. struct efx_async_filter_insertion *req;
  782. struct efx_arfs_rule *rule;
  783. struct flow_keys fk;
  784. int slot_idx;
  785. bool new;
  786. int rc;
  787. /* find a free slot */
  788. for (slot_idx = 0; slot_idx < EFX_RPS_MAX_IN_FLIGHT; slot_idx++)
  789. if (!test_and_set_bit(slot_idx, &efx->rps_slot_map))
  790. break;
  791. if (slot_idx >= EFX_RPS_MAX_IN_FLIGHT)
  792. return -EBUSY;
  793. if (flow_id == RPS_FLOW_ID_INVALID) {
  794. rc = -EINVAL;
  795. goto out_clear;
  796. }
  797. if (!skb_flow_dissect_flow_keys(skb, &fk, 0)) {
  798. rc = -EPROTONOSUPPORT;
  799. goto out_clear;
  800. }
  801. if (fk.basic.n_proto != htons(ETH_P_IP) && fk.basic.n_proto != htons(ETH_P_IPV6)) {
  802. rc = -EPROTONOSUPPORT;
  803. goto out_clear;
  804. }
  805. if (fk.control.flags & FLOW_DIS_IS_FRAGMENT) {
  806. rc = -EPROTONOSUPPORT;
  807. goto out_clear;
  808. }
  809. req = efx->rps_slot + slot_idx;
  810. efx_filter_init_rx(&req->spec, EFX_FILTER_PRI_HINT,
  811. efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0,
  812. rxq_index);
  813. req->spec.match_flags =
  814. EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
  815. EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
  816. EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
  817. req->spec.ether_type = fk.basic.n_proto;
  818. req->spec.ip_proto = fk.basic.ip_proto;
  819. if (fk.basic.n_proto == htons(ETH_P_IP)) {
  820. req->spec.rem_host[0] = fk.addrs.v4addrs.src;
  821. req->spec.loc_host[0] = fk.addrs.v4addrs.dst;
  822. } else {
  823. memcpy(req->spec.rem_host, &fk.addrs.v6addrs.src,
  824. sizeof(struct in6_addr));
  825. memcpy(req->spec.loc_host, &fk.addrs.v6addrs.dst,
  826. sizeof(struct in6_addr));
  827. }
  828. req->spec.rem_port = fk.ports.src;
  829. req->spec.loc_port = fk.ports.dst;
  830. if (efx->rps_hash_table) {
  831. /* Add it to ARFS hash table */
  832. spin_lock(&efx->rps_hash_lock);
  833. rule = efx_rps_hash_add(efx, &req->spec, &new);
  834. if (!rule) {
  835. rc = -ENOMEM;
  836. goto out_unlock;
  837. }
  838. if (new)
  839. rule->arfs_id = efx->rps_next_id++ % RPS_NO_FILTER;
  840. rc = rule->arfs_id;
  841. /* Skip if existing or pending filter already does the right thing */
  842. if (!new && rule->rxq_index == rxq_index &&
  843. rule->filter_id >= EFX_ARFS_FILTER_ID_PENDING)
  844. goto out_unlock;
  845. rule->rxq_index = rxq_index;
  846. rule->filter_id = EFX_ARFS_FILTER_ID_PENDING;
  847. spin_unlock(&efx->rps_hash_lock);
  848. } else {
  849. /* Without an ARFS hash table, we just use arfs_id 0 for all
  850. * filters. This means if multiple flows hash to the same
  851. * flow_id, all but the most recently touched will be eligible
  852. * for expiry.
  853. */
  854. rc = 0;
  855. }
  856. /* Queue the request */
  857. dev_hold(req->net_dev = net_dev);
  858. INIT_WORK(&req->work, efx_filter_rfs_work);
  859. req->rxq_index = rxq_index;
  860. req->flow_id = flow_id;
  861. schedule_work(&req->work);
  862. return rc;
  863. out_unlock:
  864. spin_unlock(&efx->rps_hash_lock);
  865. out_clear:
  866. clear_bit(slot_idx, &efx->rps_slot_map);
  867. return rc;
  868. }
  869. bool __efx_siena_filter_rfs_expire(struct efx_channel *channel,
  870. unsigned int quota)
  871. {
  872. bool (*expire_one)(struct efx_nic *efx, u32 flow_id, unsigned int index);
  873. struct efx_nic *efx = channel->efx;
  874. unsigned int index, size, start;
  875. u32 flow_id;
  876. if (!mutex_trylock(&efx->rps_mutex))
  877. return false;
  878. expire_one = efx->type->filter_rfs_expire_one;
  879. index = channel->rfs_expire_index;
  880. start = index;
  881. size = efx->type->max_rx_ip_filters;
  882. while (quota) {
  883. flow_id = channel->rps_flow_id[index];
  884. if (flow_id != RPS_FLOW_ID_INVALID) {
  885. quota--;
  886. if (expire_one(efx, flow_id, index)) {
  887. netif_info(efx, rx_status, efx->net_dev,
  888. "expired filter %d [channel %u flow %u]\n",
  889. index, channel->channel, flow_id);
  890. channel->rps_flow_id[index] = RPS_FLOW_ID_INVALID;
  891. channel->rfs_filter_count--;
  892. }
  893. }
  894. if (++index == size)
  895. index = 0;
  896. /* If we were called with a quota that exceeds the total number
  897. * of filters in the table (which shouldn't happen, but could
  898. * if two callers race), ensure that we don't loop forever -
  899. * stop when we've examined every row of the table.
  900. */
  901. if (index == start)
  902. break;
  903. }
  904. channel->rfs_expire_index = index;
  905. mutex_unlock(&efx->rps_mutex);
  906. return true;
  907. }
  908. #endif /* CONFIG_RFS_ACCEL */