tx_common.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /****************************************************************************
  3. * Driver for Solarflare network controllers and boards
  4. * Copyright 2018 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include "net_driver.h"
  11. #include "efx.h"
  12. #include "nic_common.h"
  13. #include "tx_common.h"
  14. #include <net/gso.h>
  15. static unsigned int efx_tx_cb_page_count(struct efx_tx_queue *tx_queue)
  16. {
  17. return DIV_ROUND_UP(tx_queue->ptr_mask + 1,
  18. PAGE_SIZE >> EFX_TX_CB_ORDER);
  19. }
  20. int efx_siena_probe_tx_queue(struct efx_tx_queue *tx_queue)
  21. {
  22. struct efx_nic *efx = tx_queue->efx;
  23. unsigned int entries;
  24. int rc;
  25. /* Create the smallest power-of-two aligned ring */
  26. entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
  27. EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
  28. tx_queue->ptr_mask = entries - 1;
  29. netif_dbg(efx, probe, efx->net_dev,
  30. "creating TX queue %d size %#x mask %#x\n",
  31. tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
  32. /* Allocate software ring */
  33. tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
  34. GFP_KERNEL);
  35. if (!tx_queue->buffer)
  36. return -ENOMEM;
  37. tx_queue->cb_page = kcalloc(efx_tx_cb_page_count(tx_queue),
  38. sizeof(tx_queue->cb_page[0]), GFP_KERNEL);
  39. if (!tx_queue->cb_page) {
  40. rc = -ENOMEM;
  41. goto fail1;
  42. }
  43. /* Allocate hardware ring, determine TXQ type */
  44. rc = efx_nic_probe_tx(tx_queue);
  45. if (rc)
  46. goto fail2;
  47. tx_queue->channel->tx_queue_by_type[tx_queue->type] = tx_queue;
  48. return 0;
  49. fail2:
  50. kfree(tx_queue->cb_page);
  51. tx_queue->cb_page = NULL;
  52. fail1:
  53. kfree(tx_queue->buffer);
  54. tx_queue->buffer = NULL;
  55. return rc;
  56. }
  57. void efx_siena_init_tx_queue(struct efx_tx_queue *tx_queue)
  58. {
  59. struct efx_nic *efx = tx_queue->efx;
  60. netif_dbg(efx, drv, efx->net_dev,
  61. "initialising TX queue %d\n", tx_queue->queue);
  62. tx_queue->insert_count = 0;
  63. tx_queue->notify_count = 0;
  64. tx_queue->write_count = 0;
  65. tx_queue->packet_write_count = 0;
  66. tx_queue->old_write_count = 0;
  67. tx_queue->read_count = 0;
  68. tx_queue->old_read_count = 0;
  69. tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
  70. tx_queue->xmit_pending = false;
  71. tx_queue->timestamping = (efx_siena_ptp_use_mac_tx_timestamps(efx) &&
  72. tx_queue->channel == efx_siena_ptp_channel(efx));
  73. tx_queue->completed_timestamp_major = 0;
  74. tx_queue->completed_timestamp_minor = 0;
  75. tx_queue->xdp_tx = efx_channel_is_xdp_tx(tx_queue->channel);
  76. tx_queue->tso_version = 0;
  77. /* Set up TX descriptor ring */
  78. efx_nic_init_tx(tx_queue);
  79. tx_queue->initialised = true;
  80. }
  81. void efx_siena_remove_tx_queue(struct efx_tx_queue *tx_queue)
  82. {
  83. int i;
  84. if (!tx_queue->buffer)
  85. return;
  86. netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
  87. "destroying TX queue %d\n", tx_queue->queue);
  88. efx_nic_remove_tx(tx_queue);
  89. if (tx_queue->cb_page) {
  90. for (i = 0; i < efx_tx_cb_page_count(tx_queue); i++)
  91. efx_siena_free_buffer(tx_queue->efx,
  92. &tx_queue->cb_page[i]);
  93. kfree(tx_queue->cb_page);
  94. tx_queue->cb_page = NULL;
  95. }
  96. kfree(tx_queue->buffer);
  97. tx_queue->buffer = NULL;
  98. tx_queue->channel->tx_queue_by_type[tx_queue->type] = NULL;
  99. }
  100. static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  101. struct efx_tx_buffer *buffer,
  102. unsigned int *pkts_compl,
  103. unsigned int *bytes_compl)
  104. {
  105. if (buffer->unmap_len) {
  106. struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
  107. dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
  108. if (buffer->flags & EFX_TX_BUF_MAP_SINGLE)
  109. dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
  110. DMA_TO_DEVICE);
  111. else
  112. dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
  113. DMA_TO_DEVICE);
  114. buffer->unmap_len = 0;
  115. }
  116. if (buffer->flags & EFX_TX_BUF_SKB) {
  117. struct sk_buff *skb = (struct sk_buff *)buffer->skb;
  118. EFX_WARN_ON_PARANOID(!pkts_compl || !bytes_compl);
  119. (*pkts_compl)++;
  120. (*bytes_compl) += skb->len;
  121. if (tx_queue->timestamping &&
  122. (tx_queue->completed_timestamp_major ||
  123. tx_queue->completed_timestamp_minor)) {
  124. struct skb_shared_hwtstamps hwtstamp;
  125. hwtstamp.hwtstamp =
  126. efx_siena_ptp_nic_to_kernel_time(tx_queue);
  127. skb_tstamp_tx(skb, &hwtstamp);
  128. tx_queue->completed_timestamp_major = 0;
  129. tx_queue->completed_timestamp_minor = 0;
  130. }
  131. dev_consume_skb_any((struct sk_buff *)buffer->skb);
  132. netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
  133. "TX queue %d transmission id %x complete\n",
  134. tx_queue->queue, tx_queue->read_count);
  135. } else if (buffer->flags & EFX_TX_BUF_XDP) {
  136. xdp_return_frame_rx_napi(buffer->xdpf);
  137. }
  138. buffer->len = 0;
  139. buffer->flags = 0;
  140. }
  141. void efx_siena_fini_tx_queue(struct efx_tx_queue *tx_queue)
  142. {
  143. struct efx_tx_buffer *buffer;
  144. netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
  145. "shutting down TX queue %d\n", tx_queue->queue);
  146. if (!tx_queue->buffer)
  147. return;
  148. /* Free any buffers left in the ring */
  149. while (tx_queue->read_count != tx_queue->write_count) {
  150. unsigned int pkts_compl = 0, bytes_compl = 0;
  151. buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
  152. efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
  153. ++tx_queue->read_count;
  154. }
  155. tx_queue->xmit_pending = false;
  156. netdev_tx_reset_queue(tx_queue->core_txq);
  157. }
  158. /* Remove packets from the TX queue
  159. *
  160. * This removes packets from the TX queue, up to and including the
  161. * specified index.
  162. */
  163. static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
  164. unsigned int index,
  165. unsigned int *pkts_compl,
  166. unsigned int *bytes_compl)
  167. {
  168. struct efx_nic *efx = tx_queue->efx;
  169. unsigned int stop_index, read_ptr;
  170. stop_index = (index + 1) & tx_queue->ptr_mask;
  171. read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
  172. while (read_ptr != stop_index) {
  173. struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
  174. if (!efx_tx_buffer_in_use(buffer)) {
  175. netif_err(efx, tx_err, efx->net_dev,
  176. "TX queue %d spurious TX completion id %d\n",
  177. tx_queue->queue, read_ptr);
  178. efx_siena_schedule_reset(efx, RESET_TYPE_TX_SKIP);
  179. return;
  180. }
  181. efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl);
  182. ++tx_queue->read_count;
  183. read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
  184. }
  185. }
  186. void efx_siena_xmit_done_check_empty(struct efx_tx_queue *tx_queue)
  187. {
  188. if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
  189. tx_queue->old_write_count = READ_ONCE(tx_queue->write_count);
  190. if (tx_queue->read_count == tx_queue->old_write_count) {
  191. /* Ensure that read_count is flushed. */
  192. smp_mb();
  193. tx_queue->empty_read_count =
  194. tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
  195. }
  196. }
  197. }
  198. void efx_siena_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
  199. {
  200. unsigned int fill_level, pkts_compl = 0, bytes_compl = 0;
  201. struct efx_nic *efx = tx_queue->efx;
  202. EFX_WARN_ON_ONCE_PARANOID(index > tx_queue->ptr_mask);
  203. efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl);
  204. tx_queue->pkts_compl += pkts_compl;
  205. tx_queue->bytes_compl += bytes_compl;
  206. if (pkts_compl > 1)
  207. ++tx_queue->merge_events;
  208. /* See if we need to restart the netif queue. This memory
  209. * barrier ensures that we write read_count (inside
  210. * efx_dequeue_buffers()) before reading the queue status.
  211. */
  212. smp_mb();
  213. if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) &&
  214. likely(efx->port_enabled) &&
  215. likely(netif_device_present(efx->net_dev))) {
  216. fill_level = efx_channel_tx_fill_level(tx_queue->channel);
  217. if (fill_level <= efx->txq_wake_thresh)
  218. netif_tx_wake_queue(tx_queue->core_txq);
  219. }
  220. efx_siena_xmit_done_check_empty(tx_queue);
  221. }
  222. /* Remove buffers put into a tx_queue for the current packet.
  223. * None of the buffers must have an skb attached.
  224. */
  225. void efx_siena_enqueue_unwind(struct efx_tx_queue *tx_queue,
  226. unsigned int insert_count)
  227. {
  228. struct efx_tx_buffer *buffer;
  229. unsigned int bytes_compl = 0;
  230. unsigned int pkts_compl = 0;
  231. /* Work backwards until we hit the original insert pointer value */
  232. while (tx_queue->insert_count != insert_count) {
  233. --tx_queue->insert_count;
  234. buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
  235. efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
  236. }
  237. }
  238. struct efx_tx_buffer *efx_siena_tx_map_chunk(struct efx_tx_queue *tx_queue,
  239. dma_addr_t dma_addr, size_t len)
  240. {
  241. const struct efx_nic_type *nic_type = tx_queue->efx->type;
  242. struct efx_tx_buffer *buffer;
  243. unsigned int dma_len;
  244. /* Map the fragment taking account of NIC-dependent DMA limits. */
  245. do {
  246. buffer = efx_tx_queue_get_insert_buffer(tx_queue);
  247. if (nic_type->tx_limit_len)
  248. dma_len = nic_type->tx_limit_len(tx_queue, dma_addr, len);
  249. else
  250. dma_len = len;
  251. buffer->len = dma_len;
  252. buffer->dma_addr = dma_addr;
  253. buffer->flags = EFX_TX_BUF_CONT;
  254. len -= dma_len;
  255. dma_addr += dma_len;
  256. ++tx_queue->insert_count;
  257. } while (len);
  258. return buffer;
  259. }
  260. static int efx_tx_tso_header_length(struct sk_buff *skb)
  261. {
  262. size_t header_len;
  263. if (skb->encapsulation)
  264. header_len = skb_inner_transport_offset(skb) +
  265. (inner_tcp_hdr(skb)->doff << 2u);
  266. else
  267. header_len = skb_transport_offset(skb) +
  268. (tcp_hdr(skb)->doff << 2u);
  269. return header_len;
  270. }
  271. /* Map all data from an SKB for DMA and create descriptors on the queue. */
  272. int efx_siena_tx_map_data(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
  273. unsigned int segment_count)
  274. {
  275. struct efx_nic *efx = tx_queue->efx;
  276. struct device *dma_dev = &efx->pci_dev->dev;
  277. unsigned int frag_index, nr_frags;
  278. dma_addr_t dma_addr, unmap_addr;
  279. unsigned short dma_flags;
  280. size_t len, unmap_len;
  281. nr_frags = skb_shinfo(skb)->nr_frags;
  282. frag_index = 0;
  283. /* Map header data. */
  284. len = skb_headlen(skb);
  285. dma_addr = dma_map_single(dma_dev, skb->data, len, DMA_TO_DEVICE);
  286. dma_flags = EFX_TX_BUF_MAP_SINGLE;
  287. unmap_len = len;
  288. unmap_addr = dma_addr;
  289. if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
  290. return -EIO;
  291. if (segment_count) {
  292. /* For TSO we need to put the header in to a separate
  293. * descriptor. Map this separately if necessary.
  294. */
  295. size_t header_len = efx_tx_tso_header_length(skb);
  296. if (header_len != len) {
  297. tx_queue->tso_long_headers++;
  298. efx_siena_tx_map_chunk(tx_queue, dma_addr, header_len);
  299. len -= header_len;
  300. dma_addr += header_len;
  301. }
  302. }
  303. /* Add descriptors for each fragment. */
  304. do {
  305. struct efx_tx_buffer *buffer;
  306. skb_frag_t *fragment;
  307. buffer = efx_siena_tx_map_chunk(tx_queue, dma_addr, len);
  308. /* The final descriptor for a fragment is responsible for
  309. * unmapping the whole fragment.
  310. */
  311. buffer->flags = EFX_TX_BUF_CONT | dma_flags;
  312. buffer->unmap_len = unmap_len;
  313. buffer->dma_offset = buffer->dma_addr - unmap_addr;
  314. if (frag_index >= nr_frags) {
  315. /* Store SKB details with the final buffer for
  316. * the completion.
  317. */
  318. buffer->skb = skb;
  319. buffer->flags = EFX_TX_BUF_SKB | dma_flags;
  320. return 0;
  321. }
  322. /* Move on to the next fragment. */
  323. fragment = &skb_shinfo(skb)->frags[frag_index++];
  324. len = skb_frag_size(fragment);
  325. dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len,
  326. DMA_TO_DEVICE);
  327. dma_flags = 0;
  328. unmap_len = len;
  329. unmap_addr = dma_addr;
  330. if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
  331. return -EIO;
  332. } while (1);
  333. }
  334. unsigned int efx_siena_tx_max_skb_descs(struct efx_nic *efx)
  335. {
  336. /* Header and payload descriptor for each output segment, plus
  337. * one for every input fragment boundary within a segment
  338. */
  339. unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
  340. /* Possibly one more per segment for option descriptors */
  341. if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
  342. max_descs += EFX_TSO_MAX_SEGS;
  343. /* Possibly more for PCIe page boundaries within input fragments */
  344. if (PAGE_SIZE > EFX_PAGE_SIZE)
  345. max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
  346. DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE));
  347. return max_descs;
  348. }
  349. /*
  350. * Fallback to software TSO.
  351. *
  352. * This is used if we are unable to send a GSO packet through hardware TSO.
  353. * This should only ever happen due to per-queue restrictions - unsupported
  354. * packets should first be filtered by the feature flags.
  355. *
  356. * Returns 0 on success, error code otherwise.
  357. */
  358. int efx_siena_tx_tso_fallback(struct efx_tx_queue *tx_queue,
  359. struct sk_buff *skb)
  360. {
  361. struct sk_buff *segments, *next;
  362. segments = skb_gso_segment(skb, 0);
  363. if (IS_ERR(segments))
  364. return PTR_ERR(segments);
  365. dev_consume_skb_any(skb);
  366. skb_list_walk_safe(segments, skb, next) {
  367. skb_mark_not_on_list(skb);
  368. efx_enqueue_skb(tx_queue, skb);
  369. }
  370. return 0;
  371. }