stmmac_ptp.h 4.1 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /******************************************************************************
  3. PTP Header file
  4. Copyright (C) 2013 Vayavya Labs Pvt Ltd
  5. Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
  6. ******************************************************************************/
  7. #ifndef __STMMAC_PTP_H__
  8. #define __STMMAC_PTP_H__
  9. #define PTP_XGMAC_OFFSET 0xd00
  10. #define PTP_GMAC4_OFFSET 0xb00
  11. #define PTP_GMAC3_X_OFFSET 0x700
  12. /* IEEE 1588 PTP register offsets */
  13. #define PTP_TCR 0x00 /* Timestamp Control Reg */
  14. #define PTP_SSIR 0x04 /* Sub-Second Increment Reg */
  15. #define PTP_STSR 0x08 /* System Time – Seconds Regr */
  16. #define PTP_STNSR 0x0c /* System Time – Nanoseconds Reg */
  17. #define PTP_STSUR 0x10 /* System Time – Seconds Update Reg */
  18. #define PTP_STNSUR 0x14 /* System Time – Nanoseconds Update Reg */
  19. #define PTP_TAR 0x18 /* Timestamp Addend Reg */
  20. #define PTP_ACR 0x40 /* Auxiliary Control Reg */
  21. #define PTP_ATNR 0x48 /* Auxiliary Timestamp - Nanoseconds Reg */
  22. #define PTP_ATSR 0x4c /* Auxiliary Timestamp - Seconds Reg */
  23. #define PTP_TS_INGR_CORR_NS 0x58 /* Ingress timestamp correction nanoseconds */
  24. #define PTP_TS_EGR_CORR_NS 0x5C /* Egress timestamp correction nanoseconds*/
  25. #define PTP_TS_INGR_CORR_SNS 0x60 /* Ingress timestamp correction subnanoseconds */
  26. #define PTP_TS_EGR_CORR_SNS 0x64 /* Egress timestamp correction subnanoseconds */
  27. #define PTP_TS_INGR_LAT 0x68 /* MAC internal Ingress Latency */
  28. #define PTP_TS_EGR_LAT 0x6c /* MAC internal Egress Latency */
  29. #define PTP_STNSUR_ADDSUB_SHIFT 31
  30. #define PTP_DIGITAL_ROLLOVER_MODE 0x3B9ACA00 /* 10e9-1 ns */
  31. #define PTP_BINARY_ROLLOVER_MODE 0x80000000 /* ~0.466 ns */
  32. /* PTP Timestamp control register defines */
  33. #define PTP_TCR_TSENA BIT(0) /* Timestamp Enable */
  34. #define PTP_TCR_TSCFUPDT BIT(1) /* Timestamp Fine/Coarse Update */
  35. #define PTP_TCR_TSINIT BIT(2) /* Timestamp Initialize */
  36. #define PTP_TCR_TSUPDT BIT(3) /* Timestamp Update */
  37. #define PTP_TCR_TSTRIG BIT(4) /* Timestamp Interrupt Trigger Enable */
  38. #define PTP_TCR_TSADDREG BIT(5) /* Addend Reg Update */
  39. #define PTP_TCR_TSENALL BIT(8) /* Enable Timestamp for All Frames */
  40. #define PTP_TCR_TSCTRLSSR BIT(9) /* Digital or Binary Rollover Control */
  41. /* Enable PTP packet Processing for Version 2 Format */
  42. #define PTP_TCR_TSVER2ENA BIT(10)
  43. /* Enable Processing of PTP over Ethernet Frames */
  44. #define PTP_TCR_TSIPENA BIT(11)
  45. /* Enable Processing of PTP Frames Sent over IPv6-UDP */
  46. #define PTP_TCR_TSIPV6ENA BIT(12)
  47. /* Enable Processing of PTP Frames Sent over IPv4-UDP */
  48. #define PTP_TCR_TSIPV4ENA BIT(13)
  49. /* Enable Timestamp Snapshot for Event Messages */
  50. #define PTP_TCR_TSEVNTENA BIT(14)
  51. /* Enable Snapshot for Messages Relevant to Master */
  52. #define PTP_TCR_TSMSTRENA BIT(15)
  53. /* Select PTP packets for Taking Snapshots
  54. * On gmac4 specifically:
  55. * Enable SYNC, Pdelay_Req, Pdelay_Resp when TSEVNTENA is enabled.
  56. * or
  57. * Enable SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp,
  58. * Pdelay_Resp_Follow_Up if TSEVNTENA is disabled
  59. */
  60. #define PTP_TCR_SNAPTYPSEL_1 BIT(16)
  61. /* Enable MAC address for PTP Frame Filtering */
  62. #define PTP_TCR_TSENMACADDR BIT(18)
  63. /* SSIR defines */
  64. #define PTP_SSIR_SSINC_MAX 0xff
  65. #define GMAC4_PTP_SSIR_SSINC_SHIFT 16
  66. /* Auxiliary Control defines */
  67. #define PTP_ACR_ATSFC BIT(0) /* Auxiliary Snapshot FIFO Clear */
  68. #define PTP_ACR_ATSEN0 BIT(4) /* Auxiliary Snapshot 0 Enable */
  69. #define PTP_ACR_ATSEN1 BIT(5) /* Auxiliary Snapshot 1 Enable */
  70. #define PTP_ACR_ATSEN2 BIT(6) /* Auxiliary Snapshot 2 Enable */
  71. #define PTP_ACR_ATSEN3 BIT(7) /* Auxiliary Snapshot 3 Enable */
  72. #define PTP_ACR_ATSEN(index) (PTP_ACR_ATSEN0 << (index))
  73. #define PTP_ACR_MASK GENMASK(7, 4) /* Aux Snapshot Mask */
  74. #define PMC_ART_VALUE0 0x01 /* PMC_ART[15:0] timer value */
  75. #define PMC_ART_VALUE1 0x02 /* PMC_ART[31:16] timer value */
  76. #define PMC_ART_VALUE2 0x03 /* PMC_ART[47:32] timer value */
  77. #define PMC_ART_VALUE3 0x04 /* PMC_ART[63:48] timer value */
  78. #define GMAC4_ART_TIME_SHIFT 16 /* ART TIME 16-bits shift */
  79. enum aux_snapshot {
  80. AUX_SNAPSHOT0 = 0x10,
  81. AUX_SNAPSHOT1 = 0x20,
  82. AUX_SNAPSHOT2 = 0x40,
  83. AUX_SNAPSHOT3 = 0x80,
  84. };
  85. #endif /* __STMMAC_PTP_H__ */