dp83td510.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Driver for the Texas Instruments DP83TD510 PHY
  3. * Copyright (c) 2022 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
  4. */
  5. #include <linux/bitfield.h>
  6. #include <linux/ethtool_netlink.h>
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/phy.h>
  10. #define DP83TD510E_PHY_ID 0x20000181
  11. /* MDIO_MMD_VEND2 registers */
  12. #define DP83TD510E_PHY_STS 0x10
  13. /* Bit 7 - mii_interrupt, active high. Clears on read.
  14. * Note: Clearing does not necessarily deactivate IRQ pin if interrupts pending.
  15. * This differs from the DP83TD510E datasheet (2020) which states this bit
  16. * clears on write 0.
  17. */
  18. #define DP83TD510E_STS_MII_INT BIT(7)
  19. #define DP83TD510E_LINK_STATUS BIT(0)
  20. #define DP83TD510E_GEN_CFG 0x11
  21. #define DP83TD510E_GENCFG_INT_POLARITY BIT(3)
  22. #define DP83TD510E_GENCFG_INT_EN BIT(1)
  23. #define DP83TD510E_GENCFG_INT_OE BIT(0)
  24. #define DP83TD510E_INTERRUPT_REG_1 0x12
  25. #define DP83TD510E_INT1_LINK BIT(13)
  26. #define DP83TD510E_INT1_LINK_EN BIT(5)
  27. #define DP83TD510E_CTRL 0x1f
  28. #define DP83TD510E_CTRL_HW_RESET BIT(15)
  29. #define DP83TD510E_CTRL_SW_RESET BIT(14)
  30. #define DP83TD510E_AN_STAT_1 0x60c
  31. #define DP83TD510E_MASTER_SLAVE_RESOL_FAIL BIT(15)
  32. #define DP83TD510E_MSE_DETECT 0xa85
  33. #define DP83TD510_SQI_MAX 7
  34. /* Register values are converted to SNR(dB) as suggested by
  35. * "Application Report - DP83TD510E Cable Diagnostics Toolkit":
  36. * SNR(dB) = -10 * log10 (VAL/2^17) - 1.76 dB.
  37. * SQI ranges are implemented according to "OPEN ALLIANCE - Advanced diagnostic
  38. * features for 100BASE-T1 automotive Ethernet PHYs"
  39. */
  40. static const u16 dp83td510_mse_sqi_map[] = {
  41. 0x0569, /* < 18dB */
  42. 0x044c, /* 18dB =< SNR < 19dB */
  43. 0x0369, /* 19dB =< SNR < 20dB */
  44. 0x02b6, /* 20dB =< SNR < 21dB */
  45. 0x0227, /* 21dB =< SNR < 22dB */
  46. 0x01b6, /* 22dB =< SNR < 23dB */
  47. 0x015b, /* 23dB =< SNR < 24dB */
  48. 0x0000 /* 24dB =< SNR */
  49. };
  50. struct dp83td510_priv {
  51. bool alcd_test_active;
  52. };
  53. /* Time Domain Reflectometry (TDR) Functionality of DP83TD510 PHY
  54. *
  55. * I assume that this PHY is using a variation of Spread Spectrum Time Domain
  56. * Reflectometry (SSTDR) rather than the commonly used TDR found in many PHYs.
  57. * Here are the following observations which likely confirm this:
  58. * - The DP83TD510 PHY transmits a modulated signal of configurable length
  59. * (default 16000 µs) instead of a single pulse pattern, which is typical
  60. * for traditional TDR.
  61. * - The pulse observed on the wire, triggered by the HW RESET register, is not
  62. * part of the cable testing process.
  63. *
  64. * I assume that SSTDR seems to be a logical choice for the 10BaseT1L
  65. * environment due to improved noise resistance, making it suitable for
  66. * environments with significant electrical noise, such as long 10BaseT1L cable
  67. * runs.
  68. *
  69. * Configuration Variables:
  70. * The SSTDR variation used in this PHY involves more configuration variables
  71. * that can dramatically affect the functionality and precision of cable
  72. * testing. Since most of these configuration options are either not well
  73. * documented or documented with minimal details, the following sections
  74. * describe my understanding and observations of these variables and their
  75. * impact on TDR functionality.
  76. *
  77. * Timeline:
  78. * ,<--cfg_pre_silence_time
  79. * | ,<-SSTDR Modulated Transmission
  80. * | | ,<--cfg_post_silence_time
  81. * | | | ,<--Force Link Mode
  82. * |<--'-->|<-------'------->|<--'-->|<--------'------->|
  83. *
  84. * - cfg_pre_silence_time: Optional silence time before TDR transmission starts.
  85. * - SSTDR Modulated Transmission: Transmission duration configured by
  86. * cfg_tdr_tx_duration and amplitude configured by cfg_tdr_tx_type.
  87. * - cfg_post_silence_time: Silence time after TDR transmission.
  88. * - Force Link Mode: If nothing is configured after cfg_post_silence_time,
  89. * the PHY continues in force link mode without autonegotiation.
  90. */
  91. #define DP83TD510E_TDR_CFG 0x1e
  92. #define DP83TD510E_TDR_START BIT(15)
  93. #define DP83TD510E_TDR_DONE BIT(1)
  94. #define DP83TD510E_TDR_FAIL BIT(0)
  95. #define DP83TD510E_TDR_CFG1 0x300
  96. /* cfg_tdr_tx_type: Transmit voltage level for TDR.
  97. * 0 = 1V, 1 = 2.4V
  98. * Note: Using different voltage levels may not work
  99. * in all configuration variations. For example, setting
  100. * 2.4V may give different cable length measurements.
  101. * Other settings may be needed to make it work properly.
  102. */
  103. #define DP83TD510E_TDR_TX_TYPE BIT(12)
  104. #define DP83TD510E_TDR_TX_TYPE_1V 0
  105. #define DP83TD510E_TDR_TX_TYPE_2_4V 1
  106. /* cfg_post_silence_time: Time after the TDR sequence. Since we force master mode
  107. * for the TDR will proceed with forced link state after this time. For Linux
  108. * it is better to set max value to avoid false link state detection.
  109. */
  110. #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME GENMASK(3, 2)
  111. #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_0MS 0
  112. #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_10MS 1
  113. #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_100MS 2
  114. #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_1000MS 3
  115. /* cfg_pre_silence_time: Time before the TDR sequence. It should be enough to
  116. * settle down all pulses and reflections. Since for 10BASE-T1L we have
  117. * maximum 2000m cable length, we can set it to 1ms.
  118. */
  119. #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME GENMASK(1, 0)
  120. #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_0MS 0
  121. #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_10MS 1
  122. #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_100MS 2
  123. #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_1000MS 3
  124. #define DP83TD510E_TDR_CFG2 0x301
  125. #define DP83TD510E_TDR_END_TAP_INDEX_1 GENMASK(14, 8)
  126. #define DP83TD510E_TDR_END_TAP_INDEX_1_DEF 36
  127. #define DP83TD510E_TDR_START_TAP_INDEX_1 GENMASK(6, 0)
  128. #define DP83TD510E_TDR_START_TAP_INDEX_1_DEF 4
  129. #define DP83TD510E_TDR_CFG3 0x302
  130. /* cfg_tdr_tx_duration: Duration of the TDR transmission in microseconds.
  131. * This value sets the duration of the modulated signal used for TDR
  132. * measurements.
  133. * - Default: 16000 µs
  134. * - Observation: A minimum duration of 6000 µs is recommended to ensure
  135. * accurate detection of cable faults. Durations shorter than 6000 µs may
  136. * result in incomplete data, especially for shorter cables (e.g., 20 meters),
  137. * leading to false "OK" results. Longer durations (e.g., 6000 µs or more)
  138. * provide better accuracy, particularly for detecting open circuits.
  139. */
  140. #define DP83TD510E_TDR_TX_DURATION_US GENMASK(15, 0)
  141. #define DP83TD510E_TDR_TX_DURATION_US_DEF 16000
  142. #define DP83TD510E_TDR_FAULT_CFG1 0x303
  143. #define DP83TD510E_TDR_FLT_LOC_OFFSET_1 GENMASK(14, 8)
  144. #define DP83TD510E_TDR_FLT_LOC_OFFSET_1_DEF 4
  145. #define DP83TD510E_TDR_FLT_INIT_1 GENMASK(7, 0)
  146. #define DP83TD510E_TDR_FLT_INIT_1_DEF 62
  147. #define DP83TD510E_TDR_FAULT_STAT 0x30c
  148. #define DP83TD510E_TDR_PEAK_DETECT BIT(11)
  149. #define DP83TD510E_TDR_PEAK_SIGN BIT(10)
  150. #define DP83TD510E_TDR_PEAK_LOCATION GENMASK(9, 0)
  151. /* Not documented registers and values but recommended according to
  152. * "DP83TD510E Cable Diagnostics Toolkit revC"
  153. */
  154. #define DP83TD510E_UNKN_030E 0x30e
  155. #define DP83TD510E_030E_VAL 0x2520
  156. #define DP83TD510E_ALCD_STAT 0xa9f
  157. #define DP83TD510E_ALCD_COMPLETE BIT(15)
  158. #define DP83TD510E_ALCD_CABLE_LENGTH GENMASK(10, 0)
  159. static int dp83td510_config_intr(struct phy_device *phydev)
  160. {
  161. int ret;
  162. if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  163. ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
  164. DP83TD510E_INTERRUPT_REG_1,
  165. DP83TD510E_INT1_LINK_EN);
  166. if (ret)
  167. return ret;
  168. ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
  169. DP83TD510E_GEN_CFG,
  170. DP83TD510E_GENCFG_INT_POLARITY |
  171. DP83TD510E_GENCFG_INT_EN |
  172. DP83TD510E_GENCFG_INT_OE);
  173. } else {
  174. ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
  175. DP83TD510E_INTERRUPT_REG_1, 0x0);
  176. if (ret)
  177. return ret;
  178. ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
  179. DP83TD510E_GEN_CFG,
  180. DP83TD510E_GENCFG_INT_EN);
  181. if (ret)
  182. return ret;
  183. }
  184. return ret;
  185. }
  186. static irqreturn_t dp83td510_handle_interrupt(struct phy_device *phydev)
  187. {
  188. int ret;
  189. /* Read the current enabled interrupts */
  190. ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_INTERRUPT_REG_1);
  191. if (ret < 0) {
  192. phy_error(phydev);
  193. return IRQ_NONE;
  194. } else if (!(ret & DP83TD510E_INT1_LINK_EN) ||
  195. !(ret & DP83TD510E_INT1_LINK)) {
  196. return IRQ_NONE;
  197. }
  198. phy_trigger_machine(phydev);
  199. return IRQ_HANDLED;
  200. }
  201. static int dp83td510_read_status(struct phy_device *phydev)
  202. {
  203. u16 phy_sts;
  204. int ret;
  205. phydev->speed = SPEED_UNKNOWN;
  206. phydev->duplex = DUPLEX_UNKNOWN;
  207. phydev->pause = 0;
  208. phydev->asym_pause = 0;
  209. linkmode_zero(phydev->lp_advertising);
  210. phy_sts = phy_read(phydev, DP83TD510E_PHY_STS);
  211. phydev->link = !!(phy_sts & DP83TD510E_LINK_STATUS);
  212. if (phydev->link) {
  213. /* This PHY supports only one link mode: 10BaseT1L_Full */
  214. phydev->duplex = DUPLEX_FULL;
  215. phydev->speed = SPEED_10;
  216. if (phydev->autoneg == AUTONEG_ENABLE) {
  217. ret = genphy_c45_read_lpa(phydev);
  218. if (ret)
  219. return ret;
  220. phy_resolve_aneg_linkmode(phydev);
  221. }
  222. }
  223. if (phydev->autoneg == AUTONEG_ENABLE) {
  224. ret = genphy_c45_baset1_read_status(phydev);
  225. if (ret < 0)
  226. return ret;
  227. ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
  228. DP83TD510E_AN_STAT_1);
  229. if (ret < 0)
  230. return ret;
  231. if (ret & DP83TD510E_MASTER_SLAVE_RESOL_FAIL)
  232. phydev->master_slave_state = MASTER_SLAVE_STATE_ERR;
  233. } else {
  234. return genphy_c45_pma_baset1_read_master_slave(phydev);
  235. }
  236. return 0;
  237. }
  238. static int dp83td510_config_aneg(struct phy_device *phydev)
  239. {
  240. bool changed = false;
  241. int ret;
  242. ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
  243. if (ret < 0)
  244. return ret;
  245. if (phydev->autoneg == AUTONEG_DISABLE)
  246. return genphy_c45_an_disable_aneg(phydev);
  247. ret = genphy_c45_an_config_aneg(phydev);
  248. if (ret < 0)
  249. return ret;
  250. if (ret > 0)
  251. changed = true;
  252. return genphy_c45_check_and_restart_aneg(phydev, changed);
  253. }
  254. static int dp83td510_get_sqi(struct phy_device *phydev)
  255. {
  256. int sqi, ret;
  257. u16 mse_val;
  258. if (!phydev->link)
  259. return 0;
  260. ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT);
  261. if (ret < 0)
  262. return ret;
  263. mse_val = 0xFFFF & ret;
  264. for (sqi = 0; sqi < ARRAY_SIZE(dp83td510_mse_sqi_map); sqi++) {
  265. if (mse_val >= dp83td510_mse_sqi_map[sqi])
  266. return sqi;
  267. }
  268. return -EINVAL;
  269. }
  270. static int dp83td510_get_sqi_max(struct phy_device *phydev)
  271. {
  272. return DP83TD510_SQI_MAX;
  273. }
  274. /**
  275. * dp83td510_cable_test_start - Start the cable test for the DP83TD510 PHY.
  276. * @phydev: Pointer to the phy_device structure.
  277. *
  278. * This sequence is implemented according to the "Application Note DP83TD510E
  279. * Cable Diagnostics Toolkit revC".
  280. *
  281. * Returns: 0 on success, a negative error code on failure.
  282. */
  283. static int dp83td510_cable_test_start(struct phy_device *phydev)
  284. {
  285. struct dp83td510_priv *priv = phydev->priv;
  286. int ret;
  287. /* If link partner is active, we won't be able to use TDR, since
  288. * we can't force link partner to be silent. The autonegotiation
  289. * pulses will be too frequent and the TDR sequence will be
  290. * too long. So, TDR will always fail. Since the link is established
  291. * we already know that the cable is working, so we can get some
  292. * extra information line the cable length using ALCD.
  293. */
  294. if (phydev->link) {
  295. priv->alcd_test_active = true;
  296. return 0;
  297. }
  298. priv->alcd_test_active = false;
  299. ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL,
  300. DP83TD510E_CTRL_HW_RESET);
  301. if (ret)
  302. return ret;
  303. ret = genphy_c45_an_disable_aneg(phydev);
  304. if (ret)
  305. return ret;
  306. /* Force master mode */
  307. ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
  308. MDIO_PMA_PMD_BT1_CTRL_CFG_MST);
  309. if (ret)
  310. return ret;
  311. /* There is no official recommendation for this register, but it is
  312. * better to use 1V for TDR since other values seems to be optimized
  313. * for this amplitude. Except of amplitude, it is better to configure
  314. * pre TDR silence time to 10ms to avoid false reflections (value 0
  315. * seems to be too short, otherwise we need to implement own silence
  316. * time). Also, post TDR silence time should be set to 1000ms to avoid
  317. * false link state detection, it fits to the polling time of the
  318. * PHY framework. The idea is to wait until
  319. * dp83td510_cable_test_get_status() will be called and reconfigure
  320. * the PHY to the default state within the post silence time window.
  321. */
  322. ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG1,
  323. DP83TD510E_TDR_TX_TYPE |
  324. DP83TD510E_TDR_CFG1_POST_SILENCE_TIME |
  325. DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME,
  326. DP83TD510E_TDR_TX_TYPE_1V |
  327. DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_10MS |
  328. DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_1000MS);
  329. if (ret)
  330. return ret;
  331. ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG2,
  332. FIELD_PREP(DP83TD510E_TDR_END_TAP_INDEX_1,
  333. DP83TD510E_TDR_END_TAP_INDEX_1_DEF) |
  334. FIELD_PREP(DP83TD510E_TDR_START_TAP_INDEX_1,
  335. DP83TD510E_TDR_START_TAP_INDEX_1_DEF));
  336. if (ret)
  337. return ret;
  338. ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_FAULT_CFG1,
  339. FIELD_PREP(DP83TD510E_TDR_FLT_LOC_OFFSET_1,
  340. DP83TD510E_TDR_FLT_LOC_OFFSET_1_DEF) |
  341. FIELD_PREP(DP83TD510E_TDR_FLT_INIT_1,
  342. DP83TD510E_TDR_FLT_INIT_1_DEF));
  343. if (ret)
  344. return ret;
  345. /* Undocumented register, from the "Application Note DP83TD510E Cable
  346. * Diagnostics Toolkit revC".
  347. */
  348. ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_UNKN_030E,
  349. DP83TD510E_030E_VAL);
  350. if (ret)
  351. return ret;
  352. ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG3,
  353. DP83TD510E_TDR_TX_DURATION_US_DEF);
  354. if (ret)
  355. return ret;
  356. ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL,
  357. DP83TD510E_CTRL_SW_RESET);
  358. if (ret)
  359. return ret;
  360. return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG,
  361. DP83TD510E_TDR_START);
  362. }
  363. /**
  364. * dp83td510_cable_test_get_tdr_status - Get the status of the TDR test for the
  365. * DP83TD510 PHY.
  366. * @phydev: Pointer to the phy_device structure.
  367. * @finished: Pointer to a boolean that indicates whether the test is finished.
  368. *
  369. * The function sets the @finished flag to true if the test is complete.
  370. *
  371. * Returns: 0 on success or a negative error code on failure.
  372. */
  373. static int dp83td510_cable_test_get_tdr_status(struct phy_device *phydev,
  374. bool *finished)
  375. {
  376. int ret, stat;
  377. ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG);
  378. if (ret < 0)
  379. return ret;
  380. if (!(ret & DP83TD510E_TDR_DONE))
  381. return 0;
  382. if (!(ret & DP83TD510E_TDR_FAIL)) {
  383. int location;
  384. ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
  385. DP83TD510E_TDR_FAULT_STAT);
  386. if (ret < 0)
  387. return ret;
  388. if (ret & DP83TD510E_TDR_PEAK_DETECT) {
  389. if (ret & DP83TD510E_TDR_PEAK_SIGN)
  390. stat = ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
  391. else
  392. stat = ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
  393. location = FIELD_GET(DP83TD510E_TDR_PEAK_LOCATION,
  394. ret) * 100;
  395. ethnl_cable_test_fault_length(phydev,
  396. ETHTOOL_A_CABLE_PAIR_A,
  397. location);
  398. } else {
  399. stat = ETHTOOL_A_CABLE_RESULT_CODE_OK;
  400. }
  401. } else {
  402. /* Most probably we have active link partner */
  403. stat = ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
  404. }
  405. *finished = true;
  406. ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, stat);
  407. return phy_init_hw(phydev);
  408. }
  409. /**
  410. * dp83td510_cable_test_get_alcd_status - Get the status of the ALCD test for the
  411. * DP83TD510 PHY.
  412. * @phydev: Pointer to the phy_device structure.
  413. * @finished: Pointer to a boolean that indicates whether the test is finished.
  414. *
  415. * The function sets the @finished flag to true if the test is complete.
  416. * The function reads the cable length and reports it to the user.
  417. *
  418. * Returns: 0 on success or a negative error code on failure.
  419. */
  420. static int dp83td510_cable_test_get_alcd_status(struct phy_device *phydev,
  421. bool *finished)
  422. {
  423. unsigned int location;
  424. int ret, phy_sts;
  425. phy_sts = phy_read(phydev, DP83TD510E_PHY_STS);
  426. if (!(phy_sts & DP83TD510E_LINK_STATUS)) {
  427. /* If the link is down, we can't do any thing usable now */
  428. ethnl_cable_test_result_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A,
  429. ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC,
  430. ETHTOOL_A_CABLE_INF_SRC_ALCD);
  431. *finished = true;
  432. return 0;
  433. }
  434. ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_ALCD_STAT);
  435. if (ret < 0)
  436. return ret;
  437. if (!(ret & DP83TD510E_ALCD_COMPLETE))
  438. return 0;
  439. location = FIELD_GET(DP83TD510E_ALCD_CABLE_LENGTH, ret) * 100;
  440. ethnl_cable_test_fault_length_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A,
  441. location,
  442. ETHTOOL_A_CABLE_INF_SRC_ALCD);
  443. ethnl_cable_test_result_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A,
  444. ETHTOOL_A_CABLE_RESULT_CODE_OK,
  445. ETHTOOL_A_CABLE_INF_SRC_ALCD);
  446. *finished = true;
  447. return 0;
  448. }
  449. /**
  450. * dp83td510_cable_test_get_status - Get the status of the cable test for the
  451. * DP83TD510 PHY.
  452. * @phydev: Pointer to the phy_device structure.
  453. * @finished: Pointer to a boolean that indicates whether the test is finished.
  454. *
  455. * The function sets the @finished flag to true if the test is complete.
  456. *
  457. * Returns: 0 on success or a negative error code on failure.
  458. */
  459. static int dp83td510_cable_test_get_status(struct phy_device *phydev,
  460. bool *finished)
  461. {
  462. struct dp83td510_priv *priv = phydev->priv;
  463. *finished = false;
  464. if (priv->alcd_test_active)
  465. return dp83td510_cable_test_get_alcd_status(phydev, finished);
  466. return dp83td510_cable_test_get_tdr_status(phydev, finished);
  467. }
  468. static int dp83td510_get_features(struct phy_device *phydev)
  469. {
  470. /* This PHY can't respond on MDIO bus if no RMII clock is enabled.
  471. * In case RMII mode is used (most meaningful mode for this PHY) and
  472. * the PHY do not have own XTAL, and CLK providing MAC is not probed,
  473. * we won't be able to read all needed ability registers.
  474. * So provide it manually.
  475. */
  476. linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
  477. linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
  478. linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
  479. linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
  480. phydev->supported);
  481. return 0;
  482. }
  483. static int dp83td510_probe(struct phy_device *phydev)
  484. {
  485. struct device *dev = &phydev->mdio.dev;
  486. struct dp83td510_priv *priv;
  487. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  488. if (!priv)
  489. return -ENOMEM;
  490. phydev->priv = priv;
  491. return 0;
  492. }
  493. static struct phy_driver dp83td510_driver[] = {
  494. {
  495. PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID),
  496. .name = "TI DP83TD510E",
  497. .flags = PHY_POLL_CABLE_TEST,
  498. .probe = dp83td510_probe,
  499. .config_aneg = dp83td510_config_aneg,
  500. .read_status = dp83td510_read_status,
  501. .get_features = dp83td510_get_features,
  502. .config_intr = dp83td510_config_intr,
  503. .handle_interrupt = dp83td510_handle_interrupt,
  504. .get_sqi = dp83td510_get_sqi,
  505. .get_sqi_max = dp83td510_get_sqi_max,
  506. .cable_test_start = dp83td510_cable_test_start,
  507. .cable_test_get_status = dp83td510_cable_test_get_status,
  508. .suspend = genphy_suspend,
  509. .resume = genphy_resume,
  510. } };
  511. module_phy_driver(dp83td510_driver);
  512. static struct mdio_device_id __maybe_unused dp83td510_tbl[] = {
  513. { PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID) },
  514. { }
  515. };
  516. MODULE_DEVICE_TABLE(mdio, dp83td510_tbl);
  517. MODULE_DESCRIPTION("Texas Instruments DP83TD510E PHY driver");
  518. MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
  519. MODULE_LICENSE("GPL v2");