dp_rx.c 157 KB

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  1. // SPDX-License-Identifier: BSD-3-Clause-Clear
  2. /*
  3. * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/ieee80211.h>
  7. #include <linux/kernel.h>
  8. #include <linux/skbuff.h>
  9. #include <crypto/hash.h>
  10. #include "core.h"
  11. #include "debug.h"
  12. #include "debugfs_htt_stats.h"
  13. #include "debugfs_sta.h"
  14. #include "hal_desc.h"
  15. #include "hw.h"
  16. #include "dp_rx.h"
  17. #include "hal_rx.h"
  18. #include "dp_tx.h"
  19. #include "peer.h"
  20. #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
  21. static inline
  22. u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
  23. {
  24. return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
  25. }
  26. static inline
  27. enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
  28. struct hal_rx_desc *desc)
  29. {
  30. if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
  31. return HAL_ENCRYPT_TYPE_OPEN;
  32. return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
  33. }
  34. static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
  35. struct hal_rx_desc *desc)
  36. {
  37. return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
  38. }
  39. static inline
  40. bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab,
  41. struct hal_rx_desc *desc)
  42. {
  43. return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc);
  44. }
  45. static inline
  46. u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
  47. struct hal_rx_desc *desc)
  48. {
  49. return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
  50. }
  51. static inline
  52. bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
  53. struct hal_rx_desc *desc)
  54. {
  55. return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
  56. }
  57. static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
  58. struct hal_rx_desc *desc)
  59. {
  60. return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
  61. }
  62. static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
  63. struct sk_buff *skb)
  64. {
  65. struct ieee80211_hdr *hdr;
  66. hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
  67. return ieee80211_has_morefrags(hdr->frame_control);
  68. }
  69. static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
  70. struct sk_buff *skb)
  71. {
  72. struct ieee80211_hdr *hdr;
  73. hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
  74. return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
  75. }
  76. static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
  77. struct hal_rx_desc *desc)
  78. {
  79. return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
  80. }
  81. static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
  82. struct hal_rx_desc *desc)
  83. {
  84. return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
  85. }
  86. static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
  87. {
  88. return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
  89. __le32_to_cpu(attn->info2));
  90. }
  91. static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
  92. {
  93. return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
  94. __le32_to_cpu(attn->info1));
  95. }
  96. static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
  97. {
  98. return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
  99. __le32_to_cpu(attn->info1));
  100. }
  101. static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
  102. {
  103. return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
  104. __le32_to_cpu(attn->info2)) ==
  105. RX_DESC_DECRYPT_STATUS_CODE_OK);
  106. }
  107. static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
  108. {
  109. u32 info = __le32_to_cpu(attn->info1);
  110. u32 errmap = 0;
  111. if (info & RX_ATTENTION_INFO1_FCS_ERR)
  112. errmap |= DP_RX_MPDU_ERR_FCS;
  113. if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
  114. errmap |= DP_RX_MPDU_ERR_DECRYPT;
  115. if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
  116. errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
  117. if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
  118. errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
  119. if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
  120. errmap |= DP_RX_MPDU_ERR_OVERFLOW;
  121. if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
  122. errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
  123. if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
  124. errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
  125. return errmap;
  126. }
  127. static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
  128. struct hal_rx_desc *desc)
  129. {
  130. struct rx_attention *rx_attention;
  131. u32 errmap;
  132. rx_attention = ath11k_dp_rx_get_attention(ab, desc);
  133. errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
  134. return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
  135. }
  136. static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
  137. struct hal_rx_desc *desc)
  138. {
  139. return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
  140. }
  141. static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
  142. struct hal_rx_desc *desc)
  143. {
  144. return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
  145. }
  146. static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
  147. struct hal_rx_desc *desc)
  148. {
  149. return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
  150. }
  151. static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
  152. struct hal_rx_desc *desc)
  153. {
  154. return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
  155. }
  156. static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
  157. struct hal_rx_desc *desc)
  158. {
  159. return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
  160. }
  161. static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
  162. struct hal_rx_desc *desc)
  163. {
  164. return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
  165. }
  166. static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
  167. struct hal_rx_desc *desc)
  168. {
  169. return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
  170. }
  171. static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
  172. struct hal_rx_desc *desc)
  173. {
  174. return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
  175. }
  176. static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
  177. struct hal_rx_desc *desc)
  178. {
  179. return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
  180. }
  181. static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
  182. struct hal_rx_desc *desc)
  183. {
  184. return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
  185. }
  186. static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
  187. struct hal_rx_desc *desc)
  188. {
  189. return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
  190. }
  191. static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
  192. struct hal_rx_desc *desc)
  193. {
  194. return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
  195. }
  196. static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
  197. struct hal_rx_desc *fdesc,
  198. struct hal_rx_desc *ldesc)
  199. {
  200. ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
  201. }
  202. static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
  203. {
  204. return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
  205. __le32_to_cpu(attn->info1));
  206. }
  207. static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
  208. struct hal_rx_desc *rx_desc)
  209. {
  210. u8 *rx_pkt_hdr;
  211. rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
  212. return rx_pkt_hdr;
  213. }
  214. static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
  215. struct hal_rx_desc *rx_desc)
  216. {
  217. u32 tlv_tag;
  218. tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
  219. return tlv_tag == HAL_RX_MPDU_START;
  220. }
  221. static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
  222. struct hal_rx_desc *rx_desc)
  223. {
  224. return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
  225. }
  226. static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
  227. struct hal_rx_desc *desc,
  228. u16 len)
  229. {
  230. ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
  231. }
  232. static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
  233. struct hal_rx_desc *desc)
  234. {
  235. struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
  236. return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
  237. (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
  238. __le32_to_cpu(attn->info1)));
  239. }
  240. static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
  241. struct hal_rx_desc *desc)
  242. {
  243. return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
  244. }
  245. static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
  246. struct hal_rx_desc *desc)
  247. {
  248. return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
  249. }
  250. static void ath11k_dp_service_mon_ring(struct timer_list *t)
  251. {
  252. struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer);
  253. int i;
  254. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
  255. ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
  256. mod_timer(&ab->mon_reap_timer, jiffies +
  257. msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
  258. }
  259. static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
  260. {
  261. int i, reaped = 0;
  262. unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
  263. do {
  264. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++)
  265. reaped += ath11k_dp_rx_process_mon_rings(ab, i,
  266. NULL,
  267. DP_MON_SERVICE_BUDGET);
  268. /* nothing more to reap */
  269. if (reaped < DP_MON_SERVICE_BUDGET)
  270. return 0;
  271. } while (time_before(jiffies, timeout));
  272. ath11k_warn(ab, "dp mon ring purge timeout");
  273. return -ETIMEDOUT;
  274. }
  275. /* Returns number of Rx buffers replenished */
  276. int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
  277. struct dp_rxdma_ring *rx_ring,
  278. int req_entries,
  279. enum hal_rx_buf_return_buf_manager mgr)
  280. {
  281. struct hal_srng *srng;
  282. u32 *desc;
  283. struct sk_buff *skb;
  284. int num_free;
  285. int num_remain;
  286. int buf_id;
  287. u32 cookie;
  288. dma_addr_t paddr;
  289. req_entries = min(req_entries, rx_ring->bufs_max);
  290. srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
  291. spin_lock_bh(&srng->lock);
  292. ath11k_hal_srng_access_begin(ab, srng);
  293. num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
  294. if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
  295. req_entries = num_free;
  296. req_entries = min(num_free, req_entries);
  297. num_remain = req_entries;
  298. while (num_remain > 0) {
  299. skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
  300. DP_RX_BUFFER_ALIGN_SIZE);
  301. if (!skb)
  302. break;
  303. if (!IS_ALIGNED((unsigned long)skb->data,
  304. DP_RX_BUFFER_ALIGN_SIZE)) {
  305. skb_pull(skb,
  306. PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
  307. skb->data);
  308. }
  309. paddr = dma_map_single(ab->dev, skb->data,
  310. skb->len + skb_tailroom(skb),
  311. DMA_FROM_DEVICE);
  312. if (dma_mapping_error(ab->dev, paddr))
  313. goto fail_free_skb;
  314. spin_lock_bh(&rx_ring->idr_lock);
  315. buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 1,
  316. (rx_ring->bufs_max * 3) + 1, GFP_ATOMIC);
  317. spin_unlock_bh(&rx_ring->idr_lock);
  318. if (buf_id <= 0)
  319. goto fail_dma_unmap;
  320. desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
  321. if (!desc)
  322. goto fail_idr_remove;
  323. ATH11K_SKB_RXCB(skb)->paddr = paddr;
  324. cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
  325. FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
  326. num_remain--;
  327. ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
  328. }
  329. ath11k_hal_srng_access_end(ab, srng);
  330. spin_unlock_bh(&srng->lock);
  331. return req_entries - num_remain;
  332. fail_idr_remove:
  333. spin_lock_bh(&rx_ring->idr_lock);
  334. idr_remove(&rx_ring->bufs_idr, buf_id);
  335. spin_unlock_bh(&rx_ring->idr_lock);
  336. fail_dma_unmap:
  337. dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
  338. DMA_FROM_DEVICE);
  339. fail_free_skb:
  340. dev_kfree_skb_any(skb);
  341. ath11k_hal_srng_access_end(ab, srng);
  342. spin_unlock_bh(&srng->lock);
  343. return req_entries - num_remain;
  344. }
  345. static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
  346. struct dp_rxdma_ring *rx_ring)
  347. {
  348. struct sk_buff *skb;
  349. int buf_id;
  350. spin_lock_bh(&rx_ring->idr_lock);
  351. idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
  352. idr_remove(&rx_ring->bufs_idr, buf_id);
  353. /* TODO: Understand where internal driver does this dma_unmap
  354. * of rxdma_buffer.
  355. */
  356. dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
  357. skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
  358. dev_kfree_skb_any(skb);
  359. }
  360. idr_destroy(&rx_ring->bufs_idr);
  361. spin_unlock_bh(&rx_ring->idr_lock);
  362. return 0;
  363. }
  364. static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
  365. {
  366. struct ath11k_pdev_dp *dp = &ar->dp;
  367. struct ath11k_base *ab = ar->ab;
  368. struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
  369. int i;
  370. ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
  371. rx_ring = &dp->rxdma_mon_buf_ring;
  372. ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
  373. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
  374. rx_ring = &dp->rx_mon_status_refill_ring[i];
  375. ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
  376. }
  377. return 0;
  378. }
  379. static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
  380. struct dp_rxdma_ring *rx_ring,
  381. u32 ringtype)
  382. {
  383. struct ath11k_pdev_dp *dp = &ar->dp;
  384. int num_entries;
  385. num_entries = rx_ring->refill_buf_ring.size /
  386. ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
  387. rx_ring->bufs_max = num_entries;
  388. ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
  389. ar->ab->hw_params.hal_params->rx_buf_rbm);
  390. return 0;
  391. }
  392. static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
  393. {
  394. struct ath11k_pdev_dp *dp = &ar->dp;
  395. struct ath11k_base *ab = ar->ab;
  396. struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
  397. int i;
  398. ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
  399. if (ar->ab->hw_params.rxdma1_enable) {
  400. rx_ring = &dp->rxdma_mon_buf_ring;
  401. ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
  402. }
  403. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
  404. rx_ring = &dp->rx_mon_status_refill_ring[i];
  405. ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
  406. }
  407. return 0;
  408. }
  409. static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
  410. {
  411. struct ath11k_pdev_dp *dp = &ar->dp;
  412. struct ath11k_base *ab = ar->ab;
  413. int i;
  414. ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
  415. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
  416. if (ab->hw_params.rx_mac_buf_ring)
  417. ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
  418. ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
  419. ath11k_dp_srng_cleanup(ab,
  420. &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
  421. }
  422. ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
  423. }
  424. void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
  425. {
  426. struct ath11k_dp *dp = &ab->dp;
  427. int i;
  428. for (i = 0; i < DP_REO_DST_RING_MAX; i++)
  429. ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
  430. }
  431. int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
  432. {
  433. struct ath11k_dp *dp = &ab->dp;
  434. int ret;
  435. int i;
  436. for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
  437. ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
  438. HAL_REO_DST, i, 0,
  439. DP_REO_DST_RING_SIZE);
  440. if (ret) {
  441. ath11k_warn(ab, "failed to setup reo_dst_ring\n");
  442. goto err_reo_cleanup;
  443. }
  444. }
  445. return 0;
  446. err_reo_cleanup:
  447. ath11k_dp_pdev_reo_cleanup(ab);
  448. return ret;
  449. }
  450. static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
  451. {
  452. struct ath11k_pdev_dp *dp = &ar->dp;
  453. struct ath11k_base *ab = ar->ab;
  454. struct dp_srng *srng = NULL;
  455. int i;
  456. int ret;
  457. ret = ath11k_dp_srng_setup(ar->ab,
  458. &dp->rx_refill_buf_ring.refill_buf_ring,
  459. HAL_RXDMA_BUF, 0,
  460. dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
  461. if (ret) {
  462. ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
  463. return ret;
  464. }
  465. if (ar->ab->hw_params.rx_mac_buf_ring) {
  466. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
  467. ret = ath11k_dp_srng_setup(ar->ab,
  468. &dp->rx_mac_buf_ring[i],
  469. HAL_RXDMA_BUF, 1,
  470. dp->mac_id + i, 1024);
  471. if (ret) {
  472. ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
  473. i);
  474. return ret;
  475. }
  476. }
  477. }
  478. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
  479. ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
  480. HAL_RXDMA_DST, 0, dp->mac_id + i,
  481. DP_RXDMA_ERR_DST_RING_SIZE);
  482. if (ret) {
  483. ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
  484. return ret;
  485. }
  486. }
  487. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
  488. srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
  489. ret = ath11k_dp_srng_setup(ar->ab,
  490. srng,
  491. HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
  492. DP_RXDMA_MON_STATUS_RING_SIZE);
  493. if (ret) {
  494. ath11k_warn(ar->ab,
  495. "failed to setup rx_mon_status_refill_ring %d\n", i);
  496. return ret;
  497. }
  498. }
  499. /* if rxdma1_enable is false, then it doesn't need
  500. * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
  501. * and rxdma_mon_desc_ring.
  502. * init reap timer for QCA6390.
  503. */
  504. if (!ar->ab->hw_params.rxdma1_enable) {
  505. //init mon status buffer reap timer
  506. timer_setup(&ar->ab->mon_reap_timer,
  507. ath11k_dp_service_mon_ring, 0);
  508. return 0;
  509. }
  510. ret = ath11k_dp_srng_setup(ar->ab,
  511. &dp->rxdma_mon_buf_ring.refill_buf_ring,
  512. HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
  513. DP_RXDMA_MONITOR_BUF_RING_SIZE);
  514. if (ret) {
  515. ath11k_warn(ar->ab,
  516. "failed to setup HAL_RXDMA_MONITOR_BUF\n");
  517. return ret;
  518. }
  519. ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
  520. HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
  521. DP_RXDMA_MONITOR_DST_RING_SIZE);
  522. if (ret) {
  523. ath11k_warn(ar->ab,
  524. "failed to setup HAL_RXDMA_MONITOR_DST\n");
  525. return ret;
  526. }
  527. ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
  528. HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
  529. DP_RXDMA_MONITOR_DESC_RING_SIZE);
  530. if (ret) {
  531. ath11k_warn(ar->ab,
  532. "failed to setup HAL_RXDMA_MONITOR_DESC\n");
  533. return ret;
  534. }
  535. return 0;
  536. }
  537. void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
  538. {
  539. struct ath11k_dp *dp = &ab->dp;
  540. struct dp_reo_cmd *cmd, *tmp;
  541. struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
  542. struct dp_rx_tid *rx_tid;
  543. spin_lock_bh(&dp->reo_cmd_lock);
  544. list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
  545. list_del(&cmd->list);
  546. rx_tid = &cmd->data;
  547. if (rx_tid->vaddr_unaligned) {
  548. dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
  549. rx_tid->vaddr_unaligned,
  550. rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
  551. rx_tid->vaddr_unaligned = NULL;
  552. }
  553. kfree(cmd);
  554. }
  555. list_for_each_entry_safe(cmd_cache, tmp_cache,
  556. &dp->reo_cmd_cache_flush_list, list) {
  557. list_del(&cmd_cache->list);
  558. dp->reo_cmd_cache_flush_count--;
  559. rx_tid = &cmd_cache->data;
  560. if (rx_tid->vaddr_unaligned) {
  561. dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
  562. rx_tid->vaddr_unaligned,
  563. rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
  564. rx_tid->vaddr_unaligned = NULL;
  565. }
  566. kfree(cmd_cache);
  567. }
  568. spin_unlock_bh(&dp->reo_cmd_lock);
  569. }
  570. static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
  571. enum hal_reo_cmd_status status)
  572. {
  573. struct dp_rx_tid *rx_tid = ctx;
  574. if (status != HAL_REO_CMD_SUCCESS)
  575. ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
  576. rx_tid->tid, status);
  577. if (rx_tid->vaddr_unaligned) {
  578. dma_free_noncoherent(dp->ab->dev, rx_tid->unaligned_size,
  579. rx_tid->vaddr_unaligned,
  580. rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
  581. rx_tid->vaddr_unaligned = NULL;
  582. }
  583. }
  584. static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
  585. struct dp_rx_tid *rx_tid)
  586. {
  587. struct ath11k_hal_reo_cmd cmd = {0};
  588. unsigned long tot_desc_sz, desc_sz;
  589. int ret;
  590. tot_desc_sz = rx_tid->size;
  591. desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
  592. while (tot_desc_sz > desc_sz) {
  593. tot_desc_sz -= desc_sz;
  594. cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
  595. cmd.addr_hi = upper_32_bits(rx_tid->paddr);
  596. ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
  597. HAL_REO_CMD_FLUSH_CACHE, &cmd,
  598. NULL);
  599. if (ret)
  600. ath11k_warn(ab,
  601. "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
  602. rx_tid->tid, ret);
  603. }
  604. memset(&cmd, 0, sizeof(cmd));
  605. cmd.addr_lo = lower_32_bits(rx_tid->paddr);
  606. cmd.addr_hi = upper_32_bits(rx_tid->paddr);
  607. cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
  608. ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
  609. HAL_REO_CMD_FLUSH_CACHE,
  610. &cmd, ath11k_dp_reo_cmd_free);
  611. if (ret) {
  612. ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
  613. rx_tid->tid, ret);
  614. dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
  615. rx_tid->vaddr_unaligned,
  616. rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
  617. rx_tid->vaddr_unaligned = NULL;
  618. }
  619. }
  620. static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
  621. enum hal_reo_cmd_status status)
  622. {
  623. struct ath11k_base *ab = dp->ab;
  624. struct dp_rx_tid *rx_tid = ctx;
  625. struct dp_reo_cache_flush_elem *elem, *tmp;
  626. if (status == HAL_REO_CMD_DRAIN) {
  627. goto free_desc;
  628. } else if (status != HAL_REO_CMD_SUCCESS) {
  629. /* Shouldn't happen! Cleanup in case of other failure? */
  630. ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
  631. rx_tid->tid, status);
  632. return;
  633. }
  634. elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
  635. if (!elem)
  636. goto free_desc;
  637. elem->ts = jiffies;
  638. memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
  639. spin_lock_bh(&dp->reo_cmd_lock);
  640. list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
  641. dp->reo_cmd_cache_flush_count++;
  642. /* Flush and invalidate aged REO desc from HW cache */
  643. list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
  644. list) {
  645. if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
  646. time_after(jiffies, elem->ts +
  647. msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
  648. list_del(&elem->list);
  649. dp->reo_cmd_cache_flush_count--;
  650. spin_unlock_bh(&dp->reo_cmd_lock);
  651. ath11k_dp_reo_cache_flush(ab, &elem->data);
  652. kfree(elem);
  653. spin_lock_bh(&dp->reo_cmd_lock);
  654. }
  655. }
  656. spin_unlock_bh(&dp->reo_cmd_lock);
  657. return;
  658. free_desc:
  659. dma_free_noncoherent(ab->dev, rx_tid->unaligned_size,
  660. rx_tid->vaddr_unaligned,
  661. rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
  662. rx_tid->vaddr_unaligned = NULL;
  663. }
  664. void ath11k_peer_rx_tid_delete(struct ath11k *ar,
  665. struct ath11k_peer *peer, u8 tid)
  666. {
  667. struct ath11k_hal_reo_cmd cmd = {0};
  668. struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
  669. int ret;
  670. if (!rx_tid->active)
  671. return;
  672. rx_tid->active = false;
  673. cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
  674. cmd.addr_lo = lower_32_bits(rx_tid->paddr);
  675. cmd.addr_hi = upper_32_bits(rx_tid->paddr);
  676. cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
  677. ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
  678. HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
  679. ath11k_dp_rx_tid_del_func);
  680. if (ret) {
  681. if (ret != -ESHUTDOWN)
  682. ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
  683. tid, ret);
  684. dma_free_noncoherent(ar->ab->dev, rx_tid->unaligned_size,
  685. rx_tid->vaddr_unaligned,
  686. rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
  687. rx_tid->vaddr_unaligned = NULL;
  688. }
  689. rx_tid->paddr = 0;
  690. rx_tid->paddr_unaligned = 0;
  691. rx_tid->size = 0;
  692. rx_tid->unaligned_size = 0;
  693. }
  694. static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
  695. u32 *link_desc,
  696. enum hal_wbm_rel_bm_act action)
  697. {
  698. struct ath11k_dp *dp = &ab->dp;
  699. struct hal_srng *srng;
  700. u32 *desc;
  701. int ret = 0;
  702. srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
  703. spin_lock_bh(&srng->lock);
  704. ath11k_hal_srng_access_begin(ab, srng);
  705. desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
  706. if (!desc) {
  707. ret = -ENOBUFS;
  708. goto exit;
  709. }
  710. ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
  711. action);
  712. exit:
  713. ath11k_hal_srng_access_end(ab, srng);
  714. spin_unlock_bh(&srng->lock);
  715. return ret;
  716. }
  717. static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
  718. {
  719. struct ath11k_base *ab = rx_tid->ab;
  720. lockdep_assert_held(&ab->base_lock);
  721. if (rx_tid->dst_ring_desc) {
  722. if (rel_link_desc)
  723. ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
  724. HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
  725. kfree(rx_tid->dst_ring_desc);
  726. rx_tid->dst_ring_desc = NULL;
  727. }
  728. rx_tid->cur_sn = 0;
  729. rx_tid->last_frag_no = 0;
  730. rx_tid->rx_frag_bitmap = 0;
  731. __skb_queue_purge(&rx_tid->rx_frags);
  732. }
  733. void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
  734. {
  735. struct dp_rx_tid *rx_tid;
  736. int i;
  737. lockdep_assert_held(&ar->ab->base_lock);
  738. for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
  739. rx_tid = &peer->rx_tid[i];
  740. spin_unlock_bh(&ar->ab->base_lock);
  741. del_timer_sync(&rx_tid->frag_timer);
  742. spin_lock_bh(&ar->ab->base_lock);
  743. ath11k_dp_rx_frags_cleanup(rx_tid, true);
  744. }
  745. }
  746. void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
  747. {
  748. struct dp_rx_tid *rx_tid;
  749. int i;
  750. lockdep_assert_held(&ar->ab->base_lock);
  751. for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
  752. rx_tid = &peer->rx_tid[i];
  753. ath11k_peer_rx_tid_delete(ar, peer, i);
  754. ath11k_dp_rx_frags_cleanup(rx_tid, true);
  755. spin_unlock_bh(&ar->ab->base_lock);
  756. del_timer_sync(&rx_tid->frag_timer);
  757. spin_lock_bh(&ar->ab->base_lock);
  758. }
  759. }
  760. static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
  761. struct ath11k_peer *peer,
  762. struct dp_rx_tid *rx_tid,
  763. u32 ba_win_sz, u16 ssn,
  764. bool update_ssn)
  765. {
  766. struct ath11k_hal_reo_cmd cmd = {0};
  767. int ret;
  768. cmd.addr_lo = lower_32_bits(rx_tid->paddr);
  769. cmd.addr_hi = upper_32_bits(rx_tid->paddr);
  770. cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
  771. cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
  772. cmd.ba_window_size = ba_win_sz;
  773. if (update_ssn) {
  774. cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
  775. cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
  776. }
  777. ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
  778. HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
  779. NULL);
  780. if (ret) {
  781. ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
  782. rx_tid->tid, ret);
  783. return ret;
  784. }
  785. rx_tid->ba_win_sz = ba_win_sz;
  786. return 0;
  787. }
  788. static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
  789. const u8 *peer_mac, int vdev_id, u8 tid)
  790. {
  791. struct ath11k_peer *peer;
  792. struct dp_rx_tid *rx_tid;
  793. spin_lock_bh(&ab->base_lock);
  794. peer = ath11k_peer_find(ab, vdev_id, peer_mac);
  795. if (!peer) {
  796. ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
  797. goto unlock_exit;
  798. }
  799. rx_tid = &peer->rx_tid[tid];
  800. if (!rx_tid->active)
  801. goto unlock_exit;
  802. dma_free_noncoherent(ab->dev, rx_tid->unaligned_size, rx_tid->vaddr_unaligned,
  803. rx_tid->paddr_unaligned, DMA_BIDIRECTIONAL);
  804. rx_tid->vaddr_unaligned = NULL;
  805. rx_tid->active = false;
  806. unlock_exit:
  807. spin_unlock_bh(&ab->base_lock);
  808. }
  809. int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
  810. u8 tid, u32 ba_win_sz, u16 ssn,
  811. enum hal_pn_type pn_type)
  812. {
  813. struct ath11k_base *ab = ar->ab;
  814. struct ath11k_peer *peer;
  815. struct dp_rx_tid *rx_tid;
  816. u32 hw_desc_sz, *vaddr;
  817. void *vaddr_unaligned;
  818. dma_addr_t paddr;
  819. int ret;
  820. spin_lock_bh(&ab->base_lock);
  821. peer = ath11k_peer_find(ab, vdev_id, peer_mac);
  822. if (!peer) {
  823. ath11k_warn(ab, "failed to find the peer %pM to set up rx tid\n",
  824. peer_mac);
  825. spin_unlock_bh(&ab->base_lock);
  826. return -ENOENT;
  827. }
  828. rx_tid = &peer->rx_tid[tid];
  829. /* Update the tid queue if it is already setup */
  830. if (rx_tid->active) {
  831. paddr = rx_tid->paddr;
  832. ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
  833. ba_win_sz, ssn, true);
  834. spin_unlock_bh(&ab->base_lock);
  835. if (ret) {
  836. ath11k_warn(ab, "failed to update reo for peer %pM rx tid %d\n: %d",
  837. peer_mac, tid, ret);
  838. return ret;
  839. }
  840. ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
  841. peer_mac, paddr,
  842. tid, 1, ba_win_sz);
  843. if (ret)
  844. ath11k_warn(ab, "failed to send wmi rx reorder queue for peer %pM tid %d: %d\n",
  845. peer_mac, tid, ret);
  846. return ret;
  847. }
  848. rx_tid->tid = tid;
  849. rx_tid->ba_win_sz = ba_win_sz;
  850. /* TODO: Optimize the memory allocation for qos tid based on
  851. * the actual BA window size in REO tid update path.
  852. */
  853. if (tid == HAL_DESC_REO_NON_QOS_TID)
  854. hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
  855. else
  856. hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
  857. rx_tid->unaligned_size = hw_desc_sz + HAL_LINK_DESC_ALIGN - 1;
  858. vaddr_unaligned = dma_alloc_noncoherent(ab->dev, rx_tid->unaligned_size, &paddr,
  859. DMA_BIDIRECTIONAL, GFP_ATOMIC);
  860. if (!vaddr_unaligned) {
  861. spin_unlock_bh(&ab->base_lock);
  862. return -ENOMEM;
  863. }
  864. rx_tid->vaddr_unaligned = vaddr_unaligned;
  865. vaddr = PTR_ALIGN(vaddr_unaligned, HAL_LINK_DESC_ALIGN);
  866. rx_tid->paddr_unaligned = paddr;
  867. rx_tid->paddr = rx_tid->paddr_unaligned + ((unsigned long)vaddr -
  868. (unsigned long)rx_tid->vaddr_unaligned);
  869. ath11k_hal_reo_qdesc_setup(vaddr, tid, ba_win_sz, ssn, pn_type);
  870. rx_tid->size = hw_desc_sz;
  871. rx_tid->active = true;
  872. /* After dma_alloc_noncoherent, vaddr is being modified for reo qdesc setup.
  873. * Since these changes are not reflected in the device, driver now needs to
  874. * explicitly call dma_sync_single_for_device.
  875. */
  876. dma_sync_single_for_device(ab->dev, rx_tid->paddr,
  877. rx_tid->size,
  878. DMA_TO_DEVICE);
  879. spin_unlock_bh(&ab->base_lock);
  880. ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, rx_tid->paddr,
  881. tid, 1, ba_win_sz);
  882. if (ret) {
  883. ath11k_warn(ar->ab, "failed to setup rx reorder queue for peer %pM tid %d: %d\n",
  884. peer_mac, tid, ret);
  885. ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
  886. }
  887. return ret;
  888. }
  889. int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
  890. struct ieee80211_ampdu_params *params)
  891. {
  892. struct ath11k_base *ab = ar->ab;
  893. struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
  894. int vdev_id = arsta->arvif->vdev_id;
  895. int ret;
  896. ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
  897. params->tid, params->buf_size,
  898. params->ssn, arsta->pn_type);
  899. if (ret)
  900. ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
  901. return ret;
  902. }
  903. int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
  904. struct ieee80211_ampdu_params *params)
  905. {
  906. struct ath11k_base *ab = ar->ab;
  907. struct ath11k_peer *peer;
  908. struct ath11k_sta *arsta = ath11k_sta_to_arsta(params->sta);
  909. int vdev_id = arsta->arvif->vdev_id;
  910. dma_addr_t paddr;
  911. bool active;
  912. int ret;
  913. spin_lock_bh(&ab->base_lock);
  914. peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
  915. if (!peer) {
  916. ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
  917. spin_unlock_bh(&ab->base_lock);
  918. return -ENOENT;
  919. }
  920. paddr = peer->rx_tid[params->tid].paddr;
  921. active = peer->rx_tid[params->tid].active;
  922. if (!active) {
  923. spin_unlock_bh(&ab->base_lock);
  924. return 0;
  925. }
  926. ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
  927. spin_unlock_bh(&ab->base_lock);
  928. if (ret) {
  929. ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
  930. params->tid, ret);
  931. return ret;
  932. }
  933. ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
  934. params->sta->addr, paddr,
  935. params->tid, 1, 1);
  936. if (ret)
  937. ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
  938. ret);
  939. return ret;
  940. }
  941. int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
  942. const u8 *peer_addr,
  943. enum set_key_cmd key_cmd,
  944. struct ieee80211_key_conf *key)
  945. {
  946. struct ath11k *ar = arvif->ar;
  947. struct ath11k_base *ab = ar->ab;
  948. struct ath11k_hal_reo_cmd cmd = {0};
  949. struct ath11k_peer *peer;
  950. struct dp_rx_tid *rx_tid;
  951. u8 tid;
  952. int ret = 0;
  953. /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
  954. * We use mac80211 PN/TSC replay check functionality for bcast/mcast
  955. * for now.
  956. */
  957. if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
  958. return 0;
  959. cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
  960. cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
  961. HAL_REO_CMD_UPD0_PN_SIZE |
  962. HAL_REO_CMD_UPD0_PN_VALID |
  963. HAL_REO_CMD_UPD0_PN_CHECK |
  964. HAL_REO_CMD_UPD0_SVLD;
  965. switch (key->cipher) {
  966. case WLAN_CIPHER_SUITE_TKIP:
  967. case WLAN_CIPHER_SUITE_CCMP:
  968. case WLAN_CIPHER_SUITE_CCMP_256:
  969. case WLAN_CIPHER_SUITE_GCMP:
  970. case WLAN_CIPHER_SUITE_GCMP_256:
  971. if (key_cmd == SET_KEY) {
  972. cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
  973. cmd.pn_size = 48;
  974. }
  975. break;
  976. default:
  977. break;
  978. }
  979. spin_lock_bh(&ab->base_lock);
  980. peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
  981. if (!peer) {
  982. ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
  983. spin_unlock_bh(&ab->base_lock);
  984. return -ENOENT;
  985. }
  986. for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
  987. rx_tid = &peer->rx_tid[tid];
  988. if (!rx_tid->active)
  989. continue;
  990. cmd.addr_lo = lower_32_bits(rx_tid->paddr);
  991. cmd.addr_hi = upper_32_bits(rx_tid->paddr);
  992. ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
  993. HAL_REO_CMD_UPDATE_RX_QUEUE,
  994. &cmd, NULL);
  995. if (ret) {
  996. ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
  997. tid, ret);
  998. break;
  999. }
  1000. }
  1001. spin_unlock_bh(&ab->base_lock);
  1002. return ret;
  1003. }
  1004. static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
  1005. u16 peer_id)
  1006. {
  1007. int i;
  1008. for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
  1009. if (ppdu_stats->user_stats[i].is_valid_peer_id) {
  1010. if (peer_id == ppdu_stats->user_stats[i].peer_id)
  1011. return i;
  1012. } else {
  1013. return i;
  1014. }
  1015. }
  1016. return -EINVAL;
  1017. }
  1018. static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
  1019. u16 tag, u16 len, const void *ptr,
  1020. void *data)
  1021. {
  1022. struct htt_ppdu_stats_info *ppdu_info;
  1023. struct htt_ppdu_user_stats *user_stats;
  1024. int cur_user;
  1025. u16 peer_id;
  1026. ppdu_info = data;
  1027. switch (tag) {
  1028. case HTT_PPDU_STATS_TAG_COMMON:
  1029. if (len < sizeof(struct htt_ppdu_stats_common)) {
  1030. ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
  1031. len, tag);
  1032. return -EINVAL;
  1033. }
  1034. memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
  1035. sizeof(struct htt_ppdu_stats_common));
  1036. break;
  1037. case HTT_PPDU_STATS_TAG_USR_RATE:
  1038. if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
  1039. ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
  1040. len, tag);
  1041. return -EINVAL;
  1042. }
  1043. peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
  1044. cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
  1045. peer_id);
  1046. if (cur_user < 0)
  1047. return -EINVAL;
  1048. user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
  1049. user_stats->peer_id = peer_id;
  1050. user_stats->is_valid_peer_id = true;
  1051. memcpy((void *)&user_stats->rate, ptr,
  1052. sizeof(struct htt_ppdu_stats_user_rate));
  1053. user_stats->tlv_flags |= BIT(tag);
  1054. break;
  1055. case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
  1056. if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
  1057. ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
  1058. len, tag);
  1059. return -EINVAL;
  1060. }
  1061. peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
  1062. cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
  1063. peer_id);
  1064. if (cur_user < 0)
  1065. return -EINVAL;
  1066. user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
  1067. user_stats->peer_id = peer_id;
  1068. user_stats->is_valid_peer_id = true;
  1069. memcpy((void *)&user_stats->cmpltn_cmn, ptr,
  1070. sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
  1071. user_stats->tlv_flags |= BIT(tag);
  1072. break;
  1073. case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
  1074. if (len <
  1075. sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
  1076. ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
  1077. len, tag);
  1078. return -EINVAL;
  1079. }
  1080. peer_id =
  1081. ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
  1082. cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
  1083. peer_id);
  1084. if (cur_user < 0)
  1085. return -EINVAL;
  1086. user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
  1087. user_stats->peer_id = peer_id;
  1088. user_stats->is_valid_peer_id = true;
  1089. memcpy((void *)&user_stats->ack_ba, ptr,
  1090. sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
  1091. user_stats->tlv_flags |= BIT(tag);
  1092. break;
  1093. }
  1094. return 0;
  1095. }
  1096. int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
  1097. int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
  1098. const void *ptr, void *data),
  1099. void *data)
  1100. {
  1101. const struct htt_tlv *tlv;
  1102. const void *begin = ptr;
  1103. u16 tlv_tag, tlv_len;
  1104. int ret = -EINVAL;
  1105. while (len > 0) {
  1106. if (len < sizeof(*tlv)) {
  1107. ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
  1108. ptr - begin, len, sizeof(*tlv));
  1109. return -EINVAL;
  1110. }
  1111. tlv = (struct htt_tlv *)ptr;
  1112. tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
  1113. tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
  1114. ptr += sizeof(*tlv);
  1115. len -= sizeof(*tlv);
  1116. if (tlv_len > len) {
  1117. ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
  1118. tlv_tag, ptr - begin, len, tlv_len);
  1119. return -EINVAL;
  1120. }
  1121. ret = iter(ab, tlv_tag, tlv_len, ptr, data);
  1122. if (ret == -ENOMEM)
  1123. return ret;
  1124. ptr += tlv_len;
  1125. len -= tlv_len;
  1126. }
  1127. return 0;
  1128. }
  1129. static void
  1130. ath11k_update_per_peer_tx_stats(struct ath11k *ar,
  1131. struct htt_ppdu_stats *ppdu_stats, u8 user)
  1132. {
  1133. struct ath11k_base *ab = ar->ab;
  1134. struct ath11k_peer *peer;
  1135. struct ieee80211_sta *sta;
  1136. struct ath11k_sta *arsta;
  1137. struct htt_ppdu_stats_user_rate *user_rate;
  1138. struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
  1139. struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
  1140. struct htt_ppdu_stats_common *common = &ppdu_stats->common;
  1141. int ret;
  1142. u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
  1143. u32 succ_bytes = 0;
  1144. u16 rate = 0, succ_pkts = 0;
  1145. u32 tx_duration = 0;
  1146. u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
  1147. bool is_ampdu = false;
  1148. if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
  1149. return;
  1150. if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
  1151. is_ampdu =
  1152. HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
  1153. if (usr_stats->tlv_flags &
  1154. BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
  1155. succ_bytes = usr_stats->ack_ba.success_bytes;
  1156. succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
  1157. usr_stats->ack_ba.info);
  1158. tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
  1159. usr_stats->ack_ba.info);
  1160. }
  1161. if (common->fes_duration_us)
  1162. tx_duration = common->fes_duration_us;
  1163. user_rate = &usr_stats->rate;
  1164. flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
  1165. bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
  1166. nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
  1167. mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
  1168. sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
  1169. dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
  1170. /* Note: If host configured fixed rates and in some other special
  1171. * cases, the broadcast/management frames are sent in different rates.
  1172. * Firmware rate's control to be skipped for this?
  1173. */
  1174. if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
  1175. ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
  1176. return;
  1177. }
  1178. if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
  1179. ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
  1180. return;
  1181. }
  1182. if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
  1183. ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
  1184. mcs, nss);
  1185. return;
  1186. }
  1187. if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
  1188. ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
  1189. flags,
  1190. &rate_idx,
  1191. &rate);
  1192. if (ret < 0)
  1193. return;
  1194. }
  1195. rcu_read_lock();
  1196. spin_lock_bh(&ab->base_lock);
  1197. peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
  1198. if (!peer || !peer->sta) {
  1199. spin_unlock_bh(&ab->base_lock);
  1200. rcu_read_unlock();
  1201. return;
  1202. }
  1203. sta = peer->sta;
  1204. arsta = ath11k_sta_to_arsta(sta);
  1205. memset(&arsta->txrate, 0, sizeof(arsta->txrate));
  1206. switch (flags) {
  1207. case WMI_RATE_PREAMBLE_OFDM:
  1208. arsta->txrate.legacy = rate;
  1209. break;
  1210. case WMI_RATE_PREAMBLE_CCK:
  1211. arsta->txrate.legacy = rate;
  1212. break;
  1213. case WMI_RATE_PREAMBLE_HT:
  1214. arsta->txrate.mcs = mcs + 8 * (nss - 1);
  1215. arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
  1216. if (sgi)
  1217. arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
  1218. break;
  1219. case WMI_RATE_PREAMBLE_VHT:
  1220. arsta->txrate.mcs = mcs;
  1221. arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
  1222. if (sgi)
  1223. arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
  1224. break;
  1225. case WMI_RATE_PREAMBLE_HE:
  1226. arsta->txrate.mcs = mcs;
  1227. arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
  1228. arsta->txrate.he_dcm = dcm;
  1229. arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
  1230. arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc
  1231. ((user_rate->ru_end -
  1232. user_rate->ru_start) + 1);
  1233. break;
  1234. }
  1235. arsta->txrate.nss = nss;
  1236. arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
  1237. arsta->tx_duration += tx_duration;
  1238. memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
  1239. /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
  1240. * So skip peer stats update for mgmt packets.
  1241. */
  1242. if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
  1243. memset(peer_stats, 0, sizeof(*peer_stats));
  1244. peer_stats->succ_pkts = succ_pkts;
  1245. peer_stats->succ_bytes = succ_bytes;
  1246. peer_stats->is_ampdu = is_ampdu;
  1247. peer_stats->duration = tx_duration;
  1248. peer_stats->ba_fails =
  1249. HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
  1250. HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
  1251. if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
  1252. ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
  1253. }
  1254. spin_unlock_bh(&ab->base_lock);
  1255. rcu_read_unlock();
  1256. }
  1257. static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
  1258. struct htt_ppdu_stats *ppdu_stats)
  1259. {
  1260. u8 user;
  1261. for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
  1262. ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
  1263. }
  1264. static
  1265. struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
  1266. u32 ppdu_id)
  1267. {
  1268. struct htt_ppdu_stats_info *ppdu_info;
  1269. lockdep_assert_held(&ar->data_lock);
  1270. if (!list_empty(&ar->ppdu_stats_info)) {
  1271. list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
  1272. if (ppdu_info->ppdu_id == ppdu_id)
  1273. return ppdu_info;
  1274. }
  1275. if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
  1276. ppdu_info = list_first_entry(&ar->ppdu_stats_info,
  1277. typeof(*ppdu_info), list);
  1278. list_del(&ppdu_info->list);
  1279. ar->ppdu_stat_list_depth--;
  1280. ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
  1281. kfree(ppdu_info);
  1282. }
  1283. }
  1284. ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
  1285. if (!ppdu_info)
  1286. return NULL;
  1287. list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
  1288. ar->ppdu_stat_list_depth++;
  1289. return ppdu_info;
  1290. }
  1291. static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
  1292. struct sk_buff *skb)
  1293. {
  1294. struct ath11k_htt_ppdu_stats_msg *msg;
  1295. struct htt_ppdu_stats_info *ppdu_info;
  1296. struct ath11k *ar;
  1297. int ret;
  1298. u8 pdev_id;
  1299. u32 ppdu_id, len;
  1300. msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
  1301. len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
  1302. pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
  1303. ppdu_id = msg->ppdu_id;
  1304. rcu_read_lock();
  1305. ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
  1306. if (!ar) {
  1307. ret = -EINVAL;
  1308. goto out;
  1309. }
  1310. if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
  1311. trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
  1312. spin_lock_bh(&ar->data_lock);
  1313. ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
  1314. if (!ppdu_info) {
  1315. ret = -EINVAL;
  1316. goto out_unlock_data;
  1317. }
  1318. ppdu_info->ppdu_id = ppdu_id;
  1319. ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
  1320. ath11k_htt_tlv_ppdu_stats_parse,
  1321. (void *)ppdu_info);
  1322. if (ret) {
  1323. ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
  1324. goto out_unlock_data;
  1325. }
  1326. out_unlock_data:
  1327. spin_unlock_bh(&ar->data_lock);
  1328. out:
  1329. rcu_read_unlock();
  1330. return ret;
  1331. }
  1332. static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
  1333. {
  1334. struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
  1335. struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
  1336. struct ath11k *ar;
  1337. u8 pdev_id;
  1338. pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
  1339. rcu_read_lock();
  1340. ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
  1341. if (!ar) {
  1342. ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
  1343. goto out;
  1344. }
  1345. trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
  1346. ar->ab->pktlog_defs_checksum);
  1347. out:
  1348. rcu_read_unlock();
  1349. }
  1350. static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
  1351. struct sk_buff *skb)
  1352. {
  1353. u32 *data = (u32 *)skb->data;
  1354. u8 pdev_id, ring_type, ring_id, pdev_idx;
  1355. u16 hp, tp;
  1356. u32 backpressure_time;
  1357. struct ath11k_bp_stats *bp_stats;
  1358. pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
  1359. ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
  1360. ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
  1361. ++data;
  1362. hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
  1363. tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
  1364. ++data;
  1365. backpressure_time = *data;
  1366. ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
  1367. pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
  1368. if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
  1369. if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
  1370. return;
  1371. bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
  1372. } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
  1373. pdev_idx = DP_HW2SW_MACID(pdev_id);
  1374. if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
  1375. return;
  1376. bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
  1377. } else {
  1378. ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
  1379. ring_type);
  1380. return;
  1381. }
  1382. spin_lock_bh(&ab->base_lock);
  1383. bp_stats->hp = hp;
  1384. bp_stats->tp = tp;
  1385. bp_stats->count++;
  1386. bp_stats->jiffies = jiffies;
  1387. spin_unlock_bh(&ab->base_lock);
  1388. }
  1389. void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
  1390. struct sk_buff *skb)
  1391. {
  1392. struct ath11k_dp *dp = &ab->dp;
  1393. struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
  1394. enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
  1395. u16 peer_id;
  1396. u8 vdev_id;
  1397. u8 mac_addr[ETH_ALEN];
  1398. u16 peer_mac_h16;
  1399. u16 ast_hash;
  1400. u16 hw_peer_id;
  1401. ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
  1402. switch (type) {
  1403. case HTT_T2H_MSG_TYPE_VERSION_CONF:
  1404. dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
  1405. resp->version_msg.version);
  1406. dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
  1407. resp->version_msg.version);
  1408. complete(&dp->htt_tgt_version_received);
  1409. break;
  1410. case HTT_T2H_MSG_TYPE_PEER_MAP:
  1411. vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
  1412. resp->peer_map_ev.info);
  1413. peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
  1414. resp->peer_map_ev.info);
  1415. peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
  1416. resp->peer_map_ev.info1);
  1417. ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
  1418. peer_mac_h16, mac_addr);
  1419. ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
  1420. break;
  1421. case HTT_T2H_MSG_TYPE_PEER_MAP2:
  1422. vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
  1423. resp->peer_map_ev.info);
  1424. peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
  1425. resp->peer_map_ev.info);
  1426. peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
  1427. resp->peer_map_ev.info1);
  1428. ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
  1429. peer_mac_h16, mac_addr);
  1430. ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
  1431. resp->peer_map_ev.info2);
  1432. hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
  1433. resp->peer_map_ev.info1);
  1434. ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
  1435. hw_peer_id);
  1436. break;
  1437. case HTT_T2H_MSG_TYPE_PEER_UNMAP:
  1438. case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
  1439. peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
  1440. resp->peer_unmap_ev.info);
  1441. ath11k_peer_unmap_event(ab, peer_id);
  1442. break;
  1443. case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
  1444. ath11k_htt_pull_ppdu_stats(ab, skb);
  1445. break;
  1446. case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
  1447. ath11k_debugfs_htt_ext_stats_handler(ab, skb);
  1448. break;
  1449. case HTT_T2H_MSG_TYPE_PKTLOG:
  1450. ath11k_htt_pktlog(ab, skb);
  1451. break;
  1452. case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
  1453. ath11k_htt_backpressure_event_handler(ab, skb);
  1454. break;
  1455. default:
  1456. ath11k_warn(ab, "htt event %d not handled\n", type);
  1457. break;
  1458. }
  1459. dev_kfree_skb_any(skb);
  1460. }
  1461. static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
  1462. struct sk_buff_head *msdu_list,
  1463. struct sk_buff *first, struct sk_buff *last,
  1464. u8 l3pad_bytes, int msdu_len)
  1465. {
  1466. struct ath11k_base *ab = ar->ab;
  1467. struct sk_buff *skb;
  1468. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
  1469. int buf_first_hdr_len, buf_first_len;
  1470. struct hal_rx_desc *ldesc;
  1471. int space_extra, rem_len, buf_len;
  1472. u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
  1473. /* As the msdu is spread across multiple rx buffers,
  1474. * find the offset to the start of msdu for computing
  1475. * the length of the msdu in the first buffer.
  1476. */
  1477. buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
  1478. buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
  1479. if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
  1480. skb_put(first, buf_first_hdr_len + msdu_len);
  1481. skb_pull(first, buf_first_hdr_len);
  1482. return 0;
  1483. }
  1484. ldesc = (struct hal_rx_desc *)last->data;
  1485. rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
  1486. rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
  1487. /* MSDU spans over multiple buffers because the length of the MSDU
  1488. * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
  1489. * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
  1490. */
  1491. skb_put(first, DP_RX_BUFFER_SIZE);
  1492. skb_pull(first, buf_first_hdr_len);
  1493. /* When an MSDU spread over multiple buffers attention, MSDU_END and
  1494. * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
  1495. */
  1496. ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
  1497. space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
  1498. if (space_extra > 0 &&
  1499. (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
  1500. /* Free up all buffers of the MSDU */
  1501. while ((skb = __skb_dequeue(msdu_list)) != NULL) {
  1502. rxcb = ATH11K_SKB_RXCB(skb);
  1503. if (!rxcb->is_continuation) {
  1504. dev_kfree_skb_any(skb);
  1505. break;
  1506. }
  1507. dev_kfree_skb_any(skb);
  1508. }
  1509. return -ENOMEM;
  1510. }
  1511. rem_len = msdu_len - buf_first_len;
  1512. while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
  1513. rxcb = ATH11K_SKB_RXCB(skb);
  1514. if (rxcb->is_continuation)
  1515. buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
  1516. else
  1517. buf_len = rem_len;
  1518. if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
  1519. WARN_ON_ONCE(1);
  1520. dev_kfree_skb_any(skb);
  1521. return -EINVAL;
  1522. }
  1523. skb_put(skb, buf_len + hal_rx_desc_sz);
  1524. skb_pull(skb, hal_rx_desc_sz);
  1525. skb_copy_from_linear_data(skb, skb_put(first, buf_len),
  1526. buf_len);
  1527. dev_kfree_skb_any(skb);
  1528. rem_len -= buf_len;
  1529. if (!rxcb->is_continuation)
  1530. break;
  1531. }
  1532. return 0;
  1533. }
  1534. static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
  1535. struct sk_buff *first)
  1536. {
  1537. struct sk_buff *skb;
  1538. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
  1539. if (!rxcb->is_continuation)
  1540. return first;
  1541. skb_queue_walk(msdu_list, skb) {
  1542. rxcb = ATH11K_SKB_RXCB(skb);
  1543. if (!rxcb->is_continuation)
  1544. return skb;
  1545. }
  1546. return NULL;
  1547. }
  1548. static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
  1549. {
  1550. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
  1551. struct rx_attention *rx_attention;
  1552. bool ip_csum_fail, l4_csum_fail;
  1553. rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
  1554. ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
  1555. l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
  1556. msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
  1557. CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
  1558. }
  1559. int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, enum hal_encrypt_type enctype)
  1560. {
  1561. switch (enctype) {
  1562. case HAL_ENCRYPT_TYPE_OPEN:
  1563. case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
  1564. case HAL_ENCRYPT_TYPE_TKIP_MIC:
  1565. return 0;
  1566. case HAL_ENCRYPT_TYPE_CCMP_128:
  1567. return IEEE80211_CCMP_MIC_LEN;
  1568. case HAL_ENCRYPT_TYPE_CCMP_256:
  1569. return IEEE80211_CCMP_256_MIC_LEN;
  1570. case HAL_ENCRYPT_TYPE_GCMP_128:
  1571. case HAL_ENCRYPT_TYPE_AES_GCMP_256:
  1572. return IEEE80211_GCMP_MIC_LEN;
  1573. case HAL_ENCRYPT_TYPE_WEP_40:
  1574. case HAL_ENCRYPT_TYPE_WEP_104:
  1575. case HAL_ENCRYPT_TYPE_WEP_128:
  1576. case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
  1577. case HAL_ENCRYPT_TYPE_WAPI:
  1578. break;
  1579. }
  1580. ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
  1581. return 0;
  1582. }
  1583. static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
  1584. enum hal_encrypt_type enctype)
  1585. {
  1586. switch (enctype) {
  1587. case HAL_ENCRYPT_TYPE_OPEN:
  1588. return 0;
  1589. case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
  1590. case HAL_ENCRYPT_TYPE_TKIP_MIC:
  1591. return IEEE80211_TKIP_IV_LEN;
  1592. case HAL_ENCRYPT_TYPE_CCMP_128:
  1593. return IEEE80211_CCMP_HDR_LEN;
  1594. case HAL_ENCRYPT_TYPE_CCMP_256:
  1595. return IEEE80211_CCMP_256_HDR_LEN;
  1596. case HAL_ENCRYPT_TYPE_GCMP_128:
  1597. case HAL_ENCRYPT_TYPE_AES_GCMP_256:
  1598. return IEEE80211_GCMP_HDR_LEN;
  1599. case HAL_ENCRYPT_TYPE_WEP_40:
  1600. case HAL_ENCRYPT_TYPE_WEP_104:
  1601. case HAL_ENCRYPT_TYPE_WEP_128:
  1602. case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
  1603. case HAL_ENCRYPT_TYPE_WAPI:
  1604. break;
  1605. }
  1606. ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
  1607. return 0;
  1608. }
  1609. static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
  1610. enum hal_encrypt_type enctype)
  1611. {
  1612. switch (enctype) {
  1613. case HAL_ENCRYPT_TYPE_OPEN:
  1614. case HAL_ENCRYPT_TYPE_CCMP_128:
  1615. case HAL_ENCRYPT_TYPE_CCMP_256:
  1616. case HAL_ENCRYPT_TYPE_GCMP_128:
  1617. case HAL_ENCRYPT_TYPE_AES_GCMP_256:
  1618. return 0;
  1619. case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
  1620. case HAL_ENCRYPT_TYPE_TKIP_MIC:
  1621. return IEEE80211_TKIP_ICV_LEN;
  1622. case HAL_ENCRYPT_TYPE_WEP_40:
  1623. case HAL_ENCRYPT_TYPE_WEP_104:
  1624. case HAL_ENCRYPT_TYPE_WEP_128:
  1625. case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
  1626. case HAL_ENCRYPT_TYPE_WAPI:
  1627. break;
  1628. }
  1629. ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
  1630. return 0;
  1631. }
  1632. static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
  1633. struct sk_buff *msdu,
  1634. u8 *first_hdr,
  1635. enum hal_encrypt_type enctype,
  1636. struct ieee80211_rx_status *status)
  1637. {
  1638. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
  1639. u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
  1640. struct ieee80211_hdr *hdr;
  1641. size_t hdr_len;
  1642. u8 da[ETH_ALEN];
  1643. u8 sa[ETH_ALEN];
  1644. u16 qos_ctl = 0;
  1645. u8 *qos;
  1646. /* copy SA & DA and pull decapped header */
  1647. hdr = (struct ieee80211_hdr *)msdu->data;
  1648. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  1649. ether_addr_copy(da, ieee80211_get_DA(hdr));
  1650. ether_addr_copy(sa, ieee80211_get_SA(hdr));
  1651. skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
  1652. if (rxcb->is_first_msdu) {
  1653. /* original 802.11 header is valid for the first msdu
  1654. * hence we can reuse the same header
  1655. */
  1656. hdr = (struct ieee80211_hdr *)first_hdr;
  1657. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  1658. /* Each A-MSDU subframe will be reported as a separate MSDU,
  1659. * so strip the A-MSDU bit from QoS Ctl.
  1660. */
  1661. if (ieee80211_is_data_qos(hdr->frame_control)) {
  1662. qos = ieee80211_get_qos_ctl(hdr);
  1663. qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
  1664. }
  1665. } else {
  1666. /* Rebuild qos header if this is a middle/last msdu */
  1667. hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
  1668. /* Reset the order bit as the HT_Control header is stripped */
  1669. hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
  1670. qos_ctl = rxcb->tid;
  1671. if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
  1672. qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
  1673. /* TODO Add other QoS ctl fields when required */
  1674. /* copy decap header before overwriting for reuse below */
  1675. memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
  1676. }
  1677. if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
  1678. memcpy(skb_push(msdu,
  1679. ath11k_dp_rx_crypto_param_len(ar, enctype)),
  1680. (void *)hdr + hdr_len,
  1681. ath11k_dp_rx_crypto_param_len(ar, enctype));
  1682. }
  1683. if (!rxcb->is_first_msdu) {
  1684. memcpy(skb_push(msdu,
  1685. IEEE80211_QOS_CTL_LEN), &qos_ctl,
  1686. IEEE80211_QOS_CTL_LEN);
  1687. memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
  1688. return;
  1689. }
  1690. memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
  1691. /* original 802.11 header has a different DA and in
  1692. * case of 4addr it may also have different SA
  1693. */
  1694. hdr = (struct ieee80211_hdr *)msdu->data;
  1695. ether_addr_copy(ieee80211_get_DA(hdr), da);
  1696. ether_addr_copy(ieee80211_get_SA(hdr), sa);
  1697. }
  1698. static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
  1699. enum hal_encrypt_type enctype,
  1700. struct ieee80211_rx_status *status,
  1701. bool decrypted)
  1702. {
  1703. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
  1704. struct ieee80211_hdr *hdr;
  1705. size_t hdr_len;
  1706. size_t crypto_len;
  1707. if (!rxcb->is_first_msdu ||
  1708. !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
  1709. WARN_ON_ONCE(1);
  1710. return;
  1711. }
  1712. skb_trim(msdu, msdu->len - FCS_LEN);
  1713. if (!decrypted)
  1714. return;
  1715. hdr = (void *)msdu->data;
  1716. /* Tail */
  1717. if (status->flag & RX_FLAG_IV_STRIPPED) {
  1718. skb_trim(msdu, msdu->len -
  1719. ath11k_dp_rx_crypto_mic_len(ar, enctype));
  1720. skb_trim(msdu, msdu->len -
  1721. ath11k_dp_rx_crypto_icv_len(ar, enctype));
  1722. } else {
  1723. /* MIC */
  1724. if (status->flag & RX_FLAG_MIC_STRIPPED)
  1725. skb_trim(msdu, msdu->len -
  1726. ath11k_dp_rx_crypto_mic_len(ar, enctype));
  1727. /* ICV */
  1728. if (status->flag & RX_FLAG_ICV_STRIPPED)
  1729. skb_trim(msdu, msdu->len -
  1730. ath11k_dp_rx_crypto_icv_len(ar, enctype));
  1731. }
  1732. /* MMIC */
  1733. if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
  1734. !ieee80211_has_morefrags(hdr->frame_control) &&
  1735. enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
  1736. skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
  1737. /* Head */
  1738. if (status->flag & RX_FLAG_IV_STRIPPED) {
  1739. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  1740. crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
  1741. memmove((void *)msdu->data + crypto_len,
  1742. (void *)msdu->data, hdr_len);
  1743. skb_pull(msdu, crypto_len);
  1744. }
  1745. }
  1746. static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
  1747. struct sk_buff *msdu,
  1748. enum hal_encrypt_type enctype)
  1749. {
  1750. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
  1751. struct ieee80211_hdr *hdr;
  1752. size_t hdr_len, crypto_len;
  1753. void *rfc1042;
  1754. bool is_amsdu;
  1755. is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
  1756. hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
  1757. rfc1042 = hdr;
  1758. if (rxcb->is_first_msdu) {
  1759. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  1760. crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
  1761. rfc1042 += hdr_len + crypto_len;
  1762. }
  1763. if (is_amsdu)
  1764. rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
  1765. return rfc1042;
  1766. }
  1767. static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
  1768. struct sk_buff *msdu,
  1769. u8 *first_hdr,
  1770. enum hal_encrypt_type enctype,
  1771. struct ieee80211_rx_status *status)
  1772. {
  1773. struct ieee80211_hdr *hdr;
  1774. struct ethhdr *eth;
  1775. size_t hdr_len;
  1776. u8 da[ETH_ALEN];
  1777. u8 sa[ETH_ALEN];
  1778. void *rfc1042;
  1779. rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
  1780. if (WARN_ON_ONCE(!rfc1042))
  1781. return;
  1782. /* pull decapped header and copy SA & DA */
  1783. eth = (struct ethhdr *)msdu->data;
  1784. ether_addr_copy(da, eth->h_dest);
  1785. ether_addr_copy(sa, eth->h_source);
  1786. skb_pull(msdu, sizeof(struct ethhdr));
  1787. /* push rfc1042/llc/snap */
  1788. memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
  1789. sizeof(struct ath11k_dp_rfc1042_hdr));
  1790. /* push original 802.11 header */
  1791. hdr = (struct ieee80211_hdr *)first_hdr;
  1792. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  1793. if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
  1794. memcpy(skb_push(msdu,
  1795. ath11k_dp_rx_crypto_param_len(ar, enctype)),
  1796. (void *)hdr + hdr_len,
  1797. ath11k_dp_rx_crypto_param_len(ar, enctype));
  1798. }
  1799. memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
  1800. /* original 802.11 header has a different DA and in
  1801. * case of 4addr it may also have different SA
  1802. */
  1803. hdr = (struct ieee80211_hdr *)msdu->data;
  1804. ether_addr_copy(ieee80211_get_DA(hdr), da);
  1805. ether_addr_copy(ieee80211_get_SA(hdr), sa);
  1806. }
  1807. static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
  1808. struct hal_rx_desc *rx_desc,
  1809. enum hal_encrypt_type enctype,
  1810. struct ieee80211_rx_status *status,
  1811. bool decrypted)
  1812. {
  1813. u8 *first_hdr;
  1814. u8 decap;
  1815. struct ethhdr *ehdr;
  1816. first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
  1817. decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
  1818. switch (decap) {
  1819. case DP_RX_DECAP_TYPE_NATIVE_WIFI:
  1820. ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
  1821. enctype, status);
  1822. break;
  1823. case DP_RX_DECAP_TYPE_RAW:
  1824. ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
  1825. decrypted);
  1826. break;
  1827. case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
  1828. ehdr = (struct ethhdr *)msdu->data;
  1829. /* mac80211 allows fast path only for authorized STA */
  1830. if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
  1831. ATH11K_SKB_RXCB(msdu)->is_eapol = true;
  1832. ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
  1833. enctype, status);
  1834. break;
  1835. }
  1836. /* PN for mcast packets will be validated in mac80211;
  1837. * remove eth header and add 802.11 header.
  1838. */
  1839. if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
  1840. ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
  1841. enctype, status);
  1842. break;
  1843. case DP_RX_DECAP_TYPE_8023:
  1844. /* TODO: Handle undecap for these formats */
  1845. break;
  1846. }
  1847. }
  1848. static struct ath11k_peer *
  1849. ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
  1850. {
  1851. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
  1852. struct hal_rx_desc *rx_desc = rxcb->rx_desc;
  1853. struct ath11k_peer *peer = NULL;
  1854. lockdep_assert_held(&ab->base_lock);
  1855. if (rxcb->peer_id)
  1856. peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
  1857. if (peer)
  1858. return peer;
  1859. if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
  1860. return NULL;
  1861. peer = ath11k_peer_find_by_addr(ab,
  1862. ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
  1863. return peer;
  1864. }
  1865. static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
  1866. struct sk_buff *msdu,
  1867. struct hal_rx_desc *rx_desc,
  1868. struct ieee80211_rx_status *rx_status)
  1869. {
  1870. bool fill_crypto_hdr;
  1871. enum hal_encrypt_type enctype;
  1872. bool is_decrypted = false;
  1873. struct ath11k_skb_rxcb *rxcb;
  1874. struct ieee80211_hdr *hdr;
  1875. struct ath11k_peer *peer;
  1876. struct rx_attention *rx_attention;
  1877. u32 err_bitmap;
  1878. /* PN for multicast packets will be checked in mac80211 */
  1879. rxcb = ATH11K_SKB_RXCB(msdu);
  1880. fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
  1881. rxcb->is_mcbc = fill_crypto_hdr;
  1882. if (rxcb->is_mcbc) {
  1883. rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
  1884. rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
  1885. }
  1886. spin_lock_bh(&ar->ab->base_lock);
  1887. peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
  1888. if (peer) {
  1889. if (rxcb->is_mcbc)
  1890. enctype = peer->sec_type_grp;
  1891. else
  1892. enctype = peer->sec_type;
  1893. } else {
  1894. enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
  1895. }
  1896. spin_unlock_bh(&ar->ab->base_lock);
  1897. rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
  1898. err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
  1899. if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
  1900. is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
  1901. /* Clear per-MPDU flags while leaving per-PPDU flags intact */
  1902. rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
  1903. RX_FLAG_MMIC_ERROR |
  1904. RX_FLAG_DECRYPTED |
  1905. RX_FLAG_IV_STRIPPED |
  1906. RX_FLAG_MMIC_STRIPPED);
  1907. if (err_bitmap & DP_RX_MPDU_ERR_FCS)
  1908. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  1909. if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
  1910. rx_status->flag |= RX_FLAG_MMIC_ERROR;
  1911. if (is_decrypted) {
  1912. rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
  1913. if (fill_crypto_hdr)
  1914. rx_status->flag |= RX_FLAG_MIC_STRIPPED |
  1915. RX_FLAG_ICV_STRIPPED;
  1916. else
  1917. rx_status->flag |= RX_FLAG_IV_STRIPPED |
  1918. RX_FLAG_PN_VALIDATED;
  1919. }
  1920. ath11k_dp_rx_h_csum_offload(ar, msdu);
  1921. ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
  1922. enctype, rx_status, is_decrypted);
  1923. if (!is_decrypted || fill_crypto_hdr)
  1924. return;
  1925. if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
  1926. DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
  1927. hdr = (void *)msdu->data;
  1928. hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
  1929. }
  1930. }
  1931. static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
  1932. struct ieee80211_rx_status *rx_status)
  1933. {
  1934. struct ieee80211_supported_band *sband;
  1935. enum rx_msdu_start_pkt_type pkt_type;
  1936. u8 bw;
  1937. u8 rate_mcs, nss;
  1938. u8 sgi;
  1939. bool is_cck, is_ldpc;
  1940. pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
  1941. bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
  1942. rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
  1943. nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
  1944. sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
  1945. switch (pkt_type) {
  1946. case RX_MSDU_START_PKT_TYPE_11A:
  1947. case RX_MSDU_START_PKT_TYPE_11B:
  1948. is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
  1949. sband = &ar->mac.sbands[rx_status->band];
  1950. rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
  1951. is_cck);
  1952. break;
  1953. case RX_MSDU_START_PKT_TYPE_11N:
  1954. rx_status->encoding = RX_ENC_HT;
  1955. if (rate_mcs > ATH11K_HT_MCS_MAX) {
  1956. ath11k_warn(ar->ab,
  1957. "Received with invalid mcs in HT mode %d\n",
  1958. rate_mcs);
  1959. break;
  1960. }
  1961. rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
  1962. if (sgi)
  1963. rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
  1964. rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
  1965. break;
  1966. case RX_MSDU_START_PKT_TYPE_11AC:
  1967. rx_status->encoding = RX_ENC_VHT;
  1968. rx_status->rate_idx = rate_mcs;
  1969. if (rate_mcs > ATH11K_VHT_MCS_MAX) {
  1970. ath11k_warn(ar->ab,
  1971. "Received with invalid mcs in VHT mode %d\n",
  1972. rate_mcs);
  1973. break;
  1974. }
  1975. rx_status->nss = nss;
  1976. if (sgi)
  1977. rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
  1978. rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
  1979. is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc);
  1980. if (is_ldpc)
  1981. rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
  1982. break;
  1983. case RX_MSDU_START_PKT_TYPE_11AX:
  1984. rx_status->rate_idx = rate_mcs;
  1985. if (rate_mcs > ATH11K_HE_MCS_MAX) {
  1986. ath11k_warn(ar->ab,
  1987. "Received with invalid mcs in HE mode %d\n",
  1988. rate_mcs);
  1989. break;
  1990. }
  1991. rx_status->encoding = RX_ENC_HE;
  1992. rx_status->nss = nss;
  1993. rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
  1994. rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
  1995. break;
  1996. }
  1997. }
  1998. static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
  1999. struct ieee80211_rx_status *rx_status)
  2000. {
  2001. u8 channel_num;
  2002. u32 center_freq, meta_data;
  2003. struct ieee80211_channel *channel;
  2004. rx_status->freq = 0;
  2005. rx_status->rate_idx = 0;
  2006. rx_status->nss = 0;
  2007. rx_status->encoding = RX_ENC_LEGACY;
  2008. rx_status->bw = RATE_INFO_BW_20;
  2009. rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
  2010. meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
  2011. channel_num = meta_data;
  2012. center_freq = meta_data >> 16;
  2013. if (center_freq >= ATH11K_MIN_6G_FREQ &&
  2014. center_freq <= ATH11K_MAX_6G_FREQ) {
  2015. rx_status->band = NL80211_BAND_6GHZ;
  2016. rx_status->freq = center_freq;
  2017. } else if (channel_num >= 1 && channel_num <= 14) {
  2018. rx_status->band = NL80211_BAND_2GHZ;
  2019. } else if (channel_num >= 36 && channel_num <= 177) {
  2020. rx_status->band = NL80211_BAND_5GHZ;
  2021. } else {
  2022. spin_lock_bh(&ar->data_lock);
  2023. channel = ar->rx_channel;
  2024. if (channel) {
  2025. rx_status->band = channel->band;
  2026. channel_num =
  2027. ieee80211_frequency_to_channel(channel->center_freq);
  2028. }
  2029. spin_unlock_bh(&ar->data_lock);
  2030. ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
  2031. rx_desc, sizeof(struct hal_rx_desc));
  2032. }
  2033. if (rx_status->band != NL80211_BAND_6GHZ)
  2034. rx_status->freq = ieee80211_channel_to_frequency(channel_num,
  2035. rx_status->band);
  2036. ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
  2037. }
  2038. static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
  2039. struct sk_buff *msdu,
  2040. struct ieee80211_rx_status *status)
  2041. {
  2042. static const struct ieee80211_radiotap_he known = {
  2043. .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
  2044. IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
  2045. .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
  2046. };
  2047. struct ieee80211_rx_status *rx_status;
  2048. struct ieee80211_radiotap_he *he = NULL;
  2049. struct ieee80211_sta *pubsta = NULL;
  2050. struct ath11k_peer *peer;
  2051. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
  2052. u8 decap = DP_RX_DECAP_TYPE_RAW;
  2053. bool is_mcbc = rxcb->is_mcbc;
  2054. bool is_eapol = rxcb->is_eapol;
  2055. if (status->encoding == RX_ENC_HE &&
  2056. !(status->flag & RX_FLAG_RADIOTAP_HE) &&
  2057. !(status->flag & RX_FLAG_SKIP_MONITOR)) {
  2058. he = skb_push(msdu, sizeof(known));
  2059. memcpy(he, &known, sizeof(known));
  2060. status->flag |= RX_FLAG_RADIOTAP_HE;
  2061. }
  2062. if (!(status->flag & RX_FLAG_ONLY_MONITOR))
  2063. decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
  2064. spin_lock_bh(&ar->ab->base_lock);
  2065. peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
  2066. if (peer && peer->sta)
  2067. pubsta = peer->sta;
  2068. spin_unlock_bh(&ar->ab->base_lock);
  2069. ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
  2070. "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
  2071. msdu,
  2072. msdu->len,
  2073. peer ? peer->addr : NULL,
  2074. rxcb->tid,
  2075. is_mcbc ? "mcast" : "ucast",
  2076. rxcb->seq_no,
  2077. (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
  2078. (status->encoding == RX_ENC_HT) ? "ht" : "",
  2079. (status->encoding == RX_ENC_VHT) ? "vht" : "",
  2080. (status->encoding == RX_ENC_HE) ? "he" : "",
  2081. (status->bw == RATE_INFO_BW_40) ? "40" : "",
  2082. (status->bw == RATE_INFO_BW_80) ? "80" : "",
  2083. (status->bw == RATE_INFO_BW_160) ? "160" : "",
  2084. status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
  2085. status->rate_idx,
  2086. status->nss,
  2087. status->freq,
  2088. status->band, status->flag,
  2089. !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
  2090. !!(status->flag & RX_FLAG_MMIC_ERROR),
  2091. !!(status->flag & RX_FLAG_AMSDU_MORE));
  2092. ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
  2093. msdu->data, msdu->len);
  2094. rx_status = IEEE80211_SKB_RXCB(msdu);
  2095. *rx_status = *status;
  2096. /* TODO: trace rx packet */
  2097. /* PN for multicast packets are not validate in HW,
  2098. * so skip 802.3 rx path
  2099. * Also, fast_rx expects the STA to be authorized, hence
  2100. * eapol packets are sent in slow path.
  2101. */
  2102. if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
  2103. !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
  2104. rx_status->flag |= RX_FLAG_8023;
  2105. ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
  2106. }
  2107. static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
  2108. struct sk_buff *msdu,
  2109. struct sk_buff_head *msdu_list,
  2110. struct ieee80211_rx_status *rx_status)
  2111. {
  2112. struct ath11k_base *ab = ar->ab;
  2113. struct hal_rx_desc *rx_desc, *lrx_desc;
  2114. struct rx_attention *rx_attention;
  2115. struct ath11k_skb_rxcb *rxcb;
  2116. struct sk_buff *last_buf;
  2117. u8 l3_pad_bytes;
  2118. u8 *hdr_status;
  2119. u16 msdu_len;
  2120. int ret;
  2121. u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
  2122. last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
  2123. if (!last_buf) {
  2124. ath11k_warn(ab,
  2125. "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
  2126. ret = -EIO;
  2127. goto free_out;
  2128. }
  2129. rx_desc = (struct hal_rx_desc *)msdu->data;
  2130. if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
  2131. ath11k_warn(ar->ab, "msdu len not valid\n");
  2132. ret = -EIO;
  2133. goto free_out;
  2134. }
  2135. lrx_desc = (struct hal_rx_desc *)last_buf->data;
  2136. rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
  2137. if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
  2138. ath11k_warn(ab, "msdu_done bit in attention is not set\n");
  2139. ret = -EIO;
  2140. goto free_out;
  2141. }
  2142. rxcb = ATH11K_SKB_RXCB(msdu);
  2143. rxcb->rx_desc = rx_desc;
  2144. msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
  2145. l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
  2146. if (rxcb->is_frag) {
  2147. skb_pull(msdu, hal_rx_desc_sz);
  2148. } else if (!rxcb->is_continuation) {
  2149. if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
  2150. hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
  2151. ret = -EINVAL;
  2152. ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
  2153. ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
  2154. sizeof(struct ieee80211_hdr));
  2155. ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
  2156. sizeof(struct hal_rx_desc));
  2157. goto free_out;
  2158. }
  2159. skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
  2160. skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
  2161. } else {
  2162. ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
  2163. msdu, last_buf,
  2164. l3_pad_bytes, msdu_len);
  2165. if (ret) {
  2166. ath11k_warn(ab,
  2167. "failed to coalesce msdu rx buffer%d\n", ret);
  2168. goto free_out;
  2169. }
  2170. }
  2171. ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
  2172. ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
  2173. rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
  2174. return 0;
  2175. free_out:
  2176. return ret;
  2177. }
  2178. static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
  2179. struct napi_struct *napi,
  2180. struct sk_buff_head *msdu_list,
  2181. int mac_id)
  2182. {
  2183. struct sk_buff *msdu;
  2184. struct ath11k *ar;
  2185. struct ieee80211_rx_status rx_status = {0};
  2186. int ret;
  2187. if (skb_queue_empty(msdu_list))
  2188. return;
  2189. if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) {
  2190. __skb_queue_purge(msdu_list);
  2191. return;
  2192. }
  2193. ar = ab->pdevs[mac_id].ar;
  2194. if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) {
  2195. __skb_queue_purge(msdu_list);
  2196. return;
  2197. }
  2198. while ((msdu = __skb_dequeue(msdu_list))) {
  2199. ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
  2200. if (unlikely(ret)) {
  2201. ath11k_dbg(ab, ATH11K_DBG_DATA,
  2202. "Unable to process msdu %d", ret);
  2203. dev_kfree_skb_any(msdu);
  2204. continue;
  2205. }
  2206. ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
  2207. }
  2208. }
  2209. int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
  2210. struct napi_struct *napi, int budget)
  2211. {
  2212. struct ath11k_dp *dp = &ab->dp;
  2213. struct dp_rxdma_ring *rx_ring;
  2214. int num_buffs_reaped[MAX_RADIOS] = {0};
  2215. struct sk_buff_head msdu_list[MAX_RADIOS];
  2216. struct ath11k_skb_rxcb *rxcb;
  2217. int total_msdu_reaped = 0;
  2218. struct hal_srng *srng;
  2219. struct sk_buff *msdu;
  2220. bool done = false;
  2221. int buf_id, mac_id;
  2222. struct ath11k *ar;
  2223. struct hal_reo_dest_ring *desc;
  2224. enum hal_reo_dest_ring_push_reason push_reason;
  2225. u32 cookie, info0, rx_msdu_info0, rx_mpdu_info0;
  2226. int i;
  2227. for (i = 0; i < MAX_RADIOS; i++)
  2228. __skb_queue_head_init(&msdu_list[i]);
  2229. srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
  2230. spin_lock_bh(&srng->lock);
  2231. try_again:
  2232. ath11k_hal_srng_access_begin(ab, srng);
  2233. while (likely(desc =
  2234. (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab,
  2235. srng))) {
  2236. cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
  2237. READ_ONCE(desc->buf_addr_info.info1));
  2238. buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
  2239. cookie);
  2240. mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
  2241. if (unlikely(buf_id == 0))
  2242. continue;
  2243. ar = ab->pdevs[mac_id].ar;
  2244. rx_ring = &ar->dp.rx_refill_buf_ring;
  2245. spin_lock_bh(&rx_ring->idr_lock);
  2246. msdu = idr_find(&rx_ring->bufs_idr, buf_id);
  2247. if (unlikely(!msdu)) {
  2248. ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
  2249. buf_id);
  2250. spin_unlock_bh(&rx_ring->idr_lock);
  2251. continue;
  2252. }
  2253. idr_remove(&rx_ring->bufs_idr, buf_id);
  2254. spin_unlock_bh(&rx_ring->idr_lock);
  2255. rxcb = ATH11K_SKB_RXCB(msdu);
  2256. dma_unmap_single(ab->dev, rxcb->paddr,
  2257. msdu->len + skb_tailroom(msdu),
  2258. DMA_FROM_DEVICE);
  2259. num_buffs_reaped[mac_id]++;
  2260. info0 = READ_ONCE(desc->info0);
  2261. push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
  2262. info0);
  2263. if (unlikely(push_reason !=
  2264. HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) {
  2265. dev_kfree_skb_any(msdu);
  2266. ab->soc_stats.hal_reo_error[ring_id]++;
  2267. continue;
  2268. }
  2269. rx_msdu_info0 = READ_ONCE(desc->rx_msdu_info.info0);
  2270. rx_mpdu_info0 = READ_ONCE(desc->rx_mpdu_info.info0);
  2271. rxcb->is_first_msdu = !!(rx_msdu_info0 &
  2272. RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
  2273. rxcb->is_last_msdu = !!(rx_msdu_info0 &
  2274. RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
  2275. rxcb->is_continuation = !!(rx_msdu_info0 &
  2276. RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
  2277. rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
  2278. READ_ONCE(desc->rx_mpdu_info.meta_data));
  2279. rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
  2280. rx_mpdu_info0);
  2281. rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
  2282. info0);
  2283. rxcb->mac_id = mac_id;
  2284. __skb_queue_tail(&msdu_list[mac_id], msdu);
  2285. if (rxcb->is_continuation) {
  2286. done = false;
  2287. } else {
  2288. total_msdu_reaped++;
  2289. done = true;
  2290. }
  2291. if (total_msdu_reaped >= budget)
  2292. break;
  2293. }
  2294. /* Hw might have updated the head pointer after we cached it.
  2295. * In this case, even though there are entries in the ring we'll
  2296. * get rx_desc NULL. Give the read another try with updated cached
  2297. * head pointer so that we can reap complete MPDU in the current
  2298. * rx processing.
  2299. */
  2300. if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) {
  2301. ath11k_hal_srng_access_end(ab, srng);
  2302. goto try_again;
  2303. }
  2304. ath11k_hal_srng_access_end(ab, srng);
  2305. spin_unlock_bh(&srng->lock);
  2306. if (unlikely(!total_msdu_reaped))
  2307. goto exit;
  2308. for (i = 0; i < ab->num_radios; i++) {
  2309. if (!num_buffs_reaped[i])
  2310. continue;
  2311. ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i);
  2312. ar = ab->pdevs[i].ar;
  2313. rx_ring = &ar->dp.rx_refill_buf_ring;
  2314. ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
  2315. ab->hw_params.hal_params->rx_buf_rbm);
  2316. }
  2317. exit:
  2318. return total_msdu_reaped;
  2319. }
  2320. static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
  2321. struct hal_rx_mon_ppdu_info *ppdu_info)
  2322. {
  2323. struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
  2324. u32 num_msdu;
  2325. int i;
  2326. if (!rx_stats)
  2327. return;
  2328. arsta->rssi_comb = ppdu_info->rssi_comb;
  2329. ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb);
  2330. num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
  2331. ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
  2332. rx_stats->num_msdu += num_msdu;
  2333. rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
  2334. ppdu_info->tcp_ack_msdu_count;
  2335. rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
  2336. rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
  2337. if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
  2338. ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
  2339. ppdu_info->nss = 1;
  2340. ppdu_info->mcs = HAL_RX_MAX_MCS;
  2341. ppdu_info->tid = IEEE80211_NUM_TIDS;
  2342. }
  2343. if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
  2344. rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
  2345. if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
  2346. rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
  2347. if (ppdu_info->gi < HAL_RX_GI_MAX)
  2348. rx_stats->gi_count[ppdu_info->gi] += num_msdu;
  2349. if (ppdu_info->bw < HAL_RX_BW_MAX)
  2350. rx_stats->bw_count[ppdu_info->bw] += num_msdu;
  2351. if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
  2352. rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
  2353. if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
  2354. rx_stats->tid_count[ppdu_info->tid] += num_msdu;
  2355. if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
  2356. rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
  2357. if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
  2358. rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
  2359. if (ppdu_info->is_stbc)
  2360. rx_stats->stbc_count += num_msdu;
  2361. if (ppdu_info->beamformed)
  2362. rx_stats->beamformed_count += num_msdu;
  2363. if (ppdu_info->num_mpdu_fcs_ok > 1)
  2364. rx_stats->ampdu_msdu_count += num_msdu;
  2365. else
  2366. rx_stats->non_ampdu_msdu_count += num_msdu;
  2367. rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
  2368. rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
  2369. rx_stats->dcm_count += ppdu_info->dcm;
  2370. rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
  2371. arsta->rssi_comb = ppdu_info->rssi_comb;
  2372. BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) >
  2373. ARRAY_SIZE(ppdu_info->rssi_chain_pri20));
  2374. for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++)
  2375. arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i];
  2376. rx_stats->rx_duration += ppdu_info->rx_duration;
  2377. arsta->rx_duration = rx_stats->rx_duration;
  2378. }
  2379. static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
  2380. struct dp_rxdma_ring *rx_ring,
  2381. int *buf_id)
  2382. {
  2383. struct sk_buff *skb;
  2384. dma_addr_t paddr;
  2385. skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
  2386. DP_RX_BUFFER_ALIGN_SIZE);
  2387. if (!skb)
  2388. goto fail_alloc_skb;
  2389. if (!IS_ALIGNED((unsigned long)skb->data,
  2390. DP_RX_BUFFER_ALIGN_SIZE)) {
  2391. skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
  2392. skb->data);
  2393. }
  2394. paddr = dma_map_single(ab->dev, skb->data,
  2395. skb->len + skb_tailroom(skb),
  2396. DMA_FROM_DEVICE);
  2397. if (unlikely(dma_mapping_error(ab->dev, paddr)))
  2398. goto fail_free_skb;
  2399. spin_lock_bh(&rx_ring->idr_lock);
  2400. *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
  2401. rx_ring->bufs_max, GFP_ATOMIC);
  2402. spin_unlock_bh(&rx_ring->idr_lock);
  2403. if (*buf_id < 0)
  2404. goto fail_dma_unmap;
  2405. ATH11K_SKB_RXCB(skb)->paddr = paddr;
  2406. return skb;
  2407. fail_dma_unmap:
  2408. dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
  2409. DMA_FROM_DEVICE);
  2410. fail_free_skb:
  2411. dev_kfree_skb_any(skb);
  2412. fail_alloc_skb:
  2413. return NULL;
  2414. }
  2415. int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
  2416. struct dp_rxdma_ring *rx_ring,
  2417. int req_entries,
  2418. enum hal_rx_buf_return_buf_manager mgr)
  2419. {
  2420. struct hal_srng *srng;
  2421. u32 *desc;
  2422. struct sk_buff *skb;
  2423. int num_free;
  2424. int num_remain;
  2425. int buf_id;
  2426. u32 cookie;
  2427. dma_addr_t paddr;
  2428. req_entries = min(req_entries, rx_ring->bufs_max);
  2429. srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
  2430. spin_lock_bh(&srng->lock);
  2431. ath11k_hal_srng_access_begin(ab, srng);
  2432. num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
  2433. req_entries = min(num_free, req_entries);
  2434. num_remain = req_entries;
  2435. while (num_remain > 0) {
  2436. skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
  2437. &buf_id);
  2438. if (!skb)
  2439. break;
  2440. paddr = ATH11K_SKB_RXCB(skb)->paddr;
  2441. desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
  2442. if (!desc)
  2443. goto fail_desc_get;
  2444. cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
  2445. FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
  2446. num_remain--;
  2447. ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
  2448. }
  2449. ath11k_hal_srng_access_end(ab, srng);
  2450. spin_unlock_bh(&srng->lock);
  2451. return req_entries - num_remain;
  2452. fail_desc_get:
  2453. spin_lock_bh(&rx_ring->idr_lock);
  2454. idr_remove(&rx_ring->bufs_idr, buf_id);
  2455. spin_unlock_bh(&rx_ring->idr_lock);
  2456. dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
  2457. DMA_FROM_DEVICE);
  2458. dev_kfree_skb_any(skb);
  2459. ath11k_hal_srng_access_end(ab, srng);
  2460. spin_unlock_bh(&srng->lock);
  2461. return req_entries - num_remain;
  2462. }
  2463. #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535
  2464. static void
  2465. ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon,
  2466. struct hal_tlv_hdr *tlv)
  2467. {
  2468. struct hal_rx_ppdu_start *ppdu_start;
  2469. u16 ppdu_id_diff, ppdu_id, tlv_len;
  2470. u8 *ptr;
  2471. /* PPDU id is part of second tlv, move ptr to second tlv */
  2472. tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
  2473. ptr = (u8 *)tlv;
  2474. ptr += sizeof(*tlv) + tlv_len;
  2475. tlv = (struct hal_tlv_hdr *)ptr;
  2476. if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START)
  2477. return;
  2478. ptr += sizeof(*tlv);
  2479. ppdu_start = (struct hal_rx_ppdu_start *)ptr;
  2480. ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
  2481. __le32_to_cpu(ppdu_start->info0));
  2482. if (pmon->sw_mon_entries.ppdu_id < ppdu_id) {
  2483. pmon->buf_state = DP_MON_STATUS_LEAD;
  2484. ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id;
  2485. if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
  2486. pmon->buf_state = DP_MON_STATUS_LAG;
  2487. } else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) {
  2488. pmon->buf_state = DP_MON_STATUS_LAG;
  2489. ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id;
  2490. if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
  2491. pmon->buf_state = DP_MON_STATUS_LEAD;
  2492. }
  2493. }
  2494. static enum dp_mon_status_buf_state
  2495. ath11k_dp_rx_mon_buf_done(struct ath11k_base *ab, struct hal_srng *srng,
  2496. struct dp_rxdma_ring *rx_ring)
  2497. {
  2498. struct ath11k_skb_rxcb *rxcb;
  2499. struct hal_tlv_hdr *tlv;
  2500. struct sk_buff *skb;
  2501. void *status_desc;
  2502. dma_addr_t paddr;
  2503. u32 cookie;
  2504. int buf_id;
  2505. u8 rbm;
  2506. status_desc = ath11k_hal_srng_src_next_peek(ab, srng);
  2507. if (!status_desc)
  2508. return DP_MON_STATUS_NO_DMA;
  2509. ath11k_hal_rx_buf_addr_info_get(status_desc, &paddr, &cookie, &rbm);
  2510. buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
  2511. spin_lock_bh(&rx_ring->idr_lock);
  2512. skb = idr_find(&rx_ring->bufs_idr, buf_id);
  2513. spin_unlock_bh(&rx_ring->idr_lock);
  2514. if (!skb)
  2515. return DP_MON_STATUS_NO_DMA;
  2516. rxcb = ATH11K_SKB_RXCB(skb);
  2517. dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
  2518. skb->len + skb_tailroom(skb),
  2519. DMA_FROM_DEVICE);
  2520. tlv = (struct hal_tlv_hdr *)skb->data;
  2521. if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_STATUS_BUFFER_DONE)
  2522. return DP_MON_STATUS_NO_DMA;
  2523. return DP_MON_STATUS_REPLINISH;
  2524. }
  2525. static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
  2526. int *budget, struct sk_buff_head *skb_list)
  2527. {
  2528. struct ath11k *ar;
  2529. const struct ath11k_hw_hal_params *hal_params;
  2530. enum dp_mon_status_buf_state reap_status;
  2531. struct ath11k_pdev_dp *dp;
  2532. struct dp_rxdma_ring *rx_ring;
  2533. struct ath11k_mon_data *pmon;
  2534. struct hal_srng *srng;
  2535. void *rx_mon_status_desc;
  2536. struct sk_buff *skb;
  2537. struct ath11k_skb_rxcb *rxcb;
  2538. struct hal_tlv_hdr *tlv;
  2539. u32 cookie;
  2540. int buf_id, srng_id;
  2541. dma_addr_t paddr;
  2542. u8 rbm;
  2543. int num_buffs_reaped = 0;
  2544. ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
  2545. dp = &ar->dp;
  2546. pmon = &dp->mon_data;
  2547. srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
  2548. rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
  2549. srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
  2550. spin_lock_bh(&srng->lock);
  2551. ath11k_hal_srng_access_begin(ab, srng);
  2552. while (*budget) {
  2553. *budget -= 1;
  2554. rx_mon_status_desc =
  2555. ath11k_hal_srng_src_peek(ab, srng);
  2556. if (!rx_mon_status_desc) {
  2557. pmon->buf_state = DP_MON_STATUS_REPLINISH;
  2558. break;
  2559. }
  2560. ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
  2561. &cookie, &rbm);
  2562. if (paddr) {
  2563. buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
  2564. spin_lock_bh(&rx_ring->idr_lock);
  2565. skb = idr_find(&rx_ring->bufs_idr, buf_id);
  2566. spin_unlock_bh(&rx_ring->idr_lock);
  2567. if (!skb) {
  2568. ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
  2569. buf_id);
  2570. pmon->buf_state = DP_MON_STATUS_REPLINISH;
  2571. goto move_next;
  2572. }
  2573. rxcb = ATH11K_SKB_RXCB(skb);
  2574. dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
  2575. skb->len + skb_tailroom(skb),
  2576. DMA_FROM_DEVICE);
  2577. tlv = (struct hal_tlv_hdr *)skb->data;
  2578. if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
  2579. HAL_RX_STATUS_BUFFER_DONE) {
  2580. ath11k_warn(ab, "mon status DONE not set %lx, buf_id %d\n",
  2581. FIELD_GET(HAL_TLV_HDR_TAG,
  2582. tlv->tl), buf_id);
  2583. /* RxDMA status done bit might not be set even
  2584. * though tp is moved by HW.
  2585. */
  2586. /* If done status is missing:
  2587. * 1. As per MAC team's suggestion,
  2588. * when HP + 1 entry is peeked and if DMA
  2589. * is not done and if HP + 2 entry's DMA done
  2590. * is set. skip HP + 1 entry and
  2591. * start processing in next interrupt.
  2592. * 2. If HP + 2 entry's DMA done is not set,
  2593. * poll onto HP + 1 entry DMA done to be set.
  2594. * Check status for same buffer for next time
  2595. * dp_rx_mon_status_srng_process
  2596. */
  2597. reap_status = ath11k_dp_rx_mon_buf_done(ab, srng,
  2598. rx_ring);
  2599. if (reap_status == DP_MON_STATUS_NO_DMA)
  2600. continue;
  2601. spin_lock_bh(&rx_ring->idr_lock);
  2602. idr_remove(&rx_ring->bufs_idr, buf_id);
  2603. spin_unlock_bh(&rx_ring->idr_lock);
  2604. dma_unmap_single(ab->dev, rxcb->paddr,
  2605. skb->len + skb_tailroom(skb),
  2606. DMA_FROM_DEVICE);
  2607. dev_kfree_skb_any(skb);
  2608. pmon->buf_state = DP_MON_STATUS_REPLINISH;
  2609. goto move_next;
  2610. }
  2611. spin_lock_bh(&rx_ring->idr_lock);
  2612. idr_remove(&rx_ring->bufs_idr, buf_id);
  2613. spin_unlock_bh(&rx_ring->idr_lock);
  2614. if (ab->hw_params.full_monitor_mode) {
  2615. ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv);
  2616. if (paddr == pmon->mon_status_paddr)
  2617. pmon->buf_state = DP_MON_STATUS_MATCH;
  2618. }
  2619. dma_unmap_single(ab->dev, rxcb->paddr,
  2620. skb->len + skb_tailroom(skb),
  2621. DMA_FROM_DEVICE);
  2622. __skb_queue_tail(skb_list, skb);
  2623. } else {
  2624. pmon->buf_state = DP_MON_STATUS_REPLINISH;
  2625. }
  2626. move_next:
  2627. skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
  2628. &buf_id);
  2629. if (!skb) {
  2630. hal_params = ab->hw_params.hal_params;
  2631. ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
  2632. hal_params->rx_buf_rbm);
  2633. num_buffs_reaped++;
  2634. break;
  2635. }
  2636. rxcb = ATH11K_SKB_RXCB(skb);
  2637. cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
  2638. FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
  2639. ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
  2640. cookie,
  2641. ab->hw_params.hal_params->rx_buf_rbm);
  2642. ath11k_hal_srng_src_get_next_entry(ab, srng);
  2643. num_buffs_reaped++;
  2644. }
  2645. ath11k_hal_srng_access_end(ab, srng);
  2646. spin_unlock_bh(&srng->lock);
  2647. return num_buffs_reaped;
  2648. }
  2649. static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
  2650. {
  2651. struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
  2652. spin_lock_bh(&rx_tid->ab->base_lock);
  2653. if (rx_tid->last_frag_no &&
  2654. rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
  2655. spin_unlock_bh(&rx_tid->ab->base_lock);
  2656. return;
  2657. }
  2658. ath11k_dp_rx_frags_cleanup(rx_tid, true);
  2659. spin_unlock_bh(&rx_tid->ab->base_lock);
  2660. }
  2661. int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
  2662. {
  2663. struct ath11k_base *ab = ar->ab;
  2664. struct crypto_shash *tfm;
  2665. struct ath11k_peer *peer;
  2666. struct dp_rx_tid *rx_tid;
  2667. int i;
  2668. tfm = crypto_alloc_shash("michael_mic", 0, 0);
  2669. if (IS_ERR(tfm)) {
  2670. ath11k_warn(ab, "failed to allocate michael_mic shash: %ld\n",
  2671. PTR_ERR(tfm));
  2672. return PTR_ERR(tfm);
  2673. }
  2674. spin_lock_bh(&ab->base_lock);
  2675. peer = ath11k_peer_find(ab, vdev_id, peer_mac);
  2676. if (!peer) {
  2677. ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
  2678. spin_unlock_bh(&ab->base_lock);
  2679. crypto_free_shash(tfm);
  2680. return -ENOENT;
  2681. }
  2682. for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
  2683. rx_tid = &peer->rx_tid[i];
  2684. rx_tid->ab = ab;
  2685. timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
  2686. skb_queue_head_init(&rx_tid->rx_frags);
  2687. }
  2688. peer->tfm_mmic = tfm;
  2689. peer->dp_setup_done = true;
  2690. spin_unlock_bh(&ab->base_lock);
  2691. return 0;
  2692. }
  2693. static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
  2694. struct ieee80211_hdr *hdr, u8 *data,
  2695. size_t data_len, u8 *mic)
  2696. {
  2697. SHASH_DESC_ON_STACK(desc, tfm);
  2698. u8 mic_hdr[16] = {0};
  2699. u8 tid = 0;
  2700. int ret;
  2701. if (!tfm)
  2702. return -EINVAL;
  2703. desc->tfm = tfm;
  2704. ret = crypto_shash_setkey(tfm, key, 8);
  2705. if (ret)
  2706. goto out;
  2707. ret = crypto_shash_init(desc);
  2708. if (ret)
  2709. goto out;
  2710. /* TKIP MIC header */
  2711. memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
  2712. memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
  2713. if (ieee80211_is_data_qos(hdr->frame_control))
  2714. tid = ieee80211_get_tid(hdr);
  2715. mic_hdr[12] = tid;
  2716. ret = crypto_shash_update(desc, mic_hdr, 16);
  2717. if (ret)
  2718. goto out;
  2719. ret = crypto_shash_update(desc, data, data_len);
  2720. if (ret)
  2721. goto out;
  2722. ret = crypto_shash_final(desc, mic);
  2723. out:
  2724. shash_desc_zero(desc);
  2725. return ret;
  2726. }
  2727. static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
  2728. struct sk_buff *msdu)
  2729. {
  2730. struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
  2731. struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
  2732. struct ieee80211_key_conf *key_conf;
  2733. struct ieee80211_hdr *hdr;
  2734. u8 mic[IEEE80211_CCMP_MIC_LEN];
  2735. int head_len, tail_len, ret;
  2736. size_t data_len;
  2737. u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
  2738. u8 *key, *data;
  2739. u8 key_idx;
  2740. if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
  2741. HAL_ENCRYPT_TYPE_TKIP_MIC)
  2742. return 0;
  2743. hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
  2744. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  2745. head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
  2746. tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
  2747. if (!is_multicast_ether_addr(hdr->addr1))
  2748. key_idx = peer->ucast_keyidx;
  2749. else
  2750. key_idx = peer->mcast_keyidx;
  2751. key_conf = peer->keys[key_idx];
  2752. data = msdu->data + head_len;
  2753. data_len = msdu->len - head_len - tail_len;
  2754. key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
  2755. ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
  2756. if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
  2757. goto mic_fail;
  2758. return 0;
  2759. mic_fail:
  2760. (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
  2761. (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
  2762. rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
  2763. RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
  2764. skb_pull(msdu, hal_rx_desc_sz);
  2765. ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
  2766. ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
  2767. HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
  2768. ieee80211_rx(ar->hw, msdu);
  2769. return -EINVAL;
  2770. }
  2771. static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
  2772. enum hal_encrypt_type enctype, u32 flags)
  2773. {
  2774. struct ieee80211_hdr *hdr;
  2775. size_t hdr_len;
  2776. size_t crypto_len;
  2777. u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
  2778. if (!flags)
  2779. return;
  2780. hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
  2781. if (flags & RX_FLAG_MIC_STRIPPED)
  2782. skb_trim(msdu, msdu->len -
  2783. ath11k_dp_rx_crypto_mic_len(ar, enctype));
  2784. if (flags & RX_FLAG_ICV_STRIPPED)
  2785. skb_trim(msdu, msdu->len -
  2786. ath11k_dp_rx_crypto_icv_len(ar, enctype));
  2787. if (flags & RX_FLAG_IV_STRIPPED) {
  2788. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  2789. crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
  2790. memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
  2791. (void *)msdu->data + hal_rx_desc_sz, hdr_len);
  2792. skb_pull(msdu, crypto_len);
  2793. }
  2794. }
  2795. static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
  2796. struct ath11k_peer *peer,
  2797. struct dp_rx_tid *rx_tid,
  2798. struct sk_buff **defrag_skb)
  2799. {
  2800. struct hal_rx_desc *rx_desc;
  2801. struct sk_buff *skb, *first_frag, *last_frag;
  2802. struct ieee80211_hdr *hdr;
  2803. struct rx_attention *rx_attention;
  2804. enum hal_encrypt_type enctype;
  2805. bool is_decrypted = false;
  2806. int msdu_len = 0;
  2807. int extra_space;
  2808. u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
  2809. first_frag = skb_peek(&rx_tid->rx_frags);
  2810. last_frag = skb_peek_tail(&rx_tid->rx_frags);
  2811. skb_queue_walk(&rx_tid->rx_frags, skb) {
  2812. flags = 0;
  2813. rx_desc = (struct hal_rx_desc *)skb->data;
  2814. hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
  2815. enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
  2816. if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
  2817. rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
  2818. is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
  2819. }
  2820. if (is_decrypted) {
  2821. if (skb != first_frag)
  2822. flags |= RX_FLAG_IV_STRIPPED;
  2823. if (skb != last_frag)
  2824. flags |= RX_FLAG_ICV_STRIPPED |
  2825. RX_FLAG_MIC_STRIPPED;
  2826. }
  2827. /* RX fragments are always raw packets */
  2828. if (skb != last_frag)
  2829. skb_trim(skb, skb->len - FCS_LEN);
  2830. ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
  2831. if (skb != first_frag)
  2832. skb_pull(skb, hal_rx_desc_sz +
  2833. ieee80211_hdrlen(hdr->frame_control));
  2834. msdu_len += skb->len;
  2835. }
  2836. extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
  2837. if (extra_space > 0 &&
  2838. (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
  2839. return -ENOMEM;
  2840. __skb_unlink(first_frag, &rx_tid->rx_frags);
  2841. while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
  2842. skb_put_data(first_frag, skb->data, skb->len);
  2843. dev_kfree_skb_any(skb);
  2844. }
  2845. hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
  2846. hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
  2847. ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
  2848. if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
  2849. first_frag = NULL;
  2850. *defrag_skb = first_frag;
  2851. return 0;
  2852. }
  2853. static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
  2854. struct sk_buff *defrag_skb)
  2855. {
  2856. struct ath11k_base *ab = ar->ab;
  2857. struct ath11k_pdev_dp *dp = &ar->dp;
  2858. struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
  2859. struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
  2860. struct hal_reo_entrance_ring *reo_ent_ring;
  2861. struct hal_reo_dest_ring *reo_dest_ring;
  2862. struct dp_link_desc_bank *link_desc_banks;
  2863. struct hal_rx_msdu_link *msdu_link;
  2864. struct hal_rx_msdu_details *msdu0;
  2865. struct hal_srng *srng;
  2866. dma_addr_t paddr;
  2867. u32 desc_bank, msdu_info, mpdu_info;
  2868. u32 dst_idx, cookie, hal_rx_desc_sz;
  2869. int ret, buf_id;
  2870. hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
  2871. link_desc_banks = ab->dp.link_desc_banks;
  2872. reo_dest_ring = rx_tid->dst_ring_desc;
  2873. ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
  2874. msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
  2875. (paddr - link_desc_banks[desc_bank].paddr));
  2876. msdu0 = &msdu_link->msdu_link[0];
  2877. dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
  2878. memset(msdu0, 0, sizeof(*msdu0));
  2879. msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
  2880. FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
  2881. FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
  2882. FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
  2883. defrag_skb->len - hal_rx_desc_sz) |
  2884. FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
  2885. FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
  2886. FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
  2887. msdu0->rx_msdu_info.info0 = msdu_info;
  2888. /* change msdu len in hal rx desc */
  2889. ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
  2890. paddr = dma_map_single(ab->dev, defrag_skb->data,
  2891. defrag_skb->len + skb_tailroom(defrag_skb),
  2892. DMA_TO_DEVICE);
  2893. if (dma_mapping_error(ab->dev, paddr))
  2894. return -ENOMEM;
  2895. spin_lock_bh(&rx_refill_ring->idr_lock);
  2896. buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
  2897. rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
  2898. spin_unlock_bh(&rx_refill_ring->idr_lock);
  2899. if (buf_id < 0) {
  2900. ret = -ENOMEM;
  2901. goto err_unmap_dma;
  2902. }
  2903. ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
  2904. cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
  2905. FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
  2906. ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
  2907. ab->hw_params.hal_params->rx_buf_rbm);
  2908. /* Fill mpdu details into reo entrance ring */
  2909. srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
  2910. spin_lock_bh(&srng->lock);
  2911. ath11k_hal_srng_access_begin(ab, srng);
  2912. reo_ent_ring = (struct hal_reo_entrance_ring *)
  2913. ath11k_hal_srng_src_get_next_entry(ab, srng);
  2914. if (!reo_ent_ring) {
  2915. ath11k_hal_srng_access_end(ab, srng);
  2916. spin_unlock_bh(&srng->lock);
  2917. ret = -ENOSPC;
  2918. goto err_free_idr;
  2919. }
  2920. memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
  2921. ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
  2922. ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
  2923. HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
  2924. mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
  2925. FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
  2926. FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
  2927. FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
  2928. FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
  2929. FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
  2930. FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
  2931. reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
  2932. reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
  2933. reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
  2934. reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
  2935. FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
  2936. reo_dest_ring->info0)) |
  2937. FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
  2938. ath11k_hal_srng_access_end(ab, srng);
  2939. spin_unlock_bh(&srng->lock);
  2940. return 0;
  2941. err_free_idr:
  2942. spin_lock_bh(&rx_refill_ring->idr_lock);
  2943. idr_remove(&rx_refill_ring->bufs_idr, buf_id);
  2944. spin_unlock_bh(&rx_refill_ring->idr_lock);
  2945. err_unmap_dma:
  2946. dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
  2947. DMA_TO_DEVICE);
  2948. return ret;
  2949. }
  2950. static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
  2951. struct sk_buff *a, struct sk_buff *b)
  2952. {
  2953. int frag1, frag2;
  2954. frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
  2955. frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
  2956. return frag1 - frag2;
  2957. }
  2958. static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
  2959. struct sk_buff_head *frag_list,
  2960. struct sk_buff *cur_frag)
  2961. {
  2962. struct sk_buff *skb;
  2963. int cmp;
  2964. skb_queue_walk(frag_list, skb) {
  2965. cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
  2966. if (cmp < 0)
  2967. continue;
  2968. __skb_queue_before(frag_list, skb, cur_frag);
  2969. return;
  2970. }
  2971. __skb_queue_tail(frag_list, cur_frag);
  2972. }
  2973. static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
  2974. {
  2975. struct ieee80211_hdr *hdr;
  2976. u64 pn = 0;
  2977. u8 *ehdr;
  2978. u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
  2979. hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
  2980. ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
  2981. pn = ehdr[0];
  2982. pn |= (u64)ehdr[1] << 8;
  2983. pn |= (u64)ehdr[4] << 16;
  2984. pn |= (u64)ehdr[5] << 24;
  2985. pn |= (u64)ehdr[6] << 32;
  2986. pn |= (u64)ehdr[7] << 40;
  2987. return pn;
  2988. }
  2989. static bool
  2990. ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
  2991. {
  2992. enum hal_encrypt_type encrypt_type;
  2993. struct sk_buff *first_frag, *skb;
  2994. struct hal_rx_desc *desc;
  2995. u64 last_pn;
  2996. u64 cur_pn;
  2997. first_frag = skb_peek(&rx_tid->rx_frags);
  2998. desc = (struct hal_rx_desc *)first_frag->data;
  2999. encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
  3000. if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
  3001. encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
  3002. encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
  3003. encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
  3004. return true;
  3005. last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
  3006. skb_queue_walk(&rx_tid->rx_frags, skb) {
  3007. if (skb == first_frag)
  3008. continue;
  3009. cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
  3010. if (cur_pn != last_pn + 1)
  3011. return false;
  3012. last_pn = cur_pn;
  3013. }
  3014. return true;
  3015. }
  3016. static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
  3017. struct sk_buff *msdu,
  3018. u32 *ring_desc)
  3019. {
  3020. struct ath11k_base *ab = ar->ab;
  3021. struct hal_rx_desc *rx_desc;
  3022. struct ath11k_peer *peer;
  3023. struct dp_rx_tid *rx_tid;
  3024. struct sk_buff *defrag_skb = NULL;
  3025. u32 peer_id;
  3026. u16 seqno, frag_no;
  3027. u8 tid;
  3028. int ret = 0;
  3029. bool more_frags;
  3030. bool is_mcbc;
  3031. rx_desc = (struct hal_rx_desc *)msdu->data;
  3032. peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
  3033. tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
  3034. seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
  3035. frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
  3036. more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
  3037. is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
  3038. /* Multicast/Broadcast fragments are not expected */
  3039. if (is_mcbc)
  3040. return -EINVAL;
  3041. if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
  3042. !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
  3043. tid > IEEE80211_NUM_TIDS)
  3044. return -EINVAL;
  3045. /* received unfragmented packet in reo
  3046. * exception ring, this shouldn't happen
  3047. * as these packets typically come from
  3048. * reo2sw srngs.
  3049. */
  3050. if (WARN_ON_ONCE(!frag_no && !more_frags))
  3051. return -EINVAL;
  3052. spin_lock_bh(&ab->base_lock);
  3053. peer = ath11k_peer_find_by_id(ab, peer_id);
  3054. if (!peer) {
  3055. ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
  3056. peer_id);
  3057. ret = -ENOENT;
  3058. goto out_unlock;
  3059. }
  3060. if (!peer->dp_setup_done) {
  3061. ath11k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
  3062. peer->addr, peer_id);
  3063. ret = -ENOENT;
  3064. goto out_unlock;
  3065. }
  3066. rx_tid = &peer->rx_tid[tid];
  3067. if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
  3068. skb_queue_empty(&rx_tid->rx_frags)) {
  3069. /* Flush stored fragments and start a new sequence */
  3070. ath11k_dp_rx_frags_cleanup(rx_tid, true);
  3071. rx_tid->cur_sn = seqno;
  3072. }
  3073. if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
  3074. /* Fragment already present */
  3075. ret = -EINVAL;
  3076. goto out_unlock;
  3077. }
  3078. if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap)))
  3079. __skb_queue_tail(&rx_tid->rx_frags, msdu);
  3080. else
  3081. ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
  3082. rx_tid->rx_frag_bitmap |= BIT(frag_no);
  3083. if (!more_frags)
  3084. rx_tid->last_frag_no = frag_no;
  3085. if (frag_no == 0) {
  3086. rx_tid->dst_ring_desc = kmemdup(ring_desc,
  3087. sizeof(*rx_tid->dst_ring_desc),
  3088. GFP_ATOMIC);
  3089. if (!rx_tid->dst_ring_desc) {
  3090. ret = -ENOMEM;
  3091. goto out_unlock;
  3092. }
  3093. } else {
  3094. ath11k_dp_rx_link_desc_return(ab, ring_desc,
  3095. HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
  3096. }
  3097. if (!rx_tid->last_frag_no ||
  3098. rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
  3099. mod_timer(&rx_tid->frag_timer, jiffies +
  3100. ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
  3101. goto out_unlock;
  3102. }
  3103. spin_unlock_bh(&ab->base_lock);
  3104. del_timer_sync(&rx_tid->frag_timer);
  3105. spin_lock_bh(&ab->base_lock);
  3106. peer = ath11k_peer_find_by_id(ab, peer_id);
  3107. if (!peer)
  3108. goto err_frags_cleanup;
  3109. if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
  3110. goto err_frags_cleanup;
  3111. if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
  3112. goto err_frags_cleanup;
  3113. if (!defrag_skb)
  3114. goto err_frags_cleanup;
  3115. if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
  3116. goto err_frags_cleanup;
  3117. ath11k_dp_rx_frags_cleanup(rx_tid, false);
  3118. goto out_unlock;
  3119. err_frags_cleanup:
  3120. dev_kfree_skb_any(defrag_skb);
  3121. ath11k_dp_rx_frags_cleanup(rx_tid, true);
  3122. out_unlock:
  3123. spin_unlock_bh(&ab->base_lock);
  3124. return ret;
  3125. }
  3126. static int
  3127. ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
  3128. {
  3129. struct ath11k_pdev_dp *dp = &ar->dp;
  3130. struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
  3131. struct sk_buff *msdu;
  3132. struct ath11k_skb_rxcb *rxcb;
  3133. struct hal_rx_desc *rx_desc;
  3134. u8 *hdr_status;
  3135. u16 msdu_len;
  3136. u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
  3137. spin_lock_bh(&rx_ring->idr_lock);
  3138. msdu = idr_find(&rx_ring->bufs_idr, buf_id);
  3139. if (!msdu) {
  3140. ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
  3141. buf_id);
  3142. spin_unlock_bh(&rx_ring->idr_lock);
  3143. return -EINVAL;
  3144. }
  3145. idr_remove(&rx_ring->bufs_idr, buf_id);
  3146. spin_unlock_bh(&rx_ring->idr_lock);
  3147. rxcb = ATH11K_SKB_RXCB(msdu);
  3148. dma_unmap_single(ar->ab->dev, rxcb->paddr,
  3149. msdu->len + skb_tailroom(msdu),
  3150. DMA_FROM_DEVICE);
  3151. if (drop) {
  3152. dev_kfree_skb_any(msdu);
  3153. return 0;
  3154. }
  3155. rcu_read_lock();
  3156. if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
  3157. dev_kfree_skb_any(msdu);
  3158. goto exit;
  3159. }
  3160. if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
  3161. dev_kfree_skb_any(msdu);
  3162. goto exit;
  3163. }
  3164. rx_desc = (struct hal_rx_desc *)msdu->data;
  3165. msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
  3166. if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
  3167. hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
  3168. ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
  3169. ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
  3170. sizeof(struct ieee80211_hdr));
  3171. ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
  3172. sizeof(struct hal_rx_desc));
  3173. dev_kfree_skb_any(msdu);
  3174. goto exit;
  3175. }
  3176. skb_put(msdu, hal_rx_desc_sz + msdu_len);
  3177. if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
  3178. dev_kfree_skb_any(msdu);
  3179. ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
  3180. HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
  3181. }
  3182. exit:
  3183. rcu_read_unlock();
  3184. return 0;
  3185. }
  3186. int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
  3187. int budget)
  3188. {
  3189. u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
  3190. struct dp_link_desc_bank *link_desc_banks;
  3191. enum hal_rx_buf_return_buf_manager rbm;
  3192. int tot_n_bufs_reaped, quota, ret, i;
  3193. int n_bufs_reaped[MAX_RADIOS] = {0};
  3194. struct dp_rxdma_ring *rx_ring;
  3195. struct dp_srng *reo_except;
  3196. u32 desc_bank, num_msdus;
  3197. struct hal_srng *srng;
  3198. struct ath11k_dp *dp;
  3199. void *link_desc_va;
  3200. int buf_id, mac_id;
  3201. struct ath11k *ar;
  3202. dma_addr_t paddr;
  3203. u32 *desc;
  3204. bool is_frag;
  3205. u8 drop = 0;
  3206. tot_n_bufs_reaped = 0;
  3207. quota = budget;
  3208. dp = &ab->dp;
  3209. reo_except = &dp->reo_except_ring;
  3210. link_desc_banks = dp->link_desc_banks;
  3211. srng = &ab->hal.srng_list[reo_except->ring_id];
  3212. spin_lock_bh(&srng->lock);
  3213. ath11k_hal_srng_access_begin(ab, srng);
  3214. while (budget &&
  3215. (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
  3216. struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
  3217. ab->soc_stats.err_ring_pkts++;
  3218. ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
  3219. &desc_bank);
  3220. if (ret) {
  3221. ath11k_warn(ab, "failed to parse error reo desc %d\n",
  3222. ret);
  3223. continue;
  3224. }
  3225. link_desc_va = link_desc_banks[desc_bank].vaddr +
  3226. (paddr - link_desc_banks[desc_bank].paddr);
  3227. ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
  3228. &rbm);
  3229. if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
  3230. rbm != HAL_RX_BUF_RBM_SW1_BM &&
  3231. rbm != HAL_RX_BUF_RBM_SW3_BM) {
  3232. ab->soc_stats.invalid_rbm++;
  3233. ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
  3234. ath11k_dp_rx_link_desc_return(ab, desc,
  3235. HAL_WBM_REL_BM_ACT_REL_MSDU);
  3236. continue;
  3237. }
  3238. is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
  3239. /* Process only rx fragments with one msdu per link desc below, and drop
  3240. * msdu's indicated due to error reasons.
  3241. */
  3242. if (!is_frag || num_msdus > 1) {
  3243. drop = 1;
  3244. /* Return the link desc back to wbm idle list */
  3245. ath11k_dp_rx_link_desc_return(ab, desc,
  3246. HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
  3247. }
  3248. for (i = 0; i < num_msdus; i++) {
  3249. buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
  3250. msdu_cookies[i]);
  3251. mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
  3252. msdu_cookies[i]);
  3253. ar = ab->pdevs[mac_id].ar;
  3254. if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
  3255. n_bufs_reaped[mac_id]++;
  3256. tot_n_bufs_reaped++;
  3257. }
  3258. }
  3259. if (tot_n_bufs_reaped >= quota) {
  3260. tot_n_bufs_reaped = quota;
  3261. goto exit;
  3262. }
  3263. budget = quota - tot_n_bufs_reaped;
  3264. }
  3265. exit:
  3266. ath11k_hal_srng_access_end(ab, srng);
  3267. spin_unlock_bh(&srng->lock);
  3268. for (i = 0; i < ab->num_radios; i++) {
  3269. if (!n_bufs_reaped[i])
  3270. continue;
  3271. ar = ab->pdevs[i].ar;
  3272. rx_ring = &ar->dp.rx_refill_buf_ring;
  3273. ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
  3274. ab->hw_params.hal_params->rx_buf_rbm);
  3275. }
  3276. return tot_n_bufs_reaped;
  3277. }
  3278. static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
  3279. int msdu_len,
  3280. struct sk_buff_head *msdu_list)
  3281. {
  3282. struct sk_buff *skb, *tmp;
  3283. struct ath11k_skb_rxcb *rxcb;
  3284. int n_buffs;
  3285. n_buffs = DIV_ROUND_UP(msdu_len,
  3286. (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
  3287. skb_queue_walk_safe(msdu_list, skb, tmp) {
  3288. rxcb = ATH11K_SKB_RXCB(skb);
  3289. if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
  3290. rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
  3291. if (!n_buffs)
  3292. break;
  3293. __skb_unlink(skb, msdu_list);
  3294. dev_kfree_skb_any(skb);
  3295. n_buffs--;
  3296. }
  3297. }
  3298. }
  3299. static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
  3300. struct ieee80211_rx_status *status,
  3301. struct sk_buff_head *msdu_list)
  3302. {
  3303. u16 msdu_len;
  3304. struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
  3305. struct rx_attention *rx_attention;
  3306. u8 l3pad_bytes;
  3307. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
  3308. u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
  3309. msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
  3310. if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
  3311. /* First buffer will be freed by the caller, so deduct it's length */
  3312. msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
  3313. ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
  3314. return -EINVAL;
  3315. }
  3316. rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
  3317. if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
  3318. ath11k_warn(ar->ab,
  3319. "msdu_done bit not set in null_q_des processing\n");
  3320. __skb_queue_purge(msdu_list);
  3321. return -EIO;
  3322. }
  3323. /* Handle NULL queue descriptor violations arising out a missing
  3324. * REO queue for a given peer or a given TID. This typically
  3325. * may happen if a packet is received on a QOS enabled TID before the
  3326. * ADDBA negotiation for that TID, when the TID queue is setup. Or
  3327. * it may also happen for MC/BC frames if they are not routed to the
  3328. * non-QOS TID queue, in the absence of any other default TID queue.
  3329. * This error can show up both in a REO destination or WBM release ring.
  3330. */
  3331. rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
  3332. rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
  3333. if (rxcb->is_frag) {
  3334. skb_pull(msdu, hal_rx_desc_sz);
  3335. } else {
  3336. l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
  3337. if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
  3338. return -EINVAL;
  3339. skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
  3340. skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
  3341. }
  3342. ath11k_dp_rx_h_ppdu(ar, desc, status);
  3343. ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
  3344. rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
  3345. /* Please note that caller will having the access to msdu and completing
  3346. * rx with mac80211. Need not worry about cleaning up amsdu_list.
  3347. */
  3348. return 0;
  3349. }
  3350. static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
  3351. struct ieee80211_rx_status *status,
  3352. struct sk_buff_head *msdu_list)
  3353. {
  3354. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
  3355. bool drop = false;
  3356. ar->ab->soc_stats.reo_error[rxcb->err_code]++;
  3357. switch (rxcb->err_code) {
  3358. case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
  3359. if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
  3360. drop = true;
  3361. break;
  3362. case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
  3363. /* TODO: Do not drop PN failed packets in the driver;
  3364. * instead, it is good to drop such packets in mac80211
  3365. * after incrementing the replay counters.
  3366. */
  3367. fallthrough;
  3368. default:
  3369. /* TODO: Review other errors and process them to mac80211
  3370. * as appropriate.
  3371. */
  3372. drop = true;
  3373. break;
  3374. }
  3375. return drop;
  3376. }
  3377. static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
  3378. struct ieee80211_rx_status *status)
  3379. {
  3380. u16 msdu_len;
  3381. struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
  3382. u8 l3pad_bytes;
  3383. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
  3384. u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
  3385. rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
  3386. rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
  3387. l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
  3388. msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
  3389. skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
  3390. skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
  3391. ath11k_dp_rx_h_ppdu(ar, desc, status);
  3392. status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
  3393. RX_FLAG_DECRYPTED);
  3394. ath11k_dp_rx_h_undecap(ar, msdu, desc,
  3395. HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
  3396. }
  3397. static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu,
  3398. struct ieee80211_rx_status *status)
  3399. {
  3400. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
  3401. bool drop = false;
  3402. ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
  3403. switch (rxcb->err_code) {
  3404. case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
  3405. ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
  3406. break;
  3407. default:
  3408. /* TODO: Review other rxdma error code to check if anything is
  3409. * worth reporting to mac80211
  3410. */
  3411. drop = true;
  3412. break;
  3413. }
  3414. return drop;
  3415. }
  3416. static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
  3417. struct napi_struct *napi,
  3418. struct sk_buff *msdu,
  3419. struct sk_buff_head *msdu_list)
  3420. {
  3421. struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
  3422. struct ieee80211_rx_status rxs = {0};
  3423. bool drop = true;
  3424. switch (rxcb->err_rel_src) {
  3425. case HAL_WBM_REL_SRC_MODULE_REO:
  3426. drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
  3427. break;
  3428. case HAL_WBM_REL_SRC_MODULE_RXDMA:
  3429. drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
  3430. break;
  3431. default:
  3432. /* msdu will get freed */
  3433. break;
  3434. }
  3435. if (drop) {
  3436. dev_kfree_skb_any(msdu);
  3437. return;
  3438. }
  3439. ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
  3440. }
  3441. int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
  3442. struct napi_struct *napi, int budget)
  3443. {
  3444. struct ath11k *ar;
  3445. struct ath11k_dp *dp = &ab->dp;
  3446. struct dp_rxdma_ring *rx_ring;
  3447. struct hal_rx_wbm_rel_info err_info;
  3448. struct hal_srng *srng;
  3449. struct sk_buff *msdu;
  3450. struct sk_buff_head msdu_list[MAX_RADIOS];
  3451. struct ath11k_skb_rxcb *rxcb;
  3452. u32 *rx_desc;
  3453. int buf_id, mac_id;
  3454. int num_buffs_reaped[MAX_RADIOS] = {0};
  3455. int total_num_buffs_reaped = 0;
  3456. int ret, i;
  3457. for (i = 0; i < ab->num_radios; i++)
  3458. __skb_queue_head_init(&msdu_list[i]);
  3459. srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
  3460. spin_lock_bh(&srng->lock);
  3461. ath11k_hal_srng_access_begin(ab, srng);
  3462. while (budget) {
  3463. rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
  3464. if (!rx_desc)
  3465. break;
  3466. ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
  3467. if (ret) {
  3468. ath11k_warn(ab,
  3469. "failed to parse rx error in wbm_rel ring desc %d\n",
  3470. ret);
  3471. continue;
  3472. }
  3473. buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
  3474. mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
  3475. ar = ab->pdevs[mac_id].ar;
  3476. rx_ring = &ar->dp.rx_refill_buf_ring;
  3477. spin_lock_bh(&rx_ring->idr_lock);
  3478. msdu = idr_find(&rx_ring->bufs_idr, buf_id);
  3479. if (!msdu) {
  3480. ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
  3481. buf_id, mac_id);
  3482. spin_unlock_bh(&rx_ring->idr_lock);
  3483. continue;
  3484. }
  3485. idr_remove(&rx_ring->bufs_idr, buf_id);
  3486. spin_unlock_bh(&rx_ring->idr_lock);
  3487. rxcb = ATH11K_SKB_RXCB(msdu);
  3488. dma_unmap_single(ab->dev, rxcb->paddr,
  3489. msdu->len + skb_tailroom(msdu),
  3490. DMA_FROM_DEVICE);
  3491. num_buffs_reaped[mac_id]++;
  3492. total_num_buffs_reaped++;
  3493. budget--;
  3494. if (err_info.push_reason !=
  3495. HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
  3496. dev_kfree_skb_any(msdu);
  3497. continue;
  3498. }
  3499. rxcb->err_rel_src = err_info.err_rel_src;
  3500. rxcb->err_code = err_info.err_code;
  3501. rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
  3502. __skb_queue_tail(&msdu_list[mac_id], msdu);
  3503. }
  3504. ath11k_hal_srng_access_end(ab, srng);
  3505. spin_unlock_bh(&srng->lock);
  3506. if (!total_num_buffs_reaped)
  3507. goto done;
  3508. for (i = 0; i < ab->num_radios; i++) {
  3509. if (!num_buffs_reaped[i])
  3510. continue;
  3511. ar = ab->pdevs[i].ar;
  3512. rx_ring = &ar->dp.rx_refill_buf_ring;
  3513. ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
  3514. ab->hw_params.hal_params->rx_buf_rbm);
  3515. }
  3516. rcu_read_lock();
  3517. for (i = 0; i < ab->num_radios; i++) {
  3518. if (!rcu_dereference(ab->pdevs_active[i])) {
  3519. __skb_queue_purge(&msdu_list[i]);
  3520. continue;
  3521. }
  3522. ar = ab->pdevs[i].ar;
  3523. if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
  3524. __skb_queue_purge(&msdu_list[i]);
  3525. continue;
  3526. }
  3527. while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
  3528. ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
  3529. }
  3530. rcu_read_unlock();
  3531. done:
  3532. return total_num_buffs_reaped;
  3533. }
  3534. int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
  3535. {
  3536. struct ath11k *ar;
  3537. struct dp_srng *err_ring;
  3538. struct dp_rxdma_ring *rx_ring;
  3539. struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
  3540. struct hal_srng *srng;
  3541. u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
  3542. enum hal_rx_buf_return_buf_manager rbm;
  3543. enum hal_reo_entr_rxdma_ecode rxdma_err_code;
  3544. struct ath11k_skb_rxcb *rxcb;
  3545. struct sk_buff *skb;
  3546. struct hal_reo_entrance_ring *entr_ring;
  3547. void *desc;
  3548. int num_buf_freed = 0;
  3549. int quota = budget;
  3550. dma_addr_t paddr;
  3551. u32 desc_bank;
  3552. void *link_desc_va;
  3553. int num_msdus;
  3554. int i;
  3555. int buf_id;
  3556. ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
  3557. err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
  3558. mac_id)];
  3559. rx_ring = &ar->dp.rx_refill_buf_ring;
  3560. srng = &ab->hal.srng_list[err_ring->ring_id];
  3561. spin_lock_bh(&srng->lock);
  3562. ath11k_hal_srng_access_begin(ab, srng);
  3563. while (quota-- &&
  3564. (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
  3565. ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
  3566. entr_ring = (struct hal_reo_entrance_ring *)desc;
  3567. rxdma_err_code =
  3568. FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
  3569. entr_ring->info1);
  3570. ab->soc_stats.rxdma_error[rxdma_err_code]++;
  3571. link_desc_va = link_desc_banks[desc_bank].vaddr +
  3572. (paddr - link_desc_banks[desc_bank].paddr);
  3573. ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
  3574. msdu_cookies, &rbm);
  3575. for (i = 0; i < num_msdus; i++) {
  3576. buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
  3577. msdu_cookies[i]);
  3578. spin_lock_bh(&rx_ring->idr_lock);
  3579. skb = idr_find(&rx_ring->bufs_idr, buf_id);
  3580. if (!skb) {
  3581. ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
  3582. buf_id);
  3583. spin_unlock_bh(&rx_ring->idr_lock);
  3584. continue;
  3585. }
  3586. idr_remove(&rx_ring->bufs_idr, buf_id);
  3587. spin_unlock_bh(&rx_ring->idr_lock);
  3588. rxcb = ATH11K_SKB_RXCB(skb);
  3589. dma_unmap_single(ab->dev, rxcb->paddr,
  3590. skb->len + skb_tailroom(skb),
  3591. DMA_FROM_DEVICE);
  3592. dev_kfree_skb_any(skb);
  3593. num_buf_freed++;
  3594. }
  3595. ath11k_dp_rx_link_desc_return(ab, desc,
  3596. HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
  3597. }
  3598. ath11k_hal_srng_access_end(ab, srng);
  3599. spin_unlock_bh(&srng->lock);
  3600. if (num_buf_freed)
  3601. ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
  3602. ab->hw_params.hal_params->rx_buf_rbm);
  3603. return budget - quota;
  3604. }
  3605. void ath11k_dp_process_reo_status(struct ath11k_base *ab)
  3606. {
  3607. struct ath11k_dp *dp = &ab->dp;
  3608. struct hal_srng *srng;
  3609. struct dp_reo_cmd *cmd, *tmp;
  3610. bool found = false;
  3611. u32 *reo_desc;
  3612. u16 tag;
  3613. struct hal_reo_status reo_status;
  3614. srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
  3615. memset(&reo_status, 0, sizeof(reo_status));
  3616. spin_lock_bh(&srng->lock);
  3617. ath11k_hal_srng_access_begin(ab, srng);
  3618. while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
  3619. tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
  3620. switch (tag) {
  3621. case HAL_REO_GET_QUEUE_STATS_STATUS:
  3622. ath11k_hal_reo_status_queue_stats(ab, reo_desc,
  3623. &reo_status);
  3624. break;
  3625. case HAL_REO_FLUSH_QUEUE_STATUS:
  3626. ath11k_hal_reo_flush_queue_status(ab, reo_desc,
  3627. &reo_status);
  3628. break;
  3629. case HAL_REO_FLUSH_CACHE_STATUS:
  3630. ath11k_hal_reo_flush_cache_status(ab, reo_desc,
  3631. &reo_status);
  3632. break;
  3633. case HAL_REO_UNBLOCK_CACHE_STATUS:
  3634. ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
  3635. &reo_status);
  3636. break;
  3637. case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
  3638. ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
  3639. &reo_status);
  3640. break;
  3641. case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
  3642. ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
  3643. &reo_status);
  3644. break;
  3645. case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
  3646. ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
  3647. &reo_status);
  3648. break;
  3649. default:
  3650. ath11k_warn(ab, "Unknown reo status type %d\n", tag);
  3651. continue;
  3652. }
  3653. spin_lock_bh(&dp->reo_cmd_lock);
  3654. list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
  3655. if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
  3656. found = true;
  3657. list_del(&cmd->list);
  3658. break;
  3659. }
  3660. }
  3661. spin_unlock_bh(&dp->reo_cmd_lock);
  3662. if (found) {
  3663. cmd->handler(dp, (void *)&cmd->data,
  3664. reo_status.uniform_hdr.cmd_status);
  3665. kfree(cmd);
  3666. }
  3667. found = false;
  3668. }
  3669. ath11k_hal_srng_access_end(ab, srng);
  3670. spin_unlock_bh(&srng->lock);
  3671. }
  3672. void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
  3673. {
  3674. struct ath11k *ar = ab->pdevs[mac_id].ar;
  3675. ath11k_dp_rx_pdev_srng_free(ar);
  3676. ath11k_dp_rxdma_pdev_buf_free(ar);
  3677. }
  3678. int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
  3679. {
  3680. struct ath11k *ar = ab->pdevs[mac_id].ar;
  3681. struct ath11k_pdev_dp *dp = &ar->dp;
  3682. u32 ring_id;
  3683. int i;
  3684. int ret;
  3685. ret = ath11k_dp_rx_pdev_srng_alloc(ar);
  3686. if (ret) {
  3687. ath11k_warn(ab, "failed to setup rx srngs\n");
  3688. return ret;
  3689. }
  3690. ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
  3691. if (ret) {
  3692. ath11k_warn(ab, "failed to setup rxdma ring\n");
  3693. return ret;
  3694. }
  3695. ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
  3696. ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
  3697. if (ret) {
  3698. ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
  3699. ret);
  3700. return ret;
  3701. }
  3702. if (ab->hw_params.rx_mac_buf_ring) {
  3703. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
  3704. ring_id = dp->rx_mac_buf_ring[i].ring_id;
  3705. ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
  3706. mac_id + i, HAL_RXDMA_BUF);
  3707. if (ret) {
  3708. ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
  3709. i, ret);
  3710. return ret;
  3711. }
  3712. }
  3713. }
  3714. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
  3715. ring_id = dp->rxdma_err_dst_ring[i].ring_id;
  3716. ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
  3717. mac_id + i, HAL_RXDMA_DST);
  3718. if (ret) {
  3719. ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
  3720. i, ret);
  3721. return ret;
  3722. }
  3723. }
  3724. if (!ab->hw_params.rxdma1_enable)
  3725. goto config_refill_ring;
  3726. ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
  3727. ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
  3728. mac_id, HAL_RXDMA_MONITOR_BUF);
  3729. if (ret) {
  3730. ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
  3731. ret);
  3732. return ret;
  3733. }
  3734. ret = ath11k_dp_tx_htt_srng_setup(ab,
  3735. dp->rxdma_mon_dst_ring.ring_id,
  3736. mac_id, HAL_RXDMA_MONITOR_DST);
  3737. if (ret) {
  3738. ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
  3739. ret);
  3740. return ret;
  3741. }
  3742. ret = ath11k_dp_tx_htt_srng_setup(ab,
  3743. dp->rxdma_mon_desc_ring.ring_id,
  3744. mac_id, HAL_RXDMA_MONITOR_DESC);
  3745. if (ret) {
  3746. ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
  3747. ret);
  3748. return ret;
  3749. }
  3750. config_refill_ring:
  3751. for (i = 0; i < ab->hw_params.num_rxdma_per_pdev; i++) {
  3752. ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
  3753. ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
  3754. HAL_RXDMA_MONITOR_STATUS);
  3755. if (ret) {
  3756. ath11k_warn(ab,
  3757. "failed to configure mon_status_refill_ring%d %d\n",
  3758. i, ret);
  3759. return ret;
  3760. }
  3761. }
  3762. return 0;
  3763. }
  3764. static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
  3765. {
  3766. if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
  3767. *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
  3768. *total_len -= *frag_len;
  3769. } else {
  3770. *frag_len = *total_len;
  3771. *total_len = 0;
  3772. }
  3773. }
  3774. static
  3775. int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
  3776. void *p_last_buf_addr_info,
  3777. u8 mac_id)
  3778. {
  3779. struct ath11k_pdev_dp *dp = &ar->dp;
  3780. struct dp_srng *dp_srng;
  3781. void *hal_srng;
  3782. void *src_srng_desc;
  3783. int ret = 0;
  3784. if (ar->ab->hw_params.rxdma1_enable) {
  3785. dp_srng = &dp->rxdma_mon_desc_ring;
  3786. hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
  3787. } else {
  3788. dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
  3789. hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
  3790. }
  3791. ath11k_hal_srng_access_begin(ar->ab, hal_srng);
  3792. src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
  3793. if (src_srng_desc) {
  3794. struct ath11k_buffer_addr *src_desc = src_srng_desc;
  3795. *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
  3796. } else {
  3797. ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
  3798. "Monitor Link Desc Ring %d Full", mac_id);
  3799. ret = -ENOMEM;
  3800. }
  3801. ath11k_hal_srng_access_end(ar->ab, hal_srng);
  3802. return ret;
  3803. }
  3804. static
  3805. void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
  3806. dma_addr_t *paddr, u32 *sw_cookie,
  3807. u8 *rbm,
  3808. void **pp_buf_addr_info)
  3809. {
  3810. struct hal_rx_msdu_link *msdu_link = rx_msdu_link_desc;
  3811. struct ath11k_buffer_addr *buf_addr_info;
  3812. buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
  3813. ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
  3814. *pp_buf_addr_info = (void *)buf_addr_info;
  3815. }
  3816. static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
  3817. {
  3818. if (skb->len > len) {
  3819. skb_trim(skb, len);
  3820. } else {
  3821. if (skb_tailroom(skb) < len - skb->len) {
  3822. if ((pskb_expand_head(skb, 0,
  3823. len - skb->len - skb_tailroom(skb),
  3824. GFP_ATOMIC))) {
  3825. dev_kfree_skb_any(skb);
  3826. return -ENOMEM;
  3827. }
  3828. }
  3829. skb_put(skb, (len - skb->len));
  3830. }
  3831. return 0;
  3832. }
  3833. static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
  3834. void *msdu_link_desc,
  3835. struct hal_rx_msdu_list *msdu_list,
  3836. u16 *num_msdus)
  3837. {
  3838. struct hal_rx_msdu_details *msdu_details = NULL;
  3839. struct rx_msdu_desc *msdu_desc_info = NULL;
  3840. struct hal_rx_msdu_link *msdu_link = NULL;
  3841. int i;
  3842. u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
  3843. u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
  3844. u8 tmp = 0;
  3845. msdu_link = msdu_link_desc;
  3846. msdu_details = &msdu_link->msdu_link[0];
  3847. for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
  3848. if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
  3849. msdu_details[i].buf_addr_info.info0) == 0) {
  3850. msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
  3851. msdu_desc_info->info0 |= last;
  3852. ;
  3853. break;
  3854. }
  3855. msdu_desc_info = &msdu_details[i].rx_msdu_info;
  3856. if (!i)
  3857. msdu_desc_info->info0 |= first;
  3858. else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
  3859. msdu_desc_info->info0 |= last;
  3860. msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
  3861. msdu_list->msdu_info[i].msdu_len =
  3862. HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
  3863. msdu_list->sw_cookie[i] =
  3864. FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
  3865. msdu_details[i].buf_addr_info.info1);
  3866. tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
  3867. msdu_details[i].buf_addr_info.info1);
  3868. msdu_list->rbm[i] = tmp;
  3869. }
  3870. *num_msdus = i;
  3871. }
  3872. static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
  3873. u32 *rx_bufs_used)
  3874. {
  3875. u32 ret = 0;
  3876. if ((*ppdu_id < msdu_ppdu_id) &&
  3877. ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
  3878. *ppdu_id = msdu_ppdu_id;
  3879. ret = msdu_ppdu_id;
  3880. } else if ((*ppdu_id > msdu_ppdu_id) &&
  3881. ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
  3882. /* mon_dst is behind than mon_status
  3883. * skip dst_ring and free it
  3884. */
  3885. *rx_bufs_used += 1;
  3886. *ppdu_id = msdu_ppdu_id;
  3887. ret = msdu_ppdu_id;
  3888. }
  3889. return ret;
  3890. }
  3891. static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
  3892. bool *is_frag, u32 *total_len,
  3893. u32 *frag_len, u32 *msdu_cnt)
  3894. {
  3895. if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
  3896. if (!*is_frag) {
  3897. *total_len = info->msdu_len;
  3898. *is_frag = true;
  3899. }
  3900. ath11k_dp_mon_set_frag_len(total_len,
  3901. frag_len);
  3902. } else {
  3903. if (*is_frag) {
  3904. ath11k_dp_mon_set_frag_len(total_len,
  3905. frag_len);
  3906. } else {
  3907. *frag_len = info->msdu_len;
  3908. }
  3909. *is_frag = false;
  3910. *msdu_cnt -= 1;
  3911. }
  3912. }
  3913. static u32
  3914. ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
  3915. void *ring_entry, struct sk_buff **head_msdu,
  3916. struct sk_buff **tail_msdu, u32 *npackets,
  3917. u32 *ppdu_id)
  3918. {
  3919. struct ath11k_pdev_dp *dp = &ar->dp;
  3920. struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
  3921. struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
  3922. struct sk_buff *msdu = NULL, *last = NULL;
  3923. struct hal_rx_msdu_list msdu_list;
  3924. void *p_buf_addr_info, *p_last_buf_addr_info;
  3925. struct hal_rx_desc *rx_desc;
  3926. void *rx_msdu_link_desc;
  3927. dma_addr_t paddr;
  3928. u16 num_msdus = 0;
  3929. u32 rx_buf_size, rx_pkt_offset, sw_cookie;
  3930. u32 rx_bufs_used = 0, i = 0;
  3931. u32 msdu_ppdu_id = 0, msdu_cnt = 0;
  3932. u32 total_len = 0, frag_len = 0;
  3933. bool is_frag, is_first_msdu;
  3934. bool drop_mpdu = false;
  3935. struct ath11k_skb_rxcb *rxcb;
  3936. struct hal_reo_entrance_ring *ent_desc = ring_entry;
  3937. int buf_id;
  3938. u32 rx_link_buf_info[2];
  3939. u8 rbm;
  3940. if (!ar->ab->hw_params.rxdma1_enable)
  3941. rx_ring = &dp->rx_refill_buf_ring;
  3942. ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
  3943. &sw_cookie,
  3944. &p_last_buf_addr_info, &rbm,
  3945. &msdu_cnt);
  3946. if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
  3947. ent_desc->info1) ==
  3948. HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
  3949. u8 rxdma_err =
  3950. FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
  3951. ent_desc->info1);
  3952. if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
  3953. rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
  3954. rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
  3955. drop_mpdu = true;
  3956. pmon->rx_mon_stats.dest_mpdu_drop++;
  3957. }
  3958. }
  3959. is_frag = false;
  3960. is_first_msdu = true;
  3961. do {
  3962. if (pmon->mon_last_linkdesc_paddr == paddr) {
  3963. pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
  3964. return rx_bufs_used;
  3965. }
  3966. if (ar->ab->hw_params.rxdma1_enable)
  3967. rx_msdu_link_desc =
  3968. (void *)pmon->link_desc_banks[sw_cookie].vaddr +
  3969. (paddr - pmon->link_desc_banks[sw_cookie].paddr);
  3970. else
  3971. rx_msdu_link_desc =
  3972. (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
  3973. (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
  3974. ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
  3975. &num_msdus);
  3976. for (i = 0; i < num_msdus; i++) {
  3977. u32 l2_hdr_offset;
  3978. if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
  3979. ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
  3980. "i %d last_cookie %d is same\n",
  3981. i, pmon->mon_last_buf_cookie);
  3982. drop_mpdu = true;
  3983. pmon->rx_mon_stats.dup_mon_buf_cnt++;
  3984. continue;
  3985. }
  3986. buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
  3987. msdu_list.sw_cookie[i]);
  3988. spin_lock_bh(&rx_ring->idr_lock);
  3989. msdu = idr_find(&rx_ring->bufs_idr, buf_id);
  3990. spin_unlock_bh(&rx_ring->idr_lock);
  3991. if (!msdu) {
  3992. ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
  3993. "msdu_pop: invalid buf_id %d\n", buf_id);
  3994. break;
  3995. }
  3996. rxcb = ATH11K_SKB_RXCB(msdu);
  3997. if (!rxcb->unmapped) {
  3998. dma_unmap_single(ar->ab->dev, rxcb->paddr,
  3999. msdu->len +
  4000. skb_tailroom(msdu),
  4001. DMA_FROM_DEVICE);
  4002. rxcb->unmapped = 1;
  4003. }
  4004. if (drop_mpdu) {
  4005. ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
  4006. "i %d drop msdu %p *ppdu_id %x\n",
  4007. i, msdu, *ppdu_id);
  4008. dev_kfree_skb_any(msdu);
  4009. msdu = NULL;
  4010. goto next_msdu;
  4011. }
  4012. rx_desc = (struct hal_rx_desc *)msdu->data;
  4013. rx_pkt_offset = sizeof(struct hal_rx_desc);
  4014. l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
  4015. if (is_first_msdu) {
  4016. if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
  4017. drop_mpdu = true;
  4018. dev_kfree_skb_any(msdu);
  4019. msdu = NULL;
  4020. pmon->mon_last_linkdesc_paddr = paddr;
  4021. goto next_msdu;
  4022. }
  4023. msdu_ppdu_id =
  4024. ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
  4025. if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
  4026. ppdu_id,
  4027. &rx_bufs_used)) {
  4028. if (rx_bufs_used) {
  4029. drop_mpdu = true;
  4030. dev_kfree_skb_any(msdu);
  4031. msdu = NULL;
  4032. goto next_msdu;
  4033. }
  4034. return rx_bufs_used;
  4035. }
  4036. pmon->mon_last_linkdesc_paddr = paddr;
  4037. is_first_msdu = false;
  4038. }
  4039. ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
  4040. &is_frag, &total_len,
  4041. &frag_len, &msdu_cnt);
  4042. rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
  4043. ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
  4044. if (!(*head_msdu))
  4045. *head_msdu = msdu;
  4046. else if (last)
  4047. last->next = msdu;
  4048. last = msdu;
  4049. next_msdu:
  4050. pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
  4051. rx_bufs_used++;
  4052. spin_lock_bh(&rx_ring->idr_lock);
  4053. idr_remove(&rx_ring->bufs_idr, buf_id);
  4054. spin_unlock_bh(&rx_ring->idr_lock);
  4055. }
  4056. ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
  4057. ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
  4058. &sw_cookie, &rbm,
  4059. &p_buf_addr_info);
  4060. if (ar->ab->hw_params.rxdma1_enable) {
  4061. if (ath11k_dp_rx_monitor_link_desc_return(ar,
  4062. p_last_buf_addr_info,
  4063. dp->mac_id))
  4064. ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
  4065. "dp_rx_monitor_link_desc_return failed");
  4066. } else {
  4067. ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
  4068. HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
  4069. }
  4070. p_last_buf_addr_info = p_buf_addr_info;
  4071. } while (paddr && msdu_cnt);
  4072. if (last)
  4073. last->next = NULL;
  4074. *tail_msdu = msdu;
  4075. if (msdu_cnt == 0)
  4076. *npackets = 1;
  4077. return rx_bufs_used;
  4078. }
  4079. static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
  4080. {
  4081. u32 rx_pkt_offset, l2_hdr_offset;
  4082. rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
  4083. l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
  4084. (struct hal_rx_desc *)msdu->data);
  4085. skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
  4086. }
  4087. static struct sk_buff *
  4088. ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
  4089. u32 mac_id, struct sk_buff *head_msdu,
  4090. struct sk_buff *last_msdu,
  4091. struct ieee80211_rx_status *rxs, bool *fcs_err)
  4092. {
  4093. struct ath11k_base *ab = ar->ab;
  4094. struct sk_buff *msdu, *prev_buf;
  4095. struct hal_rx_desc *rx_desc;
  4096. char *hdr_desc;
  4097. u8 *dest, decap_format;
  4098. struct ieee80211_hdr_3addr *wh;
  4099. struct rx_attention *rx_attention;
  4100. u32 err_bitmap;
  4101. if (!head_msdu)
  4102. goto err_merge_fail;
  4103. rx_desc = (struct hal_rx_desc *)head_msdu->data;
  4104. rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
  4105. err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
  4106. if (err_bitmap & DP_RX_MPDU_ERR_FCS)
  4107. *fcs_err = true;
  4108. if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
  4109. return NULL;
  4110. decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
  4111. ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
  4112. if (decap_format == DP_RX_DECAP_TYPE_RAW) {
  4113. ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
  4114. prev_buf = head_msdu;
  4115. msdu = head_msdu->next;
  4116. while (msdu) {
  4117. ath11k_dp_rx_msdus_set_payload(ar, msdu);
  4118. prev_buf = msdu;
  4119. msdu = msdu->next;
  4120. }
  4121. prev_buf->next = NULL;
  4122. skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
  4123. } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
  4124. u8 qos_pkt = 0;
  4125. rx_desc = (struct hal_rx_desc *)head_msdu->data;
  4126. hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
  4127. /* Base size */
  4128. wh = (struct ieee80211_hdr_3addr *)hdr_desc;
  4129. if (ieee80211_is_data_qos(wh->frame_control))
  4130. qos_pkt = 1;
  4131. msdu = head_msdu;
  4132. while (msdu) {
  4133. ath11k_dp_rx_msdus_set_payload(ar, msdu);
  4134. if (qos_pkt) {
  4135. dest = skb_push(msdu, sizeof(__le16));
  4136. if (!dest)
  4137. goto err_merge_fail;
  4138. memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr));
  4139. }
  4140. prev_buf = msdu;
  4141. msdu = msdu->next;
  4142. }
  4143. dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
  4144. if (!dest)
  4145. goto err_merge_fail;
  4146. ath11k_dbg(ab, ATH11K_DBG_DATA,
  4147. "mpdu_buf %p mpdu_buf->len %u",
  4148. prev_buf, prev_buf->len);
  4149. } else {
  4150. ath11k_dbg(ab, ATH11K_DBG_DATA,
  4151. "decap format %d is not supported!\n",
  4152. decap_format);
  4153. goto err_merge_fail;
  4154. }
  4155. return head_msdu;
  4156. err_merge_fail:
  4157. return NULL;
  4158. }
  4159. static void
  4160. ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status,
  4161. u8 *rtap_buf)
  4162. {
  4163. u32 rtap_len = 0;
  4164. put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]);
  4165. rtap_len += 2;
  4166. put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]);
  4167. rtap_len += 2;
  4168. put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]);
  4169. rtap_len += 2;
  4170. put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]);
  4171. rtap_len += 2;
  4172. put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]);
  4173. rtap_len += 2;
  4174. put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]);
  4175. }
  4176. static void
  4177. ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status,
  4178. u8 *rtap_buf)
  4179. {
  4180. u32 rtap_len = 0;
  4181. put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]);
  4182. rtap_len += 2;
  4183. put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]);
  4184. rtap_len += 2;
  4185. rtap_buf[rtap_len] = rx_status->he_RU[0];
  4186. rtap_len += 1;
  4187. rtap_buf[rtap_len] = rx_status->he_RU[1];
  4188. rtap_len += 1;
  4189. rtap_buf[rtap_len] = rx_status->he_RU[2];
  4190. rtap_len += 1;
  4191. rtap_buf[rtap_len] = rx_status->he_RU[3];
  4192. }
  4193. static void ath11k_update_radiotap(struct ath11k *ar,
  4194. struct hal_rx_mon_ppdu_info *ppduinfo,
  4195. struct sk_buff *mon_skb,
  4196. struct ieee80211_rx_status *rxs)
  4197. {
  4198. struct ieee80211_supported_band *sband;
  4199. u8 *ptr = NULL;
  4200. rxs->flag |= RX_FLAG_MACTIME_START;
  4201. rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR;
  4202. if (ppduinfo->nss)
  4203. rxs->nss = ppduinfo->nss;
  4204. if (ppduinfo->he_mu_flags) {
  4205. rxs->flag |= RX_FLAG_RADIOTAP_HE_MU;
  4206. rxs->encoding = RX_ENC_HE;
  4207. ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu));
  4208. ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr);
  4209. } else if (ppduinfo->he_flags) {
  4210. rxs->flag |= RX_FLAG_RADIOTAP_HE;
  4211. rxs->encoding = RX_ENC_HE;
  4212. ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he));
  4213. ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr);
  4214. rxs->rate_idx = ppduinfo->rate;
  4215. } else if (ppduinfo->vht_flags) {
  4216. rxs->encoding = RX_ENC_VHT;
  4217. rxs->rate_idx = ppduinfo->rate;
  4218. } else if (ppduinfo->ht_flags) {
  4219. rxs->encoding = RX_ENC_HT;
  4220. rxs->rate_idx = ppduinfo->rate;
  4221. } else {
  4222. rxs->encoding = RX_ENC_LEGACY;
  4223. sband = &ar->mac.sbands[rxs->band];
  4224. rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate,
  4225. ppduinfo->cck_flag);
  4226. }
  4227. rxs->mactime = ppduinfo->tsft;
  4228. }
  4229. static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
  4230. struct sk_buff *head_msdu,
  4231. struct hal_rx_mon_ppdu_info *ppduinfo,
  4232. struct sk_buff *tail_msdu,
  4233. struct napi_struct *napi)
  4234. {
  4235. struct ath11k_pdev_dp *dp = &ar->dp;
  4236. struct sk_buff *mon_skb, *skb_next, *header;
  4237. struct ieee80211_rx_status *rxs = &dp->rx_status;
  4238. bool fcs_err = false;
  4239. mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
  4240. tail_msdu, rxs, &fcs_err);
  4241. if (!mon_skb)
  4242. goto mon_deliver_fail;
  4243. header = mon_skb;
  4244. rxs->flag = 0;
  4245. if (fcs_err)
  4246. rxs->flag = RX_FLAG_FAILED_FCS_CRC;
  4247. do {
  4248. skb_next = mon_skb->next;
  4249. if (!skb_next)
  4250. rxs->flag &= ~RX_FLAG_AMSDU_MORE;
  4251. else
  4252. rxs->flag |= RX_FLAG_AMSDU_MORE;
  4253. if (mon_skb == header) {
  4254. header = NULL;
  4255. rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
  4256. } else {
  4257. rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
  4258. }
  4259. rxs->flag |= RX_FLAG_ONLY_MONITOR;
  4260. ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs);
  4261. ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
  4262. mon_skb = skb_next;
  4263. } while (mon_skb);
  4264. rxs->flag = 0;
  4265. return 0;
  4266. mon_deliver_fail:
  4267. mon_skb = head_msdu;
  4268. while (mon_skb) {
  4269. skb_next = mon_skb->next;
  4270. dev_kfree_skb_any(mon_skb);
  4271. mon_skb = skb_next;
  4272. }
  4273. return -EINVAL;
  4274. }
  4275. /* The destination ring processing is stuck if the destination is not
  4276. * moving while status ring moves 16 PPDU. The destination ring processing
  4277. * skips this destination ring PPDU as a workaround.
  4278. */
  4279. #define MON_DEST_RING_STUCK_MAX_CNT 16
  4280. static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
  4281. u32 quota, struct napi_struct *napi)
  4282. {
  4283. struct ath11k_pdev_dp *dp = &ar->dp;
  4284. struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
  4285. const struct ath11k_hw_hal_params *hal_params;
  4286. void *ring_entry;
  4287. void *mon_dst_srng;
  4288. u32 ppdu_id;
  4289. u32 rx_bufs_used;
  4290. u32 ring_id;
  4291. struct ath11k_pdev_mon_stats *rx_mon_stats;
  4292. u32 npackets = 0;
  4293. u32 mpdu_rx_bufs_used;
  4294. if (ar->ab->hw_params.rxdma1_enable)
  4295. ring_id = dp->rxdma_mon_dst_ring.ring_id;
  4296. else
  4297. ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
  4298. mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
  4299. spin_lock_bh(&pmon->mon_lock);
  4300. ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
  4301. ppdu_id = pmon->mon_ppdu_info.ppdu_id;
  4302. rx_bufs_used = 0;
  4303. rx_mon_stats = &pmon->rx_mon_stats;
  4304. while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
  4305. struct sk_buff *head_msdu, *tail_msdu;
  4306. head_msdu = NULL;
  4307. tail_msdu = NULL;
  4308. mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
  4309. &head_msdu,
  4310. &tail_msdu,
  4311. &npackets, &ppdu_id);
  4312. rx_bufs_used += mpdu_rx_bufs_used;
  4313. if (mpdu_rx_bufs_used) {
  4314. dp->mon_dest_ring_stuck_cnt = 0;
  4315. } else {
  4316. dp->mon_dest_ring_stuck_cnt++;
  4317. rx_mon_stats->dest_mon_not_reaped++;
  4318. }
  4319. if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) {
  4320. rx_mon_stats->dest_mon_stuck++;
  4321. ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
  4322. "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n",
  4323. pmon->mon_ppdu_info.ppdu_id, ppdu_id,
  4324. dp->mon_dest_ring_stuck_cnt,
  4325. rx_mon_stats->dest_mon_not_reaped,
  4326. rx_mon_stats->dest_mon_stuck);
  4327. pmon->mon_ppdu_info.ppdu_id = ppdu_id;
  4328. continue;
  4329. }
  4330. if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
  4331. pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
  4332. ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
  4333. "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n",
  4334. ppdu_id, pmon->mon_ppdu_info.ppdu_id,
  4335. rx_mon_stats->dest_mon_not_reaped,
  4336. rx_mon_stats->dest_mon_stuck);
  4337. break;
  4338. }
  4339. if (head_msdu && tail_msdu) {
  4340. ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
  4341. &pmon->mon_ppdu_info,
  4342. tail_msdu, napi);
  4343. rx_mon_stats->dest_mpdu_done++;
  4344. }
  4345. ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
  4346. mon_dst_srng);
  4347. }
  4348. ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
  4349. spin_unlock_bh(&pmon->mon_lock);
  4350. if (rx_bufs_used) {
  4351. rx_mon_stats->dest_ppdu_done++;
  4352. hal_params = ar->ab->hw_params.hal_params;
  4353. if (ar->ab->hw_params.rxdma1_enable)
  4354. ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
  4355. &dp->rxdma_mon_buf_ring,
  4356. rx_bufs_used,
  4357. hal_params->rx_buf_rbm);
  4358. else
  4359. ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
  4360. &dp->rx_refill_buf_ring,
  4361. rx_bufs_used,
  4362. hal_params->rx_buf_rbm);
  4363. }
  4364. }
  4365. int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
  4366. struct napi_struct *napi, int budget)
  4367. {
  4368. struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
  4369. enum hal_rx_mon_status hal_status;
  4370. struct sk_buff *skb;
  4371. struct sk_buff_head skb_list;
  4372. struct ath11k_peer *peer;
  4373. struct ath11k_sta *arsta;
  4374. int num_buffs_reaped = 0;
  4375. u32 rx_buf_sz;
  4376. u16 log_type;
  4377. struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data;
  4378. struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats;
  4379. struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
  4380. __skb_queue_head_init(&skb_list);
  4381. num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
  4382. &skb_list);
  4383. if (!num_buffs_reaped)
  4384. goto exit;
  4385. memset(ppdu_info, 0, sizeof(*ppdu_info));
  4386. ppdu_info->peer_id = HAL_INVALID_PEERID;
  4387. while ((skb = __skb_dequeue(&skb_list))) {
  4388. if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
  4389. log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
  4390. rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
  4391. } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
  4392. log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
  4393. rx_buf_sz = DP_RX_BUFFER_SIZE;
  4394. } else {
  4395. log_type = ATH11K_PKTLOG_TYPE_INVALID;
  4396. rx_buf_sz = 0;
  4397. }
  4398. if (log_type != ATH11K_PKTLOG_TYPE_INVALID)
  4399. trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
  4400. memset(ppdu_info, 0, sizeof(*ppdu_info));
  4401. ppdu_info->peer_id = HAL_INVALID_PEERID;
  4402. hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb);
  4403. if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
  4404. pmon->mon_ppdu_status == DP_PPDU_STATUS_START &&
  4405. hal_status == HAL_TLV_STATUS_PPDU_DONE) {
  4406. rx_mon_stats->status_ppdu_done++;
  4407. pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
  4408. if (!ab->hw_params.full_monitor_mode) {
  4409. ath11k_dp_rx_mon_dest_process(ar, mac_id,
  4410. budget, napi);
  4411. pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
  4412. }
  4413. }
  4414. if (ppdu_info->peer_id == HAL_INVALID_PEERID ||
  4415. hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
  4416. dev_kfree_skb_any(skb);
  4417. continue;
  4418. }
  4419. rcu_read_lock();
  4420. spin_lock_bh(&ab->base_lock);
  4421. peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id);
  4422. if (!peer || !peer->sta) {
  4423. ath11k_dbg(ab, ATH11K_DBG_DATA,
  4424. "failed to find the peer with peer_id %d\n",
  4425. ppdu_info->peer_id);
  4426. goto next_skb;
  4427. }
  4428. arsta = ath11k_sta_to_arsta(peer->sta);
  4429. ath11k_dp_rx_update_peer_stats(arsta, ppdu_info);
  4430. if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
  4431. trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
  4432. next_skb:
  4433. spin_unlock_bh(&ab->base_lock);
  4434. rcu_read_unlock();
  4435. dev_kfree_skb_any(skb);
  4436. memset(ppdu_info, 0, sizeof(*ppdu_info));
  4437. ppdu_info->peer_id = HAL_INVALID_PEERID;
  4438. }
  4439. exit:
  4440. return num_buffs_reaped;
  4441. }
  4442. static u32
  4443. ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar,
  4444. void *ring_entry, struct sk_buff **head_msdu,
  4445. struct sk_buff **tail_msdu,
  4446. struct hal_sw_mon_ring_entries *sw_mon_entries)
  4447. {
  4448. struct ath11k_pdev_dp *dp = &ar->dp;
  4449. struct ath11k_mon_data *pmon = &dp->mon_data;
  4450. struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
  4451. struct sk_buff *msdu = NULL, *last = NULL;
  4452. struct hal_sw_monitor_ring *sw_desc = ring_entry;
  4453. struct hal_rx_msdu_list msdu_list;
  4454. struct hal_rx_desc *rx_desc;
  4455. struct ath11k_skb_rxcb *rxcb;
  4456. void *rx_msdu_link_desc;
  4457. void *p_buf_addr_info, *p_last_buf_addr_info;
  4458. int buf_id, i = 0;
  4459. u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset;
  4460. u32 rx_bufs_used = 0, msdu_cnt = 0;
  4461. u32 total_len = 0, frag_len = 0, sw_cookie;
  4462. u16 num_msdus = 0;
  4463. u8 rxdma_err, rbm;
  4464. bool is_frag, is_first_msdu;
  4465. bool drop_mpdu = false;
  4466. ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries);
  4467. sw_cookie = sw_mon_entries->mon_dst_sw_cookie;
  4468. sw_mon_entries->end_of_ppdu = false;
  4469. sw_mon_entries->drop_ppdu = false;
  4470. p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info;
  4471. msdu_cnt = sw_mon_entries->msdu_cnt;
  4472. sw_mon_entries->end_of_ppdu =
  4473. FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0);
  4474. if (sw_mon_entries->end_of_ppdu)
  4475. return rx_bufs_used;
  4476. if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON,
  4477. sw_desc->info0) ==
  4478. HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
  4479. rxdma_err =
  4480. FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE,
  4481. sw_desc->info0);
  4482. if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
  4483. rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
  4484. rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
  4485. pmon->rx_mon_stats.dest_mpdu_drop++;
  4486. drop_mpdu = true;
  4487. }
  4488. }
  4489. is_frag = false;
  4490. is_first_msdu = true;
  4491. do {
  4492. rx_msdu_link_desc =
  4493. (u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
  4494. (sw_mon_entries->mon_dst_paddr -
  4495. pmon->link_desc_banks[sw_cookie].paddr);
  4496. ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
  4497. &num_msdus);
  4498. for (i = 0; i < num_msdus; i++) {
  4499. buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
  4500. msdu_list.sw_cookie[i]);
  4501. spin_lock_bh(&rx_ring->idr_lock);
  4502. msdu = idr_find(&rx_ring->bufs_idr, buf_id);
  4503. if (!msdu) {
  4504. ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
  4505. "full mon msdu_pop: invalid buf_id %d\n",
  4506. buf_id);
  4507. spin_unlock_bh(&rx_ring->idr_lock);
  4508. break;
  4509. }
  4510. idr_remove(&rx_ring->bufs_idr, buf_id);
  4511. spin_unlock_bh(&rx_ring->idr_lock);
  4512. rxcb = ATH11K_SKB_RXCB(msdu);
  4513. if (!rxcb->unmapped) {
  4514. dma_unmap_single(ar->ab->dev, rxcb->paddr,
  4515. msdu->len +
  4516. skb_tailroom(msdu),
  4517. DMA_FROM_DEVICE);
  4518. rxcb->unmapped = 1;
  4519. }
  4520. if (drop_mpdu) {
  4521. ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
  4522. "full mon: i %d drop msdu %p *ppdu_id %x\n",
  4523. i, msdu, sw_mon_entries->ppdu_id);
  4524. dev_kfree_skb_any(msdu);
  4525. msdu_cnt--;
  4526. goto next_msdu;
  4527. }
  4528. rx_desc = (struct hal_rx_desc *)msdu->data;
  4529. rx_pkt_offset = sizeof(struct hal_rx_desc);
  4530. l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
  4531. if (is_first_msdu) {
  4532. if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
  4533. drop_mpdu = true;
  4534. dev_kfree_skb_any(msdu);
  4535. msdu = NULL;
  4536. goto next_msdu;
  4537. }
  4538. is_first_msdu = false;
  4539. }
  4540. ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
  4541. &is_frag, &total_len,
  4542. &frag_len, &msdu_cnt);
  4543. rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
  4544. ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
  4545. if (!(*head_msdu))
  4546. *head_msdu = msdu;
  4547. else if (last)
  4548. last->next = msdu;
  4549. last = msdu;
  4550. next_msdu:
  4551. rx_bufs_used++;
  4552. }
  4553. ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc,
  4554. &sw_mon_entries->mon_dst_paddr,
  4555. &sw_mon_entries->mon_dst_sw_cookie,
  4556. &rbm,
  4557. &p_buf_addr_info);
  4558. if (ath11k_dp_rx_monitor_link_desc_return(ar,
  4559. p_last_buf_addr_info,
  4560. dp->mac_id))
  4561. ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
  4562. "full mon: dp_rx_monitor_link_desc_return failed\n");
  4563. p_last_buf_addr_info = p_buf_addr_info;
  4564. } while (sw_mon_entries->mon_dst_paddr && msdu_cnt);
  4565. if (last)
  4566. last->next = NULL;
  4567. *tail_msdu = msdu;
  4568. return rx_bufs_used;
  4569. }
  4570. static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp,
  4571. struct dp_full_mon_mpdu *mon_mpdu,
  4572. struct sk_buff *head,
  4573. struct sk_buff *tail)
  4574. {
  4575. mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
  4576. if (!mon_mpdu)
  4577. return -ENOMEM;
  4578. list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list);
  4579. mon_mpdu->head = head;
  4580. mon_mpdu->tail = tail;
  4581. return 0;
  4582. }
  4583. static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp,
  4584. struct dp_full_mon_mpdu *mon_mpdu)
  4585. {
  4586. struct dp_full_mon_mpdu *tmp;
  4587. struct sk_buff *tmp_msdu, *skb_next;
  4588. if (list_empty(&dp->dp_full_mon_mpdu_list))
  4589. return;
  4590. list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
  4591. list_del(&mon_mpdu->list);
  4592. tmp_msdu = mon_mpdu->head;
  4593. while (tmp_msdu) {
  4594. skb_next = tmp_msdu->next;
  4595. dev_kfree_skb_any(tmp_msdu);
  4596. tmp_msdu = skb_next;
  4597. }
  4598. kfree(mon_mpdu);
  4599. }
  4600. }
  4601. static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar,
  4602. int mac_id,
  4603. struct ath11k_mon_data *pmon,
  4604. struct napi_struct *napi)
  4605. {
  4606. struct ath11k_pdev_mon_stats *rx_mon_stats;
  4607. struct dp_full_mon_mpdu *tmp;
  4608. struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
  4609. struct sk_buff *head_msdu, *tail_msdu;
  4610. struct ath11k_base *ab = ar->ab;
  4611. struct ath11k_dp *dp = &ab->dp;
  4612. int ret;
  4613. rx_mon_stats = &pmon->rx_mon_stats;
  4614. list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
  4615. list_del(&mon_mpdu->list);
  4616. head_msdu = mon_mpdu->head;
  4617. tail_msdu = mon_mpdu->tail;
  4618. if (head_msdu && tail_msdu) {
  4619. ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu,
  4620. &pmon->mon_ppdu_info,
  4621. tail_msdu, napi);
  4622. rx_mon_stats->dest_mpdu_done++;
  4623. ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n");
  4624. }
  4625. kfree(mon_mpdu);
  4626. }
  4627. return ret;
  4628. }
  4629. static int
  4630. ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id,
  4631. struct napi_struct *napi, int budget)
  4632. {
  4633. struct ath11k *ar = ab->pdevs[mac_id].ar;
  4634. struct ath11k_pdev_dp *dp = &ar->dp;
  4635. struct ath11k_mon_data *pmon = &dp->mon_data;
  4636. struct hal_sw_mon_ring_entries *sw_mon_entries;
  4637. int quota = 0, work = 0, count;
  4638. sw_mon_entries = &pmon->sw_mon_entries;
  4639. while (pmon->hold_mon_dst_ring) {
  4640. quota = ath11k_dp_rx_process_mon_status(ab, mac_id,
  4641. napi, 1);
  4642. if (pmon->buf_state == DP_MON_STATUS_MATCH) {
  4643. count = sw_mon_entries->status_buf_count;
  4644. if (count > 1) {
  4645. quota += ath11k_dp_rx_process_mon_status(ab, mac_id,
  4646. napi, count);
  4647. }
  4648. ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id,
  4649. pmon, napi);
  4650. pmon->hold_mon_dst_ring = false;
  4651. } else if (!pmon->mon_status_paddr ||
  4652. pmon->buf_state == DP_MON_STATUS_LEAD) {
  4653. sw_mon_entries->drop_ppdu = true;
  4654. pmon->hold_mon_dst_ring = false;
  4655. }
  4656. if (!quota)
  4657. break;
  4658. work += quota;
  4659. }
  4660. if (sw_mon_entries->drop_ppdu)
  4661. ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu);
  4662. return work;
  4663. }
  4664. static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id,
  4665. struct napi_struct *napi, int budget)
  4666. {
  4667. struct ath11k *ar = ab->pdevs[mac_id].ar;
  4668. struct ath11k_pdev_dp *dp = &ar->dp;
  4669. struct ath11k_mon_data *pmon = &dp->mon_data;
  4670. struct hal_sw_mon_ring_entries *sw_mon_entries;
  4671. struct ath11k_pdev_mon_stats *rx_mon_stats;
  4672. struct sk_buff *head_msdu, *tail_msdu;
  4673. void *mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id];
  4674. void *ring_entry;
  4675. u32 rx_bufs_used = 0, mpdu_rx_bufs_used;
  4676. int quota = 0, ret;
  4677. bool break_dst_ring = false;
  4678. spin_lock_bh(&pmon->mon_lock);
  4679. sw_mon_entries = &pmon->sw_mon_entries;
  4680. rx_mon_stats = &pmon->rx_mon_stats;
  4681. if (pmon->hold_mon_dst_ring) {
  4682. spin_unlock_bh(&pmon->mon_lock);
  4683. goto reap_status_ring;
  4684. }
  4685. ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
  4686. while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
  4687. head_msdu = NULL;
  4688. tail_msdu = NULL;
  4689. mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry,
  4690. &head_msdu,
  4691. &tail_msdu,
  4692. sw_mon_entries);
  4693. rx_bufs_used += mpdu_rx_bufs_used;
  4694. if (!sw_mon_entries->end_of_ppdu) {
  4695. if (head_msdu) {
  4696. ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp,
  4697. pmon->mon_mpdu,
  4698. head_msdu,
  4699. tail_msdu);
  4700. if (ret)
  4701. break_dst_ring = true;
  4702. }
  4703. goto next_entry;
  4704. } else {
  4705. if (!sw_mon_entries->ppdu_id &&
  4706. !sw_mon_entries->mon_status_paddr) {
  4707. break_dst_ring = true;
  4708. goto next_entry;
  4709. }
  4710. }
  4711. rx_mon_stats->dest_ppdu_done++;
  4712. pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
  4713. pmon->buf_state = DP_MON_STATUS_LAG;
  4714. pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr;
  4715. pmon->hold_mon_dst_ring = true;
  4716. next_entry:
  4717. ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
  4718. mon_dst_srng);
  4719. if (break_dst_ring)
  4720. break;
  4721. }
  4722. ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
  4723. spin_unlock_bh(&pmon->mon_lock);
  4724. if (rx_bufs_used) {
  4725. ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
  4726. &dp->rxdma_mon_buf_ring,
  4727. rx_bufs_used,
  4728. HAL_RX_BUF_RBM_SW3_BM);
  4729. }
  4730. reap_status_ring:
  4731. quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id,
  4732. napi, budget);
  4733. return quota;
  4734. }
  4735. int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
  4736. struct napi_struct *napi, int budget)
  4737. {
  4738. struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
  4739. int ret = 0;
  4740. if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
  4741. ab->hw_params.full_monitor_mode)
  4742. ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget);
  4743. else
  4744. ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
  4745. return ret;
  4746. }
  4747. static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
  4748. {
  4749. struct ath11k_pdev_dp *dp = &ar->dp;
  4750. struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
  4751. skb_queue_head_init(&pmon->rx_status_q);
  4752. pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
  4753. memset(&pmon->rx_mon_stats, 0,
  4754. sizeof(pmon->rx_mon_stats));
  4755. return 0;
  4756. }
  4757. int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
  4758. {
  4759. struct ath11k_pdev_dp *dp = &ar->dp;
  4760. struct ath11k_mon_data *pmon = &dp->mon_data;
  4761. struct hal_srng *mon_desc_srng = NULL;
  4762. struct dp_srng *dp_srng;
  4763. int ret = 0;
  4764. u32 n_link_desc = 0;
  4765. ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
  4766. if (ret) {
  4767. ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
  4768. return ret;
  4769. }
  4770. /* if rxdma1_enable is false, no need to setup
  4771. * rxdma_mon_desc_ring.
  4772. */
  4773. if (!ar->ab->hw_params.rxdma1_enable)
  4774. return 0;
  4775. dp_srng = &dp->rxdma_mon_desc_ring;
  4776. n_link_desc = dp_srng->size /
  4777. ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
  4778. mon_desc_srng =
  4779. &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
  4780. ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
  4781. HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
  4782. n_link_desc);
  4783. if (ret) {
  4784. ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
  4785. return ret;
  4786. }
  4787. pmon->mon_last_linkdesc_paddr = 0;
  4788. pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
  4789. spin_lock_init(&pmon->mon_lock);
  4790. return 0;
  4791. }
  4792. static int ath11k_dp_mon_link_free(struct ath11k *ar)
  4793. {
  4794. struct ath11k_pdev_dp *dp = &ar->dp;
  4795. struct ath11k_mon_data *pmon = &dp->mon_data;
  4796. ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
  4797. HAL_RXDMA_MONITOR_DESC,
  4798. &dp->rxdma_mon_desc_ring);
  4799. return 0;
  4800. }
  4801. int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
  4802. {
  4803. ath11k_dp_mon_link_free(ar);
  4804. return 0;
  4805. }
  4806. int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
  4807. {
  4808. /* start reap timer */
  4809. mod_timer(&ab->mon_reap_timer,
  4810. jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
  4811. return 0;
  4812. }
  4813. int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
  4814. {
  4815. int ret;
  4816. if (stop_timer)
  4817. del_timer_sync(&ab->mon_reap_timer);
  4818. /* reap all the monitor related rings */
  4819. ret = ath11k_dp_purge_mon_ring(ab);
  4820. if (ret) {
  4821. ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
  4822. return ret;
  4823. }
  4824. return 0;
  4825. }