dbring.c 8.5 KB

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  1. // SPDX-License-Identifier: BSD-3-Clause-Clear
  2. /*
  3. * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include "core.h"
  7. #include "debug.h"
  8. static int ath12k_dbring_bufs_replenish(struct ath12k *ar,
  9. struct ath12k_dbring *ring,
  10. struct ath12k_dbring_element *buff,
  11. gfp_t gfp)
  12. {
  13. struct ath12k_base *ab = ar->ab;
  14. struct hal_srng *srng;
  15. dma_addr_t paddr;
  16. void *ptr_aligned, *ptr_unaligned, *desc;
  17. int ret;
  18. int buf_id;
  19. u32 cookie;
  20. srng = &ab->hal.srng_list[ring->refill_srng.ring_id];
  21. lockdep_assert_held(&srng->lock);
  22. ath12k_hal_srng_access_begin(ab, srng);
  23. ptr_unaligned = buff->payload;
  24. ptr_aligned = PTR_ALIGN(ptr_unaligned, ring->buf_align);
  25. paddr = dma_map_single(ab->dev, ptr_aligned, ring->buf_sz,
  26. DMA_FROM_DEVICE);
  27. ret = dma_mapping_error(ab->dev, paddr);
  28. if (ret)
  29. goto err;
  30. spin_lock_bh(&ring->idr_lock);
  31. buf_id = idr_alloc(&ring->bufs_idr, buff, 0, ring->bufs_max, gfp);
  32. spin_unlock_bh(&ring->idr_lock);
  33. if (buf_id < 0) {
  34. ret = -ENOBUFS;
  35. goto err_dma_unmap;
  36. }
  37. desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
  38. if (!desc) {
  39. ret = -ENOENT;
  40. goto err_idr_remove;
  41. }
  42. buff->paddr = paddr;
  43. cookie = u32_encode_bits(ar->pdev_idx, DP_RXDMA_BUF_COOKIE_PDEV_ID) |
  44. u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID);
  45. ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, 0);
  46. ath12k_hal_srng_access_end(ab, srng);
  47. return 0;
  48. err_idr_remove:
  49. spin_lock_bh(&ring->idr_lock);
  50. idr_remove(&ring->bufs_idr, buf_id);
  51. spin_unlock_bh(&ring->idr_lock);
  52. err_dma_unmap:
  53. dma_unmap_single(ab->dev, paddr, ring->buf_sz,
  54. DMA_FROM_DEVICE);
  55. err:
  56. ath12k_hal_srng_access_end(ab, srng);
  57. return ret;
  58. }
  59. static int ath12k_dbring_fill_bufs(struct ath12k *ar,
  60. struct ath12k_dbring *ring,
  61. gfp_t gfp)
  62. {
  63. struct ath12k_dbring_element *buff;
  64. struct hal_srng *srng;
  65. struct ath12k_base *ab = ar->ab;
  66. int num_remain, req_entries, num_free;
  67. u32 align;
  68. int size, ret;
  69. srng = &ab->hal.srng_list[ring->refill_srng.ring_id];
  70. spin_lock_bh(&srng->lock);
  71. num_free = ath12k_hal_srng_src_num_free(ab, srng, true);
  72. req_entries = min(num_free, ring->bufs_max);
  73. num_remain = req_entries;
  74. align = ring->buf_align;
  75. size = sizeof(*buff) + ring->buf_sz + align - 1;
  76. while (num_remain > 0) {
  77. buff = kzalloc(size, gfp);
  78. if (!buff)
  79. break;
  80. ret = ath12k_dbring_bufs_replenish(ar, ring, buff, gfp);
  81. if (ret) {
  82. ath12k_warn(ab, "failed to replenish db ring num_remain %d req_ent %d\n",
  83. num_remain, req_entries);
  84. kfree(buff);
  85. break;
  86. }
  87. num_remain--;
  88. }
  89. spin_unlock_bh(&srng->lock);
  90. return num_remain;
  91. }
  92. int ath12k_dbring_wmi_cfg_setup(struct ath12k *ar,
  93. struct ath12k_dbring *ring,
  94. enum wmi_direct_buffer_module id)
  95. {
  96. struct ath12k_wmi_pdev_dma_ring_cfg_arg arg = {0};
  97. int ret;
  98. if (id >= WMI_DIRECT_BUF_MAX)
  99. return -EINVAL;
  100. arg.pdev_id = DP_SW2HW_MACID(ring->pdev_id);
  101. arg.module_id = id;
  102. arg.base_paddr_lo = lower_32_bits(ring->refill_srng.paddr);
  103. arg.base_paddr_hi = upper_32_bits(ring->refill_srng.paddr);
  104. arg.head_idx_paddr_lo = lower_32_bits(ring->hp_addr);
  105. arg.head_idx_paddr_hi = upper_32_bits(ring->hp_addr);
  106. arg.tail_idx_paddr_lo = lower_32_bits(ring->tp_addr);
  107. arg.tail_idx_paddr_hi = upper_32_bits(ring->tp_addr);
  108. arg.num_elems = ring->bufs_max;
  109. arg.buf_size = ring->buf_sz;
  110. arg.num_resp_per_event = ring->num_resp_per_event;
  111. arg.event_timeout_ms = ring->event_timeout_ms;
  112. ret = ath12k_wmi_pdev_dma_ring_cfg(ar, &arg);
  113. if (ret) {
  114. ath12k_warn(ar->ab, "failed to setup db ring cfg\n");
  115. return ret;
  116. }
  117. return 0;
  118. }
  119. int ath12k_dbring_set_cfg(struct ath12k *ar, struct ath12k_dbring *ring,
  120. u32 num_resp_per_event, u32 event_timeout_ms,
  121. int (*handler)(struct ath12k *,
  122. struct ath12k_dbring_data *))
  123. {
  124. if (WARN_ON(!ring))
  125. return -EINVAL;
  126. ring->num_resp_per_event = num_resp_per_event;
  127. ring->event_timeout_ms = event_timeout_ms;
  128. ring->handler = handler;
  129. return 0;
  130. }
  131. int ath12k_dbring_buf_setup(struct ath12k *ar,
  132. struct ath12k_dbring *ring,
  133. struct ath12k_dbring_cap *db_cap)
  134. {
  135. struct ath12k_base *ab = ar->ab;
  136. struct hal_srng *srng;
  137. int ret;
  138. srng = &ab->hal.srng_list[ring->refill_srng.ring_id];
  139. ring->bufs_max = ring->refill_srng.size /
  140. ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_DIR_BUF);
  141. ring->buf_sz = db_cap->min_buf_sz;
  142. ring->buf_align = db_cap->min_buf_align;
  143. ring->pdev_id = db_cap->pdev_id;
  144. ring->hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng);
  145. ring->tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng);
  146. ret = ath12k_dbring_fill_bufs(ar, ring, GFP_KERNEL);
  147. return ret;
  148. }
  149. int ath12k_dbring_srng_setup(struct ath12k *ar, struct ath12k_dbring *ring,
  150. int ring_num, int num_entries)
  151. {
  152. int ret;
  153. ret = ath12k_dp_srng_setup(ar->ab, &ring->refill_srng, HAL_RXDMA_DIR_BUF,
  154. ring_num, ar->pdev_idx, num_entries);
  155. if (ret < 0) {
  156. ath12k_warn(ar->ab, "failed to setup srng: %d ring_id %d\n",
  157. ret, ring_num);
  158. goto err;
  159. }
  160. return 0;
  161. err:
  162. ath12k_dp_srng_cleanup(ar->ab, &ring->refill_srng);
  163. return ret;
  164. }
  165. int ath12k_dbring_get_cap(struct ath12k_base *ab,
  166. u8 pdev_idx,
  167. enum wmi_direct_buffer_module id,
  168. struct ath12k_dbring_cap *db_cap)
  169. {
  170. int i;
  171. if (!ab->num_db_cap || !ab->db_caps)
  172. return -ENOENT;
  173. if (id >= WMI_DIRECT_BUF_MAX)
  174. return -EINVAL;
  175. for (i = 0; i < ab->num_db_cap; i++) {
  176. if (pdev_idx == ab->db_caps[i].pdev_id &&
  177. id == ab->db_caps[i].id) {
  178. *db_cap = ab->db_caps[i];
  179. return 0;
  180. }
  181. }
  182. return -ENOENT;
  183. }
  184. int ath12k_dbring_buffer_release_event(struct ath12k_base *ab,
  185. struct ath12k_dbring_buf_release_event *ev)
  186. {
  187. struct ath12k_dbring *ring = NULL;
  188. struct hal_srng *srng;
  189. struct ath12k *ar;
  190. struct ath12k_dbring_element *buff;
  191. struct ath12k_dbring_data handler_data;
  192. struct ath12k_buffer_addr desc;
  193. u8 *vaddr_unalign;
  194. u32 num_entry, num_buff_reaped;
  195. u8 pdev_idx, rbm;
  196. u32 cookie;
  197. int buf_id;
  198. int size;
  199. dma_addr_t paddr;
  200. int ret = 0;
  201. pdev_idx = le32_to_cpu(ev->fixed.pdev_id);
  202. if (pdev_idx >= ab->num_radios) {
  203. ath12k_warn(ab, "Invalid pdev id %d\n", pdev_idx);
  204. return -EINVAL;
  205. }
  206. if (ev->fixed.num_buf_release_entry !=
  207. ev->fixed.num_meta_data_entry) {
  208. ath12k_warn(ab, "Buffer entry %d mismatch meta entry %d\n",
  209. ev->fixed.num_buf_release_entry,
  210. ev->fixed.num_meta_data_entry);
  211. return -EINVAL;
  212. }
  213. ar = ab->pdevs[pdev_idx].ar;
  214. rcu_read_lock();
  215. if (!rcu_dereference(ab->pdevs_active[pdev_idx])) {
  216. ret = -EINVAL;
  217. goto rcu_unlock;
  218. }
  219. switch (ev->fixed.module_id) {
  220. case WMI_DIRECT_BUF_SPECTRAL:
  221. break;
  222. default:
  223. ring = NULL;
  224. ath12k_warn(ab, "Recv dma buffer release ev on unsupp module %d\n",
  225. ev->fixed.module_id);
  226. break;
  227. }
  228. if (!ring) {
  229. ret = -EINVAL;
  230. goto rcu_unlock;
  231. }
  232. srng = &ab->hal.srng_list[ring->refill_srng.ring_id];
  233. num_entry = le32_to_cpu(ev->fixed.num_buf_release_entry);
  234. size = sizeof(*buff) + ring->buf_sz + ring->buf_align - 1;
  235. num_buff_reaped = 0;
  236. spin_lock_bh(&srng->lock);
  237. while (num_buff_reaped < num_entry) {
  238. desc.info0 = ev->buf_entry[num_buff_reaped].paddr_lo;
  239. desc.info1 = ev->buf_entry[num_buff_reaped].paddr_hi;
  240. handler_data.meta = ev->meta_data[num_buff_reaped];
  241. num_buff_reaped++;
  242. ath12k_hal_rx_buf_addr_info_get(&desc, &paddr, &cookie, &rbm);
  243. buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
  244. spin_lock_bh(&ring->idr_lock);
  245. buff = idr_find(&ring->bufs_idr, buf_id);
  246. if (!buff) {
  247. spin_unlock_bh(&ring->idr_lock);
  248. continue;
  249. }
  250. idr_remove(&ring->bufs_idr, buf_id);
  251. spin_unlock_bh(&ring->idr_lock);
  252. dma_unmap_single(ab->dev, buff->paddr, ring->buf_sz,
  253. DMA_FROM_DEVICE);
  254. if (ring->handler) {
  255. vaddr_unalign = buff->payload;
  256. handler_data.data = PTR_ALIGN(vaddr_unalign,
  257. ring->buf_align);
  258. handler_data.data_sz = ring->buf_sz;
  259. ring->handler(ar, &handler_data);
  260. }
  261. memset(buff, 0, size);
  262. ath12k_dbring_bufs_replenish(ar, ring, buff, GFP_ATOMIC);
  263. }
  264. spin_unlock_bh(&srng->lock);
  265. rcu_unlock:
  266. rcu_read_unlock();
  267. return ret;
  268. }
  269. void ath12k_dbring_srng_cleanup(struct ath12k *ar, struct ath12k_dbring *ring)
  270. {
  271. ath12k_dp_srng_cleanup(ar->ab, &ring->refill_srng);
  272. }
  273. void ath12k_dbring_buf_cleanup(struct ath12k *ar, struct ath12k_dbring *ring)
  274. {
  275. struct ath12k_dbring_element *buff;
  276. int buf_id;
  277. spin_lock_bh(&ring->idr_lock);
  278. idr_for_each_entry(&ring->bufs_idr, buff, buf_id) {
  279. idr_remove(&ring->bufs_idr, buf_id);
  280. dma_unmap_single(ar->ab->dev, buff->paddr,
  281. ring->buf_sz, DMA_FROM_DEVICE);
  282. kfree(buff);
  283. }
  284. idr_destroy(&ring->bufs_idr);
  285. spin_unlock_bh(&ring->idr_lock);
  286. }