dp_rx.c 117 KB

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  1. // SPDX-License-Identifier: BSD-3-Clause-Clear
  2. /*
  3. * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/ieee80211.h>
  7. #include <linux/kernel.h>
  8. #include <linux/skbuff.h>
  9. #include <crypto/hash.h>
  10. #include "core.h"
  11. #include "debug.h"
  12. #include "hal_desc.h"
  13. #include "hw.h"
  14. #include "dp_rx.h"
  15. #include "hal_rx.h"
  16. #include "dp_tx.h"
  17. #include "peer.h"
  18. #include "dp_mon.h"
  19. #include "debugfs_htt_stats.h"
  20. #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
  21. static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab,
  22. struct hal_rx_desc *desc)
  23. {
  24. if (!ab->hal_rx_ops->rx_desc_encrypt_valid(desc))
  25. return HAL_ENCRYPT_TYPE_OPEN;
  26. return ab->hal_rx_ops->rx_desc_get_encrypt_type(desc);
  27. }
  28. u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab,
  29. struct hal_rx_desc *desc)
  30. {
  31. return ab->hal_rx_ops->rx_desc_get_decap_type(desc);
  32. }
  33. static u8 ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base *ab,
  34. struct hal_rx_desc *desc)
  35. {
  36. return ab->hal_rx_ops->rx_desc_get_mesh_ctl(desc);
  37. }
  38. static bool ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base *ab,
  39. struct hal_rx_desc *desc)
  40. {
  41. return ab->hal_rx_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
  42. }
  43. static bool ath12k_dp_rx_h_fc_valid(struct ath12k_base *ab,
  44. struct hal_rx_desc *desc)
  45. {
  46. return ab->hal_rx_ops->rx_desc_get_mpdu_fc_valid(desc);
  47. }
  48. static bool ath12k_dp_rx_h_more_frags(struct ath12k_base *ab,
  49. struct sk_buff *skb)
  50. {
  51. struct ieee80211_hdr *hdr;
  52. hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz);
  53. return ieee80211_has_morefrags(hdr->frame_control);
  54. }
  55. static u16 ath12k_dp_rx_h_frag_no(struct ath12k_base *ab,
  56. struct sk_buff *skb)
  57. {
  58. struct ieee80211_hdr *hdr;
  59. hdr = (struct ieee80211_hdr *)(skb->data + ab->hal.hal_desc_sz);
  60. return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
  61. }
  62. static u16 ath12k_dp_rx_h_seq_no(struct ath12k_base *ab,
  63. struct hal_rx_desc *desc)
  64. {
  65. return ab->hal_rx_ops->rx_desc_get_mpdu_start_seq_no(desc);
  66. }
  67. static bool ath12k_dp_rx_h_msdu_done(struct ath12k_base *ab,
  68. struct hal_rx_desc *desc)
  69. {
  70. return ab->hal_rx_ops->dp_rx_h_msdu_done(desc);
  71. }
  72. static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab,
  73. struct hal_rx_desc *desc)
  74. {
  75. return ab->hal_rx_ops->dp_rx_h_l4_cksum_fail(desc);
  76. }
  77. static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab,
  78. struct hal_rx_desc *desc)
  79. {
  80. return ab->hal_rx_ops->dp_rx_h_ip_cksum_fail(desc);
  81. }
  82. static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab,
  83. struct hal_rx_desc *desc)
  84. {
  85. return ab->hal_rx_ops->dp_rx_h_is_decrypted(desc);
  86. }
  87. u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab,
  88. struct hal_rx_desc *desc)
  89. {
  90. return ab->hal_rx_ops->dp_rx_h_mpdu_err(desc);
  91. }
  92. static u16 ath12k_dp_rx_h_msdu_len(struct ath12k_base *ab,
  93. struct hal_rx_desc *desc)
  94. {
  95. return ab->hal_rx_ops->rx_desc_get_msdu_len(desc);
  96. }
  97. static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab,
  98. struct hal_rx_desc *desc)
  99. {
  100. return ab->hal_rx_ops->rx_desc_get_msdu_sgi(desc);
  101. }
  102. static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab,
  103. struct hal_rx_desc *desc)
  104. {
  105. return ab->hal_rx_ops->rx_desc_get_msdu_rate_mcs(desc);
  106. }
  107. static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab,
  108. struct hal_rx_desc *desc)
  109. {
  110. return ab->hal_rx_ops->rx_desc_get_msdu_rx_bw(desc);
  111. }
  112. static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab,
  113. struct hal_rx_desc *desc)
  114. {
  115. return ab->hal_rx_ops->rx_desc_get_msdu_freq(desc);
  116. }
  117. static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab,
  118. struct hal_rx_desc *desc)
  119. {
  120. return ab->hal_rx_ops->rx_desc_get_msdu_pkt_type(desc);
  121. }
  122. static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab,
  123. struct hal_rx_desc *desc)
  124. {
  125. return hweight8(ab->hal_rx_ops->rx_desc_get_msdu_nss(desc));
  126. }
  127. static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab,
  128. struct hal_rx_desc *desc)
  129. {
  130. return ab->hal_rx_ops->rx_desc_get_mpdu_tid(desc);
  131. }
  132. static u16 ath12k_dp_rx_h_peer_id(struct ath12k_base *ab,
  133. struct hal_rx_desc *desc)
  134. {
  135. return ab->hal_rx_ops->rx_desc_get_mpdu_peer_id(desc);
  136. }
  137. u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab,
  138. struct hal_rx_desc *desc)
  139. {
  140. return ab->hal_rx_ops->rx_desc_get_l3_pad_bytes(desc);
  141. }
  142. static bool ath12k_dp_rx_h_first_msdu(struct ath12k_base *ab,
  143. struct hal_rx_desc *desc)
  144. {
  145. return ab->hal_rx_ops->rx_desc_get_first_msdu(desc);
  146. }
  147. static bool ath12k_dp_rx_h_last_msdu(struct ath12k_base *ab,
  148. struct hal_rx_desc *desc)
  149. {
  150. return ab->hal_rx_ops->rx_desc_get_last_msdu(desc);
  151. }
  152. static void ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base *ab,
  153. struct hal_rx_desc *fdesc,
  154. struct hal_rx_desc *ldesc)
  155. {
  156. ab->hal_rx_ops->rx_desc_copy_end_tlv(fdesc, ldesc);
  157. }
  158. static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab,
  159. struct hal_rx_desc *desc,
  160. u16 len)
  161. {
  162. ab->hal_rx_ops->rx_desc_set_msdu_len(desc, len);
  163. }
  164. static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab,
  165. struct hal_rx_desc *desc)
  166. {
  167. return (ath12k_dp_rx_h_first_msdu(ab, desc) &&
  168. ab->hal_rx_ops->rx_desc_is_da_mcbc(desc));
  169. }
  170. static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab,
  171. struct hal_rx_desc *desc)
  172. {
  173. return ab->hal_rx_ops->rx_desc_mac_addr2_valid(desc);
  174. }
  175. static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab,
  176. struct hal_rx_desc *desc)
  177. {
  178. return ab->hal_rx_ops->rx_desc_mpdu_start_addr2(desc);
  179. }
  180. static void ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base *ab,
  181. struct hal_rx_desc *desc,
  182. struct ieee80211_hdr *hdr)
  183. {
  184. ab->hal_rx_ops->rx_desc_get_dot11_hdr(desc, hdr);
  185. }
  186. static void ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base *ab,
  187. struct hal_rx_desc *desc,
  188. u8 *crypto_hdr,
  189. enum hal_encrypt_type enctype)
  190. {
  191. ab->hal_rx_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype);
  192. }
  193. static inline u8 ath12k_dp_rx_get_msdu_src_link(struct ath12k_base *ab,
  194. struct hal_rx_desc *desc)
  195. {
  196. return ab->hal_rx_ops->rx_desc_get_msdu_src_link_id(desc);
  197. }
  198. static void ath12k_dp_clean_up_skb_list(struct sk_buff_head *skb_list)
  199. {
  200. struct sk_buff *skb;
  201. while ((skb = __skb_dequeue(skb_list)))
  202. dev_kfree_skb_any(skb);
  203. }
  204. static size_t ath12k_dp_list_cut_nodes(struct list_head *list,
  205. struct list_head *head,
  206. size_t count)
  207. {
  208. struct list_head *cur;
  209. struct ath12k_rx_desc_info *rx_desc;
  210. size_t nodes = 0;
  211. if (!count) {
  212. INIT_LIST_HEAD(list);
  213. goto out;
  214. }
  215. list_for_each(cur, head) {
  216. if (!count)
  217. break;
  218. rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list);
  219. rx_desc->in_use = true;
  220. count--;
  221. nodes++;
  222. }
  223. list_cut_before(list, head, cur);
  224. out:
  225. return nodes;
  226. }
  227. static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp,
  228. struct list_head *used_list)
  229. {
  230. struct ath12k_rx_desc_info *rx_desc, *safe;
  231. /* Reset the use flag */
  232. list_for_each_entry_safe(rx_desc, safe, used_list, list)
  233. rx_desc->in_use = false;
  234. spin_lock_bh(&dp->rx_desc_lock);
  235. list_splice_tail(used_list, &dp->rx_desc_free_list);
  236. spin_unlock_bh(&dp->rx_desc_lock);
  237. }
  238. /* Returns number of Rx buffers replenished */
  239. int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab,
  240. struct dp_rxdma_ring *rx_ring,
  241. struct list_head *used_list,
  242. int req_entries)
  243. {
  244. struct ath12k_buffer_addr *desc;
  245. struct hal_srng *srng;
  246. struct sk_buff *skb;
  247. int num_free;
  248. int num_remain;
  249. u32 cookie;
  250. dma_addr_t paddr;
  251. struct ath12k_dp *dp = &ab->dp;
  252. struct ath12k_rx_desc_info *rx_desc;
  253. enum hal_rx_buf_return_buf_manager mgr = ab->hw_params->hal_params->rx_buf_rbm;
  254. req_entries = min(req_entries, rx_ring->bufs_max);
  255. srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
  256. spin_lock_bh(&srng->lock);
  257. ath12k_hal_srng_access_begin(ab, srng);
  258. num_free = ath12k_hal_srng_src_num_free(ab, srng, true);
  259. if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
  260. req_entries = num_free;
  261. req_entries = min(num_free, req_entries);
  262. num_remain = req_entries;
  263. if (!num_remain)
  264. goto out;
  265. /* Get the descriptor from free list */
  266. if (list_empty(used_list)) {
  267. spin_lock_bh(&dp->rx_desc_lock);
  268. req_entries = ath12k_dp_list_cut_nodes(used_list,
  269. &dp->rx_desc_free_list,
  270. num_remain);
  271. spin_unlock_bh(&dp->rx_desc_lock);
  272. num_remain = req_entries;
  273. }
  274. while (num_remain > 0) {
  275. skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
  276. DP_RX_BUFFER_ALIGN_SIZE);
  277. if (!skb)
  278. break;
  279. if (!IS_ALIGNED((unsigned long)skb->data,
  280. DP_RX_BUFFER_ALIGN_SIZE)) {
  281. skb_pull(skb,
  282. PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
  283. skb->data);
  284. }
  285. paddr = dma_map_single(ab->dev, skb->data,
  286. skb->len + skb_tailroom(skb),
  287. DMA_FROM_DEVICE);
  288. if (dma_mapping_error(ab->dev, paddr))
  289. goto fail_free_skb;
  290. rx_desc = list_first_entry_or_null(used_list,
  291. struct ath12k_rx_desc_info,
  292. list);
  293. if (!rx_desc)
  294. goto fail_dma_unmap;
  295. rx_desc->skb = skb;
  296. cookie = rx_desc->cookie;
  297. desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
  298. if (!desc)
  299. goto fail_dma_unmap;
  300. list_del(&rx_desc->list);
  301. ATH12K_SKB_RXCB(skb)->paddr = paddr;
  302. num_remain--;
  303. ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
  304. }
  305. goto out;
  306. fail_dma_unmap:
  307. dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
  308. DMA_FROM_DEVICE);
  309. fail_free_skb:
  310. dev_kfree_skb_any(skb);
  311. out:
  312. ath12k_hal_srng_access_end(ab, srng);
  313. if (!list_empty(used_list))
  314. ath12k_dp_rx_enqueue_free(dp, used_list);
  315. spin_unlock_bh(&srng->lock);
  316. return req_entries - num_remain;
  317. }
  318. static int ath12k_dp_rxdma_mon_buf_ring_free(struct ath12k_base *ab,
  319. struct dp_rxdma_mon_ring *rx_ring)
  320. {
  321. struct sk_buff *skb;
  322. int buf_id;
  323. spin_lock_bh(&rx_ring->idr_lock);
  324. idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
  325. idr_remove(&rx_ring->bufs_idr, buf_id);
  326. /* TODO: Understand where internal driver does this dma_unmap
  327. * of rxdma_buffer.
  328. */
  329. dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
  330. skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
  331. dev_kfree_skb_any(skb);
  332. }
  333. idr_destroy(&rx_ring->bufs_idr);
  334. spin_unlock_bh(&rx_ring->idr_lock);
  335. return 0;
  336. }
  337. static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab)
  338. {
  339. struct ath12k_dp *dp = &ab->dp;
  340. ath12k_dp_rxdma_mon_buf_ring_free(ab, &dp->rxdma_mon_buf_ring);
  341. return 0;
  342. }
  343. static int ath12k_dp_rxdma_mon_ring_buf_setup(struct ath12k_base *ab,
  344. struct dp_rxdma_mon_ring *rx_ring,
  345. u32 ringtype)
  346. {
  347. int num_entries;
  348. num_entries = rx_ring->refill_buf_ring.size /
  349. ath12k_hal_srng_get_entrysize(ab, ringtype);
  350. rx_ring->bufs_max = num_entries;
  351. ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries);
  352. return 0;
  353. }
  354. static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab,
  355. struct dp_rxdma_ring *rx_ring)
  356. {
  357. LIST_HEAD(list);
  358. rx_ring->bufs_max = rx_ring->refill_buf_ring.size /
  359. ath12k_hal_srng_get_entrysize(ab, HAL_RXDMA_BUF);
  360. ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0);
  361. return 0;
  362. }
  363. static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab)
  364. {
  365. struct ath12k_dp *dp = &ab->dp;
  366. int ret;
  367. ret = ath12k_dp_rxdma_ring_buf_setup(ab, &dp->rx_refill_buf_ring);
  368. if (ret) {
  369. ath12k_warn(ab,
  370. "failed to setup HAL_RXDMA_BUF\n");
  371. return ret;
  372. }
  373. if (ab->hw_params->rxdma1_enable) {
  374. ret = ath12k_dp_rxdma_mon_ring_buf_setup(ab,
  375. &dp->rxdma_mon_buf_ring,
  376. HAL_RXDMA_MONITOR_BUF);
  377. if (ret) {
  378. ath12k_warn(ab,
  379. "failed to setup HAL_RXDMA_MONITOR_BUF\n");
  380. return ret;
  381. }
  382. }
  383. return 0;
  384. }
  385. static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar)
  386. {
  387. struct ath12k_pdev_dp *dp = &ar->dp;
  388. struct ath12k_base *ab = ar->ab;
  389. int i;
  390. for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++)
  391. ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]);
  392. }
  393. void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab)
  394. {
  395. struct ath12k_dp *dp = &ab->dp;
  396. int i;
  397. for (i = 0; i < DP_REO_DST_RING_MAX; i++)
  398. ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
  399. }
  400. int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab)
  401. {
  402. struct ath12k_dp *dp = &ab->dp;
  403. int ret;
  404. int i;
  405. for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
  406. ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
  407. HAL_REO_DST, i, 0,
  408. DP_REO_DST_RING_SIZE);
  409. if (ret) {
  410. ath12k_warn(ab, "failed to setup reo_dst_ring\n");
  411. goto err_reo_cleanup;
  412. }
  413. }
  414. return 0;
  415. err_reo_cleanup:
  416. ath12k_dp_rx_pdev_reo_cleanup(ab);
  417. return ret;
  418. }
  419. static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar)
  420. {
  421. struct ath12k_pdev_dp *dp = &ar->dp;
  422. struct ath12k_base *ab = ar->ab;
  423. int i;
  424. int ret;
  425. u32 mac_id = dp->mac_id;
  426. for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
  427. ret = ath12k_dp_srng_setup(ar->ab,
  428. &dp->rxdma_mon_dst_ring[i],
  429. HAL_RXDMA_MONITOR_DST,
  430. 0, mac_id + i,
  431. DP_RXDMA_MONITOR_DST_RING_SIZE);
  432. if (ret) {
  433. ath12k_warn(ar->ab,
  434. "failed to setup HAL_RXDMA_MONITOR_DST\n");
  435. return ret;
  436. }
  437. }
  438. return 0;
  439. }
  440. void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab)
  441. {
  442. struct ath12k_dp *dp = &ab->dp;
  443. struct ath12k_dp_rx_reo_cmd *cmd, *tmp;
  444. struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache;
  445. spin_lock_bh(&dp->reo_cmd_lock);
  446. list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
  447. list_del(&cmd->list);
  448. dma_unmap_single(ab->dev, cmd->data.paddr,
  449. cmd->data.size, DMA_BIDIRECTIONAL);
  450. kfree(cmd->data.vaddr);
  451. kfree(cmd);
  452. }
  453. list_for_each_entry_safe(cmd_cache, tmp_cache,
  454. &dp->reo_cmd_cache_flush_list, list) {
  455. list_del(&cmd_cache->list);
  456. dp->reo_cmd_cache_flush_count--;
  457. dma_unmap_single(ab->dev, cmd_cache->data.paddr,
  458. cmd_cache->data.size, DMA_BIDIRECTIONAL);
  459. kfree(cmd_cache->data.vaddr);
  460. kfree(cmd_cache);
  461. }
  462. spin_unlock_bh(&dp->reo_cmd_lock);
  463. }
  464. static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx,
  465. enum hal_reo_cmd_status status)
  466. {
  467. struct ath12k_dp_rx_tid *rx_tid = ctx;
  468. if (status != HAL_REO_CMD_SUCCESS)
  469. ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
  470. rx_tid->tid, status);
  471. dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
  472. DMA_BIDIRECTIONAL);
  473. kfree(rx_tid->vaddr);
  474. rx_tid->vaddr = NULL;
  475. }
  476. static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid,
  477. enum hal_reo_cmd_type type,
  478. struct ath12k_hal_reo_cmd *cmd,
  479. void (*cb)(struct ath12k_dp *dp, void *ctx,
  480. enum hal_reo_cmd_status status))
  481. {
  482. struct ath12k_dp *dp = &ab->dp;
  483. struct ath12k_dp_rx_reo_cmd *dp_cmd;
  484. struct hal_srng *cmd_ring;
  485. int cmd_num;
  486. cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
  487. cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd);
  488. /* cmd_num should start from 1, during failure return the error code */
  489. if (cmd_num < 0)
  490. return cmd_num;
  491. /* reo cmd ring descriptors has cmd_num starting from 1 */
  492. if (cmd_num == 0)
  493. return -EINVAL;
  494. if (!cb)
  495. return 0;
  496. /* Can this be optimized so that we keep the pending command list only
  497. * for tid delete command to free up the resource on the command status
  498. * indication?
  499. */
  500. dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC);
  501. if (!dp_cmd)
  502. return -ENOMEM;
  503. memcpy(&dp_cmd->data, rx_tid, sizeof(*rx_tid));
  504. dp_cmd->cmd_num = cmd_num;
  505. dp_cmd->handler = cb;
  506. spin_lock_bh(&dp->reo_cmd_lock);
  507. list_add_tail(&dp_cmd->list, &dp->reo_cmd_list);
  508. spin_unlock_bh(&dp->reo_cmd_lock);
  509. return 0;
  510. }
  511. static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab,
  512. struct ath12k_dp_rx_tid *rx_tid)
  513. {
  514. struct ath12k_hal_reo_cmd cmd = {0};
  515. unsigned long tot_desc_sz, desc_sz;
  516. int ret;
  517. tot_desc_sz = rx_tid->size;
  518. desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
  519. while (tot_desc_sz > desc_sz) {
  520. tot_desc_sz -= desc_sz;
  521. cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
  522. cmd.addr_hi = upper_32_bits(rx_tid->paddr);
  523. ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
  524. HAL_REO_CMD_FLUSH_CACHE, &cmd,
  525. NULL);
  526. if (ret)
  527. ath12k_warn(ab,
  528. "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
  529. rx_tid->tid, ret);
  530. }
  531. memset(&cmd, 0, sizeof(cmd));
  532. cmd.addr_lo = lower_32_bits(rx_tid->paddr);
  533. cmd.addr_hi = upper_32_bits(rx_tid->paddr);
  534. cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
  535. ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
  536. HAL_REO_CMD_FLUSH_CACHE,
  537. &cmd, ath12k_dp_reo_cmd_free);
  538. if (ret) {
  539. ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
  540. rx_tid->tid, ret);
  541. dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
  542. DMA_BIDIRECTIONAL);
  543. kfree(rx_tid->vaddr);
  544. rx_tid->vaddr = NULL;
  545. }
  546. }
  547. static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx,
  548. enum hal_reo_cmd_status status)
  549. {
  550. struct ath12k_base *ab = dp->ab;
  551. struct ath12k_dp_rx_tid *rx_tid = ctx;
  552. struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp;
  553. if (status == HAL_REO_CMD_DRAIN) {
  554. goto free_desc;
  555. } else if (status != HAL_REO_CMD_SUCCESS) {
  556. /* Shouldn't happen! Cleanup in case of other failure? */
  557. ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
  558. rx_tid->tid, status);
  559. return;
  560. }
  561. elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
  562. if (!elem)
  563. goto free_desc;
  564. elem->ts = jiffies;
  565. memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
  566. spin_lock_bh(&dp->reo_cmd_lock);
  567. list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
  568. dp->reo_cmd_cache_flush_count++;
  569. /* Flush and invalidate aged REO desc from HW cache */
  570. list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
  571. list) {
  572. if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES ||
  573. time_after(jiffies, elem->ts +
  574. msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) {
  575. list_del(&elem->list);
  576. dp->reo_cmd_cache_flush_count--;
  577. /* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send()
  578. * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list
  579. * is used in only two contexts, one is in this function called
  580. * from napi and the other in ath12k_dp_free during core destroy.
  581. * Before dp_free, the irqs would be disabled and would wait to
  582. * synchronize. Hence there wouldn’t be any race against add or
  583. * delete to this list. Hence unlock-lock is safe here.
  584. */
  585. spin_unlock_bh(&dp->reo_cmd_lock);
  586. ath12k_dp_reo_cache_flush(ab, &elem->data);
  587. kfree(elem);
  588. spin_lock_bh(&dp->reo_cmd_lock);
  589. }
  590. }
  591. spin_unlock_bh(&dp->reo_cmd_lock);
  592. return;
  593. free_desc:
  594. dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
  595. DMA_BIDIRECTIONAL);
  596. kfree(rx_tid->vaddr);
  597. rx_tid->vaddr = NULL;
  598. }
  599. static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid,
  600. dma_addr_t paddr)
  601. {
  602. struct ath12k_reo_queue_ref *qref;
  603. struct ath12k_dp *dp = &ab->dp;
  604. if (!ab->hw_params->reoq_lut_support)
  605. return;
  606. /* TODO: based on ML peer or not, select the LUT. below assumes non
  607. * ML peer
  608. */
  609. qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr +
  610. (peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
  611. qref->info0 = u32_encode_bits(lower_32_bits(paddr),
  612. BUFFER_ADDR_INFO0_ADDR);
  613. qref->info1 = u32_encode_bits(upper_32_bits(paddr),
  614. BUFFER_ADDR_INFO1_ADDR) |
  615. u32_encode_bits(tid, DP_REO_QREF_NUM);
  616. }
  617. static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid)
  618. {
  619. struct ath12k_reo_queue_ref *qref;
  620. struct ath12k_dp *dp = &ab->dp;
  621. if (!ab->hw_params->reoq_lut_support)
  622. return;
  623. /* TODO: based on ML peer or not, select the LUT. below assumes non
  624. * ML peer
  625. */
  626. qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr +
  627. (peer_id * (IEEE80211_NUM_TIDS + 1) + tid);
  628. qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR);
  629. qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) |
  630. u32_encode_bits(tid, DP_REO_QREF_NUM);
  631. }
  632. void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar,
  633. struct ath12k_peer *peer, u8 tid)
  634. {
  635. struct ath12k_hal_reo_cmd cmd = {0};
  636. struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid];
  637. int ret;
  638. if (!rx_tid->active)
  639. return;
  640. cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
  641. cmd.addr_lo = lower_32_bits(rx_tid->paddr);
  642. cmd.addr_hi = upper_32_bits(rx_tid->paddr);
  643. cmd.upd0 = HAL_REO_CMD_UPD0_VLD;
  644. ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid,
  645. HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
  646. ath12k_dp_rx_tid_del_func);
  647. if (ret) {
  648. ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
  649. tid, ret);
  650. dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
  651. DMA_BIDIRECTIONAL);
  652. kfree(rx_tid->vaddr);
  653. rx_tid->vaddr = NULL;
  654. }
  655. ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid);
  656. rx_tid->active = false;
  657. }
  658. /* TODO: it's strange (and ugly) that struct hal_reo_dest_ring is converted
  659. * to struct hal_wbm_release_ring, I couldn't figure out the logic behind
  660. * that.
  661. */
  662. static int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab,
  663. struct hal_reo_dest_ring *ring,
  664. enum hal_wbm_rel_bm_act action)
  665. {
  666. struct hal_wbm_release_ring *link_desc = (struct hal_wbm_release_ring *)ring;
  667. struct hal_wbm_release_ring *desc;
  668. struct ath12k_dp *dp = &ab->dp;
  669. struct hal_srng *srng;
  670. int ret = 0;
  671. srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
  672. spin_lock_bh(&srng->lock);
  673. ath12k_hal_srng_access_begin(ab, srng);
  674. desc = ath12k_hal_srng_src_get_next_entry(ab, srng);
  675. if (!desc) {
  676. ret = -ENOBUFS;
  677. goto exit;
  678. }
  679. ath12k_hal_rx_msdu_link_desc_set(ab, desc, link_desc, action);
  680. exit:
  681. ath12k_hal_srng_access_end(ab, srng);
  682. spin_unlock_bh(&srng->lock);
  683. return ret;
  684. }
  685. static void ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid *rx_tid,
  686. bool rel_link_desc)
  687. {
  688. struct ath12k_base *ab = rx_tid->ab;
  689. lockdep_assert_held(&ab->base_lock);
  690. if (rx_tid->dst_ring_desc) {
  691. if (rel_link_desc)
  692. ath12k_dp_rx_link_desc_return(ab, rx_tid->dst_ring_desc,
  693. HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
  694. kfree(rx_tid->dst_ring_desc);
  695. rx_tid->dst_ring_desc = NULL;
  696. }
  697. rx_tid->cur_sn = 0;
  698. rx_tid->last_frag_no = 0;
  699. rx_tid->rx_frag_bitmap = 0;
  700. __skb_queue_purge(&rx_tid->rx_frags);
  701. }
  702. void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer)
  703. {
  704. struct ath12k_dp_rx_tid *rx_tid;
  705. int i;
  706. lockdep_assert_held(&ar->ab->base_lock);
  707. for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
  708. rx_tid = &peer->rx_tid[i];
  709. ath12k_dp_rx_peer_tid_delete(ar, peer, i);
  710. ath12k_dp_rx_frags_cleanup(rx_tid, true);
  711. spin_unlock_bh(&ar->ab->base_lock);
  712. del_timer_sync(&rx_tid->frag_timer);
  713. spin_lock_bh(&ar->ab->base_lock);
  714. }
  715. }
  716. static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar,
  717. struct ath12k_peer *peer,
  718. struct ath12k_dp_rx_tid *rx_tid,
  719. u32 ba_win_sz, u16 ssn,
  720. bool update_ssn)
  721. {
  722. struct ath12k_hal_reo_cmd cmd = {0};
  723. int ret;
  724. cmd.addr_lo = lower_32_bits(rx_tid->paddr);
  725. cmd.addr_hi = upper_32_bits(rx_tid->paddr);
  726. cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
  727. cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
  728. cmd.ba_window_size = ba_win_sz;
  729. if (update_ssn) {
  730. cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
  731. cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN);
  732. }
  733. ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid,
  734. HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
  735. NULL);
  736. if (ret) {
  737. ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
  738. rx_tid->tid, ret);
  739. return ret;
  740. }
  741. rx_tid->ba_win_sz = ba_win_sz;
  742. return 0;
  743. }
  744. int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id,
  745. u8 tid, u32 ba_win_sz, u16 ssn,
  746. enum hal_pn_type pn_type)
  747. {
  748. struct ath12k_base *ab = ar->ab;
  749. struct ath12k_dp *dp = &ab->dp;
  750. struct hal_rx_reo_queue *addr_aligned;
  751. struct ath12k_peer *peer;
  752. struct ath12k_dp_rx_tid *rx_tid;
  753. u32 hw_desc_sz;
  754. void *vaddr;
  755. dma_addr_t paddr;
  756. int ret;
  757. spin_lock_bh(&ab->base_lock);
  758. peer = ath12k_peer_find(ab, vdev_id, peer_mac);
  759. if (!peer) {
  760. spin_unlock_bh(&ab->base_lock);
  761. ath12k_warn(ab, "failed to find the peer to set up rx tid\n");
  762. return -ENOENT;
  763. }
  764. if (ab->hw_params->reoq_lut_support && !dp->reoq_lut.vaddr) {
  765. spin_unlock_bh(&ab->base_lock);
  766. ath12k_warn(ab, "reo qref table is not setup\n");
  767. return -EINVAL;
  768. }
  769. if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) {
  770. ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n",
  771. peer->peer_id, tid);
  772. spin_unlock_bh(&ab->base_lock);
  773. return -EINVAL;
  774. }
  775. rx_tid = &peer->rx_tid[tid];
  776. /* Update the tid queue if it is already setup */
  777. if (rx_tid->active) {
  778. paddr = rx_tid->paddr;
  779. ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid,
  780. ba_win_sz, ssn, true);
  781. spin_unlock_bh(&ab->base_lock);
  782. if (ret) {
  783. ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid);
  784. return ret;
  785. }
  786. if (!ab->hw_params->reoq_lut_support) {
  787. ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
  788. peer_mac,
  789. paddr, tid, 1,
  790. ba_win_sz);
  791. if (ret) {
  792. ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n",
  793. tid, ret);
  794. return ret;
  795. }
  796. }
  797. return 0;
  798. }
  799. rx_tid->tid = tid;
  800. rx_tid->ba_win_sz = ba_win_sz;
  801. /* TODO: Optimize the memory allocation for qos tid based on
  802. * the actual BA window size in REO tid update path.
  803. */
  804. if (tid == HAL_DESC_REO_NON_QOS_TID)
  805. hw_desc_sz = ath12k_hal_reo_qdesc_size(ba_win_sz, tid);
  806. else
  807. hw_desc_sz = ath12k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
  808. vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
  809. if (!vaddr) {
  810. spin_unlock_bh(&ab->base_lock);
  811. return -ENOMEM;
  812. }
  813. addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
  814. ath12k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
  815. ssn, pn_type);
  816. paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
  817. DMA_BIDIRECTIONAL);
  818. ret = dma_mapping_error(ab->dev, paddr);
  819. if (ret) {
  820. spin_unlock_bh(&ab->base_lock);
  821. goto err_mem_free;
  822. }
  823. rx_tid->vaddr = vaddr;
  824. rx_tid->paddr = paddr;
  825. rx_tid->size = hw_desc_sz;
  826. rx_tid->active = true;
  827. if (ab->hw_params->reoq_lut_support) {
  828. /* Update the REO queue LUT at the corresponding peer id
  829. * and tid with qaddr.
  830. */
  831. ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, paddr);
  832. spin_unlock_bh(&ab->base_lock);
  833. } else {
  834. spin_unlock_bh(&ab->base_lock);
  835. ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
  836. paddr, tid, 1, ba_win_sz);
  837. }
  838. return ret;
  839. err_mem_free:
  840. kfree(vaddr);
  841. return ret;
  842. }
  843. int ath12k_dp_rx_ampdu_start(struct ath12k *ar,
  844. struct ieee80211_ampdu_params *params)
  845. {
  846. struct ath12k_base *ab = ar->ab;
  847. struct ath12k_sta *arsta = ath12k_sta_to_arsta(params->sta);
  848. int vdev_id = arsta->arvif->vdev_id;
  849. int ret;
  850. ret = ath12k_dp_rx_peer_tid_setup(ar, params->sta->addr, vdev_id,
  851. params->tid, params->buf_size,
  852. params->ssn, arsta->pn_type);
  853. if (ret)
  854. ath12k_warn(ab, "failed to setup rx tid %d\n", ret);
  855. return ret;
  856. }
  857. int ath12k_dp_rx_ampdu_stop(struct ath12k *ar,
  858. struct ieee80211_ampdu_params *params)
  859. {
  860. struct ath12k_base *ab = ar->ab;
  861. struct ath12k_peer *peer;
  862. struct ath12k_sta *arsta = ath12k_sta_to_arsta(params->sta);
  863. int vdev_id = arsta->arvif->vdev_id;
  864. bool active;
  865. int ret;
  866. spin_lock_bh(&ab->base_lock);
  867. peer = ath12k_peer_find(ab, vdev_id, params->sta->addr);
  868. if (!peer) {
  869. spin_unlock_bh(&ab->base_lock);
  870. ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n");
  871. return -ENOENT;
  872. }
  873. active = peer->rx_tid[params->tid].active;
  874. if (!active) {
  875. spin_unlock_bh(&ab->base_lock);
  876. return 0;
  877. }
  878. ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
  879. spin_unlock_bh(&ab->base_lock);
  880. if (ret) {
  881. ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n",
  882. params->tid, ret);
  883. return ret;
  884. }
  885. return ret;
  886. }
  887. int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_vif *arvif,
  888. const u8 *peer_addr,
  889. enum set_key_cmd key_cmd,
  890. struct ieee80211_key_conf *key)
  891. {
  892. struct ath12k *ar = arvif->ar;
  893. struct ath12k_base *ab = ar->ab;
  894. struct ath12k_hal_reo_cmd cmd = {0};
  895. struct ath12k_peer *peer;
  896. struct ath12k_dp_rx_tid *rx_tid;
  897. u8 tid;
  898. int ret = 0;
  899. /* NOTE: Enable PN/TSC replay check offload only for unicast frames.
  900. * We use mac80211 PN/TSC replay check functionality for bcast/mcast
  901. * for now.
  902. */
  903. if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
  904. return 0;
  905. cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
  906. cmd.upd0 = HAL_REO_CMD_UPD0_PN |
  907. HAL_REO_CMD_UPD0_PN_SIZE |
  908. HAL_REO_CMD_UPD0_PN_VALID |
  909. HAL_REO_CMD_UPD0_PN_CHECK |
  910. HAL_REO_CMD_UPD0_SVLD;
  911. switch (key->cipher) {
  912. case WLAN_CIPHER_SUITE_TKIP:
  913. case WLAN_CIPHER_SUITE_CCMP:
  914. case WLAN_CIPHER_SUITE_CCMP_256:
  915. case WLAN_CIPHER_SUITE_GCMP:
  916. case WLAN_CIPHER_SUITE_GCMP_256:
  917. if (key_cmd == SET_KEY) {
  918. cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
  919. cmd.pn_size = 48;
  920. }
  921. break;
  922. default:
  923. break;
  924. }
  925. spin_lock_bh(&ab->base_lock);
  926. peer = ath12k_peer_find(ab, arvif->vdev_id, peer_addr);
  927. if (!peer) {
  928. spin_unlock_bh(&ab->base_lock);
  929. ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n",
  930. peer_addr);
  931. return -ENOENT;
  932. }
  933. for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
  934. rx_tid = &peer->rx_tid[tid];
  935. if (!rx_tid->active)
  936. continue;
  937. cmd.addr_lo = lower_32_bits(rx_tid->paddr);
  938. cmd.addr_hi = upper_32_bits(rx_tid->paddr);
  939. ret = ath12k_dp_reo_cmd_send(ab, rx_tid,
  940. HAL_REO_CMD_UPDATE_RX_QUEUE,
  941. &cmd, NULL);
  942. if (ret) {
  943. ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n",
  944. tid, peer_addr, ret);
  945. break;
  946. }
  947. }
  948. spin_unlock_bh(&ab->base_lock);
  949. return ret;
  950. }
  951. static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
  952. u16 peer_id)
  953. {
  954. int i;
  955. for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
  956. if (ppdu_stats->user_stats[i].is_valid_peer_id) {
  957. if (peer_id == ppdu_stats->user_stats[i].peer_id)
  958. return i;
  959. } else {
  960. return i;
  961. }
  962. }
  963. return -EINVAL;
  964. }
  965. static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab,
  966. u16 tag, u16 len, const void *ptr,
  967. void *data)
  968. {
  969. const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *ba_status;
  970. const struct htt_ppdu_stats_usr_cmpltn_cmn *cmplt_cmn;
  971. const struct htt_ppdu_stats_user_rate *user_rate;
  972. struct htt_ppdu_stats_info *ppdu_info;
  973. struct htt_ppdu_user_stats *user_stats;
  974. int cur_user;
  975. u16 peer_id;
  976. ppdu_info = data;
  977. switch (tag) {
  978. case HTT_PPDU_STATS_TAG_COMMON:
  979. if (len < sizeof(struct htt_ppdu_stats_common)) {
  980. ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
  981. len, tag);
  982. return -EINVAL;
  983. }
  984. memcpy(&ppdu_info->ppdu_stats.common, ptr,
  985. sizeof(struct htt_ppdu_stats_common));
  986. break;
  987. case HTT_PPDU_STATS_TAG_USR_RATE:
  988. if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
  989. ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
  990. len, tag);
  991. return -EINVAL;
  992. }
  993. user_rate = ptr;
  994. peer_id = le16_to_cpu(user_rate->sw_peer_id);
  995. cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
  996. peer_id);
  997. if (cur_user < 0)
  998. return -EINVAL;
  999. user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
  1000. user_stats->peer_id = peer_id;
  1001. user_stats->is_valid_peer_id = true;
  1002. memcpy(&user_stats->rate, ptr,
  1003. sizeof(struct htt_ppdu_stats_user_rate));
  1004. user_stats->tlv_flags |= BIT(tag);
  1005. break;
  1006. case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
  1007. if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
  1008. ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
  1009. len, tag);
  1010. return -EINVAL;
  1011. }
  1012. cmplt_cmn = ptr;
  1013. peer_id = le16_to_cpu(cmplt_cmn->sw_peer_id);
  1014. cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
  1015. peer_id);
  1016. if (cur_user < 0)
  1017. return -EINVAL;
  1018. user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
  1019. user_stats->peer_id = peer_id;
  1020. user_stats->is_valid_peer_id = true;
  1021. memcpy(&user_stats->cmpltn_cmn, ptr,
  1022. sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
  1023. user_stats->tlv_flags |= BIT(tag);
  1024. break;
  1025. case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
  1026. if (len <
  1027. sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
  1028. ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n",
  1029. len, tag);
  1030. return -EINVAL;
  1031. }
  1032. ba_status = ptr;
  1033. peer_id = le16_to_cpu(ba_status->sw_peer_id);
  1034. cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
  1035. peer_id);
  1036. if (cur_user < 0)
  1037. return -EINVAL;
  1038. user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
  1039. user_stats->peer_id = peer_id;
  1040. user_stats->is_valid_peer_id = true;
  1041. memcpy(&user_stats->ack_ba, ptr,
  1042. sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
  1043. user_stats->tlv_flags |= BIT(tag);
  1044. break;
  1045. }
  1046. return 0;
  1047. }
  1048. int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len,
  1049. int (*iter)(struct ath12k_base *ar, u16 tag, u16 len,
  1050. const void *ptr, void *data),
  1051. void *data)
  1052. {
  1053. const struct htt_tlv *tlv;
  1054. const void *begin = ptr;
  1055. u16 tlv_tag, tlv_len;
  1056. int ret = -EINVAL;
  1057. while (len > 0) {
  1058. if (len < sizeof(*tlv)) {
  1059. ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
  1060. ptr - begin, len, sizeof(*tlv));
  1061. return -EINVAL;
  1062. }
  1063. tlv = (struct htt_tlv *)ptr;
  1064. tlv_tag = le32_get_bits(tlv->header, HTT_TLV_TAG);
  1065. tlv_len = le32_get_bits(tlv->header, HTT_TLV_LEN);
  1066. ptr += sizeof(*tlv);
  1067. len -= sizeof(*tlv);
  1068. if (tlv_len > len) {
  1069. ath12k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
  1070. tlv_tag, ptr - begin, len, tlv_len);
  1071. return -EINVAL;
  1072. }
  1073. ret = iter(ab, tlv_tag, tlv_len, ptr, data);
  1074. if (ret == -ENOMEM)
  1075. return ret;
  1076. ptr += tlv_len;
  1077. len -= tlv_len;
  1078. }
  1079. return 0;
  1080. }
  1081. static void
  1082. ath12k_update_per_peer_tx_stats(struct ath12k *ar,
  1083. struct htt_ppdu_stats *ppdu_stats, u8 user)
  1084. {
  1085. struct ath12k_base *ab = ar->ab;
  1086. struct ath12k_peer *peer;
  1087. struct ieee80211_sta *sta;
  1088. struct ath12k_sta *arsta;
  1089. struct htt_ppdu_stats_user_rate *user_rate;
  1090. struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
  1091. struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
  1092. struct htt_ppdu_stats_common *common = &ppdu_stats->common;
  1093. int ret;
  1094. u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
  1095. u32 v, succ_bytes = 0;
  1096. u16 tones, rate = 0, succ_pkts = 0;
  1097. u32 tx_duration = 0;
  1098. u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
  1099. bool is_ampdu = false;
  1100. if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
  1101. return;
  1102. if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
  1103. is_ampdu =
  1104. HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
  1105. if (usr_stats->tlv_flags &
  1106. BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
  1107. succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes);
  1108. succ_pkts = le32_get_bits(usr_stats->ack_ba.info,
  1109. HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M);
  1110. tid = le32_get_bits(usr_stats->ack_ba.info,
  1111. HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM);
  1112. }
  1113. if (common->fes_duration_us)
  1114. tx_duration = le32_to_cpu(common->fes_duration_us);
  1115. user_rate = &usr_stats->rate;
  1116. flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
  1117. bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
  1118. nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
  1119. mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
  1120. sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
  1121. dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
  1122. /* Note: If host configured fixed rates and in some other special
  1123. * cases, the broadcast/management frames are sent in different rates.
  1124. * Firmware rate's control to be skipped for this?
  1125. */
  1126. if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) {
  1127. ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs);
  1128. return;
  1129. }
  1130. if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH12K_VHT_MCS_MAX) {
  1131. ath12k_warn(ab, "Invalid VHT mcs %d peer stats", mcs);
  1132. return;
  1133. }
  1134. if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH12K_HT_MCS_MAX || nss < 1)) {
  1135. ath12k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
  1136. mcs, nss);
  1137. return;
  1138. }
  1139. if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
  1140. ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs,
  1141. flags,
  1142. &rate_idx,
  1143. &rate);
  1144. if (ret < 0)
  1145. return;
  1146. }
  1147. rcu_read_lock();
  1148. spin_lock_bh(&ab->base_lock);
  1149. peer = ath12k_peer_find_by_id(ab, usr_stats->peer_id);
  1150. if (!peer || !peer->sta) {
  1151. spin_unlock_bh(&ab->base_lock);
  1152. rcu_read_unlock();
  1153. return;
  1154. }
  1155. sta = peer->sta;
  1156. arsta = ath12k_sta_to_arsta(sta);
  1157. memset(&arsta->txrate, 0, sizeof(arsta->txrate));
  1158. switch (flags) {
  1159. case WMI_RATE_PREAMBLE_OFDM:
  1160. arsta->txrate.legacy = rate;
  1161. break;
  1162. case WMI_RATE_PREAMBLE_CCK:
  1163. arsta->txrate.legacy = rate;
  1164. break;
  1165. case WMI_RATE_PREAMBLE_HT:
  1166. arsta->txrate.mcs = mcs + 8 * (nss - 1);
  1167. arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
  1168. if (sgi)
  1169. arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
  1170. break;
  1171. case WMI_RATE_PREAMBLE_VHT:
  1172. arsta->txrate.mcs = mcs;
  1173. arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
  1174. if (sgi)
  1175. arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
  1176. break;
  1177. case WMI_RATE_PREAMBLE_HE:
  1178. arsta->txrate.mcs = mcs;
  1179. arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
  1180. arsta->txrate.he_dcm = dcm;
  1181. arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi);
  1182. tones = le16_to_cpu(user_rate->ru_end) -
  1183. le16_to_cpu(user_rate->ru_start) + 1;
  1184. v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones);
  1185. arsta->txrate.he_ru_alloc = v;
  1186. break;
  1187. }
  1188. arsta->txrate.nss = nss;
  1189. arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw);
  1190. arsta->tx_duration += tx_duration;
  1191. memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
  1192. /* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
  1193. * So skip peer stats update for mgmt packets.
  1194. */
  1195. if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
  1196. memset(peer_stats, 0, sizeof(*peer_stats));
  1197. peer_stats->succ_pkts = succ_pkts;
  1198. peer_stats->succ_bytes = succ_bytes;
  1199. peer_stats->is_ampdu = is_ampdu;
  1200. peer_stats->duration = tx_duration;
  1201. peer_stats->ba_fails =
  1202. HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
  1203. HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
  1204. }
  1205. spin_unlock_bh(&ab->base_lock);
  1206. rcu_read_unlock();
  1207. }
  1208. static void ath12k_htt_update_ppdu_stats(struct ath12k *ar,
  1209. struct htt_ppdu_stats *ppdu_stats)
  1210. {
  1211. u8 user;
  1212. for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
  1213. ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user);
  1214. }
  1215. static
  1216. struct htt_ppdu_stats_info *ath12k_dp_htt_get_ppdu_desc(struct ath12k *ar,
  1217. u32 ppdu_id)
  1218. {
  1219. struct htt_ppdu_stats_info *ppdu_info;
  1220. lockdep_assert_held(&ar->data_lock);
  1221. if (!list_empty(&ar->ppdu_stats_info)) {
  1222. list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
  1223. if (ppdu_info->ppdu_id == ppdu_id)
  1224. return ppdu_info;
  1225. }
  1226. if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
  1227. ppdu_info = list_first_entry(&ar->ppdu_stats_info,
  1228. typeof(*ppdu_info), list);
  1229. list_del(&ppdu_info->list);
  1230. ar->ppdu_stat_list_depth--;
  1231. ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
  1232. kfree(ppdu_info);
  1233. }
  1234. }
  1235. ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
  1236. if (!ppdu_info)
  1237. return NULL;
  1238. list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
  1239. ar->ppdu_stat_list_depth++;
  1240. return ppdu_info;
  1241. }
  1242. static void ath12k_copy_to_delay_stats(struct ath12k_peer *peer,
  1243. struct htt_ppdu_user_stats *usr_stats)
  1244. {
  1245. peer->ppdu_stats_delayba.sw_peer_id = le16_to_cpu(usr_stats->rate.sw_peer_id);
  1246. peer->ppdu_stats_delayba.info0 = le32_to_cpu(usr_stats->rate.info0);
  1247. peer->ppdu_stats_delayba.ru_end = le16_to_cpu(usr_stats->rate.ru_end);
  1248. peer->ppdu_stats_delayba.ru_start = le16_to_cpu(usr_stats->rate.ru_start);
  1249. peer->ppdu_stats_delayba.info1 = le32_to_cpu(usr_stats->rate.info1);
  1250. peer->ppdu_stats_delayba.rate_flags = le32_to_cpu(usr_stats->rate.rate_flags);
  1251. peer->ppdu_stats_delayba.resp_rate_flags =
  1252. le32_to_cpu(usr_stats->rate.resp_rate_flags);
  1253. peer->delayba_flag = true;
  1254. }
  1255. static void ath12k_copy_to_bar(struct ath12k_peer *peer,
  1256. struct htt_ppdu_user_stats *usr_stats)
  1257. {
  1258. usr_stats->rate.sw_peer_id = cpu_to_le16(peer->ppdu_stats_delayba.sw_peer_id);
  1259. usr_stats->rate.info0 = cpu_to_le32(peer->ppdu_stats_delayba.info0);
  1260. usr_stats->rate.ru_end = cpu_to_le16(peer->ppdu_stats_delayba.ru_end);
  1261. usr_stats->rate.ru_start = cpu_to_le16(peer->ppdu_stats_delayba.ru_start);
  1262. usr_stats->rate.info1 = cpu_to_le32(peer->ppdu_stats_delayba.info1);
  1263. usr_stats->rate.rate_flags = cpu_to_le32(peer->ppdu_stats_delayba.rate_flags);
  1264. usr_stats->rate.resp_rate_flags =
  1265. cpu_to_le32(peer->ppdu_stats_delayba.resp_rate_flags);
  1266. peer->delayba_flag = false;
  1267. }
  1268. static int ath12k_htt_pull_ppdu_stats(struct ath12k_base *ab,
  1269. struct sk_buff *skb)
  1270. {
  1271. struct ath12k_htt_ppdu_stats_msg *msg;
  1272. struct htt_ppdu_stats_info *ppdu_info;
  1273. struct ath12k_peer *peer = NULL;
  1274. struct htt_ppdu_user_stats *usr_stats = NULL;
  1275. u32 peer_id = 0;
  1276. struct ath12k *ar;
  1277. int ret, i;
  1278. u8 pdev_id;
  1279. u32 ppdu_id, len;
  1280. msg = (struct ath12k_htt_ppdu_stats_msg *)skb->data;
  1281. len = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE);
  1282. if (len > (skb->len - struct_size(msg, data, 0))) {
  1283. ath12k_warn(ab,
  1284. "HTT PPDU STATS event has unexpected payload size %u, should be smaller than %u\n",
  1285. len, skb->len);
  1286. return -EINVAL;
  1287. }
  1288. pdev_id = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PDEV_ID);
  1289. ppdu_id = le32_to_cpu(msg->ppdu_id);
  1290. rcu_read_lock();
  1291. ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id);
  1292. if (!ar) {
  1293. ret = -EINVAL;
  1294. goto exit;
  1295. }
  1296. spin_lock_bh(&ar->data_lock);
  1297. ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id);
  1298. if (!ppdu_info) {
  1299. spin_unlock_bh(&ar->data_lock);
  1300. ret = -EINVAL;
  1301. goto exit;
  1302. }
  1303. ppdu_info->ppdu_id = ppdu_id;
  1304. ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len,
  1305. ath12k_htt_tlv_ppdu_stats_parse,
  1306. (void *)ppdu_info);
  1307. if (ret) {
  1308. spin_unlock_bh(&ar->data_lock);
  1309. ath12k_warn(ab, "Failed to parse tlv %d\n", ret);
  1310. goto exit;
  1311. }
  1312. if (ppdu_info->ppdu_stats.common.num_users >= HTT_PPDU_STATS_MAX_USERS) {
  1313. spin_unlock_bh(&ar->data_lock);
  1314. ath12k_warn(ab,
  1315. "HTT PPDU STATS event has unexpected num_users %u, should be smaller than %u\n",
  1316. ppdu_info->ppdu_stats.common.num_users,
  1317. HTT_PPDU_STATS_MAX_USERS);
  1318. ret = -EINVAL;
  1319. goto exit;
  1320. }
  1321. /* back up data rate tlv for all peers */
  1322. if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_DATA &&
  1323. (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON)) &&
  1324. ppdu_info->delay_ba) {
  1325. for (i = 0; i < ppdu_info->ppdu_stats.common.num_users; i++) {
  1326. peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id;
  1327. spin_lock_bh(&ab->base_lock);
  1328. peer = ath12k_peer_find_by_id(ab, peer_id);
  1329. if (!peer) {
  1330. spin_unlock_bh(&ab->base_lock);
  1331. continue;
  1332. }
  1333. usr_stats = &ppdu_info->ppdu_stats.user_stats[i];
  1334. if (usr_stats->delay_ba)
  1335. ath12k_copy_to_delay_stats(peer, usr_stats);
  1336. spin_unlock_bh(&ab->base_lock);
  1337. }
  1338. }
  1339. /* restore all peers' data rate tlv to mu-bar tlv */
  1340. if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_BAR &&
  1341. (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON))) {
  1342. for (i = 0; i < ppdu_info->bar_num_users; i++) {
  1343. peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id;
  1344. spin_lock_bh(&ab->base_lock);
  1345. peer = ath12k_peer_find_by_id(ab, peer_id);
  1346. if (!peer) {
  1347. spin_unlock_bh(&ab->base_lock);
  1348. continue;
  1349. }
  1350. usr_stats = &ppdu_info->ppdu_stats.user_stats[i];
  1351. if (peer->delayba_flag)
  1352. ath12k_copy_to_bar(peer, usr_stats);
  1353. spin_unlock_bh(&ab->base_lock);
  1354. }
  1355. }
  1356. spin_unlock_bh(&ar->data_lock);
  1357. exit:
  1358. rcu_read_unlock();
  1359. return ret;
  1360. }
  1361. static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab,
  1362. struct sk_buff *skb)
  1363. {
  1364. struct ath12k_htt_mlo_offset_msg *msg;
  1365. struct ath12k_pdev *pdev;
  1366. struct ath12k *ar;
  1367. u8 pdev_id;
  1368. msg = (struct ath12k_htt_mlo_offset_msg *)skb->data;
  1369. pdev_id = u32_get_bits(__le32_to_cpu(msg->info),
  1370. HTT_T2H_MLO_OFFSET_INFO_PDEV_ID);
  1371. rcu_read_lock();
  1372. ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id);
  1373. if (!ar) {
  1374. ath12k_warn(ab, "invalid pdev id %d on htt mlo offset\n", pdev_id);
  1375. goto exit;
  1376. }
  1377. spin_lock_bh(&ar->data_lock);
  1378. pdev = ar->pdev;
  1379. pdev->timestamp.info = __le32_to_cpu(msg->info);
  1380. pdev->timestamp.sync_timestamp_lo_us = __le32_to_cpu(msg->sync_timestamp_lo_us);
  1381. pdev->timestamp.sync_timestamp_hi_us = __le32_to_cpu(msg->sync_timestamp_hi_us);
  1382. pdev->timestamp.mlo_offset_lo = __le32_to_cpu(msg->mlo_offset_lo);
  1383. pdev->timestamp.mlo_offset_hi = __le32_to_cpu(msg->mlo_offset_hi);
  1384. pdev->timestamp.mlo_offset_clks = __le32_to_cpu(msg->mlo_offset_clks);
  1385. pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks);
  1386. pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer);
  1387. spin_unlock_bh(&ar->data_lock);
  1388. exit:
  1389. rcu_read_unlock();
  1390. }
  1391. void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab,
  1392. struct sk_buff *skb)
  1393. {
  1394. struct ath12k_dp *dp = &ab->dp;
  1395. struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
  1396. enum htt_t2h_msg_type type;
  1397. u16 peer_id;
  1398. u8 vdev_id;
  1399. u8 mac_addr[ETH_ALEN];
  1400. u16 peer_mac_h16;
  1401. u16 ast_hash = 0;
  1402. u16 hw_peer_id;
  1403. type = le32_get_bits(resp->version_msg.version, HTT_T2H_MSG_TYPE);
  1404. ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
  1405. switch (type) {
  1406. case HTT_T2H_MSG_TYPE_VERSION_CONF:
  1407. dp->htt_tgt_ver_major = le32_get_bits(resp->version_msg.version,
  1408. HTT_T2H_VERSION_CONF_MAJOR);
  1409. dp->htt_tgt_ver_minor = le32_get_bits(resp->version_msg.version,
  1410. HTT_T2H_VERSION_CONF_MINOR);
  1411. complete(&dp->htt_tgt_version_received);
  1412. break;
  1413. /* TODO: remove unused peer map versions after testing */
  1414. case HTT_T2H_MSG_TYPE_PEER_MAP:
  1415. vdev_id = le32_get_bits(resp->peer_map_ev.info,
  1416. HTT_T2H_PEER_MAP_INFO_VDEV_ID);
  1417. peer_id = le32_get_bits(resp->peer_map_ev.info,
  1418. HTT_T2H_PEER_MAP_INFO_PEER_ID);
  1419. peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
  1420. HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
  1421. ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
  1422. peer_mac_h16, mac_addr);
  1423. ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
  1424. break;
  1425. case HTT_T2H_MSG_TYPE_PEER_MAP2:
  1426. vdev_id = le32_get_bits(resp->peer_map_ev.info,
  1427. HTT_T2H_PEER_MAP_INFO_VDEV_ID);
  1428. peer_id = le32_get_bits(resp->peer_map_ev.info,
  1429. HTT_T2H_PEER_MAP_INFO_PEER_ID);
  1430. peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
  1431. HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
  1432. ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
  1433. peer_mac_h16, mac_addr);
  1434. ast_hash = le32_get_bits(resp->peer_map_ev.info2,
  1435. HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL);
  1436. hw_peer_id = le32_get_bits(resp->peer_map_ev.info1,
  1437. HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID);
  1438. ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
  1439. hw_peer_id);
  1440. break;
  1441. case HTT_T2H_MSG_TYPE_PEER_MAP3:
  1442. vdev_id = le32_get_bits(resp->peer_map_ev.info,
  1443. HTT_T2H_PEER_MAP_INFO_VDEV_ID);
  1444. peer_id = le32_get_bits(resp->peer_map_ev.info,
  1445. HTT_T2H_PEER_MAP_INFO_PEER_ID);
  1446. peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1,
  1447. HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16);
  1448. ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32),
  1449. peer_mac_h16, mac_addr);
  1450. ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
  1451. peer_id);
  1452. break;
  1453. case HTT_T2H_MSG_TYPE_PEER_UNMAP:
  1454. case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
  1455. peer_id = le32_get_bits(resp->peer_unmap_ev.info,
  1456. HTT_T2H_PEER_UNMAP_INFO_PEER_ID);
  1457. ath12k_peer_unmap_event(ab, peer_id);
  1458. break;
  1459. case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
  1460. ath12k_htt_pull_ppdu_stats(ab, skb);
  1461. break;
  1462. case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
  1463. ath12k_debugfs_htt_ext_stats_handler(ab, skb);
  1464. break;
  1465. case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND:
  1466. ath12k_htt_mlo_offset_event_handler(ab, skb);
  1467. break;
  1468. default:
  1469. ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n",
  1470. type);
  1471. break;
  1472. }
  1473. dev_kfree_skb_any(skb);
  1474. }
  1475. static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar,
  1476. struct sk_buff_head *msdu_list,
  1477. struct sk_buff *first, struct sk_buff *last,
  1478. u8 l3pad_bytes, int msdu_len)
  1479. {
  1480. struct ath12k_base *ab = ar->ab;
  1481. struct sk_buff *skb;
  1482. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first);
  1483. int buf_first_hdr_len, buf_first_len;
  1484. struct hal_rx_desc *ldesc;
  1485. int space_extra, rem_len, buf_len;
  1486. u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
  1487. bool is_continuation;
  1488. /* As the msdu is spread across multiple rx buffers,
  1489. * find the offset to the start of msdu for computing
  1490. * the length of the msdu in the first buffer.
  1491. */
  1492. buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
  1493. buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
  1494. if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
  1495. skb_put(first, buf_first_hdr_len + msdu_len);
  1496. skb_pull(first, buf_first_hdr_len);
  1497. return 0;
  1498. }
  1499. ldesc = (struct hal_rx_desc *)last->data;
  1500. rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc);
  1501. rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc);
  1502. /* MSDU spans over multiple buffers because the length of the MSDU
  1503. * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
  1504. * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
  1505. */
  1506. skb_put(first, DP_RX_BUFFER_SIZE);
  1507. skb_pull(first, buf_first_hdr_len);
  1508. /* When an MSDU spread over multiple buffers MSDU_END
  1509. * tlvs are valid only in the last buffer. Copy those tlvs.
  1510. */
  1511. ath12k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
  1512. space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
  1513. if (space_extra > 0 &&
  1514. (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
  1515. /* Free up all buffers of the MSDU */
  1516. while ((skb = __skb_dequeue(msdu_list)) != NULL) {
  1517. rxcb = ATH12K_SKB_RXCB(skb);
  1518. if (!rxcb->is_continuation) {
  1519. dev_kfree_skb_any(skb);
  1520. break;
  1521. }
  1522. dev_kfree_skb_any(skb);
  1523. }
  1524. return -ENOMEM;
  1525. }
  1526. rem_len = msdu_len - buf_first_len;
  1527. while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
  1528. rxcb = ATH12K_SKB_RXCB(skb);
  1529. is_continuation = rxcb->is_continuation;
  1530. if (is_continuation)
  1531. buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
  1532. else
  1533. buf_len = rem_len;
  1534. if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
  1535. WARN_ON_ONCE(1);
  1536. dev_kfree_skb_any(skb);
  1537. return -EINVAL;
  1538. }
  1539. skb_put(skb, buf_len + hal_rx_desc_sz);
  1540. skb_pull(skb, hal_rx_desc_sz);
  1541. skb_copy_from_linear_data(skb, skb_put(first, buf_len),
  1542. buf_len);
  1543. dev_kfree_skb_any(skb);
  1544. rem_len -= buf_len;
  1545. if (!is_continuation)
  1546. break;
  1547. }
  1548. return 0;
  1549. }
  1550. static struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
  1551. struct sk_buff *first)
  1552. {
  1553. struct sk_buff *skb;
  1554. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first);
  1555. if (!rxcb->is_continuation)
  1556. return first;
  1557. skb_queue_walk(msdu_list, skb) {
  1558. rxcb = ATH12K_SKB_RXCB(skb);
  1559. if (!rxcb->is_continuation)
  1560. return skb;
  1561. }
  1562. return NULL;
  1563. }
  1564. static void ath12k_dp_rx_h_csum_offload(struct ath12k *ar, struct sk_buff *msdu)
  1565. {
  1566. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
  1567. struct ath12k_base *ab = ar->ab;
  1568. bool ip_csum_fail, l4_csum_fail;
  1569. ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rxcb->rx_desc);
  1570. l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rxcb->rx_desc);
  1571. msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
  1572. CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
  1573. }
  1574. int ath12k_dp_rx_crypto_mic_len(struct ath12k *ar, enum hal_encrypt_type enctype)
  1575. {
  1576. switch (enctype) {
  1577. case HAL_ENCRYPT_TYPE_OPEN:
  1578. case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
  1579. case HAL_ENCRYPT_TYPE_TKIP_MIC:
  1580. return 0;
  1581. case HAL_ENCRYPT_TYPE_CCMP_128:
  1582. return IEEE80211_CCMP_MIC_LEN;
  1583. case HAL_ENCRYPT_TYPE_CCMP_256:
  1584. return IEEE80211_CCMP_256_MIC_LEN;
  1585. case HAL_ENCRYPT_TYPE_GCMP_128:
  1586. case HAL_ENCRYPT_TYPE_AES_GCMP_256:
  1587. return IEEE80211_GCMP_MIC_LEN;
  1588. case HAL_ENCRYPT_TYPE_WEP_40:
  1589. case HAL_ENCRYPT_TYPE_WEP_104:
  1590. case HAL_ENCRYPT_TYPE_WEP_128:
  1591. case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
  1592. case HAL_ENCRYPT_TYPE_WAPI:
  1593. break;
  1594. }
  1595. ath12k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
  1596. return 0;
  1597. }
  1598. static int ath12k_dp_rx_crypto_param_len(struct ath12k *ar,
  1599. enum hal_encrypt_type enctype)
  1600. {
  1601. switch (enctype) {
  1602. case HAL_ENCRYPT_TYPE_OPEN:
  1603. return 0;
  1604. case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
  1605. case HAL_ENCRYPT_TYPE_TKIP_MIC:
  1606. return IEEE80211_TKIP_IV_LEN;
  1607. case HAL_ENCRYPT_TYPE_CCMP_128:
  1608. return IEEE80211_CCMP_HDR_LEN;
  1609. case HAL_ENCRYPT_TYPE_CCMP_256:
  1610. return IEEE80211_CCMP_256_HDR_LEN;
  1611. case HAL_ENCRYPT_TYPE_GCMP_128:
  1612. case HAL_ENCRYPT_TYPE_AES_GCMP_256:
  1613. return IEEE80211_GCMP_HDR_LEN;
  1614. case HAL_ENCRYPT_TYPE_WEP_40:
  1615. case HAL_ENCRYPT_TYPE_WEP_104:
  1616. case HAL_ENCRYPT_TYPE_WEP_128:
  1617. case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
  1618. case HAL_ENCRYPT_TYPE_WAPI:
  1619. break;
  1620. }
  1621. ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
  1622. return 0;
  1623. }
  1624. static int ath12k_dp_rx_crypto_icv_len(struct ath12k *ar,
  1625. enum hal_encrypt_type enctype)
  1626. {
  1627. switch (enctype) {
  1628. case HAL_ENCRYPT_TYPE_OPEN:
  1629. case HAL_ENCRYPT_TYPE_CCMP_128:
  1630. case HAL_ENCRYPT_TYPE_CCMP_256:
  1631. case HAL_ENCRYPT_TYPE_GCMP_128:
  1632. case HAL_ENCRYPT_TYPE_AES_GCMP_256:
  1633. return 0;
  1634. case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
  1635. case HAL_ENCRYPT_TYPE_TKIP_MIC:
  1636. return IEEE80211_TKIP_ICV_LEN;
  1637. case HAL_ENCRYPT_TYPE_WEP_40:
  1638. case HAL_ENCRYPT_TYPE_WEP_104:
  1639. case HAL_ENCRYPT_TYPE_WEP_128:
  1640. case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
  1641. case HAL_ENCRYPT_TYPE_WAPI:
  1642. break;
  1643. }
  1644. ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
  1645. return 0;
  1646. }
  1647. static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k *ar,
  1648. struct sk_buff *msdu,
  1649. enum hal_encrypt_type enctype,
  1650. struct ieee80211_rx_status *status)
  1651. {
  1652. struct ath12k_base *ab = ar->ab;
  1653. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
  1654. u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
  1655. struct ieee80211_hdr *hdr;
  1656. size_t hdr_len;
  1657. u8 *crypto_hdr;
  1658. u16 qos_ctl;
  1659. /* pull decapped header */
  1660. hdr = (struct ieee80211_hdr *)msdu->data;
  1661. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  1662. skb_pull(msdu, hdr_len);
  1663. /* Rebuild qos header */
  1664. hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
  1665. /* Reset the order bit as the HT_Control header is stripped */
  1666. hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
  1667. qos_ctl = rxcb->tid;
  1668. if (ath12k_dp_rx_h_mesh_ctl_present(ab, rxcb->rx_desc))
  1669. qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
  1670. /* TODO: Add other QoS ctl fields when required */
  1671. /* copy decap header before overwriting for reuse below */
  1672. memcpy(decap_hdr, hdr, hdr_len);
  1673. /* Rebuild crypto header for mac80211 use */
  1674. if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
  1675. crypto_hdr = skb_push(msdu, ath12k_dp_rx_crypto_param_len(ar, enctype));
  1676. ath12k_dp_rx_desc_get_crypto_header(ar->ab,
  1677. rxcb->rx_desc, crypto_hdr,
  1678. enctype);
  1679. }
  1680. memcpy(skb_push(msdu,
  1681. IEEE80211_QOS_CTL_LEN), &qos_ctl,
  1682. IEEE80211_QOS_CTL_LEN);
  1683. memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
  1684. }
  1685. static void ath12k_dp_rx_h_undecap_raw(struct ath12k *ar, struct sk_buff *msdu,
  1686. enum hal_encrypt_type enctype,
  1687. struct ieee80211_rx_status *status,
  1688. bool decrypted)
  1689. {
  1690. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
  1691. struct ieee80211_hdr *hdr;
  1692. size_t hdr_len;
  1693. size_t crypto_len;
  1694. if (!rxcb->is_first_msdu ||
  1695. !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
  1696. WARN_ON_ONCE(1);
  1697. return;
  1698. }
  1699. skb_trim(msdu, msdu->len - FCS_LEN);
  1700. if (!decrypted)
  1701. return;
  1702. hdr = (void *)msdu->data;
  1703. /* Tail */
  1704. if (status->flag & RX_FLAG_IV_STRIPPED) {
  1705. skb_trim(msdu, msdu->len -
  1706. ath12k_dp_rx_crypto_mic_len(ar, enctype));
  1707. skb_trim(msdu, msdu->len -
  1708. ath12k_dp_rx_crypto_icv_len(ar, enctype));
  1709. } else {
  1710. /* MIC */
  1711. if (status->flag & RX_FLAG_MIC_STRIPPED)
  1712. skb_trim(msdu, msdu->len -
  1713. ath12k_dp_rx_crypto_mic_len(ar, enctype));
  1714. /* ICV */
  1715. if (status->flag & RX_FLAG_ICV_STRIPPED)
  1716. skb_trim(msdu, msdu->len -
  1717. ath12k_dp_rx_crypto_icv_len(ar, enctype));
  1718. }
  1719. /* MMIC */
  1720. if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
  1721. !ieee80211_has_morefrags(hdr->frame_control) &&
  1722. enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
  1723. skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
  1724. /* Head */
  1725. if (status->flag & RX_FLAG_IV_STRIPPED) {
  1726. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  1727. crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
  1728. memmove(msdu->data + crypto_len, msdu->data, hdr_len);
  1729. skb_pull(msdu, crypto_len);
  1730. }
  1731. }
  1732. static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k *ar,
  1733. struct sk_buff *msdu,
  1734. struct ath12k_skb_rxcb *rxcb,
  1735. struct ieee80211_rx_status *status,
  1736. enum hal_encrypt_type enctype)
  1737. {
  1738. struct hal_rx_desc *rx_desc = rxcb->rx_desc;
  1739. struct ath12k_base *ab = ar->ab;
  1740. size_t hdr_len, crypto_len;
  1741. struct ieee80211_hdr hdr;
  1742. __le16 qos_ctl;
  1743. u8 *crypto_hdr, mesh_ctrl;
  1744. ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, &hdr);
  1745. hdr_len = ieee80211_hdrlen(hdr.frame_control);
  1746. mesh_ctrl = ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc);
  1747. if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
  1748. crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
  1749. crypto_hdr = skb_push(msdu, crypto_len);
  1750. ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype);
  1751. }
  1752. skb_push(msdu, hdr_len);
  1753. memcpy(msdu->data, &hdr, min(hdr_len, sizeof(hdr)));
  1754. if (rxcb->is_mcbc)
  1755. status->flag &= ~RX_FLAG_PN_VALIDATED;
  1756. /* Add QOS header */
  1757. if (ieee80211_is_data_qos(hdr.frame_control)) {
  1758. struct ieee80211_hdr *qos_ptr = (struct ieee80211_hdr *)msdu->data;
  1759. qos_ctl = cpu_to_le16(rxcb->tid & IEEE80211_QOS_CTL_TID_MASK);
  1760. if (mesh_ctrl)
  1761. qos_ctl |= cpu_to_le16(IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT);
  1762. memcpy(ieee80211_get_qos_ctl(qos_ptr), &qos_ctl, IEEE80211_QOS_CTL_LEN);
  1763. }
  1764. }
  1765. static void ath12k_dp_rx_h_undecap_eth(struct ath12k *ar,
  1766. struct sk_buff *msdu,
  1767. enum hal_encrypt_type enctype,
  1768. struct ieee80211_rx_status *status)
  1769. {
  1770. struct ieee80211_hdr *hdr;
  1771. struct ethhdr *eth;
  1772. u8 da[ETH_ALEN];
  1773. u8 sa[ETH_ALEN];
  1774. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
  1775. struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}};
  1776. eth = (struct ethhdr *)msdu->data;
  1777. ether_addr_copy(da, eth->h_dest);
  1778. ether_addr_copy(sa, eth->h_source);
  1779. rfc.snap_type = eth->h_proto;
  1780. skb_pull(msdu, sizeof(*eth));
  1781. memcpy(skb_push(msdu, sizeof(rfc)), &rfc,
  1782. sizeof(rfc));
  1783. ath12k_get_dot11_hdr_from_rx_desc(ar, msdu, rxcb, status, enctype);
  1784. /* original 802.11 header has a different DA and in
  1785. * case of 4addr it may also have different SA
  1786. */
  1787. hdr = (struct ieee80211_hdr *)msdu->data;
  1788. ether_addr_copy(ieee80211_get_DA(hdr), da);
  1789. ether_addr_copy(ieee80211_get_SA(hdr), sa);
  1790. }
  1791. static void ath12k_dp_rx_h_undecap(struct ath12k *ar, struct sk_buff *msdu,
  1792. struct hal_rx_desc *rx_desc,
  1793. enum hal_encrypt_type enctype,
  1794. struct ieee80211_rx_status *status,
  1795. bool decrypted)
  1796. {
  1797. struct ath12k_base *ab = ar->ab;
  1798. u8 decap;
  1799. struct ethhdr *ehdr;
  1800. decap = ath12k_dp_rx_h_decap_type(ab, rx_desc);
  1801. switch (decap) {
  1802. case DP_RX_DECAP_TYPE_NATIVE_WIFI:
  1803. ath12k_dp_rx_h_undecap_nwifi(ar, msdu, enctype, status);
  1804. break;
  1805. case DP_RX_DECAP_TYPE_RAW:
  1806. ath12k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
  1807. decrypted);
  1808. break;
  1809. case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
  1810. ehdr = (struct ethhdr *)msdu->data;
  1811. /* mac80211 allows fast path only for authorized STA */
  1812. if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
  1813. ATH12K_SKB_RXCB(msdu)->is_eapol = true;
  1814. ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status);
  1815. break;
  1816. }
  1817. /* PN for mcast packets will be validated in mac80211;
  1818. * remove eth header and add 802.11 header.
  1819. */
  1820. if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted)
  1821. ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status);
  1822. break;
  1823. case DP_RX_DECAP_TYPE_8023:
  1824. /* TODO: Handle undecap for these formats */
  1825. break;
  1826. }
  1827. }
  1828. struct ath12k_peer *
  1829. ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu)
  1830. {
  1831. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
  1832. struct hal_rx_desc *rx_desc = rxcb->rx_desc;
  1833. struct ath12k_peer *peer = NULL;
  1834. lockdep_assert_held(&ab->base_lock);
  1835. if (rxcb->peer_id)
  1836. peer = ath12k_peer_find_by_id(ab, rxcb->peer_id);
  1837. if (peer)
  1838. return peer;
  1839. if (!rx_desc || !(ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
  1840. return NULL;
  1841. peer = ath12k_peer_find_by_addr(ab,
  1842. ath12k_dp_rxdesc_get_mpdu_start_addr2(ab,
  1843. rx_desc));
  1844. return peer;
  1845. }
  1846. static void ath12k_dp_rx_h_mpdu(struct ath12k *ar,
  1847. struct sk_buff *msdu,
  1848. struct hal_rx_desc *rx_desc,
  1849. struct ieee80211_rx_status *rx_status)
  1850. {
  1851. bool fill_crypto_hdr;
  1852. struct ath12k_base *ab = ar->ab;
  1853. struct ath12k_skb_rxcb *rxcb;
  1854. enum hal_encrypt_type enctype;
  1855. bool is_decrypted = false;
  1856. struct ieee80211_hdr *hdr;
  1857. struct ath12k_peer *peer;
  1858. u32 err_bitmap;
  1859. /* PN for multicast packets will be checked in mac80211 */
  1860. rxcb = ATH12K_SKB_RXCB(msdu);
  1861. fill_crypto_hdr = ath12k_dp_rx_h_is_da_mcbc(ar->ab, rx_desc);
  1862. rxcb->is_mcbc = fill_crypto_hdr;
  1863. if (rxcb->is_mcbc)
  1864. rxcb->peer_id = ath12k_dp_rx_h_peer_id(ar->ab, rx_desc);
  1865. spin_lock_bh(&ar->ab->base_lock);
  1866. peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu);
  1867. if (peer) {
  1868. if (rxcb->is_mcbc)
  1869. enctype = peer->sec_type_grp;
  1870. else
  1871. enctype = peer->sec_type;
  1872. } else {
  1873. enctype = HAL_ENCRYPT_TYPE_OPEN;
  1874. }
  1875. spin_unlock_bh(&ar->ab->base_lock);
  1876. err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc);
  1877. if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
  1878. is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc);
  1879. /* Clear per-MPDU flags while leaving per-PPDU flags intact */
  1880. rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
  1881. RX_FLAG_MMIC_ERROR |
  1882. RX_FLAG_DECRYPTED |
  1883. RX_FLAG_IV_STRIPPED |
  1884. RX_FLAG_MMIC_STRIPPED);
  1885. if (err_bitmap & HAL_RX_MPDU_ERR_FCS)
  1886. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  1887. if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC)
  1888. rx_status->flag |= RX_FLAG_MMIC_ERROR;
  1889. if (is_decrypted) {
  1890. rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
  1891. if (fill_crypto_hdr)
  1892. rx_status->flag |= RX_FLAG_MIC_STRIPPED |
  1893. RX_FLAG_ICV_STRIPPED;
  1894. else
  1895. rx_status->flag |= RX_FLAG_IV_STRIPPED |
  1896. RX_FLAG_PN_VALIDATED;
  1897. }
  1898. ath12k_dp_rx_h_csum_offload(ar, msdu);
  1899. ath12k_dp_rx_h_undecap(ar, msdu, rx_desc,
  1900. enctype, rx_status, is_decrypted);
  1901. if (!is_decrypted || fill_crypto_hdr)
  1902. return;
  1903. if (ath12k_dp_rx_h_decap_type(ar->ab, rx_desc) !=
  1904. DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
  1905. hdr = (void *)msdu->data;
  1906. hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
  1907. }
  1908. }
  1909. static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct hal_rx_desc *rx_desc,
  1910. struct ieee80211_rx_status *rx_status)
  1911. {
  1912. struct ath12k_base *ab = ar->ab;
  1913. struct ieee80211_supported_band *sband;
  1914. enum rx_msdu_start_pkt_type pkt_type;
  1915. u8 bw;
  1916. u8 rate_mcs, nss;
  1917. u8 sgi;
  1918. bool is_cck;
  1919. pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc);
  1920. bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc);
  1921. rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc);
  1922. nss = ath12k_dp_rx_h_nss(ab, rx_desc);
  1923. sgi = ath12k_dp_rx_h_sgi(ab, rx_desc);
  1924. switch (pkt_type) {
  1925. case RX_MSDU_START_PKT_TYPE_11A:
  1926. case RX_MSDU_START_PKT_TYPE_11B:
  1927. is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
  1928. sband = &ar->mac.sbands[rx_status->band];
  1929. rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs,
  1930. is_cck);
  1931. break;
  1932. case RX_MSDU_START_PKT_TYPE_11N:
  1933. rx_status->encoding = RX_ENC_HT;
  1934. if (rate_mcs > ATH12K_HT_MCS_MAX) {
  1935. ath12k_warn(ar->ab,
  1936. "Received with invalid mcs in HT mode %d\n",
  1937. rate_mcs);
  1938. break;
  1939. }
  1940. rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
  1941. if (sgi)
  1942. rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
  1943. rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
  1944. break;
  1945. case RX_MSDU_START_PKT_TYPE_11AC:
  1946. rx_status->encoding = RX_ENC_VHT;
  1947. rx_status->rate_idx = rate_mcs;
  1948. if (rate_mcs > ATH12K_VHT_MCS_MAX) {
  1949. ath12k_warn(ar->ab,
  1950. "Received with invalid mcs in VHT mode %d\n",
  1951. rate_mcs);
  1952. break;
  1953. }
  1954. rx_status->nss = nss;
  1955. if (sgi)
  1956. rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
  1957. rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
  1958. break;
  1959. case RX_MSDU_START_PKT_TYPE_11AX:
  1960. rx_status->rate_idx = rate_mcs;
  1961. if (rate_mcs > ATH12K_HE_MCS_MAX) {
  1962. ath12k_warn(ar->ab,
  1963. "Received with invalid mcs in HE mode %d\n",
  1964. rate_mcs);
  1965. break;
  1966. }
  1967. rx_status->encoding = RX_ENC_HE;
  1968. rx_status->nss = nss;
  1969. rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi);
  1970. rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw);
  1971. break;
  1972. }
  1973. }
  1974. void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct hal_rx_desc *rx_desc,
  1975. struct ieee80211_rx_status *rx_status)
  1976. {
  1977. struct ath12k_base *ab = ar->ab;
  1978. u8 channel_num;
  1979. u32 center_freq, meta_data;
  1980. struct ieee80211_channel *channel;
  1981. rx_status->freq = 0;
  1982. rx_status->rate_idx = 0;
  1983. rx_status->nss = 0;
  1984. rx_status->encoding = RX_ENC_LEGACY;
  1985. rx_status->bw = RATE_INFO_BW_20;
  1986. rx_status->enc_flags = 0;
  1987. rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
  1988. meta_data = ath12k_dp_rx_h_freq(ab, rx_desc);
  1989. channel_num = meta_data;
  1990. center_freq = meta_data >> 16;
  1991. if (center_freq >= ATH12K_MIN_6G_FREQ &&
  1992. center_freq <= ATH12K_MAX_6G_FREQ) {
  1993. rx_status->band = NL80211_BAND_6GHZ;
  1994. rx_status->freq = center_freq;
  1995. } else if (channel_num >= 1 && channel_num <= 14) {
  1996. rx_status->band = NL80211_BAND_2GHZ;
  1997. } else if (channel_num >= 36 && channel_num <= 173) {
  1998. rx_status->band = NL80211_BAND_5GHZ;
  1999. } else {
  2000. spin_lock_bh(&ar->data_lock);
  2001. channel = ar->rx_channel;
  2002. if (channel) {
  2003. rx_status->band = channel->band;
  2004. channel_num =
  2005. ieee80211_frequency_to_channel(channel->center_freq);
  2006. }
  2007. spin_unlock_bh(&ar->data_lock);
  2008. ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "rx_desc: ",
  2009. rx_desc, sizeof(*rx_desc));
  2010. }
  2011. if (rx_status->band != NL80211_BAND_6GHZ)
  2012. rx_status->freq = ieee80211_channel_to_frequency(channel_num,
  2013. rx_status->band);
  2014. ath12k_dp_rx_h_rate(ar, rx_desc, rx_status);
  2015. }
  2016. static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi,
  2017. struct sk_buff *msdu,
  2018. struct ieee80211_rx_status *status)
  2019. {
  2020. struct ath12k_base *ab = ar->ab;
  2021. static const struct ieee80211_radiotap_he known = {
  2022. .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
  2023. IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
  2024. .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
  2025. };
  2026. struct ieee80211_radiotap_he *he;
  2027. struct ieee80211_rx_status *rx_status;
  2028. struct ieee80211_sta *pubsta;
  2029. struct ath12k_peer *peer;
  2030. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
  2031. u8 decap = DP_RX_DECAP_TYPE_RAW;
  2032. bool is_mcbc = rxcb->is_mcbc;
  2033. bool is_eapol = rxcb->is_eapol;
  2034. if (status->encoding == RX_ENC_HE && !(status->flag & RX_FLAG_RADIOTAP_HE) &&
  2035. !(status->flag & RX_FLAG_SKIP_MONITOR)) {
  2036. he = skb_push(msdu, sizeof(known));
  2037. memcpy(he, &known, sizeof(known));
  2038. status->flag |= RX_FLAG_RADIOTAP_HE;
  2039. }
  2040. if (!(status->flag & RX_FLAG_ONLY_MONITOR))
  2041. decap = ath12k_dp_rx_h_decap_type(ab, rxcb->rx_desc);
  2042. spin_lock_bh(&ab->base_lock);
  2043. peer = ath12k_dp_rx_h_find_peer(ab, msdu);
  2044. pubsta = peer ? peer->sta : NULL;
  2045. spin_unlock_bh(&ab->base_lock);
  2046. ath12k_dbg(ab, ATH12K_DBG_DATA,
  2047. "rx skb %p len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
  2048. msdu,
  2049. msdu->len,
  2050. peer ? peer->addr : NULL,
  2051. rxcb->tid,
  2052. is_mcbc ? "mcast" : "ucast",
  2053. ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc),
  2054. (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
  2055. (status->encoding == RX_ENC_HT) ? "ht" : "",
  2056. (status->encoding == RX_ENC_VHT) ? "vht" : "",
  2057. (status->encoding == RX_ENC_HE) ? "he" : "",
  2058. (status->bw == RATE_INFO_BW_40) ? "40" : "",
  2059. (status->bw == RATE_INFO_BW_80) ? "80" : "",
  2060. (status->bw == RATE_INFO_BW_160) ? "160" : "",
  2061. (status->bw == RATE_INFO_BW_320) ? "320" : "",
  2062. status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
  2063. status->rate_idx,
  2064. status->nss,
  2065. status->freq,
  2066. status->band, status->flag,
  2067. !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
  2068. !!(status->flag & RX_FLAG_MMIC_ERROR),
  2069. !!(status->flag & RX_FLAG_AMSDU_MORE));
  2070. ath12k_dbg_dump(ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ",
  2071. msdu->data, msdu->len);
  2072. rx_status = IEEE80211_SKB_RXCB(msdu);
  2073. *rx_status = *status;
  2074. /* TODO: trace rx packet */
  2075. /* PN for multicast packets are not validate in HW,
  2076. * so skip 802.3 rx path
  2077. * Also, fast_rx expects the STA to be authorized, hence
  2078. * eapol packets are sent in slow path.
  2079. */
  2080. if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
  2081. !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
  2082. rx_status->flag |= RX_FLAG_8023;
  2083. ieee80211_rx_napi(ath12k_ar_to_hw(ar), pubsta, msdu, napi);
  2084. }
  2085. static bool ath12k_dp_rx_check_nwifi_hdr_len_valid(struct ath12k_base *ab,
  2086. struct hal_rx_desc *rx_desc,
  2087. struct sk_buff *msdu)
  2088. {
  2089. struct ieee80211_hdr *hdr;
  2090. u8 decap_type;
  2091. u32 hdr_len;
  2092. decap_type = ath12k_dp_rx_h_decap_type(ab, rx_desc);
  2093. if (decap_type != DP_RX_DECAP_TYPE_NATIVE_WIFI)
  2094. return true;
  2095. hdr = (struct ieee80211_hdr *)msdu->data;
  2096. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  2097. if ((likely(hdr_len <= DP_MAX_NWIFI_HDR_LEN)))
  2098. return true;
  2099. ab->soc_stats.invalid_rbm++;
  2100. WARN_ON_ONCE(1);
  2101. return false;
  2102. }
  2103. static int ath12k_dp_rx_process_msdu(struct ath12k *ar,
  2104. struct sk_buff *msdu,
  2105. struct sk_buff_head *msdu_list,
  2106. struct ieee80211_rx_status *rx_status)
  2107. {
  2108. struct ath12k_base *ab = ar->ab;
  2109. struct hal_rx_desc *rx_desc, *lrx_desc;
  2110. struct ath12k_skb_rxcb *rxcb;
  2111. struct sk_buff *last_buf;
  2112. u8 l3_pad_bytes;
  2113. u16 msdu_len;
  2114. int ret;
  2115. u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
  2116. last_buf = ath12k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
  2117. if (!last_buf) {
  2118. ath12k_warn(ab,
  2119. "No valid Rx buffer to access MSDU_END tlv\n");
  2120. ret = -EIO;
  2121. goto free_out;
  2122. }
  2123. rx_desc = (struct hal_rx_desc *)msdu->data;
  2124. lrx_desc = (struct hal_rx_desc *)last_buf->data;
  2125. if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) {
  2126. ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n");
  2127. ret = -EIO;
  2128. goto free_out;
  2129. }
  2130. rxcb = ATH12K_SKB_RXCB(msdu);
  2131. rxcb->rx_desc = rx_desc;
  2132. msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc);
  2133. l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc);
  2134. if (rxcb->is_frag) {
  2135. skb_pull(msdu, hal_rx_desc_sz);
  2136. } else if (!rxcb->is_continuation) {
  2137. if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
  2138. ret = -EINVAL;
  2139. ath12k_warn(ab, "invalid msdu len %u\n", msdu_len);
  2140. ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", rx_desc,
  2141. sizeof(*rx_desc));
  2142. goto free_out;
  2143. }
  2144. skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
  2145. skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
  2146. } else {
  2147. ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list,
  2148. msdu, last_buf,
  2149. l3_pad_bytes, msdu_len);
  2150. if (ret) {
  2151. ath12k_warn(ab,
  2152. "failed to coalesce msdu rx buffer%d\n", ret);
  2153. goto free_out;
  2154. }
  2155. }
  2156. if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu))) {
  2157. ret = -EINVAL;
  2158. goto free_out;
  2159. }
  2160. ath12k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
  2161. ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
  2162. rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
  2163. return 0;
  2164. free_out:
  2165. return ret;
  2166. }
  2167. static void ath12k_dp_rx_process_received_packets(struct ath12k_base *ab,
  2168. struct napi_struct *napi,
  2169. struct sk_buff_head *msdu_list,
  2170. int ring_id)
  2171. {
  2172. struct ieee80211_rx_status rx_status = {0};
  2173. struct ath12k_skb_rxcb *rxcb;
  2174. struct sk_buff *msdu;
  2175. struct ath12k *ar;
  2176. u8 mac_id, pdev_id;
  2177. int ret;
  2178. if (skb_queue_empty(msdu_list))
  2179. return;
  2180. rcu_read_lock();
  2181. while ((msdu = __skb_dequeue(msdu_list))) {
  2182. rxcb = ATH12K_SKB_RXCB(msdu);
  2183. mac_id = rxcb->mac_id;
  2184. pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
  2185. ar = ab->pdevs[pdev_id].ar;
  2186. if (!rcu_dereference(ab->pdevs_active[pdev_id])) {
  2187. dev_kfree_skb_any(msdu);
  2188. continue;
  2189. }
  2190. if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) {
  2191. dev_kfree_skb_any(msdu);
  2192. continue;
  2193. }
  2194. ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
  2195. if (ret) {
  2196. ath12k_dbg(ab, ATH12K_DBG_DATA,
  2197. "Unable to process msdu %d", ret);
  2198. dev_kfree_skb_any(msdu);
  2199. continue;
  2200. }
  2201. ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
  2202. }
  2203. rcu_read_unlock();
  2204. }
  2205. static u16 ath12k_dp_rx_get_peer_id(struct ath12k_base *ab,
  2206. enum ath12k_peer_metadata_version ver,
  2207. __le32 peer_metadata)
  2208. {
  2209. switch (ver) {
  2210. default:
  2211. ath12k_warn(ab, "Unknown peer metadata version: %d", ver);
  2212. fallthrough;
  2213. case ATH12K_PEER_METADATA_V0:
  2214. return le32_get_bits(peer_metadata,
  2215. RX_MPDU_DESC_META_DATA_V0_PEER_ID);
  2216. case ATH12K_PEER_METADATA_V1:
  2217. return le32_get_bits(peer_metadata,
  2218. RX_MPDU_DESC_META_DATA_V1_PEER_ID);
  2219. case ATH12K_PEER_METADATA_V1A:
  2220. return le32_get_bits(peer_metadata,
  2221. RX_MPDU_DESC_META_DATA_V1A_PEER_ID);
  2222. case ATH12K_PEER_METADATA_V1B:
  2223. return le32_get_bits(peer_metadata,
  2224. RX_MPDU_DESC_META_DATA_V1B_PEER_ID);
  2225. }
  2226. }
  2227. int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id,
  2228. struct napi_struct *napi, int budget)
  2229. {
  2230. LIST_HEAD(rx_desc_used_list);
  2231. struct ath12k_rx_desc_info *desc_info;
  2232. struct ath12k_dp *dp = &ab->dp;
  2233. struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
  2234. struct hal_reo_dest_ring *desc;
  2235. int num_buffs_reaped = 0;
  2236. struct sk_buff_head msdu_list;
  2237. struct ath12k_skb_rxcb *rxcb;
  2238. int total_msdu_reaped = 0;
  2239. struct hal_srng *srng;
  2240. struct sk_buff *msdu;
  2241. bool done = false;
  2242. int mac_id;
  2243. u64 desc_va;
  2244. __skb_queue_head_init(&msdu_list);
  2245. srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
  2246. spin_lock_bh(&srng->lock);
  2247. try_again:
  2248. ath12k_hal_srng_access_begin(ab, srng);
  2249. while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
  2250. struct rx_mpdu_desc *mpdu_info;
  2251. struct rx_msdu_desc *msdu_info;
  2252. enum hal_reo_dest_ring_push_reason push_reason;
  2253. u32 cookie;
  2254. cookie = le32_get_bits(desc->buf_addr_info.info1,
  2255. BUFFER_ADDR_INFO1_SW_COOKIE);
  2256. mac_id = le32_get_bits(desc->info0,
  2257. HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
  2258. desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 |
  2259. le32_to_cpu(desc->buf_va_lo));
  2260. desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va);
  2261. /* retry manual desc retrieval */
  2262. if (!desc_info) {
  2263. desc_info = ath12k_dp_get_rx_desc(ab, cookie);
  2264. if (!desc_info) {
  2265. ath12k_warn(ab, "Invalid cookie in manual descriptor retrieval: 0x%x\n",
  2266. cookie);
  2267. continue;
  2268. }
  2269. }
  2270. if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
  2271. ath12k_warn(ab, "Check HW CC implementation");
  2272. msdu = desc_info->skb;
  2273. desc_info->skb = NULL;
  2274. list_add_tail(&desc_info->list, &rx_desc_used_list);
  2275. rxcb = ATH12K_SKB_RXCB(msdu);
  2276. dma_unmap_single(ab->dev, rxcb->paddr,
  2277. msdu->len + skb_tailroom(msdu),
  2278. DMA_FROM_DEVICE);
  2279. num_buffs_reaped++;
  2280. push_reason = le32_get_bits(desc->info0,
  2281. HAL_REO_DEST_RING_INFO0_PUSH_REASON);
  2282. if (push_reason !=
  2283. HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
  2284. dev_kfree_skb_any(msdu);
  2285. ab->soc_stats.hal_reo_error[ring_id]++;
  2286. continue;
  2287. }
  2288. msdu_info = &desc->rx_msdu_info;
  2289. mpdu_info = &desc->rx_mpdu_info;
  2290. rxcb->is_first_msdu = !!(le32_to_cpu(msdu_info->info0) &
  2291. RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
  2292. rxcb->is_last_msdu = !!(le32_to_cpu(msdu_info->info0) &
  2293. RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
  2294. rxcb->is_continuation = !!(le32_to_cpu(msdu_info->info0) &
  2295. RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
  2296. rxcb->mac_id = mac_id;
  2297. rxcb->peer_id = ath12k_dp_rx_get_peer_id(ab, dp->peer_metadata_ver,
  2298. mpdu_info->peer_meta_data);
  2299. rxcb->tid = le32_get_bits(mpdu_info->info0,
  2300. RX_MPDU_DESC_INFO0_TID);
  2301. __skb_queue_tail(&msdu_list, msdu);
  2302. if (!rxcb->is_continuation) {
  2303. total_msdu_reaped++;
  2304. done = true;
  2305. } else {
  2306. done = false;
  2307. }
  2308. if (total_msdu_reaped >= budget)
  2309. break;
  2310. }
  2311. /* Hw might have updated the head pointer after we cached it.
  2312. * In this case, even though there are entries in the ring we'll
  2313. * get rx_desc NULL. Give the read another try with updated cached
  2314. * head pointer so that we can reap complete MPDU in the current
  2315. * rx processing.
  2316. */
  2317. if (!done && ath12k_hal_srng_dst_num_free(ab, srng, true)) {
  2318. ath12k_hal_srng_access_end(ab, srng);
  2319. goto try_again;
  2320. }
  2321. ath12k_hal_srng_access_end(ab, srng);
  2322. spin_unlock_bh(&srng->lock);
  2323. if (!total_msdu_reaped)
  2324. goto exit;
  2325. ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list,
  2326. num_buffs_reaped);
  2327. ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list,
  2328. ring_id);
  2329. exit:
  2330. return total_msdu_reaped;
  2331. }
  2332. static void ath12k_dp_rx_frag_timer(struct timer_list *timer)
  2333. {
  2334. struct ath12k_dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
  2335. spin_lock_bh(&rx_tid->ab->base_lock);
  2336. if (rx_tid->last_frag_no &&
  2337. rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
  2338. spin_unlock_bh(&rx_tid->ab->base_lock);
  2339. return;
  2340. }
  2341. ath12k_dp_rx_frags_cleanup(rx_tid, true);
  2342. spin_unlock_bh(&rx_tid->ab->base_lock);
  2343. }
  2344. int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id)
  2345. {
  2346. struct ath12k_base *ab = ar->ab;
  2347. struct crypto_shash *tfm;
  2348. struct ath12k_peer *peer;
  2349. struct ath12k_dp_rx_tid *rx_tid;
  2350. int i;
  2351. tfm = crypto_alloc_shash("michael_mic", 0, 0);
  2352. if (IS_ERR(tfm))
  2353. return PTR_ERR(tfm);
  2354. spin_lock_bh(&ab->base_lock);
  2355. peer = ath12k_peer_find(ab, vdev_id, peer_mac);
  2356. if (!peer) {
  2357. spin_unlock_bh(&ab->base_lock);
  2358. crypto_free_shash(tfm);
  2359. ath12k_warn(ab, "failed to find the peer to set up fragment info\n");
  2360. return -ENOENT;
  2361. }
  2362. for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
  2363. rx_tid = &peer->rx_tid[i];
  2364. rx_tid->ab = ab;
  2365. timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0);
  2366. skb_queue_head_init(&rx_tid->rx_frags);
  2367. }
  2368. peer->tfm_mmic = tfm;
  2369. peer->dp_setup_done = true;
  2370. spin_unlock_bh(&ab->base_lock);
  2371. return 0;
  2372. }
  2373. static int ath12k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
  2374. struct ieee80211_hdr *hdr, u8 *data,
  2375. size_t data_len, u8 *mic)
  2376. {
  2377. SHASH_DESC_ON_STACK(desc, tfm);
  2378. u8 mic_hdr[16] = {0};
  2379. u8 tid = 0;
  2380. int ret;
  2381. if (!tfm)
  2382. return -EINVAL;
  2383. desc->tfm = tfm;
  2384. ret = crypto_shash_setkey(tfm, key, 8);
  2385. if (ret)
  2386. goto out;
  2387. ret = crypto_shash_init(desc);
  2388. if (ret)
  2389. goto out;
  2390. /* TKIP MIC header */
  2391. memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
  2392. memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
  2393. if (ieee80211_is_data_qos(hdr->frame_control))
  2394. tid = ieee80211_get_tid(hdr);
  2395. mic_hdr[12] = tid;
  2396. ret = crypto_shash_update(desc, mic_hdr, 16);
  2397. if (ret)
  2398. goto out;
  2399. ret = crypto_shash_update(desc, data, data_len);
  2400. if (ret)
  2401. goto out;
  2402. ret = crypto_shash_final(desc, mic);
  2403. out:
  2404. shash_desc_zero(desc);
  2405. return ret;
  2406. }
  2407. static int ath12k_dp_rx_h_verify_tkip_mic(struct ath12k *ar, struct ath12k_peer *peer,
  2408. struct sk_buff *msdu)
  2409. {
  2410. struct ath12k_base *ab = ar->ab;
  2411. struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
  2412. struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
  2413. struct ieee80211_key_conf *key_conf;
  2414. struct ieee80211_hdr *hdr;
  2415. u8 mic[IEEE80211_CCMP_MIC_LEN];
  2416. int head_len, tail_len, ret;
  2417. size_t data_len;
  2418. u32 hdr_len, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
  2419. u8 *key, *data;
  2420. u8 key_idx;
  2421. if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC)
  2422. return 0;
  2423. hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
  2424. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  2425. head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
  2426. tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
  2427. if (!is_multicast_ether_addr(hdr->addr1))
  2428. key_idx = peer->ucast_keyidx;
  2429. else
  2430. key_idx = peer->mcast_keyidx;
  2431. key_conf = peer->keys[key_idx];
  2432. data = msdu->data + head_len;
  2433. data_len = msdu->len - head_len - tail_len;
  2434. key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
  2435. ret = ath12k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
  2436. if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
  2437. goto mic_fail;
  2438. return 0;
  2439. mic_fail:
  2440. (ATH12K_SKB_RXCB(msdu))->is_first_msdu = true;
  2441. (ATH12K_SKB_RXCB(msdu))->is_last_msdu = true;
  2442. rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
  2443. RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
  2444. skb_pull(msdu, hal_rx_desc_sz);
  2445. if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, rx_desc, msdu)))
  2446. return -EINVAL;
  2447. ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs);
  2448. ath12k_dp_rx_h_undecap(ar, msdu, rx_desc,
  2449. HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
  2450. ieee80211_rx(ath12k_ar_to_hw(ar), msdu);
  2451. return -EINVAL;
  2452. }
  2453. static void ath12k_dp_rx_h_undecap_frag(struct ath12k *ar, struct sk_buff *msdu,
  2454. enum hal_encrypt_type enctype, u32 flags)
  2455. {
  2456. struct ieee80211_hdr *hdr;
  2457. size_t hdr_len;
  2458. size_t crypto_len;
  2459. u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
  2460. if (!flags)
  2461. return;
  2462. hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
  2463. if (flags & RX_FLAG_MIC_STRIPPED)
  2464. skb_trim(msdu, msdu->len -
  2465. ath12k_dp_rx_crypto_mic_len(ar, enctype));
  2466. if (flags & RX_FLAG_ICV_STRIPPED)
  2467. skb_trim(msdu, msdu->len -
  2468. ath12k_dp_rx_crypto_icv_len(ar, enctype));
  2469. if (flags & RX_FLAG_IV_STRIPPED) {
  2470. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  2471. crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype);
  2472. memmove(msdu->data + hal_rx_desc_sz + crypto_len,
  2473. msdu->data + hal_rx_desc_sz, hdr_len);
  2474. skb_pull(msdu, crypto_len);
  2475. }
  2476. }
  2477. static int ath12k_dp_rx_h_defrag(struct ath12k *ar,
  2478. struct ath12k_peer *peer,
  2479. struct ath12k_dp_rx_tid *rx_tid,
  2480. struct sk_buff **defrag_skb)
  2481. {
  2482. struct ath12k_base *ab = ar->ab;
  2483. struct hal_rx_desc *rx_desc;
  2484. struct sk_buff *skb, *first_frag, *last_frag;
  2485. struct ieee80211_hdr *hdr;
  2486. enum hal_encrypt_type enctype;
  2487. bool is_decrypted = false;
  2488. int msdu_len = 0;
  2489. int extra_space;
  2490. u32 flags, hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
  2491. first_frag = skb_peek(&rx_tid->rx_frags);
  2492. last_frag = skb_peek_tail(&rx_tid->rx_frags);
  2493. skb_queue_walk(&rx_tid->rx_frags, skb) {
  2494. flags = 0;
  2495. rx_desc = (struct hal_rx_desc *)skb->data;
  2496. hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
  2497. enctype = ath12k_dp_rx_h_enctype(ab, rx_desc);
  2498. if (enctype != HAL_ENCRYPT_TYPE_OPEN)
  2499. is_decrypted = ath12k_dp_rx_h_is_decrypted(ab,
  2500. rx_desc);
  2501. if (is_decrypted) {
  2502. if (skb != first_frag)
  2503. flags |= RX_FLAG_IV_STRIPPED;
  2504. if (skb != last_frag)
  2505. flags |= RX_FLAG_ICV_STRIPPED |
  2506. RX_FLAG_MIC_STRIPPED;
  2507. }
  2508. /* RX fragments are always raw packets */
  2509. if (skb != last_frag)
  2510. skb_trim(skb, skb->len - FCS_LEN);
  2511. ath12k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
  2512. if (skb != first_frag)
  2513. skb_pull(skb, hal_rx_desc_sz +
  2514. ieee80211_hdrlen(hdr->frame_control));
  2515. msdu_len += skb->len;
  2516. }
  2517. extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
  2518. if (extra_space > 0 &&
  2519. (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
  2520. return -ENOMEM;
  2521. __skb_unlink(first_frag, &rx_tid->rx_frags);
  2522. while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
  2523. skb_put_data(first_frag, skb->data, skb->len);
  2524. dev_kfree_skb_any(skb);
  2525. }
  2526. hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
  2527. hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
  2528. ATH12K_SKB_RXCB(first_frag)->is_frag = 1;
  2529. if (ath12k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
  2530. first_frag = NULL;
  2531. *defrag_skb = first_frag;
  2532. return 0;
  2533. }
  2534. static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar,
  2535. struct ath12k_dp_rx_tid *rx_tid,
  2536. struct sk_buff *defrag_skb)
  2537. {
  2538. struct ath12k_base *ab = ar->ab;
  2539. struct ath12k_dp *dp = &ab->dp;
  2540. struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
  2541. struct hal_reo_entrance_ring *reo_ent_ring;
  2542. struct hal_reo_dest_ring *reo_dest_ring;
  2543. struct dp_link_desc_bank *link_desc_banks;
  2544. struct hal_rx_msdu_link *msdu_link;
  2545. struct hal_rx_msdu_details *msdu0;
  2546. struct hal_srng *srng;
  2547. dma_addr_t link_paddr, buf_paddr;
  2548. u32 desc_bank, msdu_info, msdu_ext_info, mpdu_info;
  2549. u32 cookie, hal_rx_desc_sz, dest_ring_info0, queue_addr_hi;
  2550. int ret;
  2551. struct ath12k_rx_desc_info *desc_info;
  2552. enum hal_rx_buf_return_buf_manager idle_link_rbm = dp->idle_link_rbm;
  2553. u8 dst_ind;
  2554. hal_rx_desc_sz = ab->hal.hal_desc_sz;
  2555. link_desc_banks = dp->link_desc_banks;
  2556. reo_dest_ring = rx_tid->dst_ring_desc;
  2557. ath12k_hal_rx_reo_ent_paddr_get(ab, &reo_dest_ring->buf_addr_info,
  2558. &link_paddr, &cookie);
  2559. desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK);
  2560. msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
  2561. (link_paddr - link_desc_banks[desc_bank].paddr));
  2562. msdu0 = &msdu_link->msdu_link[0];
  2563. msdu_ext_info = le32_to_cpu(msdu0->rx_msdu_ext_info.info0);
  2564. dst_ind = u32_get_bits(msdu_ext_info, RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND);
  2565. memset(msdu0, 0, sizeof(*msdu0));
  2566. msdu_info = u32_encode_bits(1, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU) |
  2567. u32_encode_bits(1, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU) |
  2568. u32_encode_bits(0, RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) |
  2569. u32_encode_bits(defrag_skb->len - hal_rx_desc_sz,
  2570. RX_MSDU_DESC_INFO0_MSDU_LENGTH) |
  2571. u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_SA) |
  2572. u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_DA);
  2573. msdu0->rx_msdu_info.info0 = cpu_to_le32(msdu_info);
  2574. msdu0->rx_msdu_ext_info.info0 = cpu_to_le32(msdu_ext_info);
  2575. /* change msdu len in hal rx desc */
  2576. ath12k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
  2577. buf_paddr = dma_map_single(ab->dev, defrag_skb->data,
  2578. defrag_skb->len + skb_tailroom(defrag_skb),
  2579. DMA_TO_DEVICE);
  2580. if (dma_mapping_error(ab->dev, buf_paddr))
  2581. return -ENOMEM;
  2582. spin_lock_bh(&dp->rx_desc_lock);
  2583. desc_info = list_first_entry_or_null(&dp->rx_desc_free_list,
  2584. struct ath12k_rx_desc_info,
  2585. list);
  2586. if (!desc_info) {
  2587. spin_unlock_bh(&dp->rx_desc_lock);
  2588. ath12k_warn(ab, "failed to find rx desc for reinject\n");
  2589. ret = -ENOMEM;
  2590. goto err_unmap_dma;
  2591. }
  2592. desc_info->skb = defrag_skb;
  2593. desc_info->in_use = true;
  2594. list_del(&desc_info->list);
  2595. spin_unlock_bh(&dp->rx_desc_lock);
  2596. ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr;
  2597. ath12k_hal_rx_buf_addr_info_set(&msdu0->buf_addr_info, buf_paddr,
  2598. desc_info->cookie,
  2599. HAL_RX_BUF_RBM_SW3_BM);
  2600. /* Fill mpdu details into reo entrance ring */
  2601. srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id];
  2602. spin_lock_bh(&srng->lock);
  2603. ath12k_hal_srng_access_begin(ab, srng);
  2604. reo_ent_ring = ath12k_hal_srng_src_get_next_entry(ab, srng);
  2605. if (!reo_ent_ring) {
  2606. ath12k_hal_srng_access_end(ab, srng);
  2607. spin_unlock_bh(&srng->lock);
  2608. ret = -ENOSPC;
  2609. goto err_free_desc;
  2610. }
  2611. memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
  2612. ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr,
  2613. cookie,
  2614. idle_link_rbm);
  2615. mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) |
  2616. u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) |
  2617. u32_encode_bits(1, RX_MPDU_DESC_INFO0_RAW_MPDU) |
  2618. u32_encode_bits(1, RX_MPDU_DESC_INFO0_VALID_PN) |
  2619. u32_encode_bits(rx_tid->tid, RX_MPDU_DESC_INFO0_TID);
  2620. reo_ent_ring->rx_mpdu_info.info0 = cpu_to_le32(mpdu_info);
  2621. reo_ent_ring->rx_mpdu_info.peer_meta_data =
  2622. reo_dest_ring->rx_mpdu_info.peer_meta_data;
  2623. reo_ent_ring->queue_addr_lo = cpu_to_le32(lower_32_bits(rx_tid->paddr));
  2624. queue_addr_hi = upper_32_bits(rx_tid->paddr);
  2625. reo_ent_ring->info0 = le32_encode_bits(queue_addr_hi,
  2626. HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI) |
  2627. le32_encode_bits(dst_ind,
  2628. HAL_REO_ENTR_RING_INFO0_DEST_IND);
  2629. reo_ent_ring->info1 = le32_encode_bits(rx_tid->cur_sn,
  2630. HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM);
  2631. dest_ring_info0 = le32_get_bits(reo_dest_ring->info0,
  2632. HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
  2633. reo_ent_ring->info2 =
  2634. cpu_to_le32(u32_get_bits(dest_ring_info0,
  2635. HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID));
  2636. ath12k_hal_srng_access_end(ab, srng);
  2637. spin_unlock_bh(&srng->lock);
  2638. return 0;
  2639. err_free_desc:
  2640. spin_lock_bh(&dp->rx_desc_lock);
  2641. desc_info->in_use = false;
  2642. desc_info->skb = NULL;
  2643. list_add_tail(&desc_info->list, &dp->rx_desc_free_list);
  2644. spin_unlock_bh(&dp->rx_desc_lock);
  2645. err_unmap_dma:
  2646. dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb),
  2647. DMA_TO_DEVICE);
  2648. return ret;
  2649. }
  2650. static int ath12k_dp_rx_h_cmp_frags(struct ath12k_base *ab,
  2651. struct sk_buff *a, struct sk_buff *b)
  2652. {
  2653. int frag1, frag2;
  2654. frag1 = ath12k_dp_rx_h_frag_no(ab, a);
  2655. frag2 = ath12k_dp_rx_h_frag_no(ab, b);
  2656. return frag1 - frag2;
  2657. }
  2658. static void ath12k_dp_rx_h_sort_frags(struct ath12k_base *ab,
  2659. struct sk_buff_head *frag_list,
  2660. struct sk_buff *cur_frag)
  2661. {
  2662. struct sk_buff *skb;
  2663. int cmp;
  2664. skb_queue_walk(frag_list, skb) {
  2665. cmp = ath12k_dp_rx_h_cmp_frags(ab, skb, cur_frag);
  2666. if (cmp < 0)
  2667. continue;
  2668. __skb_queue_before(frag_list, skb, cur_frag);
  2669. return;
  2670. }
  2671. __skb_queue_tail(frag_list, cur_frag);
  2672. }
  2673. static u64 ath12k_dp_rx_h_get_pn(struct ath12k *ar, struct sk_buff *skb)
  2674. {
  2675. struct ieee80211_hdr *hdr;
  2676. u64 pn = 0;
  2677. u8 *ehdr;
  2678. u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
  2679. hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
  2680. ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
  2681. pn = ehdr[0];
  2682. pn |= (u64)ehdr[1] << 8;
  2683. pn |= (u64)ehdr[4] << 16;
  2684. pn |= (u64)ehdr[5] << 24;
  2685. pn |= (u64)ehdr[6] << 32;
  2686. pn |= (u64)ehdr[7] << 40;
  2687. return pn;
  2688. }
  2689. static bool
  2690. ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k *ar, struct ath12k_dp_rx_tid *rx_tid)
  2691. {
  2692. struct ath12k_base *ab = ar->ab;
  2693. enum hal_encrypt_type encrypt_type;
  2694. struct sk_buff *first_frag, *skb;
  2695. struct hal_rx_desc *desc;
  2696. u64 last_pn;
  2697. u64 cur_pn;
  2698. first_frag = skb_peek(&rx_tid->rx_frags);
  2699. desc = (struct hal_rx_desc *)first_frag->data;
  2700. encrypt_type = ath12k_dp_rx_h_enctype(ab, desc);
  2701. if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
  2702. encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
  2703. encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
  2704. encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
  2705. return true;
  2706. last_pn = ath12k_dp_rx_h_get_pn(ar, first_frag);
  2707. skb_queue_walk(&rx_tid->rx_frags, skb) {
  2708. if (skb == first_frag)
  2709. continue;
  2710. cur_pn = ath12k_dp_rx_h_get_pn(ar, skb);
  2711. if (cur_pn != last_pn + 1)
  2712. return false;
  2713. last_pn = cur_pn;
  2714. }
  2715. return true;
  2716. }
  2717. static int ath12k_dp_rx_frag_h_mpdu(struct ath12k *ar,
  2718. struct sk_buff *msdu,
  2719. struct hal_reo_dest_ring *ring_desc)
  2720. {
  2721. struct ath12k_base *ab = ar->ab;
  2722. struct hal_rx_desc *rx_desc;
  2723. struct ath12k_peer *peer;
  2724. struct ath12k_dp_rx_tid *rx_tid;
  2725. struct sk_buff *defrag_skb = NULL;
  2726. u32 peer_id;
  2727. u16 seqno, frag_no;
  2728. u8 tid;
  2729. int ret = 0;
  2730. bool more_frags;
  2731. rx_desc = (struct hal_rx_desc *)msdu->data;
  2732. peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc);
  2733. tid = ath12k_dp_rx_h_tid(ab, rx_desc);
  2734. seqno = ath12k_dp_rx_h_seq_no(ab, rx_desc);
  2735. frag_no = ath12k_dp_rx_h_frag_no(ab, msdu);
  2736. more_frags = ath12k_dp_rx_h_more_frags(ab, msdu);
  2737. if (!ath12k_dp_rx_h_seq_ctrl_valid(ab, rx_desc) ||
  2738. !ath12k_dp_rx_h_fc_valid(ab, rx_desc) ||
  2739. tid > IEEE80211_NUM_TIDS)
  2740. return -EINVAL;
  2741. /* received unfragmented packet in reo
  2742. * exception ring, this shouldn't happen
  2743. * as these packets typically come from
  2744. * reo2sw srngs.
  2745. */
  2746. if (WARN_ON_ONCE(!frag_no && !more_frags))
  2747. return -EINVAL;
  2748. spin_lock_bh(&ab->base_lock);
  2749. peer = ath12k_peer_find_by_id(ab, peer_id);
  2750. if (!peer) {
  2751. ath12k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
  2752. peer_id);
  2753. ret = -ENOENT;
  2754. goto out_unlock;
  2755. }
  2756. if (!peer->dp_setup_done) {
  2757. ath12k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n",
  2758. peer->addr, peer_id);
  2759. ret = -ENOENT;
  2760. goto out_unlock;
  2761. }
  2762. rx_tid = &peer->rx_tid[tid];
  2763. if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
  2764. skb_queue_empty(&rx_tid->rx_frags)) {
  2765. /* Flush stored fragments and start a new sequence */
  2766. ath12k_dp_rx_frags_cleanup(rx_tid, true);
  2767. rx_tid->cur_sn = seqno;
  2768. }
  2769. if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
  2770. /* Fragment already present */
  2771. ret = -EINVAL;
  2772. goto out_unlock;
  2773. }
  2774. if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap)))
  2775. __skb_queue_tail(&rx_tid->rx_frags, msdu);
  2776. else
  2777. ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu);
  2778. rx_tid->rx_frag_bitmap |= BIT(frag_no);
  2779. if (!more_frags)
  2780. rx_tid->last_frag_no = frag_no;
  2781. if (frag_no == 0) {
  2782. rx_tid->dst_ring_desc = kmemdup(ring_desc,
  2783. sizeof(*rx_tid->dst_ring_desc),
  2784. GFP_ATOMIC);
  2785. if (!rx_tid->dst_ring_desc) {
  2786. ret = -ENOMEM;
  2787. goto out_unlock;
  2788. }
  2789. } else {
  2790. ath12k_dp_rx_link_desc_return(ab, ring_desc,
  2791. HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
  2792. }
  2793. if (!rx_tid->last_frag_no ||
  2794. rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
  2795. mod_timer(&rx_tid->frag_timer, jiffies +
  2796. ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS);
  2797. goto out_unlock;
  2798. }
  2799. spin_unlock_bh(&ab->base_lock);
  2800. del_timer_sync(&rx_tid->frag_timer);
  2801. spin_lock_bh(&ab->base_lock);
  2802. peer = ath12k_peer_find_by_id(ab, peer_id);
  2803. if (!peer)
  2804. goto err_frags_cleanup;
  2805. if (!ath12k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
  2806. goto err_frags_cleanup;
  2807. if (ath12k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
  2808. goto err_frags_cleanup;
  2809. if (!defrag_skb)
  2810. goto err_frags_cleanup;
  2811. if (ath12k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
  2812. goto err_frags_cleanup;
  2813. ath12k_dp_rx_frags_cleanup(rx_tid, false);
  2814. goto out_unlock;
  2815. err_frags_cleanup:
  2816. dev_kfree_skb_any(defrag_skb);
  2817. ath12k_dp_rx_frags_cleanup(rx_tid, true);
  2818. out_unlock:
  2819. spin_unlock_bh(&ab->base_lock);
  2820. return ret;
  2821. }
  2822. static int
  2823. ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc,
  2824. struct list_head *used_list,
  2825. bool drop, u32 cookie)
  2826. {
  2827. struct ath12k_base *ab = ar->ab;
  2828. struct sk_buff *msdu;
  2829. struct ath12k_skb_rxcb *rxcb;
  2830. struct hal_rx_desc *rx_desc;
  2831. u16 msdu_len;
  2832. u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
  2833. struct ath12k_rx_desc_info *desc_info;
  2834. u64 desc_va;
  2835. desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 |
  2836. le32_to_cpu(desc->buf_va_lo));
  2837. desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va);
  2838. /* retry manual desc retrieval */
  2839. if (!desc_info) {
  2840. desc_info = ath12k_dp_get_rx_desc(ab, cookie);
  2841. if (!desc_info) {
  2842. ath12k_warn(ab, "Invalid cookie in DP rx error descriptor retrieval: 0x%x\n",
  2843. cookie);
  2844. return -EINVAL;
  2845. }
  2846. }
  2847. if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
  2848. ath12k_warn(ab, " RX Exception, Check HW CC implementation");
  2849. msdu = desc_info->skb;
  2850. desc_info->skb = NULL;
  2851. list_add_tail(&desc_info->list, used_list);
  2852. rxcb = ATH12K_SKB_RXCB(msdu);
  2853. dma_unmap_single(ar->ab->dev, rxcb->paddr,
  2854. msdu->len + skb_tailroom(msdu),
  2855. DMA_FROM_DEVICE);
  2856. if (drop) {
  2857. dev_kfree_skb_any(msdu);
  2858. return 0;
  2859. }
  2860. rcu_read_lock();
  2861. if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
  2862. dev_kfree_skb_any(msdu);
  2863. goto exit;
  2864. }
  2865. if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) {
  2866. dev_kfree_skb_any(msdu);
  2867. goto exit;
  2868. }
  2869. rx_desc = (struct hal_rx_desc *)msdu->data;
  2870. msdu_len = ath12k_dp_rx_h_msdu_len(ar->ab, rx_desc);
  2871. if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
  2872. ath12k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
  2873. ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "", rx_desc,
  2874. sizeof(*rx_desc));
  2875. dev_kfree_skb_any(msdu);
  2876. goto exit;
  2877. }
  2878. skb_put(msdu, hal_rx_desc_sz + msdu_len);
  2879. if (ath12k_dp_rx_frag_h_mpdu(ar, msdu, desc)) {
  2880. dev_kfree_skb_any(msdu);
  2881. ath12k_dp_rx_link_desc_return(ar->ab, desc,
  2882. HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
  2883. }
  2884. exit:
  2885. rcu_read_unlock();
  2886. return 0;
  2887. }
  2888. int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi,
  2889. int budget)
  2890. {
  2891. u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
  2892. struct dp_link_desc_bank *link_desc_banks;
  2893. enum hal_rx_buf_return_buf_manager rbm;
  2894. struct hal_rx_msdu_link *link_desc_va;
  2895. int tot_n_bufs_reaped, quota, ret, i;
  2896. struct hal_reo_dest_ring *reo_desc;
  2897. struct dp_rxdma_ring *rx_ring;
  2898. struct dp_srng *reo_except;
  2899. LIST_HEAD(rx_desc_used_list);
  2900. u32 desc_bank, num_msdus;
  2901. struct hal_srng *srng;
  2902. struct ath12k_dp *dp;
  2903. int mac_id;
  2904. struct ath12k *ar;
  2905. dma_addr_t paddr;
  2906. bool is_frag;
  2907. bool drop;
  2908. int pdev_id;
  2909. tot_n_bufs_reaped = 0;
  2910. quota = budget;
  2911. dp = &ab->dp;
  2912. reo_except = &dp->reo_except_ring;
  2913. link_desc_banks = dp->link_desc_banks;
  2914. srng = &ab->hal.srng_list[reo_except->ring_id];
  2915. spin_lock_bh(&srng->lock);
  2916. ath12k_hal_srng_access_begin(ab, srng);
  2917. while (budget &&
  2918. (reo_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
  2919. drop = false;
  2920. ab->soc_stats.err_ring_pkts++;
  2921. ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr,
  2922. &desc_bank);
  2923. if (ret) {
  2924. ath12k_warn(ab, "failed to parse error reo desc %d\n",
  2925. ret);
  2926. continue;
  2927. }
  2928. link_desc_va = link_desc_banks[desc_bank].vaddr +
  2929. (paddr - link_desc_banks[desc_bank].paddr);
  2930. ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
  2931. &rbm);
  2932. if (rbm != dp->idle_link_rbm &&
  2933. rbm != HAL_RX_BUF_RBM_SW3_BM &&
  2934. rbm != ab->hw_params->hal_params->rx_buf_rbm) {
  2935. ab->soc_stats.invalid_rbm++;
  2936. ath12k_warn(ab, "invalid return buffer manager %d\n", rbm);
  2937. ath12k_dp_rx_link_desc_return(ab, reo_desc,
  2938. HAL_WBM_REL_BM_ACT_REL_MSDU);
  2939. continue;
  2940. }
  2941. is_frag = !!(le32_to_cpu(reo_desc->rx_mpdu_info.info0) &
  2942. RX_MPDU_DESC_INFO0_FRAG_FLAG);
  2943. /* Process only rx fragments with one msdu per link desc below, and drop
  2944. * msdu's indicated due to error reasons.
  2945. */
  2946. if (!is_frag || num_msdus > 1) {
  2947. drop = true;
  2948. /* Return the link desc back to wbm idle list */
  2949. ath12k_dp_rx_link_desc_return(ab, reo_desc,
  2950. HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
  2951. }
  2952. for (i = 0; i < num_msdus; i++) {
  2953. mac_id = le32_get_bits(reo_desc->info0,
  2954. HAL_REO_DEST_RING_INFO0_SRC_LINK_ID);
  2955. pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
  2956. ar = ab->pdevs[pdev_id].ar;
  2957. if (!ath12k_dp_process_rx_err_buf(ar, reo_desc,
  2958. &rx_desc_used_list,
  2959. drop,
  2960. msdu_cookies[i]))
  2961. tot_n_bufs_reaped++;
  2962. }
  2963. if (tot_n_bufs_reaped >= quota) {
  2964. tot_n_bufs_reaped = quota;
  2965. goto exit;
  2966. }
  2967. budget = quota - tot_n_bufs_reaped;
  2968. }
  2969. exit:
  2970. ath12k_hal_srng_access_end(ab, srng);
  2971. spin_unlock_bh(&srng->lock);
  2972. rx_ring = &dp->rx_refill_buf_ring;
  2973. ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list,
  2974. tot_n_bufs_reaped);
  2975. return tot_n_bufs_reaped;
  2976. }
  2977. static void ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k *ar,
  2978. int msdu_len,
  2979. struct sk_buff_head *msdu_list)
  2980. {
  2981. struct sk_buff *skb, *tmp;
  2982. struct ath12k_skb_rxcb *rxcb;
  2983. int n_buffs;
  2984. n_buffs = DIV_ROUND_UP(msdu_len,
  2985. (DP_RX_BUFFER_SIZE - ar->ab->hal.hal_desc_sz));
  2986. skb_queue_walk_safe(msdu_list, skb, tmp) {
  2987. rxcb = ATH12K_SKB_RXCB(skb);
  2988. if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
  2989. rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
  2990. if (!n_buffs)
  2991. break;
  2992. __skb_unlink(skb, msdu_list);
  2993. dev_kfree_skb_any(skb);
  2994. n_buffs--;
  2995. }
  2996. }
  2997. }
  2998. static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu,
  2999. struct ieee80211_rx_status *status,
  3000. struct sk_buff_head *msdu_list)
  3001. {
  3002. struct ath12k_base *ab = ar->ab;
  3003. u16 msdu_len;
  3004. struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
  3005. u8 l3pad_bytes;
  3006. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
  3007. u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
  3008. msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc);
  3009. if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
  3010. /* First buffer will be freed by the caller, so deduct it's length */
  3011. msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
  3012. ath12k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
  3013. return -EINVAL;
  3014. }
  3015. /* Even after cleaning up the sg buffers in the msdu list with above check
  3016. * any msdu received with continuation flag needs to be dropped as invalid.
  3017. * This protects against some random err frame with continuation flag.
  3018. */
  3019. if (rxcb->is_continuation)
  3020. return -EINVAL;
  3021. if (!ath12k_dp_rx_h_msdu_done(ab, desc)) {
  3022. ath12k_warn(ar->ab,
  3023. "msdu_done bit not set in null_q_des processing\n");
  3024. __skb_queue_purge(msdu_list);
  3025. return -EIO;
  3026. }
  3027. /* Handle NULL queue descriptor violations arising out a missing
  3028. * REO queue for a given peer or a given TID. This typically
  3029. * may happen if a packet is received on a QOS enabled TID before the
  3030. * ADDBA negotiation for that TID, when the TID queue is setup. Or
  3031. * it may also happen for MC/BC frames if they are not routed to the
  3032. * non-QOS TID queue, in the absence of any other default TID queue.
  3033. * This error can show up both in a REO destination or WBM release ring.
  3034. */
  3035. if (rxcb->is_frag) {
  3036. skb_pull(msdu, hal_rx_desc_sz);
  3037. } else {
  3038. l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc);
  3039. if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
  3040. return -EINVAL;
  3041. skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
  3042. skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
  3043. }
  3044. if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu)))
  3045. return -EINVAL;
  3046. ath12k_dp_rx_h_ppdu(ar, desc, status);
  3047. ath12k_dp_rx_h_mpdu(ar, msdu, desc, status);
  3048. rxcb->tid = ath12k_dp_rx_h_tid(ab, desc);
  3049. /* Please note that caller will having the access to msdu and completing
  3050. * rx with mac80211. Need not worry about cleaning up amsdu_list.
  3051. */
  3052. return 0;
  3053. }
  3054. static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu,
  3055. struct ieee80211_rx_status *status,
  3056. struct sk_buff_head *msdu_list)
  3057. {
  3058. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
  3059. bool drop = false;
  3060. ar->ab->soc_stats.reo_error[rxcb->err_code]++;
  3061. switch (rxcb->err_code) {
  3062. case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
  3063. if (ath12k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
  3064. drop = true;
  3065. break;
  3066. case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
  3067. /* TODO: Do not drop PN failed packets in the driver;
  3068. * instead, it is good to drop such packets in mac80211
  3069. * after incrementing the replay counters.
  3070. */
  3071. fallthrough;
  3072. default:
  3073. /* TODO: Review other errors and process them to mac80211
  3074. * as appropriate.
  3075. */
  3076. drop = true;
  3077. break;
  3078. }
  3079. return drop;
  3080. }
  3081. static bool ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu,
  3082. struct ieee80211_rx_status *status)
  3083. {
  3084. struct ath12k_base *ab = ar->ab;
  3085. u16 msdu_len;
  3086. struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
  3087. u8 l3pad_bytes;
  3088. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
  3089. u32 hal_rx_desc_sz = ar->ab->hal.hal_desc_sz;
  3090. rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, desc);
  3091. rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, desc);
  3092. l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc);
  3093. msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc);
  3094. if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) {
  3095. ath12k_dbg(ab, ATH12K_DBG_DATA,
  3096. "invalid msdu len in tkip mic err %u\n", msdu_len);
  3097. ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", desc,
  3098. sizeof(*desc));
  3099. return true;
  3100. }
  3101. skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
  3102. skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
  3103. if (unlikely(!ath12k_dp_rx_check_nwifi_hdr_len_valid(ab, desc, msdu)))
  3104. return true;
  3105. ath12k_dp_rx_h_ppdu(ar, desc, status);
  3106. status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
  3107. RX_FLAG_DECRYPTED);
  3108. ath12k_dp_rx_h_undecap(ar, msdu, desc,
  3109. HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
  3110. return false;
  3111. }
  3112. static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar, struct sk_buff *msdu,
  3113. struct ieee80211_rx_status *status)
  3114. {
  3115. struct ath12k_base *ab = ar->ab;
  3116. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
  3117. struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
  3118. bool drop = false;
  3119. u32 err_bitmap;
  3120. ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
  3121. switch (rxcb->err_code) {
  3122. case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR:
  3123. case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
  3124. err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc);
  3125. if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) {
  3126. drop = ath12k_dp_rx_h_tkip_mic_err(ar, msdu, status);
  3127. break;
  3128. }
  3129. fallthrough;
  3130. default:
  3131. /* TODO: Review other rxdma error code to check if anything is
  3132. * worth reporting to mac80211
  3133. */
  3134. drop = true;
  3135. break;
  3136. }
  3137. return drop;
  3138. }
  3139. static void ath12k_dp_rx_wbm_err(struct ath12k *ar,
  3140. struct napi_struct *napi,
  3141. struct sk_buff *msdu,
  3142. struct sk_buff_head *msdu_list)
  3143. {
  3144. struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu);
  3145. struct ieee80211_rx_status rxs = {0};
  3146. bool drop = true;
  3147. switch (rxcb->err_rel_src) {
  3148. case HAL_WBM_REL_SRC_MODULE_REO:
  3149. drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
  3150. break;
  3151. case HAL_WBM_REL_SRC_MODULE_RXDMA:
  3152. drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
  3153. break;
  3154. default:
  3155. /* msdu will get freed */
  3156. break;
  3157. }
  3158. if (drop) {
  3159. dev_kfree_skb_any(msdu);
  3160. return;
  3161. }
  3162. ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
  3163. }
  3164. int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab,
  3165. struct napi_struct *napi, int budget)
  3166. {
  3167. LIST_HEAD(rx_desc_used_list);
  3168. struct ath12k *ar;
  3169. struct ath12k_dp *dp = &ab->dp;
  3170. struct dp_rxdma_ring *rx_ring;
  3171. struct hal_rx_wbm_rel_info err_info;
  3172. struct hal_srng *srng;
  3173. struct sk_buff *msdu;
  3174. struct sk_buff_head msdu_list, scatter_msdu_list;
  3175. struct ath12k_skb_rxcb *rxcb;
  3176. void *rx_desc;
  3177. u8 mac_id;
  3178. int num_buffs_reaped = 0;
  3179. struct ath12k_rx_desc_info *desc_info;
  3180. int ret, pdev_id;
  3181. struct hal_rx_desc *msdu_data;
  3182. __skb_queue_head_init(&msdu_list);
  3183. __skb_queue_head_init(&scatter_msdu_list);
  3184. srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
  3185. rx_ring = &dp->rx_refill_buf_ring;
  3186. spin_lock_bh(&srng->lock);
  3187. ath12k_hal_srng_access_begin(ab, srng);
  3188. while (budget) {
  3189. rx_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng);
  3190. if (!rx_desc)
  3191. break;
  3192. ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
  3193. if (ret) {
  3194. ath12k_warn(ab,
  3195. "failed to parse rx error in wbm_rel ring desc %d\n",
  3196. ret);
  3197. continue;
  3198. }
  3199. desc_info = err_info.rx_desc;
  3200. /* retry manual desc retrieval if hw cc is not done */
  3201. if (!desc_info) {
  3202. desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie);
  3203. if (!desc_info) {
  3204. ath12k_warn(ab, "Invalid cookie in DP WBM rx error descriptor retrieval: 0x%x\n",
  3205. err_info.cookie);
  3206. continue;
  3207. }
  3208. }
  3209. if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)
  3210. ath12k_warn(ab, "WBM RX err, Check HW CC implementation");
  3211. msdu = desc_info->skb;
  3212. desc_info->skb = NULL;
  3213. list_add_tail(&desc_info->list, &rx_desc_used_list);
  3214. rxcb = ATH12K_SKB_RXCB(msdu);
  3215. dma_unmap_single(ab->dev, rxcb->paddr,
  3216. msdu->len + skb_tailroom(msdu),
  3217. DMA_FROM_DEVICE);
  3218. num_buffs_reaped++;
  3219. if (!err_info.continuation)
  3220. budget--;
  3221. if (err_info.push_reason !=
  3222. HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
  3223. dev_kfree_skb_any(msdu);
  3224. continue;
  3225. }
  3226. msdu_data = (struct hal_rx_desc *)msdu->data;
  3227. rxcb->err_rel_src = err_info.err_rel_src;
  3228. rxcb->err_code = err_info.err_code;
  3229. rxcb->is_first_msdu = err_info.first_msdu;
  3230. rxcb->is_last_msdu = err_info.last_msdu;
  3231. rxcb->is_continuation = err_info.continuation;
  3232. rxcb->rx_desc = msdu_data;
  3233. if (err_info.continuation) {
  3234. __skb_queue_tail(&scatter_msdu_list, msdu);
  3235. continue;
  3236. }
  3237. mac_id = ath12k_dp_rx_get_msdu_src_link(ab,
  3238. msdu_data);
  3239. if (mac_id >= MAX_RADIOS) {
  3240. dev_kfree_skb_any(msdu);
  3241. /* In any case continuation bit is set
  3242. * in the previous record, cleanup scatter_msdu_list
  3243. */
  3244. ath12k_dp_clean_up_skb_list(&scatter_msdu_list);
  3245. continue;
  3246. }
  3247. if (!skb_queue_empty(&scatter_msdu_list)) {
  3248. struct sk_buff *msdu;
  3249. skb_queue_walk(&scatter_msdu_list, msdu) {
  3250. rxcb = ATH12K_SKB_RXCB(msdu);
  3251. rxcb->mac_id = mac_id;
  3252. }
  3253. skb_queue_splice_tail_init(&scatter_msdu_list,
  3254. &msdu_list);
  3255. }
  3256. rxcb = ATH12K_SKB_RXCB(msdu);
  3257. rxcb->mac_id = mac_id;
  3258. __skb_queue_tail(&msdu_list, msdu);
  3259. }
  3260. /* In any case continuation bit is set in the
  3261. * last record, cleanup scatter_msdu_list
  3262. */
  3263. ath12k_dp_clean_up_skb_list(&scatter_msdu_list);
  3264. ath12k_hal_srng_access_end(ab, srng);
  3265. spin_unlock_bh(&srng->lock);
  3266. if (!num_buffs_reaped)
  3267. goto done;
  3268. ath12k_dp_rx_bufs_replenish(ab, rx_ring, &rx_desc_used_list,
  3269. num_buffs_reaped);
  3270. rcu_read_lock();
  3271. while ((msdu = __skb_dequeue(&msdu_list))) {
  3272. rxcb = ATH12K_SKB_RXCB(msdu);
  3273. mac_id = rxcb->mac_id;
  3274. pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
  3275. ar = ab->pdevs[pdev_id].ar;
  3276. if (!ar || !rcu_dereference(ar->ab->pdevs_active[mac_id])) {
  3277. dev_kfree_skb_any(msdu);
  3278. continue;
  3279. }
  3280. if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) {
  3281. dev_kfree_skb_any(msdu);
  3282. continue;
  3283. }
  3284. ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list);
  3285. }
  3286. rcu_read_unlock();
  3287. done:
  3288. return num_buffs_reaped;
  3289. }
  3290. void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab)
  3291. {
  3292. struct ath12k_dp *dp = &ab->dp;
  3293. struct hal_tlv_64_hdr *hdr;
  3294. struct hal_srng *srng;
  3295. struct ath12k_dp_rx_reo_cmd *cmd, *tmp;
  3296. bool found = false;
  3297. u16 tag;
  3298. struct hal_reo_status reo_status;
  3299. srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
  3300. memset(&reo_status, 0, sizeof(reo_status));
  3301. spin_lock_bh(&srng->lock);
  3302. ath12k_hal_srng_access_begin(ab, srng);
  3303. while ((hdr = ath12k_hal_srng_dst_get_next_entry(ab, srng))) {
  3304. tag = u64_get_bits(hdr->tl, HAL_SRNG_TLV_HDR_TAG);
  3305. switch (tag) {
  3306. case HAL_REO_GET_QUEUE_STATS_STATUS:
  3307. ath12k_hal_reo_status_queue_stats(ab, hdr,
  3308. &reo_status);
  3309. break;
  3310. case HAL_REO_FLUSH_QUEUE_STATUS:
  3311. ath12k_hal_reo_flush_queue_status(ab, hdr,
  3312. &reo_status);
  3313. break;
  3314. case HAL_REO_FLUSH_CACHE_STATUS:
  3315. ath12k_hal_reo_flush_cache_status(ab, hdr,
  3316. &reo_status);
  3317. break;
  3318. case HAL_REO_UNBLOCK_CACHE_STATUS:
  3319. ath12k_hal_reo_unblk_cache_status(ab, hdr,
  3320. &reo_status);
  3321. break;
  3322. case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
  3323. ath12k_hal_reo_flush_timeout_list_status(ab, hdr,
  3324. &reo_status);
  3325. break;
  3326. case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
  3327. ath12k_hal_reo_desc_thresh_reached_status(ab, hdr,
  3328. &reo_status);
  3329. break;
  3330. case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
  3331. ath12k_hal_reo_update_rx_reo_queue_status(ab, hdr,
  3332. &reo_status);
  3333. break;
  3334. default:
  3335. ath12k_warn(ab, "Unknown reo status type %d\n", tag);
  3336. continue;
  3337. }
  3338. spin_lock_bh(&dp->reo_cmd_lock);
  3339. list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
  3340. if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
  3341. found = true;
  3342. list_del(&cmd->list);
  3343. break;
  3344. }
  3345. }
  3346. spin_unlock_bh(&dp->reo_cmd_lock);
  3347. if (found) {
  3348. cmd->handler(dp, (void *)&cmd->data,
  3349. reo_status.uniform_hdr.cmd_status);
  3350. kfree(cmd);
  3351. }
  3352. found = false;
  3353. }
  3354. ath12k_hal_srng_access_end(ab, srng);
  3355. spin_unlock_bh(&srng->lock);
  3356. }
  3357. void ath12k_dp_rx_free(struct ath12k_base *ab)
  3358. {
  3359. struct ath12k_dp *dp = &ab->dp;
  3360. int i;
  3361. ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
  3362. for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
  3363. if (ab->hw_params->rx_mac_buf_ring)
  3364. ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
  3365. }
  3366. for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++)
  3367. ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
  3368. ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
  3369. ath12k_dp_rxdma_buf_free(ab);
  3370. }
  3371. void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id)
  3372. {
  3373. struct ath12k *ar = ab->pdevs[mac_id].ar;
  3374. ath12k_dp_rx_pdev_srng_free(ar);
  3375. }
  3376. int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab)
  3377. {
  3378. struct ath12k_dp *dp = &ab->dp;
  3379. struct htt_rx_ring_tlv_filter tlv_filter = {0};
  3380. u32 ring_id;
  3381. int ret;
  3382. u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
  3383. ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
  3384. tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
  3385. tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
  3386. tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
  3387. HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
  3388. HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
  3389. tlv_filter.offset_valid = true;
  3390. tlv_filter.rx_packet_offset = hal_rx_desc_sz;
  3391. tlv_filter.rx_mpdu_start_offset =
  3392. ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
  3393. tlv_filter.rx_msdu_end_offset =
  3394. ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
  3395. if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) {
  3396. tlv_filter.rx_mpdu_start_wmask =
  3397. ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start();
  3398. tlv_filter.rx_msdu_end_wmask =
  3399. ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end();
  3400. ath12k_dbg(ab, ATH12K_DBG_DATA,
  3401. "Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n",
  3402. tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask);
  3403. }
  3404. ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0,
  3405. HAL_RXDMA_BUF,
  3406. DP_RXDMA_REFILL_RING_SIZE,
  3407. &tlv_filter);
  3408. return ret;
  3409. }
  3410. int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab)
  3411. {
  3412. struct ath12k_dp *dp = &ab->dp;
  3413. struct htt_rx_ring_tlv_filter tlv_filter = {0};
  3414. u32 ring_id;
  3415. int ret = 0;
  3416. u32 hal_rx_desc_sz = ab->hal.hal_desc_sz;
  3417. int i;
  3418. ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
  3419. tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING;
  3420. tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR;
  3421. tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST |
  3422. HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST |
  3423. HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA;
  3424. tlv_filter.offset_valid = true;
  3425. tlv_filter.rx_packet_offset = hal_rx_desc_sz;
  3426. tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv);
  3427. tlv_filter.rx_mpdu_start_offset =
  3428. ab->hal_rx_ops->rx_desc_get_mpdu_start_offset();
  3429. tlv_filter.rx_msdu_end_offset =
  3430. ab->hal_rx_ops->rx_desc_get_msdu_end_offset();
  3431. /* TODO: Selectively subscribe to required qwords within msdu_end
  3432. * and mpdu_start and setup the mask in below msg
  3433. * and modify the rx_desc struct
  3434. */
  3435. for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
  3436. ring_id = dp->rx_mac_buf_ring[i].ring_id;
  3437. ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i,
  3438. HAL_RXDMA_BUF,
  3439. DP_RXDMA_REFILL_RING_SIZE,
  3440. &tlv_filter);
  3441. }
  3442. return ret;
  3443. }
  3444. int ath12k_dp_rx_htt_setup(struct ath12k_base *ab)
  3445. {
  3446. struct ath12k_dp *dp = &ab->dp;
  3447. u32 ring_id;
  3448. int i, ret;
  3449. /* TODO: Need to verify the HTT setup for QCN9224 */
  3450. ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
  3451. ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF);
  3452. if (ret) {
  3453. ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
  3454. ret);
  3455. return ret;
  3456. }
  3457. if (ab->hw_params->rx_mac_buf_ring) {
  3458. for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
  3459. ring_id = dp->rx_mac_buf_ring[i].ring_id;
  3460. ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
  3461. i, HAL_RXDMA_BUF);
  3462. if (ret) {
  3463. ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
  3464. i, ret);
  3465. return ret;
  3466. }
  3467. }
  3468. }
  3469. for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) {
  3470. ring_id = dp->rxdma_err_dst_ring[i].ring_id;
  3471. ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
  3472. i, HAL_RXDMA_DST);
  3473. if (ret) {
  3474. ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
  3475. i, ret);
  3476. return ret;
  3477. }
  3478. }
  3479. if (ab->hw_params->rxdma1_enable) {
  3480. ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
  3481. ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
  3482. 0, HAL_RXDMA_MONITOR_BUF);
  3483. if (ret) {
  3484. ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
  3485. ret);
  3486. return ret;
  3487. }
  3488. }
  3489. ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab);
  3490. if (ret) {
  3491. ath12k_warn(ab, "failed to setup rxdma ring selection config\n");
  3492. return ret;
  3493. }
  3494. return 0;
  3495. }
  3496. int ath12k_dp_rx_alloc(struct ath12k_base *ab)
  3497. {
  3498. struct ath12k_dp *dp = &ab->dp;
  3499. int i, ret;
  3500. idr_init(&dp->rxdma_mon_buf_ring.bufs_idr);
  3501. spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock);
  3502. ret = ath12k_dp_srng_setup(ab,
  3503. &dp->rx_refill_buf_ring.refill_buf_ring,
  3504. HAL_RXDMA_BUF, 0, 0,
  3505. DP_RXDMA_BUF_RING_SIZE);
  3506. if (ret) {
  3507. ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n");
  3508. return ret;
  3509. }
  3510. if (ab->hw_params->rx_mac_buf_ring) {
  3511. for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
  3512. ret = ath12k_dp_srng_setup(ab,
  3513. &dp->rx_mac_buf_ring[i],
  3514. HAL_RXDMA_BUF, 1,
  3515. i, DP_RX_MAC_BUF_RING_SIZE);
  3516. if (ret) {
  3517. ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n",
  3518. i);
  3519. return ret;
  3520. }
  3521. }
  3522. }
  3523. for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) {
  3524. ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i],
  3525. HAL_RXDMA_DST, 0, i,
  3526. DP_RXDMA_ERR_DST_RING_SIZE);
  3527. if (ret) {
  3528. ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i);
  3529. return ret;
  3530. }
  3531. }
  3532. if (ab->hw_params->rxdma1_enable) {
  3533. ret = ath12k_dp_srng_setup(ab,
  3534. &dp->rxdma_mon_buf_ring.refill_buf_ring,
  3535. HAL_RXDMA_MONITOR_BUF, 0, 0,
  3536. DP_RXDMA_MONITOR_BUF_RING_SIZE);
  3537. if (ret) {
  3538. ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n");
  3539. return ret;
  3540. }
  3541. }
  3542. ret = ath12k_dp_rxdma_buf_setup(ab);
  3543. if (ret) {
  3544. ath12k_warn(ab, "failed to setup rxdma ring\n");
  3545. return ret;
  3546. }
  3547. return 0;
  3548. }
  3549. int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id)
  3550. {
  3551. struct ath12k *ar = ab->pdevs[mac_id].ar;
  3552. struct ath12k_pdev_dp *dp = &ar->dp;
  3553. u32 ring_id;
  3554. int i;
  3555. int ret;
  3556. if (!ab->hw_params->rxdma1_enable)
  3557. goto out;
  3558. ret = ath12k_dp_rx_pdev_srng_alloc(ar);
  3559. if (ret) {
  3560. ath12k_warn(ab, "failed to setup rx srngs\n");
  3561. return ret;
  3562. }
  3563. for (i = 0; i < ab->hw_params->num_rxdma_per_pdev; i++) {
  3564. ring_id = dp->rxdma_mon_dst_ring[i].ring_id;
  3565. ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id,
  3566. mac_id + i,
  3567. HAL_RXDMA_MONITOR_DST);
  3568. if (ret) {
  3569. ath12k_warn(ab,
  3570. "failed to configure rxdma_mon_dst_ring %d %d\n",
  3571. i, ret);
  3572. return ret;
  3573. }
  3574. }
  3575. out:
  3576. return 0;
  3577. }
  3578. static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar)
  3579. {
  3580. struct ath12k_pdev_dp *dp = &ar->dp;
  3581. struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data;
  3582. skb_queue_head_init(&pmon->rx_status_q);
  3583. pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
  3584. memset(&pmon->rx_mon_stats, 0,
  3585. sizeof(pmon->rx_mon_stats));
  3586. return 0;
  3587. }
  3588. int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar)
  3589. {
  3590. struct ath12k_pdev_dp *dp = &ar->dp;
  3591. struct ath12k_mon_data *pmon = &dp->mon_data;
  3592. int ret = 0;
  3593. ret = ath12k_dp_rx_pdev_mon_status_attach(ar);
  3594. if (ret) {
  3595. ath12k_warn(ar->ab, "pdev_mon_status_attach() failed");
  3596. return ret;
  3597. }
  3598. /* if rxdma1_enable is false, no need to setup
  3599. * rxdma_mon_desc_ring.
  3600. */
  3601. if (!ar->ab->hw_params->rxdma1_enable)
  3602. return 0;
  3603. pmon->mon_last_linkdesc_paddr = 0;
  3604. pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
  3605. spin_lock_init(&pmon->mon_lock);
  3606. return 0;
  3607. }