common.c 143 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /******************************************************************************
  3. *
  4. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  5. *
  6. * Contact Information:
  7. * Intel Linux Wireless <ilw@linux.intel.com>
  8. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  9. *****************************************************************************/
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/etherdevice.h>
  13. #include <linux/sched.h>
  14. #include <linux/slab.h>
  15. #include <linux/types.h>
  16. #include <linux/lockdep.h>
  17. #include <linux/pci.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/delay.h>
  20. #include <linux/skbuff.h>
  21. #include <net/mac80211.h>
  22. #include "common.h"
  23. int
  24. _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
  25. {
  26. const int interval = 10; /* microseconds */
  27. int t = 0;
  28. do {
  29. if ((_il_rd(il, addr) & mask) == (bits & mask))
  30. return t;
  31. udelay(interval);
  32. t += interval;
  33. } while (t < timeout);
  34. return -ETIMEDOUT;
  35. }
  36. EXPORT_SYMBOL(_il_poll_bit);
  37. void
  38. il_set_bit(struct il_priv *p, u32 r, u32 m)
  39. {
  40. unsigned long reg_flags;
  41. spin_lock_irqsave(&p->reg_lock, reg_flags);
  42. _il_set_bit(p, r, m);
  43. spin_unlock_irqrestore(&p->reg_lock, reg_flags);
  44. }
  45. EXPORT_SYMBOL(il_set_bit);
  46. void
  47. il_clear_bit(struct il_priv *p, u32 r, u32 m)
  48. {
  49. unsigned long reg_flags;
  50. spin_lock_irqsave(&p->reg_lock, reg_flags);
  51. _il_clear_bit(p, r, m);
  52. spin_unlock_irqrestore(&p->reg_lock, reg_flags);
  53. }
  54. EXPORT_SYMBOL(il_clear_bit);
  55. bool
  56. _il_grab_nic_access(struct il_priv *il)
  57. {
  58. int ret;
  59. u32 val;
  60. /* this bit wakes up the NIC */
  61. _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  62. /*
  63. * These bits say the device is running, and should keep running for
  64. * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
  65. * but they do not indicate that embedded SRAM is restored yet;
  66. * 3945 and 4965 have volatile SRAM, and must save/restore contents
  67. * to/from host DRAM when sleeping/waking for power-saving.
  68. * Each direction takes approximately 1/4 millisecond; with this
  69. * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
  70. * series of register accesses are expected (e.g. reading Event Log),
  71. * to keep device from sleeping.
  72. *
  73. * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
  74. * SRAM is okay/restored. We don't check that here because this call
  75. * is just for hardware register access; but GP1 MAC_SLEEP check is a
  76. * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
  77. *
  78. */
  79. ret =
  80. _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
  81. (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
  82. CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
  83. if (unlikely(ret < 0)) {
  84. val = _il_rd(il, CSR_GP_CNTRL);
  85. WARN_ONCE(1, "Timeout waiting for ucode processor access "
  86. "(CSR_GP_CNTRL 0x%08x)\n", val);
  87. _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
  88. return false;
  89. }
  90. return true;
  91. }
  92. EXPORT_SYMBOL_GPL(_il_grab_nic_access);
  93. int
  94. il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
  95. {
  96. const int interval = 10; /* microseconds */
  97. int t = 0;
  98. do {
  99. if ((il_rd(il, addr) & mask) == mask)
  100. return t;
  101. udelay(interval);
  102. t += interval;
  103. } while (t < timeout);
  104. return -ETIMEDOUT;
  105. }
  106. EXPORT_SYMBOL(il_poll_bit);
  107. u32
  108. il_rd_prph(struct il_priv *il, u32 reg)
  109. {
  110. unsigned long reg_flags;
  111. u32 val;
  112. spin_lock_irqsave(&il->reg_lock, reg_flags);
  113. _il_grab_nic_access(il);
  114. val = _il_rd_prph(il, reg);
  115. _il_release_nic_access(il);
  116. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  117. return val;
  118. }
  119. EXPORT_SYMBOL(il_rd_prph);
  120. void
  121. il_wr_prph(struct il_priv *il, u32 addr, u32 val)
  122. {
  123. unsigned long reg_flags;
  124. spin_lock_irqsave(&il->reg_lock, reg_flags);
  125. if (likely(_il_grab_nic_access(il))) {
  126. _il_wr_prph(il, addr, val);
  127. _il_release_nic_access(il);
  128. }
  129. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  130. }
  131. EXPORT_SYMBOL(il_wr_prph);
  132. u32
  133. il_read_targ_mem(struct il_priv *il, u32 addr)
  134. {
  135. unsigned long reg_flags;
  136. u32 value;
  137. spin_lock_irqsave(&il->reg_lock, reg_flags);
  138. _il_grab_nic_access(il);
  139. _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
  140. value = _il_rd(il, HBUS_TARG_MEM_RDAT);
  141. _il_release_nic_access(il);
  142. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  143. return value;
  144. }
  145. EXPORT_SYMBOL(il_read_targ_mem);
  146. void
  147. il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
  148. {
  149. unsigned long reg_flags;
  150. spin_lock_irqsave(&il->reg_lock, reg_flags);
  151. if (likely(_il_grab_nic_access(il))) {
  152. _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
  153. _il_wr(il, HBUS_TARG_MEM_WDAT, val);
  154. _il_release_nic_access(il);
  155. }
  156. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  157. }
  158. EXPORT_SYMBOL(il_write_targ_mem);
  159. const char *
  160. il_get_cmd_string(u8 cmd)
  161. {
  162. switch (cmd) {
  163. IL_CMD(N_ALIVE);
  164. IL_CMD(N_ERROR);
  165. IL_CMD(C_RXON);
  166. IL_CMD(C_RXON_ASSOC);
  167. IL_CMD(C_QOS_PARAM);
  168. IL_CMD(C_RXON_TIMING);
  169. IL_CMD(C_ADD_STA);
  170. IL_CMD(C_REM_STA);
  171. IL_CMD(C_WEPKEY);
  172. IL_CMD(N_3945_RX);
  173. IL_CMD(C_TX);
  174. IL_CMD(C_RATE_SCALE);
  175. IL_CMD(C_LEDS);
  176. IL_CMD(C_TX_LINK_QUALITY_CMD);
  177. IL_CMD(C_CHANNEL_SWITCH);
  178. IL_CMD(N_CHANNEL_SWITCH);
  179. IL_CMD(C_SPECTRUM_MEASUREMENT);
  180. IL_CMD(N_SPECTRUM_MEASUREMENT);
  181. IL_CMD(C_POWER_TBL);
  182. IL_CMD(N_PM_SLEEP);
  183. IL_CMD(N_PM_DEBUG_STATS);
  184. IL_CMD(C_SCAN);
  185. IL_CMD(C_SCAN_ABORT);
  186. IL_CMD(N_SCAN_START);
  187. IL_CMD(N_SCAN_RESULTS);
  188. IL_CMD(N_SCAN_COMPLETE);
  189. IL_CMD(N_BEACON);
  190. IL_CMD(C_TX_BEACON);
  191. IL_CMD(C_TX_PWR_TBL);
  192. IL_CMD(C_BT_CONFIG);
  193. IL_CMD(C_STATS);
  194. IL_CMD(N_STATS);
  195. IL_CMD(N_CARD_STATE);
  196. IL_CMD(N_MISSED_BEACONS);
  197. IL_CMD(C_CT_KILL_CONFIG);
  198. IL_CMD(C_SENSITIVITY);
  199. IL_CMD(C_PHY_CALIBRATION);
  200. IL_CMD(N_RX_PHY);
  201. IL_CMD(N_RX_MPDU);
  202. IL_CMD(N_RX);
  203. IL_CMD(N_COMPRESSED_BA);
  204. default:
  205. return "UNKNOWN";
  206. }
  207. }
  208. EXPORT_SYMBOL(il_get_cmd_string);
  209. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  210. static void
  211. il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd,
  212. struct il_rx_pkt *pkt)
  213. {
  214. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  215. IL_ERR("Bad return from %s (0x%08X)\n",
  216. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  217. return;
  218. }
  219. #ifdef CONFIG_IWLEGACY_DEBUG
  220. switch (cmd->hdr.cmd) {
  221. case C_TX_LINK_QUALITY_CMD:
  222. case C_SENSITIVITY:
  223. D_HC_DUMP("back from %s (0x%08X)\n",
  224. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  225. break;
  226. default:
  227. D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd),
  228. pkt->hdr.flags);
  229. }
  230. #endif
  231. }
  232. static int
  233. il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
  234. {
  235. int ret;
  236. BUG_ON(!(cmd->flags & CMD_ASYNC));
  237. /* An asynchronous command can not expect an SKB to be set. */
  238. BUG_ON(cmd->flags & CMD_WANT_SKB);
  239. /* Assign a generic callback if one is not provided */
  240. if (!cmd->callback)
  241. cmd->callback = il_generic_cmd_callback;
  242. if (test_bit(S_EXIT_PENDING, &il->status))
  243. return -EBUSY;
  244. ret = il_enqueue_hcmd(il, cmd);
  245. if (ret < 0) {
  246. IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
  247. il_get_cmd_string(cmd->id), ret);
  248. return ret;
  249. }
  250. return 0;
  251. }
  252. int
  253. il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
  254. {
  255. int cmd_idx;
  256. int ret;
  257. lockdep_assert_held(&il->mutex);
  258. BUG_ON(cmd->flags & CMD_ASYNC);
  259. /* A synchronous command can not have a callback set. */
  260. BUG_ON(cmd->callback);
  261. D_INFO("Attempting to send sync command %s\n",
  262. il_get_cmd_string(cmd->id));
  263. set_bit(S_HCMD_ACTIVE, &il->status);
  264. D_INFO("Setting HCMD_ACTIVE for command %s\n",
  265. il_get_cmd_string(cmd->id));
  266. cmd_idx = il_enqueue_hcmd(il, cmd);
  267. if (cmd_idx < 0) {
  268. ret = cmd_idx;
  269. IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
  270. il_get_cmd_string(cmd->id), ret);
  271. goto out;
  272. }
  273. ret = wait_event_timeout(il->wait_command_queue,
  274. !test_bit(S_HCMD_ACTIVE, &il->status),
  275. HOST_COMPLETE_TIMEOUT);
  276. if (!ret) {
  277. if (test_bit(S_HCMD_ACTIVE, &il->status)) {
  278. IL_ERR("Error sending %s: time out after %dms.\n",
  279. il_get_cmd_string(cmd->id),
  280. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  281. clear_bit(S_HCMD_ACTIVE, &il->status);
  282. D_INFO("Clearing HCMD_ACTIVE for command %s\n",
  283. il_get_cmd_string(cmd->id));
  284. ret = -ETIMEDOUT;
  285. goto cancel;
  286. }
  287. }
  288. if (test_bit(S_RFKILL, &il->status)) {
  289. IL_ERR("Command %s aborted: RF KILL Switch\n",
  290. il_get_cmd_string(cmd->id));
  291. ret = -ECANCELED;
  292. goto fail;
  293. }
  294. if (test_bit(S_FW_ERROR, &il->status)) {
  295. IL_ERR("Command %s failed: FW Error\n",
  296. il_get_cmd_string(cmd->id));
  297. ret = -EIO;
  298. goto fail;
  299. }
  300. if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
  301. IL_ERR("Error: Response NULL in '%s'\n",
  302. il_get_cmd_string(cmd->id));
  303. ret = -EIO;
  304. goto cancel;
  305. }
  306. ret = 0;
  307. goto out;
  308. cancel:
  309. if (cmd->flags & CMD_WANT_SKB) {
  310. /*
  311. * Cancel the CMD_WANT_SKB flag for the cmd in the
  312. * TX cmd queue. Otherwise in case the cmd comes
  313. * in later, it will possibly set an invalid
  314. * address (cmd->meta.source).
  315. */
  316. il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB;
  317. }
  318. fail:
  319. if (cmd->reply_page) {
  320. il_free_pages(il, cmd->reply_page);
  321. cmd->reply_page = 0;
  322. }
  323. out:
  324. return ret;
  325. }
  326. EXPORT_SYMBOL(il_send_cmd_sync);
  327. int
  328. il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
  329. {
  330. if (cmd->flags & CMD_ASYNC)
  331. return il_send_cmd_async(il, cmd);
  332. return il_send_cmd_sync(il, cmd);
  333. }
  334. EXPORT_SYMBOL(il_send_cmd);
  335. int
  336. il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
  337. {
  338. struct il_host_cmd cmd = {
  339. .id = id,
  340. .len = len,
  341. .data = data,
  342. };
  343. return il_send_cmd_sync(il, &cmd);
  344. }
  345. EXPORT_SYMBOL(il_send_cmd_pdu);
  346. int
  347. il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
  348. void (*callback) (struct il_priv *il,
  349. struct il_device_cmd *cmd,
  350. struct il_rx_pkt *pkt))
  351. {
  352. struct il_host_cmd cmd = {
  353. .id = id,
  354. .len = len,
  355. .data = data,
  356. };
  357. cmd.flags |= CMD_ASYNC;
  358. cmd.callback = callback;
  359. return il_send_cmd_async(il, &cmd);
  360. }
  361. EXPORT_SYMBOL(il_send_cmd_pdu_async);
  362. /* default: IL_LED_BLINK(0) using blinking idx table */
  363. static int led_mode;
  364. module_param(led_mode, int, 0444);
  365. MODULE_PARM_DESC(led_mode,
  366. "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking");
  367. /* Throughput OFF time(ms) ON time (ms)
  368. * >300 25 25
  369. * >200 to 300 40 40
  370. * >100 to 200 55 55
  371. * >70 to 100 65 65
  372. * >50 to 70 75 75
  373. * >20 to 50 85 85
  374. * >10 to 20 95 95
  375. * >5 to 10 110 110
  376. * >1 to 5 130 130
  377. * >0 to 1 167 167
  378. * <=0 SOLID ON
  379. */
  380. static const struct ieee80211_tpt_blink il_blink[] = {
  381. {.throughput = 0, .blink_time = 334},
  382. {.throughput = 1 * 1024 - 1, .blink_time = 260},
  383. {.throughput = 5 * 1024 - 1, .blink_time = 220},
  384. {.throughput = 10 * 1024 - 1, .blink_time = 190},
  385. {.throughput = 20 * 1024 - 1, .blink_time = 170},
  386. {.throughput = 50 * 1024 - 1, .blink_time = 150},
  387. {.throughput = 70 * 1024 - 1, .blink_time = 130},
  388. {.throughput = 100 * 1024 - 1, .blink_time = 110},
  389. {.throughput = 200 * 1024 - 1, .blink_time = 80},
  390. {.throughput = 300 * 1024 - 1, .blink_time = 50},
  391. };
  392. /*
  393. * Adjust led blink rate to compensate on a MAC Clock difference on every HW
  394. * Led blink rate analysis showed an average deviation of 0% on 3945,
  395. * 5% on 4965 HW.
  396. * Need to compensate on the led on/off time per HW according to the deviation
  397. * to achieve the desired led frequency
  398. * The calculation is: (100-averageDeviation)/100 * blinkTime
  399. * For code efficiency the calculation will be:
  400. * compensation = (100 - averageDeviation) * 64 / 100
  401. * NewBlinkTime = (compensation * BlinkTime) / 64
  402. */
  403. static inline u8
  404. il_blink_compensation(struct il_priv *il, u8 time, u16 compensation)
  405. {
  406. if (!compensation) {
  407. IL_ERR("undefined blink compensation: "
  408. "use pre-defined blinking time\n");
  409. return time;
  410. }
  411. return (u8) ((time * compensation) >> 6);
  412. }
  413. /* Set led pattern command */
  414. static int
  415. il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off)
  416. {
  417. struct il_led_cmd led_cmd = {
  418. .id = IL_LED_LINK,
  419. .interval = IL_DEF_LED_INTRVL
  420. };
  421. int ret;
  422. if (!test_bit(S_READY, &il->status))
  423. return -EBUSY;
  424. if (il->blink_on == on && il->blink_off == off)
  425. return 0;
  426. if (off == 0) {
  427. /* led is SOLID_ON */
  428. on = IL_LED_SOLID;
  429. }
  430. D_LED("Led blink time compensation=%u\n",
  431. il->cfg->led_compensation);
  432. led_cmd.on =
  433. il_blink_compensation(il, on,
  434. il->cfg->led_compensation);
  435. led_cmd.off =
  436. il_blink_compensation(il, off,
  437. il->cfg->led_compensation);
  438. ret = il->ops->send_led_cmd(il, &led_cmd);
  439. if (!ret) {
  440. il->blink_on = on;
  441. il->blink_off = off;
  442. }
  443. return ret;
  444. }
  445. static void
  446. il_led_brightness_set(struct led_classdev *led_cdev,
  447. enum led_brightness brightness)
  448. {
  449. struct il_priv *il = container_of(led_cdev, struct il_priv, led);
  450. unsigned long on = 0;
  451. if (brightness > 0)
  452. on = IL_LED_SOLID;
  453. il_led_cmd(il, on, 0);
  454. }
  455. static int
  456. il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
  457. unsigned long *delay_off)
  458. {
  459. struct il_priv *il = container_of(led_cdev, struct il_priv, led);
  460. return il_led_cmd(il, *delay_on, *delay_off);
  461. }
  462. void
  463. il_leds_init(struct il_priv *il)
  464. {
  465. int mode = led_mode;
  466. int ret;
  467. if (mode == IL_LED_DEFAULT)
  468. mode = il->cfg->led_mode;
  469. il->led.name =
  470. kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy));
  471. if (!il->led.name)
  472. return;
  473. il->led.brightness_set = il_led_brightness_set;
  474. il->led.blink_set = il_led_blink_set;
  475. il->led.max_brightness = 1;
  476. switch (mode) {
  477. case IL_LED_DEFAULT:
  478. WARN_ON(1);
  479. break;
  480. case IL_LED_BLINK:
  481. il->led.default_trigger =
  482. ieee80211_create_tpt_led_trigger(il->hw,
  483. IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
  484. il_blink,
  485. ARRAY_SIZE(il_blink));
  486. break;
  487. case IL_LED_RF_STATE:
  488. il->led.default_trigger = ieee80211_get_radio_led_name(il->hw);
  489. break;
  490. }
  491. ret = led_classdev_register(&il->pci_dev->dev, &il->led);
  492. if (ret) {
  493. kfree(il->led.name);
  494. return;
  495. }
  496. il->led_registered = true;
  497. }
  498. EXPORT_SYMBOL(il_leds_init);
  499. void
  500. il_leds_exit(struct il_priv *il)
  501. {
  502. if (!il->led_registered)
  503. return;
  504. led_classdev_unregister(&il->led);
  505. kfree(il->led.name);
  506. }
  507. EXPORT_SYMBOL(il_leds_exit);
  508. /************************** EEPROM BANDS ****************************
  509. *
  510. * The il_eeprom_band definitions below provide the mapping from the
  511. * EEPROM contents to the specific channel number supported for each
  512. * band.
  513. *
  514. * For example, il_priv->eeprom.band_3_channels[4] from the band_3
  515. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  516. * The specific geography and calibration information for that channel
  517. * is contained in the eeprom map itself.
  518. *
  519. * During init, we copy the eeprom information and channel map
  520. * information into il->channel_info_24/52 and il->channel_map_24/52
  521. *
  522. * channel_map_24/52 provides the idx in the channel_info array for a
  523. * given channel. We have to have two separate maps as there is channel
  524. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  525. * band_2
  526. *
  527. * A value of 0xff stored in the channel_map indicates that the channel
  528. * is not supported by the hardware at all.
  529. *
  530. * A value of 0xfe in the channel_map indicates that the channel is not
  531. * valid for Tx with the current hardware. This means that
  532. * while the system can tune and receive on a given channel, it may not
  533. * be able to associate or transmit any frames on that
  534. * channel. There is no corresponding channel information for that
  535. * entry.
  536. *
  537. *********************************************************************/
  538. /* 2.4 GHz */
  539. const u8 il_eeprom_band_1[14] = {
  540. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  541. };
  542. /* 5.2 GHz bands */
  543. static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
  544. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  545. };
  546. static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
  547. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  548. };
  549. static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
  550. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  551. };
  552. static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
  553. 145, 149, 153, 157, 161, 165
  554. };
  555. static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
  556. 1, 2, 3, 4, 5, 6, 7
  557. };
  558. static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
  559. 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
  560. };
  561. /******************************************************************************
  562. *
  563. * EEPROM related functions
  564. *
  565. ******************************************************************************/
  566. static int
  567. il_eeprom_verify_signature(struct il_priv *il)
  568. {
  569. u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
  570. int ret = 0;
  571. D_EEPROM("EEPROM signature=0x%08x\n", gp);
  572. switch (gp) {
  573. case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
  574. case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
  575. break;
  576. default:
  577. IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp);
  578. ret = -ENOENT;
  579. break;
  580. }
  581. return ret;
  582. }
  583. const u8 *
  584. il_eeprom_query_addr(const struct il_priv *il, size_t offset)
  585. {
  586. BUG_ON(offset >= il->cfg->eeprom_size);
  587. return &il->eeprom[offset];
  588. }
  589. EXPORT_SYMBOL(il_eeprom_query_addr);
  590. u16
  591. il_eeprom_query16(const struct il_priv *il, size_t offset)
  592. {
  593. if (!il->eeprom)
  594. return 0;
  595. return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8);
  596. }
  597. EXPORT_SYMBOL(il_eeprom_query16);
  598. /*
  599. * il_eeprom_init - read EEPROM contents
  600. *
  601. * Load the EEPROM contents from adapter into il->eeprom
  602. *
  603. * NOTE: This routine uses the non-debug IO access functions.
  604. */
  605. int
  606. il_eeprom_init(struct il_priv *il)
  607. {
  608. __le16 *e;
  609. u32 gp = _il_rd(il, CSR_EEPROM_GP);
  610. int sz;
  611. int ret;
  612. int addr;
  613. /* allocate eeprom */
  614. sz = il->cfg->eeprom_size;
  615. D_EEPROM("NVM size = %d\n", sz);
  616. il->eeprom = kzalloc(sz, GFP_KERNEL);
  617. if (!il->eeprom)
  618. return -ENOMEM;
  619. e = (__le16 *) il->eeprom;
  620. il->ops->apm_init(il);
  621. ret = il_eeprom_verify_signature(il);
  622. if (ret < 0) {
  623. IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  624. ret = -ENOENT;
  625. goto err;
  626. }
  627. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  628. ret = il->ops->eeprom_acquire_semaphore(il);
  629. if (ret < 0) {
  630. IL_ERR("Failed to acquire EEPROM semaphore.\n");
  631. ret = -ENOENT;
  632. goto err;
  633. }
  634. /* eeprom is an array of 16bit values */
  635. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  636. u32 r;
  637. _il_wr(il, CSR_EEPROM_REG,
  638. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  639. ret =
  640. _il_poll_bit(il, CSR_EEPROM_REG,
  641. CSR_EEPROM_REG_READ_VALID_MSK,
  642. CSR_EEPROM_REG_READ_VALID_MSK,
  643. IL_EEPROM_ACCESS_TIMEOUT);
  644. if (ret < 0) {
  645. IL_ERR("Time out reading EEPROM[%d]\n", addr);
  646. goto done;
  647. }
  648. r = _il_rd(il, CSR_EEPROM_REG);
  649. e[addr / 2] = cpu_to_le16(r >> 16);
  650. }
  651. D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM",
  652. il_eeprom_query16(il, EEPROM_VERSION));
  653. ret = 0;
  654. done:
  655. il->ops->eeprom_release_semaphore(il);
  656. err:
  657. if (ret)
  658. il_eeprom_free(il);
  659. /* Reset chip to save power until we load uCode during "up". */
  660. il_apm_stop(il);
  661. return ret;
  662. }
  663. EXPORT_SYMBOL(il_eeprom_init);
  664. void
  665. il_eeprom_free(struct il_priv *il)
  666. {
  667. kfree(il->eeprom);
  668. il->eeprom = NULL;
  669. }
  670. EXPORT_SYMBOL(il_eeprom_free);
  671. static void
  672. il_init_band_reference(const struct il_priv *il, int eep_band,
  673. int *eeprom_ch_count,
  674. const struct il_eeprom_channel **eeprom_ch_info,
  675. const u8 **eeprom_ch_idx)
  676. {
  677. u32 offset = il->cfg->regulatory_bands[eep_band - 1];
  678. switch (eep_band) {
  679. case 1: /* 2.4GHz band */
  680. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
  681. *eeprom_ch_info =
  682. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  683. offset);
  684. *eeprom_ch_idx = il_eeprom_band_1;
  685. break;
  686. case 2: /* 4.9GHz band */
  687. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
  688. *eeprom_ch_info =
  689. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  690. offset);
  691. *eeprom_ch_idx = il_eeprom_band_2;
  692. break;
  693. case 3: /* 5.2GHz band */
  694. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
  695. *eeprom_ch_info =
  696. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  697. offset);
  698. *eeprom_ch_idx = il_eeprom_band_3;
  699. break;
  700. case 4: /* 5.5GHz band */
  701. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
  702. *eeprom_ch_info =
  703. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  704. offset);
  705. *eeprom_ch_idx = il_eeprom_band_4;
  706. break;
  707. case 5: /* 5.7GHz band */
  708. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
  709. *eeprom_ch_info =
  710. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  711. offset);
  712. *eeprom_ch_idx = il_eeprom_band_5;
  713. break;
  714. case 6: /* 2.4GHz ht40 channels */
  715. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
  716. *eeprom_ch_info =
  717. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  718. offset);
  719. *eeprom_ch_idx = il_eeprom_band_6;
  720. break;
  721. case 7: /* 5 GHz ht40 channels */
  722. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
  723. *eeprom_ch_info =
  724. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  725. offset);
  726. *eeprom_ch_idx = il_eeprom_band_7;
  727. break;
  728. default:
  729. BUG();
  730. }
  731. }
  732. #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
  733. ? # x " " : "")
  734. /*
  735. * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
  736. *
  737. * Does not set up a command, or touch hardware.
  738. */
  739. static int
  740. il_mod_ht40_chan_info(struct il_priv *il, enum nl80211_band band, u16 channel,
  741. const struct il_eeprom_channel *eeprom_ch,
  742. u8 clear_ht40_extension_channel)
  743. {
  744. struct il_channel_info *ch_info;
  745. ch_info =
  746. (struct il_channel_info *)il_get_channel_info(il, band, channel);
  747. if (!il_is_channel_valid(ch_info))
  748. return -1;
  749. D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
  750. " Ad-Hoc %ssupported\n", ch_info->channel,
  751. il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
  752. CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE),
  753. CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE),
  754. CHECK_AND_PRINT(DFS), eeprom_ch->flags,
  755. eeprom_ch->max_power_avg,
  756. ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
  757. !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not ");
  758. ch_info->ht40_eeprom = *eeprom_ch;
  759. ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
  760. ch_info->ht40_flags = eeprom_ch->flags;
  761. if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
  762. ch_info->ht40_extension_channel &=
  763. ~clear_ht40_extension_channel;
  764. return 0;
  765. }
  766. #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  767. ? # x " " : "")
  768. /*
  769. * il_init_channel_map - Set up driver's info for all possible channels
  770. */
  771. int
  772. il_init_channel_map(struct il_priv *il)
  773. {
  774. int eeprom_ch_count = 0;
  775. const u8 *eeprom_ch_idx = NULL;
  776. const struct il_eeprom_channel *eeprom_ch_info = NULL;
  777. int band, ch;
  778. struct il_channel_info *ch_info;
  779. if (il->channel_count) {
  780. D_EEPROM("Channel map already initialized.\n");
  781. return 0;
  782. }
  783. D_EEPROM("Initializing regulatory info from EEPROM\n");
  784. il->channel_count =
  785. ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) +
  786. ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) +
  787. ARRAY_SIZE(il_eeprom_band_5);
  788. D_EEPROM("Parsing data for %d channels.\n", il->channel_count);
  789. il->channel_info =
  790. kcalloc(il->channel_count, sizeof(struct il_channel_info),
  791. GFP_KERNEL);
  792. if (!il->channel_info) {
  793. IL_ERR("Could not allocate channel_info\n");
  794. il->channel_count = 0;
  795. return -ENOMEM;
  796. }
  797. ch_info = il->channel_info;
  798. /* Loop through the 5 EEPROM bands adding them in order to the
  799. * channel map we maintain (that contains additional information than
  800. * what just in the EEPROM) */
  801. for (band = 1; band <= 5; band++) {
  802. il_init_band_reference(il, band, &eeprom_ch_count,
  803. &eeprom_ch_info, &eeprom_ch_idx);
  804. /* Loop through each band adding each of the channels */
  805. for (ch = 0; ch < eeprom_ch_count; ch++) {
  806. ch_info->channel = eeprom_ch_idx[ch];
  807. ch_info->band =
  808. (band ==
  809. 1) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
  810. /* permanently store EEPROM's channel regulatory flags
  811. * and max power in channel info database. */
  812. ch_info->eeprom = eeprom_ch_info[ch];
  813. /* Copy the run-time flags so they are there even on
  814. * invalid channels */
  815. ch_info->flags = eeprom_ch_info[ch].flags;
  816. /* First write that ht40 is not enabled, and then enable
  817. * one by one */
  818. ch_info->ht40_extension_channel =
  819. IEEE80211_CHAN_NO_HT40;
  820. if (!(il_is_channel_valid(ch_info))) {
  821. D_EEPROM("Ch. %d Flags %x [%sGHz] - "
  822. "No traffic\n", ch_info->channel,
  823. ch_info->flags,
  824. il_is_channel_a_band(ch_info) ? "5.2" :
  825. "2.4");
  826. ch_info++;
  827. continue;
  828. }
  829. /* Initialize regulatory-based run-time data */
  830. ch_info->max_power_avg = ch_info->curr_txpow =
  831. eeprom_ch_info[ch].max_power_avg;
  832. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  833. ch_info->min_power = 0;
  834. D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):"
  835. " Ad-Hoc %ssupported\n", ch_info->channel,
  836. il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
  837. CHECK_AND_PRINT_I(VALID),
  838. CHECK_AND_PRINT_I(IBSS),
  839. CHECK_AND_PRINT_I(ACTIVE),
  840. CHECK_AND_PRINT_I(RADAR),
  841. CHECK_AND_PRINT_I(WIDE),
  842. CHECK_AND_PRINT_I(DFS),
  843. eeprom_ch_info[ch].flags,
  844. eeprom_ch_info[ch].max_power_avg,
  845. ((eeprom_ch_info[ch].
  846. flags & EEPROM_CHANNEL_IBSS) &&
  847. !(eeprom_ch_info[ch].
  848. flags & EEPROM_CHANNEL_RADAR)) ? "" :
  849. "not ");
  850. ch_info++;
  851. }
  852. }
  853. /* Check if we do have HT40 channels */
  854. if (il->cfg->regulatory_bands[5] == EEPROM_REGULATORY_BAND_NO_HT40 &&
  855. il->cfg->regulatory_bands[6] == EEPROM_REGULATORY_BAND_NO_HT40)
  856. return 0;
  857. /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
  858. for (band = 6; band <= 7; band++) {
  859. enum nl80211_band ieeeband;
  860. il_init_band_reference(il, band, &eeprom_ch_count,
  861. &eeprom_ch_info, &eeprom_ch_idx);
  862. /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
  863. ieeeband =
  864. (band == 6) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
  865. /* Loop through each band adding each of the channels */
  866. for (ch = 0; ch < eeprom_ch_count; ch++) {
  867. /* Set up driver's info for lower half */
  868. il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch],
  869. &eeprom_ch_info[ch],
  870. IEEE80211_CHAN_NO_HT40PLUS);
  871. /* Set up driver's info for upper half */
  872. il_mod_ht40_chan_info(il, ieeeband,
  873. eeprom_ch_idx[ch] + 4,
  874. &eeprom_ch_info[ch],
  875. IEEE80211_CHAN_NO_HT40MINUS);
  876. }
  877. }
  878. return 0;
  879. }
  880. EXPORT_SYMBOL(il_init_channel_map);
  881. /*
  882. * il_free_channel_map - undo allocations in il_init_channel_map
  883. */
  884. void
  885. il_free_channel_map(struct il_priv *il)
  886. {
  887. kfree(il->channel_info);
  888. il->channel_count = 0;
  889. }
  890. EXPORT_SYMBOL(il_free_channel_map);
  891. /*
  892. * il_get_channel_info - Find driver's ilate channel info
  893. *
  894. * Based on band and channel number.
  895. */
  896. const struct il_channel_info *
  897. il_get_channel_info(const struct il_priv *il, enum nl80211_band band,
  898. u16 channel)
  899. {
  900. int i;
  901. switch (band) {
  902. case NL80211_BAND_5GHZ:
  903. for (i = 14; i < il->channel_count; i++) {
  904. if (il->channel_info[i].channel == channel)
  905. return &il->channel_info[i];
  906. }
  907. break;
  908. case NL80211_BAND_2GHZ:
  909. if (channel >= 1 && channel <= 14)
  910. return &il->channel_info[channel - 1];
  911. break;
  912. default:
  913. BUG();
  914. }
  915. return NULL;
  916. }
  917. EXPORT_SYMBOL(il_get_channel_info);
  918. /*
  919. * Setting power level allows the card to go to sleep when not busy.
  920. *
  921. * We calculate a sleep command based on the required latency, which
  922. * we get from mac80211.
  923. */
  924. #define SLP_VEC(X0, X1, X2, X3, X4) { \
  925. cpu_to_le32(X0), \
  926. cpu_to_le32(X1), \
  927. cpu_to_le32(X2), \
  928. cpu_to_le32(X3), \
  929. cpu_to_le32(X4) \
  930. }
  931. static void
  932. il_build_powertable_cmd(struct il_priv *il, struct il_powertable_cmd *cmd)
  933. {
  934. static const __le32 interval[3][IL_POWER_VEC_SIZE] = {
  935. SLP_VEC(2, 2, 4, 6, 0xFF),
  936. SLP_VEC(2, 4, 7, 10, 10),
  937. SLP_VEC(4, 7, 10, 10, 0xFF)
  938. };
  939. int i, dtim_period, no_dtim;
  940. u32 max_sleep;
  941. bool skip;
  942. memset(cmd, 0, sizeof(*cmd));
  943. if (il->power_data.pci_pm)
  944. cmd->flags |= IL_POWER_PCI_PM_MSK;
  945. /* if no Power Save, we are done */
  946. if (il->power_data.ps_disabled)
  947. return;
  948. cmd->flags = IL_POWER_DRIVER_ALLOW_SLEEP_MSK;
  949. cmd->keep_alive_seconds = 0;
  950. cmd->debug_flags = 0;
  951. cmd->rx_data_timeout = cpu_to_le32(25 * 1024);
  952. cmd->tx_data_timeout = cpu_to_le32(25 * 1024);
  953. cmd->keep_alive_beacons = 0;
  954. dtim_period = il->vif ? il->vif->bss_conf.dtim_period : 0;
  955. if (dtim_period <= 2) {
  956. memcpy(cmd->sleep_interval, interval[0], sizeof(interval[0]));
  957. no_dtim = 2;
  958. } else if (dtim_period <= 10) {
  959. memcpy(cmd->sleep_interval, interval[1], sizeof(interval[1]));
  960. no_dtim = 2;
  961. } else {
  962. memcpy(cmd->sleep_interval, interval[2], sizeof(interval[2]));
  963. no_dtim = 0;
  964. }
  965. if (dtim_period == 0) {
  966. dtim_period = 1;
  967. skip = false;
  968. } else {
  969. skip = !!no_dtim;
  970. }
  971. if (skip) {
  972. __le32 tmp = cmd->sleep_interval[IL_POWER_VEC_SIZE - 1];
  973. max_sleep = le32_to_cpu(tmp);
  974. if (max_sleep == 0xFF)
  975. max_sleep = dtim_period * (skip + 1);
  976. else if (max_sleep > dtim_period)
  977. max_sleep = (max_sleep / dtim_period) * dtim_period;
  978. cmd->flags |= IL_POWER_SLEEP_OVER_DTIM_MSK;
  979. } else {
  980. max_sleep = dtim_period;
  981. cmd->flags &= ~IL_POWER_SLEEP_OVER_DTIM_MSK;
  982. }
  983. for (i = 0; i < IL_POWER_VEC_SIZE; i++)
  984. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  985. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  986. }
  987. static int
  988. il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
  989. {
  990. D_POWER("Sending power/sleep command\n");
  991. D_POWER("Flags value = 0x%08X\n", cmd->flags);
  992. D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  993. D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  994. D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  995. le32_to_cpu(cmd->sleep_interval[0]),
  996. le32_to_cpu(cmd->sleep_interval[1]),
  997. le32_to_cpu(cmd->sleep_interval[2]),
  998. le32_to_cpu(cmd->sleep_interval[3]),
  999. le32_to_cpu(cmd->sleep_interval[4]));
  1000. return il_send_cmd_pdu(il, C_POWER_TBL,
  1001. sizeof(struct il_powertable_cmd), cmd);
  1002. }
  1003. static int
  1004. il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force)
  1005. {
  1006. int ret;
  1007. bool update_chains;
  1008. lockdep_assert_held(&il->mutex);
  1009. /* Don't update the RX chain when chain noise calibration is running */
  1010. update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
  1011. il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
  1012. if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
  1013. return 0;
  1014. if (!il_is_ready_rf(il))
  1015. return -EIO;
  1016. /* scan complete use sleep_power_next, need to be updated */
  1017. memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
  1018. if (test_bit(S_SCANNING, &il->status) && !force) {
  1019. D_INFO("Defer power set mode while scanning\n");
  1020. return 0;
  1021. }
  1022. if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
  1023. set_bit(S_POWER_PMI, &il->status);
  1024. ret = il_set_power(il, cmd);
  1025. if (!ret) {
  1026. if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
  1027. clear_bit(S_POWER_PMI, &il->status);
  1028. if (il->ops->update_chain_flags && update_chains)
  1029. il->ops->update_chain_flags(il);
  1030. else if (il->ops->update_chain_flags)
  1031. D_POWER("Cannot update the power, chain noise "
  1032. "calibration running: %d\n",
  1033. il->chain_noise_data.state);
  1034. memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
  1035. } else
  1036. IL_ERR("set power fail, ret = %d", ret);
  1037. return ret;
  1038. }
  1039. int
  1040. il_power_update_mode(struct il_priv *il, bool force)
  1041. {
  1042. struct il_powertable_cmd cmd;
  1043. il_build_powertable_cmd(il, &cmd);
  1044. return il_power_set_mode(il, &cmd, force);
  1045. }
  1046. EXPORT_SYMBOL(il_power_update_mode);
  1047. /* initialize to default */
  1048. void
  1049. il_power_initialize(struct il_priv *il)
  1050. {
  1051. u16 lctl;
  1052. pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
  1053. il->power_data.pci_pm = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
  1054. il->power_data.debug_sleep_level_override = -1;
  1055. memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd));
  1056. }
  1057. EXPORT_SYMBOL(il_power_initialize);
  1058. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  1059. * sending probe req. This should be set long enough to hear probe responses
  1060. * from more than one AP. */
  1061. #define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  1062. #define IL_ACTIVE_DWELL_TIME_52 (20)
  1063. #define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  1064. #define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  1065. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  1066. * Must be set longer than active dwell time.
  1067. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  1068. #define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  1069. #define IL_PASSIVE_DWELL_TIME_52 (10)
  1070. #define IL_PASSIVE_DWELL_BASE (100)
  1071. #define IL_CHANNEL_TUNE_TIME 5
  1072. static int
  1073. il_send_scan_abort(struct il_priv *il)
  1074. {
  1075. int ret;
  1076. struct il_rx_pkt *pkt;
  1077. struct il_host_cmd cmd = {
  1078. .id = C_SCAN_ABORT,
  1079. .flags = CMD_WANT_SKB,
  1080. };
  1081. /* Exit instantly with error when device is not ready
  1082. * to receive scan abort command or it does not perform
  1083. * hardware scan currently */
  1084. if (!test_bit(S_READY, &il->status) ||
  1085. !test_bit(S_GEO_CONFIGURED, &il->status) ||
  1086. !test_bit(S_SCAN_HW, &il->status) ||
  1087. test_bit(S_FW_ERROR, &il->status) ||
  1088. test_bit(S_EXIT_PENDING, &il->status))
  1089. return -EIO;
  1090. ret = il_send_cmd_sync(il, &cmd);
  1091. if (ret)
  1092. return ret;
  1093. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1094. if (pkt->u.status != CAN_ABORT_STATUS) {
  1095. /* The scan abort will return 1 for success or
  1096. * 2 for "failure". A failure condition can be
  1097. * due to simply not being in an active scan which
  1098. * can occur if we send the scan abort before we
  1099. * the microcode has notified us that a scan is
  1100. * completed. */
  1101. D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
  1102. ret = -EIO;
  1103. }
  1104. il_free_pages(il, cmd.reply_page);
  1105. return ret;
  1106. }
  1107. static void
  1108. il_complete_scan(struct il_priv *il, bool aborted)
  1109. {
  1110. struct cfg80211_scan_info info = {
  1111. .aborted = aborted,
  1112. };
  1113. /* check if scan was requested from mac80211 */
  1114. if (il->scan_request) {
  1115. D_SCAN("Complete scan in mac80211\n");
  1116. ieee80211_scan_completed(il->hw, &info);
  1117. }
  1118. il->scan_vif = NULL;
  1119. il->scan_request = NULL;
  1120. }
  1121. void
  1122. il_force_scan_end(struct il_priv *il)
  1123. {
  1124. lockdep_assert_held(&il->mutex);
  1125. if (!test_bit(S_SCANNING, &il->status)) {
  1126. D_SCAN("Forcing scan end while not scanning\n");
  1127. return;
  1128. }
  1129. D_SCAN("Forcing scan end\n");
  1130. clear_bit(S_SCANNING, &il->status);
  1131. clear_bit(S_SCAN_HW, &il->status);
  1132. clear_bit(S_SCAN_ABORTING, &il->status);
  1133. il_complete_scan(il, true);
  1134. }
  1135. static void
  1136. il_do_scan_abort(struct il_priv *il)
  1137. {
  1138. int ret;
  1139. lockdep_assert_held(&il->mutex);
  1140. if (!test_bit(S_SCANNING, &il->status)) {
  1141. D_SCAN("Not performing scan to abort\n");
  1142. return;
  1143. }
  1144. if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
  1145. D_SCAN("Scan abort in progress\n");
  1146. return;
  1147. }
  1148. ret = il_send_scan_abort(il);
  1149. if (ret) {
  1150. D_SCAN("Send scan abort failed %d\n", ret);
  1151. il_force_scan_end(il);
  1152. } else
  1153. D_SCAN("Successfully send scan abort\n");
  1154. }
  1155. /*
  1156. * il_scan_cancel - Cancel any currently executing HW scan
  1157. */
  1158. int
  1159. il_scan_cancel(struct il_priv *il)
  1160. {
  1161. D_SCAN("Queuing abort scan\n");
  1162. queue_work(il->workqueue, &il->abort_scan);
  1163. return 0;
  1164. }
  1165. EXPORT_SYMBOL(il_scan_cancel);
  1166. /*
  1167. * il_scan_cancel_timeout - Cancel any currently executing HW scan
  1168. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1169. *
  1170. */
  1171. int
  1172. il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
  1173. {
  1174. unsigned long timeout = jiffies + msecs_to_jiffies(ms);
  1175. lockdep_assert_held(&il->mutex);
  1176. D_SCAN("Scan cancel timeout\n");
  1177. il_do_scan_abort(il);
  1178. while (time_before_eq(jiffies, timeout)) {
  1179. if (!test_bit(S_SCAN_HW, &il->status))
  1180. break;
  1181. msleep(20);
  1182. }
  1183. return test_bit(S_SCAN_HW, &il->status);
  1184. }
  1185. EXPORT_SYMBOL(il_scan_cancel_timeout);
  1186. /* Service response to C_SCAN (0x80) */
  1187. static void
  1188. il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb)
  1189. {
  1190. #ifdef CONFIG_IWLEGACY_DEBUG
  1191. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1192. struct il_scanreq_notification *notif =
  1193. (struct il_scanreq_notification *)pkt->u.raw;
  1194. D_SCAN("Scan request status = 0x%x\n", notif->status);
  1195. #endif
  1196. }
  1197. /* Service N_SCAN_START (0x82) */
  1198. static void
  1199. il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb)
  1200. {
  1201. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1202. struct il_scanstart_notification *notif =
  1203. (struct il_scanstart_notification *)pkt->u.raw;
  1204. il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  1205. D_SCAN("Scan start: " "%d [802.11%s] "
  1206. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel,
  1207. notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high),
  1208. le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer);
  1209. }
  1210. /* Service N_SCAN_RESULTS (0x83) */
  1211. static void
  1212. il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb)
  1213. {
  1214. #ifdef CONFIG_IWLEGACY_DEBUG
  1215. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1216. struct il_scanresults_notification *notif =
  1217. (struct il_scanresults_notification *)pkt->u.raw;
  1218. D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d "
  1219. "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a",
  1220. le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low),
  1221. le32_to_cpu(notif->stats[0]),
  1222. le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
  1223. #endif
  1224. }
  1225. /* Service N_SCAN_COMPLETE (0x84) */
  1226. static void
  1227. il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb)
  1228. {
  1229. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1230. struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  1231. D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  1232. scan_notif->scanned_channels, scan_notif->tsf_low,
  1233. scan_notif->tsf_high, scan_notif->status);
  1234. /* The HW is no longer scanning */
  1235. clear_bit(S_SCAN_HW, &il->status);
  1236. D_SCAN("Scan on %sGHz took %dms\n",
  1237. (il->scan_band == NL80211_BAND_2GHZ) ? "2.4" : "5.2",
  1238. jiffies_to_msecs(jiffies - il->scan_start));
  1239. queue_work(il->workqueue, &il->scan_completed);
  1240. }
  1241. void
  1242. il_setup_rx_scan_handlers(struct il_priv *il)
  1243. {
  1244. /* scan handlers */
  1245. il->handlers[C_SCAN] = il_hdl_scan;
  1246. il->handlers[N_SCAN_START] = il_hdl_scan_start;
  1247. il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results;
  1248. il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete;
  1249. }
  1250. EXPORT_SYMBOL(il_setup_rx_scan_handlers);
  1251. u16
  1252. il_get_active_dwell_time(struct il_priv *il, enum nl80211_band band,
  1253. u8 n_probes)
  1254. {
  1255. if (band == NL80211_BAND_5GHZ)
  1256. return IL_ACTIVE_DWELL_TIME_52 +
  1257. IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  1258. else
  1259. return IL_ACTIVE_DWELL_TIME_24 +
  1260. IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  1261. }
  1262. EXPORT_SYMBOL(il_get_active_dwell_time);
  1263. u16
  1264. il_get_passive_dwell_time(struct il_priv *il, enum nl80211_band band,
  1265. struct ieee80211_vif *vif)
  1266. {
  1267. u16 value;
  1268. u16 passive =
  1269. (band ==
  1270. NL80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE +
  1271. IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE +
  1272. IL_PASSIVE_DWELL_TIME_52;
  1273. if (il_is_any_associated(il)) {
  1274. /*
  1275. * If we're associated, we clamp the maximum passive
  1276. * dwell time to be 98% of the smallest beacon interval
  1277. * (minus 2 * channel tune time)
  1278. */
  1279. value = il->vif ? il->vif->bss_conf.beacon_int : 0;
  1280. if (value > IL_PASSIVE_DWELL_BASE || !value)
  1281. value = IL_PASSIVE_DWELL_BASE;
  1282. value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
  1283. passive = min(value, passive);
  1284. }
  1285. return passive;
  1286. }
  1287. EXPORT_SYMBOL(il_get_passive_dwell_time);
  1288. void
  1289. il_init_scan_params(struct il_priv *il)
  1290. {
  1291. u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
  1292. if (!il->scan_tx_ant[NL80211_BAND_5GHZ])
  1293. il->scan_tx_ant[NL80211_BAND_5GHZ] = ant_idx;
  1294. if (!il->scan_tx_ant[NL80211_BAND_2GHZ])
  1295. il->scan_tx_ant[NL80211_BAND_2GHZ] = ant_idx;
  1296. }
  1297. EXPORT_SYMBOL(il_init_scan_params);
  1298. static int
  1299. il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif)
  1300. {
  1301. int ret;
  1302. lockdep_assert_held(&il->mutex);
  1303. cancel_delayed_work(&il->scan_check);
  1304. if (!il_is_ready_rf(il)) {
  1305. IL_WARN("Request scan called when driver not ready.\n");
  1306. return -EIO;
  1307. }
  1308. if (test_bit(S_SCAN_HW, &il->status)) {
  1309. D_SCAN("Multiple concurrent scan requests in parallel.\n");
  1310. return -EBUSY;
  1311. }
  1312. if (test_bit(S_SCAN_ABORTING, &il->status)) {
  1313. D_SCAN("Scan request while abort pending.\n");
  1314. return -EBUSY;
  1315. }
  1316. D_SCAN("Starting scan...\n");
  1317. set_bit(S_SCANNING, &il->status);
  1318. il->scan_start = jiffies;
  1319. ret = il->ops->request_scan(il, vif);
  1320. if (ret) {
  1321. clear_bit(S_SCANNING, &il->status);
  1322. return ret;
  1323. }
  1324. queue_delayed_work(il->workqueue, &il->scan_check,
  1325. IL_SCAN_CHECK_WATCHDOG);
  1326. return 0;
  1327. }
  1328. int
  1329. il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1330. struct ieee80211_scan_request *hw_req)
  1331. {
  1332. struct cfg80211_scan_request *req = &hw_req->req;
  1333. struct il_priv *il = hw->priv;
  1334. int ret;
  1335. if (req->n_channels == 0) {
  1336. IL_ERR("Can not scan on no channels.\n");
  1337. return -EINVAL;
  1338. }
  1339. mutex_lock(&il->mutex);
  1340. D_MAC80211("enter\n");
  1341. if (test_bit(S_SCANNING, &il->status)) {
  1342. D_SCAN("Scan already in progress.\n");
  1343. ret = -EAGAIN;
  1344. goto out_unlock;
  1345. }
  1346. /* mac80211 will only ask for one band at a time */
  1347. il->scan_request = req;
  1348. il->scan_vif = vif;
  1349. il->scan_band = req->channels[0]->band;
  1350. ret = il_scan_initiate(il, vif);
  1351. out_unlock:
  1352. D_MAC80211("leave ret %d\n", ret);
  1353. mutex_unlock(&il->mutex);
  1354. return ret;
  1355. }
  1356. EXPORT_SYMBOL(il_mac_hw_scan);
  1357. static void
  1358. il_bg_scan_check(struct work_struct *data)
  1359. {
  1360. struct il_priv *il =
  1361. container_of(data, struct il_priv, scan_check.work);
  1362. D_SCAN("Scan check work\n");
  1363. /* Since we are here firmware does not finish scan and
  1364. * most likely is in bad shape, so we don't bother to
  1365. * send abort command, just force scan complete to mac80211 */
  1366. mutex_lock(&il->mutex);
  1367. il_force_scan_end(il);
  1368. mutex_unlock(&il->mutex);
  1369. }
  1370. /*
  1371. * il_fill_probe_req - fill in all required fields and IE for probe request
  1372. */
  1373. u16
  1374. il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
  1375. const u8 *ta, const u8 *ies, int ie_len, int left)
  1376. {
  1377. int len = 0;
  1378. u8 *pos = NULL;
  1379. /* Make sure there is enough space for the probe request,
  1380. * two mandatory IEs and the data */
  1381. left -= 24;
  1382. if (left < 0)
  1383. return 0;
  1384. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1385. eth_broadcast_addr(frame->da);
  1386. memcpy(frame->sa, ta, ETH_ALEN);
  1387. eth_broadcast_addr(frame->bssid);
  1388. frame->seq_ctrl = 0;
  1389. len += 24;
  1390. /* ...next IE... */
  1391. pos = &frame->u.probe_req.variable[0];
  1392. /* fill in our indirect SSID IE */
  1393. left -= 2;
  1394. if (left < 0)
  1395. return 0;
  1396. *pos++ = WLAN_EID_SSID;
  1397. *pos++ = 0;
  1398. len += 2;
  1399. if (WARN_ON(left < ie_len))
  1400. return len;
  1401. if (ies && ie_len) {
  1402. memcpy(pos, ies, ie_len);
  1403. len += ie_len;
  1404. }
  1405. return (u16) len;
  1406. }
  1407. EXPORT_SYMBOL(il_fill_probe_req);
  1408. static void
  1409. il_bg_abort_scan(struct work_struct *work)
  1410. {
  1411. struct il_priv *il = container_of(work, struct il_priv, abort_scan);
  1412. D_SCAN("Abort scan work\n");
  1413. /* We keep scan_check work queued in case when firmware will not
  1414. * report back scan completed notification */
  1415. mutex_lock(&il->mutex);
  1416. il_scan_cancel_timeout(il, 200);
  1417. mutex_unlock(&il->mutex);
  1418. }
  1419. static void
  1420. il_bg_scan_completed(struct work_struct *work)
  1421. {
  1422. struct il_priv *il = container_of(work, struct il_priv, scan_completed);
  1423. bool aborted;
  1424. D_SCAN("Completed scan.\n");
  1425. cancel_delayed_work(&il->scan_check);
  1426. mutex_lock(&il->mutex);
  1427. aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
  1428. if (aborted)
  1429. D_SCAN("Aborted scan completed.\n");
  1430. if (!test_and_clear_bit(S_SCANNING, &il->status)) {
  1431. D_SCAN("Scan already completed.\n");
  1432. goto out_settings;
  1433. }
  1434. il_complete_scan(il, aborted);
  1435. out_settings:
  1436. /* Can we still talk to firmware ? */
  1437. if (!il_is_ready_rf(il))
  1438. goto out;
  1439. /*
  1440. * We do not commit power settings while scan is pending,
  1441. * do it now if the settings changed.
  1442. */
  1443. il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
  1444. il_set_tx_power(il, il->tx_power_next, false);
  1445. il->ops->post_scan(il);
  1446. out:
  1447. mutex_unlock(&il->mutex);
  1448. }
  1449. void
  1450. il_setup_scan_deferred_work(struct il_priv *il)
  1451. {
  1452. INIT_WORK(&il->scan_completed, il_bg_scan_completed);
  1453. INIT_WORK(&il->abort_scan, il_bg_abort_scan);
  1454. INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
  1455. }
  1456. EXPORT_SYMBOL(il_setup_scan_deferred_work);
  1457. void
  1458. il_cancel_scan_deferred_work(struct il_priv *il)
  1459. {
  1460. cancel_work_sync(&il->abort_scan);
  1461. cancel_work_sync(&il->scan_completed);
  1462. if (cancel_delayed_work_sync(&il->scan_check)) {
  1463. mutex_lock(&il->mutex);
  1464. il_force_scan_end(il);
  1465. mutex_unlock(&il->mutex);
  1466. }
  1467. }
  1468. EXPORT_SYMBOL(il_cancel_scan_deferred_work);
  1469. /* il->sta_lock must be held */
  1470. static void
  1471. il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
  1472. {
  1473. if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
  1474. IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n",
  1475. sta_id, il->stations[sta_id].sta.sta.addr);
  1476. if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
  1477. D_ASSOC("STA id %u addr %pM already present"
  1478. " in uCode (according to driver)\n", sta_id,
  1479. il->stations[sta_id].sta.sta.addr);
  1480. } else {
  1481. il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
  1482. D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id,
  1483. il->stations[sta_id].sta.sta.addr);
  1484. }
  1485. }
  1486. static int
  1487. il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta,
  1488. struct il_rx_pkt *pkt, bool sync)
  1489. {
  1490. u8 sta_id = addsta->sta.sta_id;
  1491. unsigned long flags;
  1492. int ret = -EIO;
  1493. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1494. IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags);
  1495. return ret;
  1496. }
  1497. D_INFO("Processing response for adding station %u\n", sta_id);
  1498. spin_lock_irqsave(&il->sta_lock, flags);
  1499. switch (pkt->u.add_sta.status) {
  1500. case ADD_STA_SUCCESS_MSK:
  1501. D_INFO("C_ADD_STA PASSED\n");
  1502. il_sta_ucode_activate(il, sta_id);
  1503. ret = 0;
  1504. break;
  1505. case ADD_STA_NO_ROOM_IN_TBL:
  1506. IL_ERR("Adding station %d failed, no room in table.\n", sta_id);
  1507. break;
  1508. case ADD_STA_NO_BLOCK_ACK_RESOURCE:
  1509. IL_ERR("Adding station %d failed, no block ack resource.\n",
  1510. sta_id);
  1511. break;
  1512. case ADD_STA_MODIFY_NON_EXIST_STA:
  1513. IL_ERR("Attempting to modify non-existing station %d\n",
  1514. sta_id);
  1515. break;
  1516. default:
  1517. D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status);
  1518. break;
  1519. }
  1520. D_INFO("%s station id %u addr %pM\n",
  1521. il->stations[sta_id].sta.mode ==
  1522. STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id,
  1523. il->stations[sta_id].sta.sta.addr);
  1524. /*
  1525. * XXX: The MAC address in the command buffer is often changed from
  1526. * the original sent to the device. That is, the MAC address
  1527. * written to the command buffer often is not the same MAC address
  1528. * read from the command buffer when the command returns. This
  1529. * issue has not yet been resolved and this debugging is left to
  1530. * observe the problem.
  1531. */
  1532. D_INFO("%s station according to cmd buffer %pM\n",
  1533. il->stations[sta_id].sta.mode ==
  1534. STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr);
  1535. spin_unlock_irqrestore(&il->sta_lock, flags);
  1536. return ret;
  1537. }
  1538. static void
  1539. il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd,
  1540. struct il_rx_pkt *pkt)
  1541. {
  1542. struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload;
  1543. il_process_add_sta_resp(il, addsta, pkt, false);
  1544. }
  1545. int
  1546. il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags)
  1547. {
  1548. struct il_rx_pkt *pkt = NULL;
  1549. int ret = 0;
  1550. u8 data[sizeof(*sta)];
  1551. struct il_host_cmd cmd = {
  1552. .id = C_ADD_STA,
  1553. .flags = flags,
  1554. .data = data,
  1555. };
  1556. u8 sta_id __maybe_unused = sta->sta.sta_id;
  1557. D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr,
  1558. flags & CMD_ASYNC ? "a" : "");
  1559. if (flags & CMD_ASYNC)
  1560. cmd.callback = il_add_sta_callback;
  1561. else {
  1562. cmd.flags |= CMD_WANT_SKB;
  1563. might_sleep();
  1564. }
  1565. cmd.len = il->ops->build_addsta_hcmd(sta, data);
  1566. ret = il_send_cmd(il, &cmd);
  1567. if (ret)
  1568. return ret;
  1569. if (flags & CMD_ASYNC)
  1570. return 0;
  1571. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1572. ret = il_process_add_sta_resp(il, sta, pkt, true);
  1573. il_free_pages(il, cmd.reply_page);
  1574. return ret;
  1575. }
  1576. EXPORT_SYMBOL(il_send_add_sta);
  1577. static void
  1578. il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta)
  1579. {
  1580. struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->deflink.ht_cap;
  1581. __le32 sta_flags;
  1582. if (!sta || !sta_ht_inf->ht_supported)
  1583. goto done;
  1584. D_ASSOC("spatial multiplexing power save mode: %s\n",
  1585. (sta->deflink.smps_mode == IEEE80211_SMPS_STATIC) ? "static" :
  1586. (sta->deflink.smps_mode == IEEE80211_SMPS_DYNAMIC) ? "dynamic" :
  1587. "disabled");
  1588. sta_flags = il->stations[idx].sta.station_flags;
  1589. sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
  1590. switch (sta->deflink.smps_mode) {
  1591. case IEEE80211_SMPS_STATIC:
  1592. sta_flags |= STA_FLG_MIMO_DIS_MSK;
  1593. break;
  1594. case IEEE80211_SMPS_DYNAMIC:
  1595. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  1596. break;
  1597. case IEEE80211_SMPS_OFF:
  1598. break;
  1599. default:
  1600. IL_WARN("Invalid MIMO PS mode %d\n", sta->deflink.smps_mode);
  1601. break;
  1602. }
  1603. sta_flags |=
  1604. cpu_to_le32((u32) sta_ht_inf->
  1605. ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  1606. sta_flags |=
  1607. cpu_to_le32((u32) sta_ht_inf->
  1608. ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  1609. if (il_is_ht40_tx_allowed(il, &sta->deflink.ht_cap))
  1610. sta_flags |= STA_FLG_HT40_EN_MSK;
  1611. else
  1612. sta_flags &= ~STA_FLG_HT40_EN_MSK;
  1613. il->stations[idx].sta.station_flags = sta_flags;
  1614. done:
  1615. return;
  1616. }
  1617. /*
  1618. * il_prep_station - Prepare station information for addition
  1619. *
  1620. * should be called with sta_lock held
  1621. */
  1622. u8
  1623. il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
  1624. struct ieee80211_sta *sta)
  1625. {
  1626. struct il_station_entry *station;
  1627. int i;
  1628. u8 sta_id = IL_INVALID_STATION;
  1629. u16 rate;
  1630. if (is_ap)
  1631. sta_id = IL_AP_ID;
  1632. else if (is_broadcast_ether_addr(addr))
  1633. sta_id = il->hw_params.bcast_id;
  1634. else
  1635. for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
  1636. if (ether_addr_equal(il->stations[i].sta.sta.addr,
  1637. addr)) {
  1638. sta_id = i;
  1639. break;
  1640. }
  1641. if (!il->stations[i].used &&
  1642. sta_id == IL_INVALID_STATION)
  1643. sta_id = i;
  1644. }
  1645. /*
  1646. * These two conditions have the same outcome, but keep them
  1647. * separate
  1648. */
  1649. if (unlikely(sta_id == IL_INVALID_STATION))
  1650. return sta_id;
  1651. /*
  1652. * uCode is not able to deal with multiple requests to add a
  1653. * station. Keep track if one is in progress so that we do not send
  1654. * another.
  1655. */
  1656. if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
  1657. D_INFO("STA %d already in process of being added.\n", sta_id);
  1658. return sta_id;
  1659. }
  1660. if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
  1661. (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
  1662. ether_addr_equal(il->stations[sta_id].sta.sta.addr, addr)) {
  1663. D_ASSOC("STA %d (%pM) already added, not adding again.\n",
  1664. sta_id, addr);
  1665. return sta_id;
  1666. }
  1667. station = &il->stations[sta_id];
  1668. station->used = IL_STA_DRIVER_ACTIVE;
  1669. D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr);
  1670. il->num_stations++;
  1671. /* Set up the C_ADD_STA command to send to device */
  1672. memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
  1673. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  1674. station->sta.mode = 0;
  1675. station->sta.sta.sta_id = sta_id;
  1676. station->sta.station_flags = 0;
  1677. /*
  1678. * OK to call unconditionally, since local stations (IBSS BSSID
  1679. * STA and broadcast STA) pass in a NULL sta, and mac80211
  1680. * doesn't allow HT IBSS.
  1681. */
  1682. il_set_ht_add_station(il, sta_id, sta);
  1683. /* 3945 only */
  1684. rate = (il->band == NL80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP;
  1685. /* Turn on both antennas for the station... */
  1686. station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
  1687. return sta_id;
  1688. }
  1689. EXPORT_SYMBOL_GPL(il_prep_station);
  1690. #define STA_WAIT_TIMEOUT (HZ/2)
  1691. /*
  1692. * il_add_station_common -
  1693. */
  1694. int
  1695. il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
  1696. struct ieee80211_sta *sta, u8 *sta_id_r)
  1697. {
  1698. unsigned long flags_spin;
  1699. int ret = 0;
  1700. u8 sta_id;
  1701. struct il_addsta_cmd sta_cmd;
  1702. *sta_id_r = 0;
  1703. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1704. sta_id = il_prep_station(il, addr, is_ap, sta);
  1705. if (sta_id == IL_INVALID_STATION) {
  1706. IL_ERR("Unable to prepare station %pM for addition\n", addr);
  1707. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1708. return -EINVAL;
  1709. }
  1710. /*
  1711. * uCode is not able to deal with multiple requests to add a
  1712. * station. Keep track if one is in progress so that we do not send
  1713. * another.
  1714. */
  1715. if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
  1716. D_INFO("STA %d already in process of being added.\n", sta_id);
  1717. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1718. return -EEXIST;
  1719. }
  1720. if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
  1721. (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
  1722. D_ASSOC("STA %d (%pM) already added, not adding again.\n",
  1723. sta_id, addr);
  1724. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1725. return -EEXIST;
  1726. }
  1727. il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
  1728. memcpy(&sta_cmd, &il->stations[sta_id].sta,
  1729. sizeof(struct il_addsta_cmd));
  1730. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1731. /* Add station to device's station table */
  1732. ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  1733. if (ret) {
  1734. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1735. IL_ERR("Adding station %pM failed.\n",
  1736. il->stations[sta_id].sta.sta.addr);
  1737. il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
  1738. il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
  1739. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1740. }
  1741. *sta_id_r = sta_id;
  1742. return ret;
  1743. }
  1744. EXPORT_SYMBOL(il_add_station_common);
  1745. /*
  1746. * il_sta_ucode_deactivate - deactivate ucode status for a station
  1747. *
  1748. * il->sta_lock must be held
  1749. */
  1750. static void
  1751. il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
  1752. {
  1753. /* Ucode must be active and driver must be non active */
  1754. if ((il->stations[sta_id].
  1755. used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
  1756. IL_STA_UCODE_ACTIVE)
  1757. IL_ERR("removed non active STA %u\n", sta_id);
  1758. il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
  1759. memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
  1760. D_ASSOC("Removed STA %u\n", sta_id);
  1761. }
  1762. static int
  1763. il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id,
  1764. bool temporary)
  1765. {
  1766. struct il_rx_pkt *pkt;
  1767. int ret;
  1768. unsigned long flags_spin;
  1769. struct il_rem_sta_cmd rm_sta_cmd;
  1770. struct il_host_cmd cmd = {
  1771. .id = C_REM_STA,
  1772. .len = sizeof(struct il_rem_sta_cmd),
  1773. .flags = CMD_SYNC,
  1774. .data = &rm_sta_cmd,
  1775. };
  1776. memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
  1777. rm_sta_cmd.num_sta = 1;
  1778. memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
  1779. cmd.flags |= CMD_WANT_SKB;
  1780. ret = il_send_cmd(il, &cmd);
  1781. if (ret)
  1782. return ret;
  1783. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1784. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1785. IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags);
  1786. ret = -EIO;
  1787. }
  1788. if (!ret) {
  1789. switch (pkt->u.rem_sta.status) {
  1790. case REM_STA_SUCCESS_MSK:
  1791. if (!temporary) {
  1792. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1793. il_sta_ucode_deactivate(il, sta_id);
  1794. spin_unlock_irqrestore(&il->sta_lock,
  1795. flags_spin);
  1796. }
  1797. D_ASSOC("C_REM_STA PASSED\n");
  1798. break;
  1799. default:
  1800. ret = -EIO;
  1801. IL_ERR("C_REM_STA failed\n");
  1802. break;
  1803. }
  1804. }
  1805. il_free_pages(il, cmd.reply_page);
  1806. return ret;
  1807. }
  1808. /*
  1809. * il_remove_station - Remove driver's knowledge of station.
  1810. */
  1811. int
  1812. il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr)
  1813. {
  1814. unsigned long flags;
  1815. if (!il_is_ready(il)) {
  1816. D_INFO("Unable to remove station %pM, device not ready.\n",
  1817. addr);
  1818. /*
  1819. * It is typical for stations to be removed when we are
  1820. * going down. Return success since device will be down
  1821. * soon anyway
  1822. */
  1823. return 0;
  1824. }
  1825. D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr);
  1826. if (WARN_ON(sta_id == IL_INVALID_STATION))
  1827. return -EINVAL;
  1828. spin_lock_irqsave(&il->sta_lock, flags);
  1829. if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
  1830. D_INFO("Removing %pM but non DRIVER active\n", addr);
  1831. goto out_err;
  1832. }
  1833. if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
  1834. D_INFO("Removing %pM but non UCODE active\n", addr);
  1835. goto out_err;
  1836. }
  1837. if (il->stations[sta_id].used & IL_STA_LOCAL) {
  1838. kfree(il->stations[sta_id].lq);
  1839. il->stations[sta_id].lq = NULL;
  1840. }
  1841. il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
  1842. il->num_stations--;
  1843. BUG_ON(il->num_stations < 0);
  1844. spin_unlock_irqrestore(&il->sta_lock, flags);
  1845. return il_send_remove_station(il, addr, sta_id, false);
  1846. out_err:
  1847. spin_unlock_irqrestore(&il->sta_lock, flags);
  1848. return -EINVAL;
  1849. }
  1850. EXPORT_SYMBOL_GPL(il_remove_station);
  1851. /*
  1852. * il_clear_ucode_stations - clear ucode station table bits
  1853. *
  1854. * This function clears all the bits in the driver indicating
  1855. * which stations are active in the ucode. Call when something
  1856. * other than explicit station management would cause this in
  1857. * the ucode, e.g. unassociated RXON.
  1858. */
  1859. void
  1860. il_clear_ucode_stations(struct il_priv *il)
  1861. {
  1862. int i;
  1863. unsigned long flags_spin;
  1864. bool cleared = false;
  1865. D_INFO("Clearing ucode stations in driver\n");
  1866. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1867. for (i = 0; i < il->hw_params.max_stations; i++) {
  1868. if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
  1869. D_INFO("Clearing ucode active for station %d\n", i);
  1870. il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
  1871. cleared = true;
  1872. }
  1873. }
  1874. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1875. if (!cleared)
  1876. D_INFO("No active stations found to be cleared\n");
  1877. }
  1878. EXPORT_SYMBOL(il_clear_ucode_stations);
  1879. /*
  1880. * il_restore_stations() - Restore driver known stations to device
  1881. *
  1882. * All stations considered active by driver, but not present in ucode, is
  1883. * restored.
  1884. *
  1885. * Function sleeps.
  1886. */
  1887. void
  1888. il_restore_stations(struct il_priv *il)
  1889. {
  1890. struct il_addsta_cmd sta_cmd;
  1891. struct il_link_quality_cmd lq;
  1892. unsigned long flags_spin;
  1893. int i;
  1894. bool found = false;
  1895. int ret;
  1896. bool send_lq;
  1897. if (!il_is_ready(il)) {
  1898. D_INFO("Not ready yet, not restoring any stations.\n");
  1899. return;
  1900. }
  1901. D_ASSOC("Restoring all known stations ... start.\n");
  1902. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1903. for (i = 0; i < il->hw_params.max_stations; i++) {
  1904. if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
  1905. !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
  1906. D_ASSOC("Restoring sta %pM\n",
  1907. il->stations[i].sta.sta.addr);
  1908. il->stations[i].sta.mode = 0;
  1909. il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
  1910. found = true;
  1911. }
  1912. }
  1913. for (i = 0; i < il->hw_params.max_stations; i++) {
  1914. if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
  1915. memcpy(&sta_cmd, &il->stations[i].sta,
  1916. sizeof(struct il_addsta_cmd));
  1917. send_lq = false;
  1918. if (il->stations[i].lq) {
  1919. memcpy(&lq, il->stations[i].lq,
  1920. sizeof(struct il_link_quality_cmd));
  1921. send_lq = true;
  1922. }
  1923. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1924. ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  1925. if (ret) {
  1926. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1927. IL_ERR("Adding station %pM failed.\n",
  1928. il->stations[i].sta.sta.addr);
  1929. il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE;
  1930. il->stations[i].used &=
  1931. ~IL_STA_UCODE_INPROGRESS;
  1932. spin_unlock_irqrestore(&il->sta_lock,
  1933. flags_spin);
  1934. }
  1935. /*
  1936. * Rate scaling has already been initialized, send
  1937. * current LQ command
  1938. */
  1939. if (send_lq)
  1940. il_send_lq_cmd(il, &lq, CMD_SYNC, true);
  1941. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1942. il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
  1943. }
  1944. }
  1945. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1946. if (!found)
  1947. D_INFO("Restoring all known stations"
  1948. " .... no stations to be restored.\n");
  1949. else
  1950. D_INFO("Restoring all known stations" " .... complete.\n");
  1951. }
  1952. EXPORT_SYMBOL(il_restore_stations);
  1953. int
  1954. il_get_free_ucode_key_idx(struct il_priv *il)
  1955. {
  1956. int i;
  1957. for (i = 0; i < il->sta_key_max_num; i++)
  1958. if (!test_and_set_bit(i, &il->ucode_key_table))
  1959. return i;
  1960. return WEP_INVALID_OFFSET;
  1961. }
  1962. EXPORT_SYMBOL(il_get_free_ucode_key_idx);
  1963. void
  1964. il_dealloc_bcast_stations(struct il_priv *il)
  1965. {
  1966. unsigned long flags;
  1967. int i;
  1968. spin_lock_irqsave(&il->sta_lock, flags);
  1969. for (i = 0; i < il->hw_params.max_stations; i++) {
  1970. if (!(il->stations[i].used & IL_STA_BCAST))
  1971. continue;
  1972. il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
  1973. il->num_stations--;
  1974. BUG_ON(il->num_stations < 0);
  1975. kfree(il->stations[i].lq);
  1976. il->stations[i].lq = NULL;
  1977. }
  1978. spin_unlock_irqrestore(&il->sta_lock, flags);
  1979. }
  1980. EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
  1981. #ifdef CONFIG_IWLEGACY_DEBUG
  1982. static void
  1983. il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
  1984. {
  1985. int i;
  1986. D_RATE("lq station id 0x%x\n", lq->sta_id);
  1987. D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk,
  1988. lq->general_params.dual_stream_ant_msk);
  1989. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
  1990. D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags);
  1991. }
  1992. #else
  1993. static inline void
  1994. il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
  1995. {
  1996. }
  1997. #endif
  1998. /*
  1999. * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
  2000. *
  2001. * It sometimes happens when a HT rate has been in use and we
  2002. * loose connectivity with AP then mac80211 will first tell us that the
  2003. * current channel is not HT anymore before removing the station. In such a
  2004. * scenario the RXON flags will be updated to indicate we are not
  2005. * communicating HT anymore, but the LQ command may still contain HT rates.
  2006. * Test for this to prevent driver from sending LQ command between the time
  2007. * RXON flags are updated and when LQ command is updated.
  2008. */
  2009. static bool
  2010. il_is_lq_table_valid(struct il_priv *il, struct il_link_quality_cmd *lq)
  2011. {
  2012. int i;
  2013. if (il->ht.enabled)
  2014. return true;
  2015. D_INFO("Channel %u is not an HT channel\n", il->active.channel);
  2016. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  2017. if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) {
  2018. D_INFO("idx %d of LQ expects HT channel\n", i);
  2019. return false;
  2020. }
  2021. }
  2022. return true;
  2023. }
  2024. /*
  2025. * il_send_lq_cmd() - Send link quality command
  2026. * @init: This command is sent as part of station initialization right
  2027. * after station has been added.
  2028. *
  2029. * The link quality command is sent as the last step of station creation.
  2030. * This is the special case in which init is set and we call a callback in
  2031. * this case to clear the state indicating that station creation is in
  2032. * progress.
  2033. */
  2034. int
  2035. il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
  2036. u8 flags, bool init)
  2037. {
  2038. int ret = 0;
  2039. unsigned long flags_spin;
  2040. struct il_host_cmd cmd = {
  2041. .id = C_TX_LINK_QUALITY_CMD,
  2042. .len = sizeof(struct il_link_quality_cmd),
  2043. .flags = flags,
  2044. .data = lq,
  2045. };
  2046. if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
  2047. return -EINVAL;
  2048. spin_lock_irqsave(&il->sta_lock, flags_spin);
  2049. if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
  2050. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2051. return -EINVAL;
  2052. }
  2053. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2054. il_dump_lq_cmd(il, lq);
  2055. BUG_ON(init && (cmd.flags & CMD_ASYNC));
  2056. if (il_is_lq_table_valid(il, lq))
  2057. ret = il_send_cmd(il, &cmd);
  2058. else
  2059. ret = -EINVAL;
  2060. if (cmd.flags & CMD_ASYNC)
  2061. return ret;
  2062. if (init) {
  2063. D_INFO("init LQ command complete,"
  2064. " clearing sta addition status for sta %d\n",
  2065. lq->sta_id);
  2066. spin_lock_irqsave(&il->sta_lock, flags_spin);
  2067. il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
  2068. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2069. }
  2070. return ret;
  2071. }
  2072. EXPORT_SYMBOL(il_send_lq_cmd);
  2073. int
  2074. il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2075. struct ieee80211_sta *sta)
  2076. {
  2077. struct il_priv *il = hw->priv;
  2078. struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
  2079. int ret;
  2080. mutex_lock(&il->mutex);
  2081. D_MAC80211("enter station %pM\n", sta->addr);
  2082. ret = il_remove_station(il, sta_common->sta_id, sta->addr);
  2083. if (ret)
  2084. IL_ERR("Error removing station %pM\n", sta->addr);
  2085. D_MAC80211("leave ret %d\n", ret);
  2086. mutex_unlock(&il->mutex);
  2087. return ret;
  2088. }
  2089. EXPORT_SYMBOL(il_mac_sta_remove);
  2090. /************************** RX-FUNCTIONS ****************************/
  2091. /*
  2092. * Rx theory of operation
  2093. *
  2094. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  2095. * each of which point to Receive Buffers to be filled by the NIC. These get
  2096. * used not only for Rx frames, but for any command response or notification
  2097. * from the NIC. The driver and NIC manage the Rx buffers by means
  2098. * of idxes into the circular buffer.
  2099. *
  2100. * Rx Queue Indexes
  2101. * The host/firmware share two idx registers for managing the Rx buffers.
  2102. *
  2103. * The READ idx maps to the first position that the firmware may be writing
  2104. * to -- the driver can read up to (but not including) this position and get
  2105. * good data.
  2106. * The READ idx is managed by the firmware once the card is enabled.
  2107. *
  2108. * The WRITE idx maps to the last position the driver has read from -- the
  2109. * position preceding WRITE is the last slot the firmware can place a packet.
  2110. *
  2111. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2112. * WRITE = READ.
  2113. *
  2114. * During initialization, the host sets up the READ queue position to the first
  2115. * IDX position, and WRITE to the last (READ - 1 wrapped)
  2116. *
  2117. * When the firmware places a packet in a buffer, it will advance the READ idx
  2118. * and fire the RX interrupt. The driver can then query the READ idx and
  2119. * process as many packets as possible, moving the WRITE idx forward as it
  2120. * resets the Rx queue buffers with new memory.
  2121. *
  2122. * The management in the driver is as follows:
  2123. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2124. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2125. * to replenish the iwl->rxq->rx_free.
  2126. * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
  2127. * iwl->rxq is replenished and the READ IDX is updated (updating the
  2128. * 'processed' and 'read' driver idxes as well)
  2129. * + A received packet is processed and handed to the kernel network stack,
  2130. * detached from the iwl->rxq. The driver 'processed' idx is updated.
  2131. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2132. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2133. * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
  2134. * were enough free buffers and RX_STALLED is set it is cleared.
  2135. *
  2136. *
  2137. * Driver sequence:
  2138. *
  2139. * il_rx_queue_alloc() Allocates rx_free
  2140. * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2141. * il_rx_queue_restock
  2142. * il_rx_queue_restock() Moves available buffers from rx_free into Rx
  2143. * queue, updates firmware pointers, and updates
  2144. * the WRITE idx. If insufficient rx_free buffers
  2145. * are available, schedules il_rx_replenish
  2146. *
  2147. * -- enable interrupts --
  2148. * ISR - il_rx() Detach il_rx_bufs from pool up to the
  2149. * READ IDX, detaching the SKB from the pool.
  2150. * Moves the packet buffer from queue to rx_used.
  2151. * Calls il_rx_queue_restock to refill any empty
  2152. * slots.
  2153. * ...
  2154. *
  2155. */
  2156. /*
  2157. * il_rx_queue_space - Return number of free slots available in queue.
  2158. */
  2159. int
  2160. il_rx_queue_space(const struct il_rx_queue *q)
  2161. {
  2162. int s = q->read - q->write;
  2163. if (s <= 0)
  2164. s += RX_QUEUE_SIZE;
  2165. /* keep some buffer to not confuse full and empty queue */
  2166. s -= 2;
  2167. if (s < 0)
  2168. s = 0;
  2169. return s;
  2170. }
  2171. EXPORT_SYMBOL(il_rx_queue_space);
  2172. /*
  2173. * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2174. */
  2175. void
  2176. il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q)
  2177. {
  2178. unsigned long flags;
  2179. u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
  2180. u32 reg;
  2181. spin_lock_irqsave(&q->lock, flags);
  2182. if (q->need_update == 0)
  2183. goto exit_unlock;
  2184. /* If power-saving is in use, make sure device is awake */
  2185. if (test_bit(S_POWER_PMI, &il->status)) {
  2186. reg = _il_rd(il, CSR_UCODE_DRV_GP1);
  2187. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2188. D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n",
  2189. reg);
  2190. il_set_bit(il, CSR_GP_CNTRL,
  2191. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2192. goto exit_unlock;
  2193. }
  2194. q->write_actual = (q->write & ~0x7);
  2195. il_wr(il, rx_wrt_ptr_reg, q->write_actual);
  2196. /* Else device is assumed to be awake */
  2197. } else {
  2198. /* Device expects a multiple of 8 */
  2199. q->write_actual = (q->write & ~0x7);
  2200. il_wr(il, rx_wrt_ptr_reg, q->write_actual);
  2201. }
  2202. q->need_update = 0;
  2203. exit_unlock:
  2204. spin_unlock_irqrestore(&q->lock, flags);
  2205. }
  2206. EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
  2207. int
  2208. il_rx_queue_alloc(struct il_priv *il)
  2209. {
  2210. struct il_rx_queue *rxq = &il->rxq;
  2211. struct device *dev = &il->pci_dev->dev;
  2212. int i;
  2213. spin_lock_init(&rxq->lock);
  2214. INIT_LIST_HEAD(&rxq->rx_free);
  2215. INIT_LIST_HEAD(&rxq->rx_used);
  2216. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  2217. rxq->bd = dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
  2218. GFP_KERNEL);
  2219. if (!rxq->bd)
  2220. goto err_bd;
  2221. rxq->rb_stts = dma_alloc_coherent(dev, sizeof(struct il_rb_status),
  2222. &rxq->rb_stts_dma, GFP_KERNEL);
  2223. if (!rxq->rb_stts)
  2224. goto err_rb;
  2225. /* Fill the rx_used queue with _all_ of the Rx buffers */
  2226. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  2227. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  2228. /* Set us so that we have processed and used all buffers, but have
  2229. * not restocked the Rx queue with fresh buffers */
  2230. rxq->read = rxq->write = 0;
  2231. rxq->write_actual = 0;
  2232. rxq->free_count = 0;
  2233. rxq->need_update = 0;
  2234. return 0;
  2235. err_rb:
  2236. dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  2237. rxq->bd_dma);
  2238. err_bd:
  2239. return -ENOMEM;
  2240. }
  2241. EXPORT_SYMBOL(il_rx_queue_alloc);
  2242. void
  2243. il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb)
  2244. {
  2245. struct il_rx_pkt *pkt = rxb_addr(rxb);
  2246. struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2247. if (!report->state) {
  2248. D_11H("Spectrum Measure Notification: Start\n");
  2249. return;
  2250. }
  2251. memcpy(&il->measure_report, report, sizeof(*report));
  2252. il->measurement_status |= MEASUREMENT_READY;
  2253. }
  2254. EXPORT_SYMBOL(il_hdl_spectrum_measurement);
  2255. /*
  2256. * returns non-zero if packet should be dropped
  2257. */
  2258. int
  2259. il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
  2260. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2261. {
  2262. u16 fc = le16_to_cpu(hdr->frame_control);
  2263. /*
  2264. * All contexts have the same setting here due to it being
  2265. * a module parameter, so OK to check any context.
  2266. */
  2267. if (il->active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2268. return 0;
  2269. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2270. return 0;
  2271. D_RX("decrypt_res:0x%x\n", decrypt_res);
  2272. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2273. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2274. /* The uCode has got a bad phase 1 Key, pushes the packet.
  2275. * Decryption will be done in SW. */
  2276. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2277. RX_RES_STATUS_BAD_KEY_TTAK)
  2278. break;
  2279. fallthrough;
  2280. case RX_RES_STATUS_SEC_TYPE_WEP:
  2281. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2282. RX_RES_STATUS_BAD_ICV_MIC) {
  2283. /* bad ICV, the packet is destroyed since the
  2284. * decryption is inplace, drop it */
  2285. D_RX("Packet destroyed\n");
  2286. return -1;
  2287. }
  2288. fallthrough;
  2289. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2290. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2291. RX_RES_STATUS_DECRYPT_OK) {
  2292. D_RX("hw decrypt successfully!!!\n");
  2293. stats->flag |= RX_FLAG_DECRYPTED;
  2294. }
  2295. break;
  2296. default:
  2297. break;
  2298. }
  2299. return 0;
  2300. }
  2301. EXPORT_SYMBOL(il_set_decrypted_flag);
  2302. /*
  2303. * il_txq_update_write_ptr - Send new write idx to hardware
  2304. */
  2305. void
  2306. il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
  2307. {
  2308. u32 reg = 0;
  2309. int txq_id = txq->q.id;
  2310. if (txq->need_update == 0)
  2311. return;
  2312. /* if we're trying to save power */
  2313. if (test_bit(S_POWER_PMI, &il->status)) {
  2314. /* wake up nic if it's powered down ...
  2315. * uCode will wake up, and interrupt us again, so next
  2316. * time we'll skip this part. */
  2317. reg = _il_rd(il, CSR_UCODE_DRV_GP1);
  2318. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2319. D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n",
  2320. txq_id, reg);
  2321. il_set_bit(il, CSR_GP_CNTRL,
  2322. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2323. return;
  2324. }
  2325. il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
  2326. /*
  2327. * else not in power-save mode,
  2328. * uCode will never sleep when we're
  2329. * trying to tx (during RFKILL, we're not trying to tx).
  2330. */
  2331. } else
  2332. _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
  2333. txq->need_update = 0;
  2334. }
  2335. EXPORT_SYMBOL(il_txq_update_write_ptr);
  2336. /*
  2337. * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
  2338. */
  2339. void
  2340. il_tx_queue_unmap(struct il_priv *il, int txq_id)
  2341. {
  2342. struct il_tx_queue *txq = &il->txq[txq_id];
  2343. struct il_queue *q = &txq->q;
  2344. if (q->n_bd == 0)
  2345. return;
  2346. while (q->write_ptr != q->read_ptr) {
  2347. il->ops->txq_free_tfd(il, txq);
  2348. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
  2349. }
  2350. }
  2351. EXPORT_SYMBOL(il_tx_queue_unmap);
  2352. /*
  2353. * il_tx_queue_free - Deallocate DMA queue.
  2354. * @txq: Transmit queue to deallocate.
  2355. *
  2356. * Empty queue by removing and destroying all BD's.
  2357. * Free all buffers.
  2358. * 0-fill, but do not free "txq" descriptor structure.
  2359. */
  2360. void
  2361. il_tx_queue_free(struct il_priv *il, int txq_id)
  2362. {
  2363. struct il_tx_queue *txq = &il->txq[txq_id];
  2364. struct device *dev = &il->pci_dev->dev;
  2365. int i;
  2366. il_tx_queue_unmap(il, txq_id);
  2367. /* De-alloc array of command/tx buffers */
  2368. if (txq->cmd) {
  2369. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  2370. kfree(txq->cmd[i]);
  2371. }
  2372. /* De-alloc circular buffer of TFDs */
  2373. if (txq->q.n_bd)
  2374. dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
  2375. txq->tfds, txq->q.dma_addr);
  2376. /* De-alloc array of per-TFD driver data */
  2377. kfree(txq->skbs);
  2378. txq->skbs = NULL;
  2379. /* deallocate arrays */
  2380. kfree(txq->cmd);
  2381. kfree(txq->meta);
  2382. txq->cmd = NULL;
  2383. txq->meta = NULL;
  2384. /* 0-fill queue descriptor structure */
  2385. memset(txq, 0, sizeof(*txq));
  2386. }
  2387. EXPORT_SYMBOL(il_tx_queue_free);
  2388. /*
  2389. * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
  2390. */
  2391. void
  2392. il_cmd_queue_unmap(struct il_priv *il)
  2393. {
  2394. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2395. struct il_queue *q = &txq->q;
  2396. int i;
  2397. if (q->n_bd == 0)
  2398. return;
  2399. while (q->read_ptr != q->write_ptr) {
  2400. i = il_get_cmd_idx(q, q->read_ptr, 0);
  2401. if (txq->meta[i].flags & CMD_MAPPED) {
  2402. dma_unmap_single(&il->pci_dev->dev,
  2403. dma_unmap_addr(&txq->meta[i], mapping),
  2404. dma_unmap_len(&txq->meta[i], len),
  2405. DMA_BIDIRECTIONAL);
  2406. txq->meta[i].flags = 0;
  2407. }
  2408. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
  2409. }
  2410. i = q->n_win;
  2411. if (txq->meta[i].flags & CMD_MAPPED) {
  2412. dma_unmap_single(&il->pci_dev->dev,
  2413. dma_unmap_addr(&txq->meta[i], mapping),
  2414. dma_unmap_len(&txq->meta[i], len),
  2415. DMA_BIDIRECTIONAL);
  2416. txq->meta[i].flags = 0;
  2417. }
  2418. }
  2419. EXPORT_SYMBOL(il_cmd_queue_unmap);
  2420. /*
  2421. * il_cmd_queue_free - Deallocate DMA queue.
  2422. *
  2423. * Empty queue by removing and destroying all BD's.
  2424. * Free all buffers.
  2425. * 0-fill, but do not free "txq" descriptor structure.
  2426. */
  2427. void
  2428. il_cmd_queue_free(struct il_priv *il)
  2429. {
  2430. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2431. struct device *dev = &il->pci_dev->dev;
  2432. int i;
  2433. il_cmd_queue_unmap(il);
  2434. /* De-alloc array of command/tx buffers */
  2435. if (txq->cmd) {
  2436. for (i = 0; i <= TFD_CMD_SLOTS; i++)
  2437. kfree(txq->cmd[i]);
  2438. }
  2439. /* De-alloc circular buffer of TFDs */
  2440. if (txq->q.n_bd)
  2441. dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
  2442. txq->tfds, txq->q.dma_addr);
  2443. /* deallocate arrays */
  2444. kfree(txq->cmd);
  2445. kfree(txq->meta);
  2446. txq->cmd = NULL;
  2447. txq->meta = NULL;
  2448. /* 0-fill queue descriptor structure */
  2449. memset(txq, 0, sizeof(*txq));
  2450. }
  2451. EXPORT_SYMBOL(il_cmd_queue_free);
  2452. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  2453. * DMA services
  2454. *
  2455. * Theory of operation
  2456. *
  2457. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  2458. * of buffer descriptors, each of which points to one or more data buffers for
  2459. * the device to read from or fill. Driver and device exchange status of each
  2460. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  2461. * entries in each circular buffer, to protect against confusing empty and full
  2462. * queue states.
  2463. *
  2464. * The device reads or writes the data in the queues via the device's several
  2465. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  2466. *
  2467. * For Tx queue, there are low mark and high mark limits. If, after queuing
  2468. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  2469. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  2470. * Tx queue resumed.
  2471. *
  2472. * See more detailed info in 4965.h.
  2473. ***************************************************/
  2474. int
  2475. il_queue_space(const struct il_queue *q)
  2476. {
  2477. int s = q->read_ptr - q->write_ptr;
  2478. if (q->read_ptr > q->write_ptr)
  2479. s -= q->n_bd;
  2480. if (s <= 0)
  2481. s += q->n_win;
  2482. /* keep some reserve to not confuse empty and full situations */
  2483. s -= 2;
  2484. if (s < 0)
  2485. s = 0;
  2486. return s;
  2487. }
  2488. EXPORT_SYMBOL(il_queue_space);
  2489. /*
  2490. * il_queue_init - Initialize queue's high/low-water and read/write idxes
  2491. */
  2492. static int
  2493. il_queue_init(struct il_priv *il, struct il_queue *q, int slots, u32 id)
  2494. {
  2495. /*
  2496. * TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  2497. * il_queue_inc_wrap and il_queue_dec_wrap are broken.
  2498. */
  2499. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  2500. /* FIXME: remove q->n_bd */
  2501. q->n_bd = TFD_QUEUE_SIZE_MAX;
  2502. q->n_win = slots;
  2503. q->id = id;
  2504. /* slots_must be power-of-two size, otherwise
  2505. * il_get_cmd_idx is broken. */
  2506. BUG_ON(!is_power_of_2(slots));
  2507. q->low_mark = q->n_win / 4;
  2508. if (q->low_mark < 4)
  2509. q->low_mark = 4;
  2510. q->high_mark = q->n_win / 8;
  2511. if (q->high_mark < 2)
  2512. q->high_mark = 2;
  2513. q->write_ptr = q->read_ptr = 0;
  2514. return 0;
  2515. }
  2516. /*
  2517. * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  2518. */
  2519. static int
  2520. il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id)
  2521. {
  2522. struct device *dev = &il->pci_dev->dev;
  2523. size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
  2524. /* Driver ilate data, only for Tx (not command) queues,
  2525. * not shared with device. */
  2526. if (id != il->cmd_queue) {
  2527. txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX,
  2528. sizeof(struct sk_buff *),
  2529. GFP_KERNEL);
  2530. if (!txq->skbs) {
  2531. IL_ERR("Fail to alloc skbs\n");
  2532. goto error;
  2533. }
  2534. } else
  2535. txq->skbs = NULL;
  2536. /* Circular buffer of transmit frame descriptors (TFDs),
  2537. * shared with device */
  2538. txq->tfds =
  2539. dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL);
  2540. if (!txq->tfds)
  2541. goto error;
  2542. txq->q.id = id;
  2543. return 0;
  2544. error:
  2545. kfree(txq->skbs);
  2546. txq->skbs = NULL;
  2547. return -ENOMEM;
  2548. }
  2549. /*
  2550. * il_tx_queue_init - Allocate and initialize one tx/cmd queue
  2551. */
  2552. int
  2553. il_tx_queue_init(struct il_priv *il, u32 txq_id)
  2554. {
  2555. int i, len, ret;
  2556. int slots, actual_slots;
  2557. struct il_tx_queue *txq = &il->txq[txq_id];
  2558. /*
  2559. * Alloc buffer array for commands (Tx or other types of commands).
  2560. * For the command queue (#4/#9), allocate command space + one big
  2561. * command for scan, since scan command is very huge; the system will
  2562. * not have two scans at the same time, so only one is needed.
  2563. * For normal Tx queues (all other queues), no super-size command
  2564. * space is needed.
  2565. */
  2566. if (txq_id == il->cmd_queue) {
  2567. slots = TFD_CMD_SLOTS;
  2568. actual_slots = slots + 1;
  2569. } else {
  2570. slots = TFD_TX_CMD_SLOTS;
  2571. actual_slots = slots;
  2572. }
  2573. txq->meta =
  2574. kcalloc(actual_slots, sizeof(struct il_cmd_meta), GFP_KERNEL);
  2575. txq->cmd =
  2576. kcalloc(actual_slots, sizeof(struct il_device_cmd *), GFP_KERNEL);
  2577. if (!txq->meta || !txq->cmd)
  2578. goto out_free_arrays;
  2579. len = sizeof(struct il_device_cmd);
  2580. for (i = 0; i < actual_slots; i++) {
  2581. /* only happens for cmd queue */
  2582. if (i == slots)
  2583. len = IL_MAX_CMD_SIZE;
  2584. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  2585. if (!txq->cmd[i])
  2586. goto err;
  2587. }
  2588. /* Alloc driver data array and TFD circular buffer */
  2589. ret = il_tx_queue_alloc(il, txq, txq_id);
  2590. if (ret)
  2591. goto err;
  2592. txq->need_update = 0;
  2593. /*
  2594. * For the default queues 0-3, set up the swq_id
  2595. * already -- all others need to get one later
  2596. * (if they need one at all).
  2597. */
  2598. if (txq_id < 4)
  2599. il_set_swq_id(txq, txq_id, txq_id);
  2600. /* Initialize queue's high/low-water marks, and head/tail idxes */
  2601. il_queue_init(il, &txq->q, slots, txq_id);
  2602. /* Tell device where to find queue */
  2603. il->ops->txq_init(il, txq);
  2604. return 0;
  2605. err:
  2606. for (i = 0; i < actual_slots; i++)
  2607. kfree(txq->cmd[i]);
  2608. out_free_arrays:
  2609. kfree(txq->meta);
  2610. txq->meta = NULL;
  2611. kfree(txq->cmd);
  2612. txq->cmd = NULL;
  2613. return -ENOMEM;
  2614. }
  2615. EXPORT_SYMBOL(il_tx_queue_init);
  2616. void
  2617. il_tx_queue_reset(struct il_priv *il, u32 txq_id)
  2618. {
  2619. int slots, actual_slots;
  2620. struct il_tx_queue *txq = &il->txq[txq_id];
  2621. if (txq_id == il->cmd_queue) {
  2622. slots = TFD_CMD_SLOTS;
  2623. actual_slots = TFD_CMD_SLOTS + 1;
  2624. } else {
  2625. slots = TFD_TX_CMD_SLOTS;
  2626. actual_slots = TFD_TX_CMD_SLOTS;
  2627. }
  2628. memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
  2629. txq->need_update = 0;
  2630. /* Initialize queue's high/low-water marks, and head/tail idxes */
  2631. il_queue_init(il, &txq->q, slots, txq_id);
  2632. /* Tell device where to find queue */
  2633. il->ops->txq_init(il, txq);
  2634. }
  2635. EXPORT_SYMBOL(il_tx_queue_reset);
  2636. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  2637. /*
  2638. * il_enqueue_hcmd - enqueue a uCode command
  2639. * @il: device ilate data point
  2640. * @cmd: a point to the ucode command structure
  2641. *
  2642. * The function returns < 0 values to indicate the operation is
  2643. * failed. On success, it turns the idx (> 0) of command in the
  2644. * command queue.
  2645. */
  2646. int
  2647. il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
  2648. {
  2649. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2650. struct il_queue *q = &txq->q;
  2651. struct il_device_cmd *out_cmd;
  2652. struct il_cmd_meta *out_meta;
  2653. dma_addr_t phys_addr;
  2654. unsigned long flags;
  2655. u8 *out_payload;
  2656. u32 idx;
  2657. u16 fix_size;
  2658. cmd->len = il->ops->get_hcmd_size(cmd->id, cmd->len);
  2659. fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr));
  2660. /* If any of the command structures end up being larger than
  2661. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  2662. * we will need to increase the size of the TFD entries
  2663. * Also, check to see if command buffer should not exceed the size
  2664. * of device_cmd and max_cmd_size. */
  2665. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  2666. !(cmd->flags & CMD_SIZE_HUGE));
  2667. BUG_ON(fix_size > IL_MAX_CMD_SIZE);
  2668. if (il_is_rfkill(il) || il_is_ctkill(il)) {
  2669. IL_WARN("Not sending command - %s KILL\n",
  2670. il_is_rfkill(il) ? "RF" : "CT");
  2671. return -EIO;
  2672. }
  2673. spin_lock_irqsave(&il->hcmd_lock, flags);
  2674. if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
  2675. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2676. IL_ERR("Restarting adapter due to command queue full\n");
  2677. queue_work(il->workqueue, &il->restart);
  2678. return -ENOSPC;
  2679. }
  2680. idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
  2681. out_cmd = txq->cmd[idx];
  2682. out_meta = &txq->meta[idx];
  2683. /* The payload is in the same place in regular and huge
  2684. * command buffers, but we need to let the compiler know when
  2685. * we're using a larger payload buffer to avoid "field-
  2686. * spanning write" warnings at run-time for huge commands.
  2687. */
  2688. if (cmd->flags & CMD_SIZE_HUGE)
  2689. out_payload = ((struct il_device_cmd_huge *)out_cmd)->cmd.payload;
  2690. else
  2691. out_payload = out_cmd->cmd.payload;
  2692. if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
  2693. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2694. return -ENOSPC;
  2695. }
  2696. memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
  2697. out_meta->flags = cmd->flags | CMD_MAPPED;
  2698. if (cmd->flags & CMD_WANT_SKB)
  2699. out_meta->source = cmd;
  2700. if (cmd->flags & CMD_ASYNC)
  2701. out_meta->callback = cmd->callback;
  2702. out_cmd->hdr.cmd = cmd->id;
  2703. memcpy(out_payload, cmd->data, cmd->len);
  2704. /* At this point, the out_cmd now has all of the incoming cmd
  2705. * information */
  2706. out_cmd->hdr.flags = 0;
  2707. out_cmd->hdr.sequence =
  2708. cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr));
  2709. if (cmd->flags & CMD_SIZE_HUGE)
  2710. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  2711. #ifdef CONFIG_IWLEGACY_DEBUG
  2712. switch (out_cmd->hdr.cmd) {
  2713. case C_TX_LINK_QUALITY_CMD:
  2714. case C_SENSITIVITY:
  2715. D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
  2716. "%d bytes at %d[%d]:%d\n",
  2717. il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
  2718. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  2719. q->write_ptr, idx, il->cmd_queue);
  2720. break;
  2721. default:
  2722. D_HC("Sending command %s (#%x), seq: 0x%04X, "
  2723. "%d bytes at %d[%d]:%d\n",
  2724. il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
  2725. le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr,
  2726. idx, il->cmd_queue);
  2727. }
  2728. #endif
  2729. phys_addr = dma_map_single(&il->pci_dev->dev, &out_cmd->hdr, fix_size,
  2730. DMA_BIDIRECTIONAL);
  2731. if (unlikely(dma_mapping_error(&il->pci_dev->dev, phys_addr))) {
  2732. idx = -ENOMEM;
  2733. goto out;
  2734. }
  2735. dma_unmap_addr_set(out_meta, mapping, phys_addr);
  2736. dma_unmap_len_set(out_meta, len, fix_size);
  2737. txq->need_update = 1;
  2738. if (il->ops->txq_update_byte_cnt_tbl)
  2739. /* Set up entry in queue's byte count circular buffer */
  2740. il->ops->txq_update_byte_cnt_tbl(il, txq, 0);
  2741. il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size, 1,
  2742. U32_PAD(cmd->len));
  2743. /* Increment and update queue's write idx */
  2744. q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
  2745. il_txq_update_write_ptr(il, txq);
  2746. out:
  2747. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2748. return idx;
  2749. }
  2750. /*
  2751. * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
  2752. *
  2753. * When FW advances 'R' idx, all entries between old and new 'R' idx
  2754. * need to be reclaimed. As result, some free space forms. If there is
  2755. * enough free space (> low mark), wake the stack that feeds us.
  2756. */
  2757. static void
  2758. il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx)
  2759. {
  2760. struct il_tx_queue *txq = &il->txq[txq_id];
  2761. struct il_queue *q = &txq->q;
  2762. int nfreed = 0;
  2763. if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
  2764. IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
  2765. "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
  2766. q->write_ptr, q->read_ptr);
  2767. return;
  2768. }
  2769. for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
  2770. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2771. if (nfreed++ > 0) {
  2772. IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
  2773. q->write_ptr, q->read_ptr);
  2774. queue_work(il->workqueue, &il->restart);
  2775. }
  2776. }
  2777. }
  2778. /*
  2779. * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2780. * @rxb: Rx buffer to reclaim
  2781. *
  2782. * If an Rx buffer has an async callback associated with it the callback
  2783. * will be executed. The attached skb (if present) will only be freed
  2784. * if the callback returns 1
  2785. */
  2786. void
  2787. il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
  2788. {
  2789. struct il_rx_pkt *pkt = rxb_addr(rxb);
  2790. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2791. int txq_id = SEQ_TO_QUEUE(sequence);
  2792. int idx = SEQ_TO_IDX(sequence);
  2793. int cmd_idx;
  2794. bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2795. struct il_device_cmd *cmd;
  2796. struct il_cmd_meta *meta;
  2797. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2798. unsigned long flags;
  2799. /* If a Tx command is being handled and it isn't in the actual
  2800. * command queue then there a command routing bug has been introduced
  2801. * in the queue management code. */
  2802. if (WARN
  2803. (txq_id != il->cmd_queue,
  2804. "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
  2805. txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr,
  2806. il->txq[il->cmd_queue].q.write_ptr)) {
  2807. il_print_hex_error(il, pkt, 32);
  2808. return;
  2809. }
  2810. cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
  2811. cmd = txq->cmd[cmd_idx];
  2812. meta = &txq->meta[cmd_idx];
  2813. txq->time_stamp = jiffies;
  2814. dma_unmap_single(&il->pci_dev->dev, dma_unmap_addr(meta, mapping),
  2815. dma_unmap_len(meta, len), DMA_BIDIRECTIONAL);
  2816. /* Input error checking is done when commands are added to queue. */
  2817. if (meta->flags & CMD_WANT_SKB) {
  2818. meta->source->reply_page = (unsigned long)rxb_addr(rxb);
  2819. rxb->page = NULL;
  2820. } else if (meta->callback)
  2821. meta->callback(il, cmd, pkt);
  2822. spin_lock_irqsave(&il->hcmd_lock, flags);
  2823. il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
  2824. if (!(meta->flags & CMD_ASYNC)) {
  2825. clear_bit(S_HCMD_ACTIVE, &il->status);
  2826. D_INFO("Clearing HCMD_ACTIVE for command %s\n",
  2827. il_get_cmd_string(cmd->hdr.cmd));
  2828. wake_up(&il->wait_command_queue);
  2829. }
  2830. /* Mark as unmapped */
  2831. meta->flags = 0;
  2832. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2833. }
  2834. EXPORT_SYMBOL(il_tx_cmd_complete);
  2835. MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
  2836. MODULE_VERSION(IWLWIFI_VERSION);
  2837. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  2838. MODULE_LICENSE("GPL");
  2839. /*
  2840. * set bt_coex_active to true, uCode will do kill/defer
  2841. * every time the priority line is asserted (BT is sending signals on the
  2842. * priority line in the PCIx).
  2843. * set bt_coex_active to false, uCode will ignore the BT activity and
  2844. * perform the normal operation
  2845. *
  2846. * User might experience transmit issue on some platform due to WiFi/BT
  2847. * co-exist problem. The possible behaviors are:
  2848. * Able to scan and finding all the available AP
  2849. * Not able to associate with any AP
  2850. * On those platforms, WiFi communication can be restored by set
  2851. * "bt_coex_active" module parameter to "false"
  2852. *
  2853. * default: bt_coex_active = true (BT_COEX_ENABLE)
  2854. */
  2855. static bool bt_coex_active = true;
  2856. module_param(bt_coex_active, bool, 0444);
  2857. MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
  2858. u32 il_debug_level;
  2859. EXPORT_SYMBOL(il_debug_level);
  2860. const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  2861. EXPORT_SYMBOL(il_bcast_addr);
  2862. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  2863. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  2864. static void
  2865. il_init_ht_hw_capab(const struct il_priv *il,
  2866. struct ieee80211_sta_ht_cap *ht_info,
  2867. enum nl80211_band band)
  2868. {
  2869. u16 max_bit_rate = 0;
  2870. u8 rx_chains_num = il->hw_params.rx_chains_num;
  2871. u8 tx_chains_num = il->hw_params.tx_chains_num;
  2872. ht_info->cap = 0;
  2873. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  2874. ht_info->ht_supported = true;
  2875. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  2876. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  2877. if (il->hw_params.ht40_channel & BIT(band)) {
  2878. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  2879. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  2880. ht_info->mcs.rx_mask[4] = 0x01;
  2881. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  2882. }
  2883. if (il->cfg->mod_params->amsdu_size_8K)
  2884. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  2885. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  2886. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  2887. ht_info->mcs.rx_mask[0] = 0xFF;
  2888. if (rx_chains_num >= 2)
  2889. ht_info->mcs.rx_mask[1] = 0xFF;
  2890. if (rx_chains_num >= 3)
  2891. ht_info->mcs.rx_mask[2] = 0xFF;
  2892. /* Highest supported Rx data rate */
  2893. max_bit_rate *= rx_chains_num;
  2894. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  2895. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  2896. /* Tx MCS capabilities */
  2897. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  2898. if (tx_chains_num != rx_chains_num) {
  2899. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  2900. ht_info->mcs.tx_params |=
  2901. ((tx_chains_num -
  2902. 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  2903. }
  2904. }
  2905. /*
  2906. * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
  2907. */
  2908. int
  2909. il_init_geos(struct il_priv *il)
  2910. {
  2911. struct il_channel_info *ch;
  2912. struct ieee80211_supported_band *sband;
  2913. struct ieee80211_channel *channels;
  2914. struct ieee80211_channel *geo_ch;
  2915. struct ieee80211_rate *rates;
  2916. int i = 0;
  2917. s8 max_tx_power = 0;
  2918. if (il->bands[NL80211_BAND_2GHZ].n_bitrates ||
  2919. il->bands[NL80211_BAND_5GHZ].n_bitrates) {
  2920. D_INFO("Geography modes already initialized.\n");
  2921. set_bit(S_GEO_CONFIGURED, &il->status);
  2922. return 0;
  2923. }
  2924. channels =
  2925. kcalloc(il->channel_count, sizeof(struct ieee80211_channel),
  2926. GFP_KERNEL);
  2927. if (!channels)
  2928. return -ENOMEM;
  2929. rates = kcalloc(RATE_COUNT_LEGACY, sizeof(*rates), GFP_KERNEL);
  2930. if (!rates) {
  2931. kfree(channels);
  2932. return -ENOMEM;
  2933. }
  2934. /* 5.2GHz channels start after the 2.4GHz channels */
  2935. sband = &il->bands[NL80211_BAND_5GHZ];
  2936. sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
  2937. /* just OFDM */
  2938. sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
  2939. sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
  2940. if (il->cfg->sku & IL_SKU_N)
  2941. il_init_ht_hw_capab(il, &sband->ht_cap, NL80211_BAND_5GHZ);
  2942. sband = &il->bands[NL80211_BAND_2GHZ];
  2943. sband->channels = channels;
  2944. /* OFDM & CCK */
  2945. sband->bitrates = rates;
  2946. sband->n_bitrates = RATE_COUNT_LEGACY;
  2947. if (il->cfg->sku & IL_SKU_N)
  2948. il_init_ht_hw_capab(il, &sband->ht_cap, NL80211_BAND_2GHZ);
  2949. il->ieee_channels = channels;
  2950. il->ieee_rates = rates;
  2951. for (i = 0; i < il->channel_count; i++) {
  2952. ch = &il->channel_info[i];
  2953. if (!il_is_channel_valid(ch))
  2954. continue;
  2955. sband = &il->bands[ch->band];
  2956. geo_ch = &sband->channels[sband->n_channels++];
  2957. geo_ch->center_freq =
  2958. ieee80211_channel_to_frequency(ch->channel, ch->band);
  2959. geo_ch->max_power = ch->max_power_avg;
  2960. geo_ch->max_antenna_gain = 0xff;
  2961. geo_ch->hw_value = ch->channel;
  2962. if (il_is_channel_valid(ch)) {
  2963. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  2964. geo_ch->flags |= IEEE80211_CHAN_NO_IR;
  2965. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  2966. geo_ch->flags |= IEEE80211_CHAN_NO_IR;
  2967. if (ch->flags & EEPROM_CHANNEL_RADAR)
  2968. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  2969. geo_ch->flags |= ch->ht40_extension_channel;
  2970. if (ch->max_power_avg > max_tx_power)
  2971. max_tx_power = ch->max_power_avg;
  2972. } else {
  2973. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  2974. }
  2975. D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel,
  2976. geo_ch->center_freq,
  2977. il_is_channel_a_band(ch) ? "5.2" : "2.4",
  2978. geo_ch->
  2979. flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid",
  2980. geo_ch->flags);
  2981. }
  2982. il->tx_power_device_lmt = max_tx_power;
  2983. il->tx_power_user_lmt = max_tx_power;
  2984. il->tx_power_next = max_tx_power;
  2985. if (il->bands[NL80211_BAND_5GHZ].n_channels == 0 &&
  2986. (il->cfg->sku & IL_SKU_A)) {
  2987. IL_INFO("Incorrectly detected BG card as ABG. "
  2988. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  2989. il->pci_dev->device, il->pci_dev->subsystem_device);
  2990. il->cfg->sku &= ~IL_SKU_A;
  2991. }
  2992. IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  2993. il->bands[NL80211_BAND_2GHZ].n_channels,
  2994. il->bands[NL80211_BAND_5GHZ].n_channels);
  2995. set_bit(S_GEO_CONFIGURED, &il->status);
  2996. return 0;
  2997. }
  2998. EXPORT_SYMBOL(il_init_geos);
  2999. /*
  3000. * il_free_geos - undo allocations in il_init_geos
  3001. */
  3002. void
  3003. il_free_geos(struct il_priv *il)
  3004. {
  3005. kfree(il->ieee_channels);
  3006. kfree(il->ieee_rates);
  3007. clear_bit(S_GEO_CONFIGURED, &il->status);
  3008. }
  3009. EXPORT_SYMBOL(il_free_geos);
  3010. static bool
  3011. il_is_channel_extension(struct il_priv *il, enum nl80211_band band,
  3012. u16 channel, u8 extension_chan_offset)
  3013. {
  3014. const struct il_channel_info *ch_info;
  3015. ch_info = il_get_channel_info(il, band, channel);
  3016. if (!il_is_channel_valid(ch_info))
  3017. return false;
  3018. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  3019. return !(ch_info->
  3020. ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS);
  3021. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  3022. return !(ch_info->
  3023. ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS);
  3024. return false;
  3025. }
  3026. bool
  3027. il_is_ht40_tx_allowed(struct il_priv *il, struct ieee80211_sta_ht_cap *ht_cap)
  3028. {
  3029. if (!il->ht.enabled || !il->ht.is_40mhz)
  3030. return false;
  3031. /*
  3032. * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  3033. * the bit will not set if it is pure 40MHz case
  3034. */
  3035. if (ht_cap && !ht_cap->ht_supported)
  3036. return false;
  3037. #ifdef CONFIG_IWLEGACY_DEBUGFS
  3038. if (il->disable_ht40)
  3039. return false;
  3040. #endif
  3041. return il_is_channel_extension(il, il->band,
  3042. le16_to_cpu(il->staging.channel),
  3043. il->ht.extension_chan_offset);
  3044. }
  3045. EXPORT_SYMBOL(il_is_ht40_tx_allowed);
  3046. static u16 noinline
  3047. il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  3048. {
  3049. u16 new_val;
  3050. u16 beacon_factor;
  3051. /*
  3052. * If mac80211 hasn't given us a beacon interval, program
  3053. * the default into the device.
  3054. */
  3055. if (!beacon_val)
  3056. return DEFAULT_BEACON_INTERVAL;
  3057. /*
  3058. * If the beacon interval we obtained from the peer
  3059. * is too large, we'll have to wake up more often
  3060. * (and in IBSS case, we'll beacon too much)
  3061. *
  3062. * For example, if max_beacon_val is 4096, and the
  3063. * requested beacon interval is 7000, we'll have to
  3064. * use 3500 to be able to wake up on the beacons.
  3065. *
  3066. * This could badly influence beacon detection stats.
  3067. */
  3068. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  3069. new_val = beacon_val / beacon_factor;
  3070. if (!new_val)
  3071. new_val = max_beacon_val;
  3072. return new_val;
  3073. }
  3074. int
  3075. il_send_rxon_timing(struct il_priv *il)
  3076. {
  3077. u64 tsf;
  3078. s32 interval_tm, rem;
  3079. struct ieee80211_conf *conf = NULL;
  3080. u16 beacon_int;
  3081. struct ieee80211_vif *vif = il->vif;
  3082. conf = &il->hw->conf;
  3083. lockdep_assert_held(&il->mutex);
  3084. memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
  3085. il->timing.timestamp = cpu_to_le64(il->timestamp);
  3086. il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
  3087. beacon_int = vif ? vif->bss_conf.beacon_int : 0;
  3088. /*
  3089. * TODO: For IBSS we need to get atim_win from mac80211,
  3090. * for now just always use 0
  3091. */
  3092. il->timing.atim_win = 0;
  3093. beacon_int =
  3094. il_adjust_beacon_interval(beacon_int,
  3095. il->hw_params.max_beacon_itrvl *
  3096. TIME_UNIT);
  3097. il->timing.beacon_interval = cpu_to_le16(beacon_int);
  3098. tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
  3099. interval_tm = beacon_int * TIME_UNIT;
  3100. rem = do_div(tsf, interval_tm);
  3101. il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  3102. il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
  3103. D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n",
  3104. le16_to_cpu(il->timing.beacon_interval),
  3105. le32_to_cpu(il->timing.beacon_init_val),
  3106. le16_to_cpu(il->timing.atim_win));
  3107. return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing),
  3108. &il->timing);
  3109. }
  3110. EXPORT_SYMBOL(il_send_rxon_timing);
  3111. void
  3112. il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt)
  3113. {
  3114. struct il_rxon_cmd *rxon = &il->staging;
  3115. if (hw_decrypt)
  3116. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  3117. else
  3118. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  3119. }
  3120. EXPORT_SYMBOL(il_set_rxon_hwcrypto);
  3121. /* validate RXON structure is valid */
  3122. int
  3123. il_check_rxon_cmd(struct il_priv *il)
  3124. {
  3125. struct il_rxon_cmd *rxon = &il->staging;
  3126. bool error = false;
  3127. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  3128. if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
  3129. IL_WARN("check 2.4G: wrong narrow\n");
  3130. error = true;
  3131. }
  3132. if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
  3133. IL_WARN("check 2.4G: wrong radar\n");
  3134. error = true;
  3135. }
  3136. } else {
  3137. if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
  3138. IL_WARN("check 5.2G: not short slot!\n");
  3139. error = true;
  3140. }
  3141. if (rxon->flags & RXON_FLG_CCK_MSK) {
  3142. IL_WARN("check 5.2G: CCK!\n");
  3143. error = true;
  3144. }
  3145. }
  3146. if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
  3147. IL_WARN("mac/bssid mcast!\n");
  3148. error = true;
  3149. }
  3150. /* make sure basic rates 6Mbps and 1Mbps are supported */
  3151. if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
  3152. (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
  3153. IL_WARN("neither 1 nor 6 are basic\n");
  3154. error = true;
  3155. }
  3156. if (le16_to_cpu(rxon->assoc_id) > 2007) {
  3157. IL_WARN("aid > 2007\n");
  3158. error = true;
  3159. }
  3160. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) ==
  3161. (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
  3162. IL_WARN("CCK and short slot\n");
  3163. error = true;
  3164. }
  3165. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) ==
  3166. (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
  3167. IL_WARN("CCK and auto detect");
  3168. error = true;
  3169. }
  3170. if ((rxon->
  3171. flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) ==
  3172. RXON_FLG_TGG_PROTECT_MSK) {
  3173. IL_WARN("TGg but no auto-detect\n");
  3174. error = true;
  3175. }
  3176. if (error)
  3177. IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel));
  3178. if (error) {
  3179. IL_ERR("Invalid RXON\n");
  3180. return -EINVAL;
  3181. }
  3182. return 0;
  3183. }
  3184. EXPORT_SYMBOL(il_check_rxon_cmd);
  3185. /*
  3186. * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  3187. * @il: staging_rxon is compared to active_rxon
  3188. *
  3189. * If the RXON structure is changing enough to require a new tune,
  3190. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  3191. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  3192. */
  3193. int
  3194. il_full_rxon_required(struct il_priv *il)
  3195. {
  3196. const struct il_rxon_cmd *staging = &il->staging;
  3197. const struct il_rxon_cmd *active = &il->active;
  3198. #define CHK(cond) \
  3199. if ((cond)) { \
  3200. D_INFO("need full RXON - " #cond "\n"); \
  3201. return 1; \
  3202. }
  3203. #define CHK_NEQ(c1, c2) \
  3204. if ((c1) != (c2)) { \
  3205. D_INFO("need full RXON - " \
  3206. #c1 " != " #c2 " - %d != %d\n", \
  3207. (c1), (c2)); \
  3208. return 1; \
  3209. }
  3210. /* These items are only settable from the full RXON command */
  3211. CHK(!il_is_associated(il));
  3212. CHK(!ether_addr_equal_64bits(staging->bssid_addr, active->bssid_addr));
  3213. CHK(!ether_addr_equal_64bits(staging->node_addr, active->node_addr));
  3214. CHK(!ether_addr_equal_64bits(staging->wlap_bssid_addr,
  3215. active->wlap_bssid_addr));
  3216. CHK_NEQ(staging->dev_type, active->dev_type);
  3217. CHK_NEQ(staging->channel, active->channel);
  3218. CHK_NEQ(staging->air_propagation, active->air_propagation);
  3219. CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
  3220. active->ofdm_ht_single_stream_basic_rates);
  3221. CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
  3222. active->ofdm_ht_dual_stream_basic_rates);
  3223. CHK_NEQ(staging->assoc_id, active->assoc_id);
  3224. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  3225. * be updated with the RXON_ASSOC command -- however only some
  3226. * flag transitions are allowed using RXON_ASSOC */
  3227. /* Check if we are not switching bands */
  3228. CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
  3229. active->flags & RXON_FLG_BAND_24G_MSK);
  3230. /* Check if we are switching association toggle */
  3231. CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
  3232. active->filter_flags & RXON_FILTER_ASSOC_MSK);
  3233. #undef CHK
  3234. #undef CHK_NEQ
  3235. return 0;
  3236. }
  3237. EXPORT_SYMBOL(il_full_rxon_required);
  3238. u8
  3239. il_get_lowest_plcp(struct il_priv *il)
  3240. {
  3241. /*
  3242. * Assign the lowest rate -- should really get this from
  3243. * the beacon skb from mac80211.
  3244. */
  3245. if (il->staging.flags & RXON_FLG_BAND_24G_MSK)
  3246. return RATE_1M_PLCP;
  3247. else
  3248. return RATE_6M_PLCP;
  3249. }
  3250. EXPORT_SYMBOL(il_get_lowest_plcp);
  3251. static void
  3252. _il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
  3253. {
  3254. struct il_rxon_cmd *rxon = &il->staging;
  3255. if (!il->ht.enabled) {
  3256. rxon->flags &=
  3257. ~(RXON_FLG_CHANNEL_MODE_MSK |
  3258. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK
  3259. | RXON_FLG_HT_PROT_MSK);
  3260. return;
  3261. }
  3262. rxon->flags |=
  3263. cpu_to_le32(il->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
  3264. /* Set up channel bandwidth:
  3265. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  3266. /* clear the HT channel mode before set the mode */
  3267. rxon->flags &=
  3268. ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3269. if (il_is_ht40_tx_allowed(il, NULL)) {
  3270. /* pure ht40 */
  3271. if (il->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  3272. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  3273. /* Note: control channel is opposite of extension channel */
  3274. switch (il->ht.extension_chan_offset) {
  3275. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  3276. rxon->flags &=
  3277. ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3278. break;
  3279. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  3280. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3281. break;
  3282. }
  3283. } else {
  3284. /* Note: control channel is opposite of extension channel */
  3285. switch (il->ht.extension_chan_offset) {
  3286. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  3287. rxon->flags &=
  3288. ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3289. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  3290. break;
  3291. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  3292. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3293. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  3294. break;
  3295. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  3296. default:
  3297. /* channel location only valid if in Mixed mode */
  3298. IL_ERR("invalid extension channel offset\n");
  3299. break;
  3300. }
  3301. }
  3302. } else {
  3303. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  3304. }
  3305. if (il->ops->set_rxon_chain)
  3306. il->ops->set_rxon_chain(il);
  3307. D_ASSOC("rxon flags 0x%X operation mode :0x%X "
  3308. "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags),
  3309. il->ht.protection, il->ht.extension_chan_offset);
  3310. }
  3311. void
  3312. il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
  3313. {
  3314. _il_set_rxon_ht(il, ht_conf);
  3315. }
  3316. EXPORT_SYMBOL(il_set_rxon_ht);
  3317. /* Return valid, unused, channel for a passive scan to reset the RF */
  3318. u8
  3319. il_get_single_channel_number(struct il_priv *il, enum nl80211_band band)
  3320. {
  3321. const struct il_channel_info *ch_info;
  3322. int i;
  3323. u8 channel = 0;
  3324. u8 min, max;
  3325. if (band == NL80211_BAND_5GHZ) {
  3326. min = 14;
  3327. max = il->channel_count;
  3328. } else {
  3329. min = 0;
  3330. max = 14;
  3331. }
  3332. for (i = min; i < max; i++) {
  3333. channel = il->channel_info[i].channel;
  3334. if (channel == le16_to_cpu(il->staging.channel))
  3335. continue;
  3336. ch_info = il_get_channel_info(il, band, channel);
  3337. if (il_is_channel_valid(ch_info))
  3338. break;
  3339. }
  3340. return channel;
  3341. }
  3342. EXPORT_SYMBOL(il_get_single_channel_number);
  3343. /*
  3344. * il_set_rxon_channel - Set the band and channel values in staging RXON
  3345. * @ch: requested channel as a pointer to struct ieee80211_channel
  3346. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  3347. * in the staging RXON flag structure based on the ch->band
  3348. */
  3349. int
  3350. il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch)
  3351. {
  3352. enum nl80211_band band = ch->band;
  3353. u16 channel = ch->hw_value;
  3354. if (le16_to_cpu(il->staging.channel) == channel && il->band == band)
  3355. return 0;
  3356. il->staging.channel = cpu_to_le16(channel);
  3357. if (band == NL80211_BAND_5GHZ)
  3358. il->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
  3359. else
  3360. il->staging.flags |= RXON_FLG_BAND_24G_MSK;
  3361. il->band = band;
  3362. D_INFO("Staging channel set to %d [%d]\n", channel, band);
  3363. return 0;
  3364. }
  3365. EXPORT_SYMBOL(il_set_rxon_channel);
  3366. void
  3367. il_set_flags_for_band(struct il_priv *il, enum nl80211_band band,
  3368. struct ieee80211_vif *vif)
  3369. {
  3370. if (band == NL80211_BAND_5GHZ) {
  3371. il->staging.flags &=
  3372. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
  3373. RXON_FLG_CCK_MSK);
  3374. il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  3375. } else {
  3376. /* Copied from il_post_associate() */
  3377. if (vif && vif->bss_conf.use_short_slot)
  3378. il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  3379. else
  3380. il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  3381. il->staging.flags |= RXON_FLG_BAND_24G_MSK;
  3382. il->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
  3383. il->staging.flags &= ~RXON_FLG_CCK_MSK;
  3384. }
  3385. }
  3386. EXPORT_SYMBOL(il_set_flags_for_band);
  3387. /*
  3388. * initialize rxon structure with default values from eeprom
  3389. */
  3390. void
  3391. il_connection_init_rx_config(struct il_priv *il)
  3392. {
  3393. const struct il_channel_info *ch_info;
  3394. memset(&il->staging, 0, sizeof(il->staging));
  3395. switch (il->iw_mode) {
  3396. case NL80211_IFTYPE_UNSPECIFIED:
  3397. il->staging.dev_type = RXON_DEV_TYPE_ESS;
  3398. break;
  3399. case NL80211_IFTYPE_STATION:
  3400. il->staging.dev_type = RXON_DEV_TYPE_ESS;
  3401. il->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  3402. break;
  3403. case NL80211_IFTYPE_ADHOC:
  3404. il->staging.dev_type = RXON_DEV_TYPE_IBSS;
  3405. il->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  3406. il->staging.filter_flags =
  3407. RXON_FILTER_BCON_AWARE_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  3408. break;
  3409. default:
  3410. IL_ERR("Unsupported interface type %d\n", il->vif->type);
  3411. return;
  3412. }
  3413. #if 0
  3414. /* TODO: Figure out when short_preamble would be set and cache from
  3415. * that */
  3416. if (!hw_to_local(il->hw)->short_preamble)
  3417. il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  3418. else
  3419. il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  3420. #endif
  3421. ch_info =
  3422. il_get_channel_info(il, il->band, le16_to_cpu(il->active.channel));
  3423. if (!ch_info)
  3424. ch_info = &il->channel_info[0];
  3425. il->staging.channel = cpu_to_le16(ch_info->channel);
  3426. il->band = ch_info->band;
  3427. il_set_flags_for_band(il, il->band, il->vif);
  3428. il->staging.ofdm_basic_rates =
  3429. (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  3430. il->staging.cck_basic_rates =
  3431. (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
  3432. /* clear both MIX and PURE40 mode flag */
  3433. il->staging.flags &=
  3434. ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40);
  3435. if (il->vif)
  3436. memcpy(il->staging.node_addr, il->vif->addr, ETH_ALEN);
  3437. il->staging.ofdm_ht_single_stream_basic_rates = 0xff;
  3438. il->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
  3439. }
  3440. EXPORT_SYMBOL(il_connection_init_rx_config);
  3441. void
  3442. il_set_rate(struct il_priv *il)
  3443. {
  3444. const struct ieee80211_supported_band *hw = NULL;
  3445. struct ieee80211_rate *rate;
  3446. int i;
  3447. hw = il_get_hw_mode(il, il->band);
  3448. if (!hw) {
  3449. IL_ERR("Failed to set rate: unable to get hw mode\n");
  3450. return;
  3451. }
  3452. il->active_rate = 0;
  3453. for (i = 0; i < hw->n_bitrates; i++) {
  3454. rate = &(hw->bitrates[i]);
  3455. if (rate->hw_value < RATE_COUNT_LEGACY)
  3456. il->active_rate |= (1 << rate->hw_value);
  3457. }
  3458. D_RATE("Set active_rate = %0x\n", il->active_rate);
  3459. il->staging.cck_basic_rates =
  3460. (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
  3461. il->staging.ofdm_basic_rates =
  3462. (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  3463. }
  3464. EXPORT_SYMBOL(il_set_rate);
  3465. void
  3466. il_chswitch_done(struct il_priv *il, bool is_success)
  3467. {
  3468. if (test_bit(S_EXIT_PENDING, &il->status))
  3469. return;
  3470. if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
  3471. ieee80211_chswitch_done(il->vif, is_success, 0);
  3472. }
  3473. EXPORT_SYMBOL(il_chswitch_done);
  3474. void
  3475. il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
  3476. {
  3477. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3478. struct il_csa_notification *csa = &(pkt->u.csa_notif);
  3479. struct il_rxon_cmd *rxon = (void *)&il->active;
  3480. if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
  3481. return;
  3482. if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
  3483. rxon->channel = csa->channel;
  3484. il->staging.channel = csa->channel;
  3485. D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
  3486. il_chswitch_done(il, true);
  3487. } else {
  3488. IL_ERR("CSA notif (fail) : channel %d\n",
  3489. le16_to_cpu(csa->channel));
  3490. il_chswitch_done(il, false);
  3491. }
  3492. }
  3493. EXPORT_SYMBOL(il_hdl_csa);
  3494. #ifdef CONFIG_IWLEGACY_DEBUG
  3495. void
  3496. il_print_rx_config_cmd(struct il_priv *il)
  3497. {
  3498. struct il_rxon_cmd *rxon = &il->staging;
  3499. D_RADIO("RX CONFIG:\n");
  3500. il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3501. D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3502. D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3503. D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags));
  3504. D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3505. D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates);
  3506. D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3507. D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3508. D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3509. D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3510. }
  3511. EXPORT_SYMBOL(il_print_rx_config_cmd);
  3512. #endif
  3513. /*
  3514. * il_irq_handle_error - called for HW or SW error interrupt from card
  3515. */
  3516. void
  3517. il_irq_handle_error(struct il_priv *il)
  3518. {
  3519. /* Set the FW error flag -- cleared on il_down */
  3520. set_bit(S_FW_ERROR, &il->status);
  3521. /* Cancel currently queued command. */
  3522. clear_bit(S_HCMD_ACTIVE, &il->status);
  3523. IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version);
  3524. il->ops->dump_nic_error_log(il);
  3525. if (il->ops->dump_fh)
  3526. il->ops->dump_fh(il, NULL, false);
  3527. #ifdef CONFIG_IWLEGACY_DEBUG
  3528. if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
  3529. il_print_rx_config_cmd(il);
  3530. #endif
  3531. wake_up(&il->wait_command_queue);
  3532. /* Keep the restart process from trying to send host
  3533. * commands by clearing the INIT status bit */
  3534. clear_bit(S_READY, &il->status);
  3535. if (!test_bit(S_EXIT_PENDING, &il->status)) {
  3536. IL_DBG(IL_DL_FW_ERRORS,
  3537. "Restarting adapter due to uCode error.\n");
  3538. if (il->cfg->mod_params->restart_fw)
  3539. queue_work(il->workqueue, &il->restart);
  3540. }
  3541. }
  3542. EXPORT_SYMBOL(il_irq_handle_error);
  3543. static int
  3544. _il_apm_stop_master(struct il_priv *il)
  3545. {
  3546. int ret = 0;
  3547. /* stop device's busmaster DMA activity */
  3548. _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  3549. ret =
  3550. _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
  3551. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  3552. if (ret < 0)
  3553. IL_WARN("Master Disable Timed Out, 100 usec\n");
  3554. D_INFO("stop master\n");
  3555. return ret;
  3556. }
  3557. void
  3558. _il_apm_stop(struct il_priv *il)
  3559. {
  3560. lockdep_assert_held(&il->reg_lock);
  3561. D_INFO("Stop card, put in low power state\n");
  3562. /* Stop device's DMA activity */
  3563. _il_apm_stop_master(il);
  3564. /* Reset the entire device */
  3565. _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  3566. udelay(10);
  3567. /*
  3568. * Clear "initialization complete" bit to move adapter from
  3569. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  3570. */
  3571. _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  3572. }
  3573. EXPORT_SYMBOL(_il_apm_stop);
  3574. void
  3575. il_apm_stop(struct il_priv *il)
  3576. {
  3577. unsigned long flags;
  3578. spin_lock_irqsave(&il->reg_lock, flags);
  3579. _il_apm_stop(il);
  3580. spin_unlock_irqrestore(&il->reg_lock, flags);
  3581. }
  3582. EXPORT_SYMBOL(il_apm_stop);
  3583. /*
  3584. * Start up NIC's basic functionality after it has been reset
  3585. * (e.g. after platform boot, or shutdown via il_apm_stop())
  3586. * NOTE: This does not load uCode nor start the embedded processor
  3587. */
  3588. int
  3589. il_apm_init(struct il_priv *il)
  3590. {
  3591. int ret = 0;
  3592. u16 lctl;
  3593. D_INFO("Init card's basic functions\n");
  3594. /*
  3595. * Use "set_bit" below rather than "write", to preserve any hardware
  3596. * bits already set by default after reset.
  3597. */
  3598. /* Disable L0S exit timer (platform NMI Work/Around) */
  3599. il_set_bit(il, CSR_GIO_CHICKEN_BITS,
  3600. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  3601. /*
  3602. * Disable L0s without affecting L1;
  3603. * don't wait for ICH L0s (ICH bug W/A)
  3604. */
  3605. il_set_bit(il, CSR_GIO_CHICKEN_BITS,
  3606. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  3607. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  3608. il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  3609. /*
  3610. * Enable HAP INTA (interrupt from management bus) to
  3611. * wake device's PCI Express link L1a -> L0s
  3612. * NOTE: This is no-op for 3945 (non-existent bit)
  3613. */
  3614. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  3615. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  3616. /*
  3617. * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
  3618. * Check if BIOS (or OS) enabled L1-ASPM on this device.
  3619. * If so (likely), disable L0S, so device moves directly L0->L1;
  3620. * costs negligible amount of power savings.
  3621. * If not (unlikely), enable L0S, so there is at least some
  3622. * power savings, even without L1.
  3623. */
  3624. if (il->cfg->set_l0s) {
  3625. ret = pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
  3626. if (!ret && (lctl & PCI_EXP_LNKCTL_ASPM_L1)) {
  3627. /* L1-ASPM enabled; disable(!) L0S */
  3628. il_set_bit(il, CSR_GIO_REG,
  3629. CSR_GIO_REG_VAL_L0S_ENABLED);
  3630. D_POWER("L1 Enabled; Disabling L0S\n");
  3631. } else {
  3632. /* L1-ASPM disabled; enable(!) L0S */
  3633. il_clear_bit(il, CSR_GIO_REG,
  3634. CSR_GIO_REG_VAL_L0S_ENABLED);
  3635. D_POWER("L1 Disabled; Enabling L0S\n");
  3636. }
  3637. }
  3638. /* Configure analog phase-lock-loop before activating to D0A */
  3639. if (il->cfg->pll_cfg_val)
  3640. il_set_bit(il, CSR_ANA_PLL_CFG,
  3641. il->cfg->pll_cfg_val);
  3642. /*
  3643. * Set "initialization complete" bit to move adapter from
  3644. * D0U* --> D0A* (powered-up active) state.
  3645. */
  3646. il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  3647. /*
  3648. * Wait for clock stabilization; once stabilized, access to
  3649. * device-internal resources is supported, e.g. il_wr_prph()
  3650. * and accesses to uCode SRAM.
  3651. */
  3652. ret =
  3653. _il_poll_bit(il, CSR_GP_CNTRL,
  3654. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  3655. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  3656. if (ret < 0) {
  3657. D_INFO("Failed to init the card\n");
  3658. goto out;
  3659. }
  3660. /*
  3661. * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
  3662. * BSM (Boostrap State Machine) is only in 3945 and 4965.
  3663. *
  3664. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  3665. * do not disable clocks. This preserves any hardware bits already
  3666. * set by default in "CLK_CTRL_REG" after reset.
  3667. */
  3668. if (il->cfg->use_bsm)
  3669. il_wr_prph(il, APMG_CLK_EN_REG,
  3670. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  3671. else
  3672. il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  3673. udelay(20);
  3674. /* Disable L1-Active */
  3675. il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
  3676. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  3677. out:
  3678. return ret;
  3679. }
  3680. EXPORT_SYMBOL(il_apm_init);
  3681. int
  3682. il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
  3683. {
  3684. int ret;
  3685. s8 prev_tx_power;
  3686. bool defer;
  3687. lockdep_assert_held(&il->mutex);
  3688. if (il->tx_power_user_lmt == tx_power && !force)
  3689. return 0;
  3690. if (!il->ops->send_tx_power)
  3691. return -EOPNOTSUPP;
  3692. /* 0 dBm mean 1 milliwatt */
  3693. if (tx_power < 0) {
  3694. IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power);
  3695. return -EINVAL;
  3696. }
  3697. if (tx_power > il->tx_power_device_lmt) {
  3698. IL_WARN("Requested user TXPOWER %d above upper limit %d.\n",
  3699. tx_power, il->tx_power_device_lmt);
  3700. return -EINVAL;
  3701. }
  3702. if (!il_is_ready_rf(il))
  3703. return -EIO;
  3704. /* scan complete and commit_rxon use tx_power_next value,
  3705. * it always need to be updated for newest request */
  3706. il->tx_power_next = tx_power;
  3707. /* do not set tx power when scanning or channel changing */
  3708. defer = test_bit(S_SCANNING, &il->status) ||
  3709. memcmp(&il->active, &il->staging, sizeof(il->staging));
  3710. if (defer && !force) {
  3711. D_INFO("Deferring tx power set\n");
  3712. return 0;
  3713. }
  3714. prev_tx_power = il->tx_power_user_lmt;
  3715. il->tx_power_user_lmt = tx_power;
  3716. ret = il->ops->send_tx_power(il);
  3717. /* if fail to set tx_power, restore the orig. tx power */
  3718. if (ret) {
  3719. il->tx_power_user_lmt = prev_tx_power;
  3720. il->tx_power_next = prev_tx_power;
  3721. }
  3722. return ret;
  3723. }
  3724. EXPORT_SYMBOL(il_set_tx_power);
  3725. void
  3726. il_send_bt_config(struct il_priv *il)
  3727. {
  3728. struct il_bt_cmd bt_cmd = {
  3729. .lead_time = BT_LEAD_TIME_DEF,
  3730. .max_kill = BT_MAX_KILL_DEF,
  3731. .kill_ack_mask = 0,
  3732. .kill_cts_mask = 0,
  3733. };
  3734. if (!bt_coex_active)
  3735. bt_cmd.flags = BT_COEX_DISABLE;
  3736. else
  3737. bt_cmd.flags = BT_COEX_ENABLE;
  3738. D_INFO("BT coex %s\n",
  3739. (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
  3740. if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd))
  3741. IL_ERR("failed to send BT Coex Config\n");
  3742. }
  3743. EXPORT_SYMBOL(il_send_bt_config);
  3744. int
  3745. il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
  3746. {
  3747. struct il_stats_cmd stats_cmd = {
  3748. .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0,
  3749. };
  3750. if (flags & CMD_ASYNC)
  3751. return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd),
  3752. &stats_cmd, NULL);
  3753. else
  3754. return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd),
  3755. &stats_cmd);
  3756. }
  3757. EXPORT_SYMBOL(il_send_stats_request);
  3758. void
  3759. il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb)
  3760. {
  3761. #ifdef CONFIG_IWLEGACY_DEBUG
  3762. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3763. struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
  3764. D_RX("sleep mode: %d, src: %d\n",
  3765. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  3766. #endif
  3767. }
  3768. EXPORT_SYMBOL(il_hdl_pm_sleep);
  3769. void
  3770. il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb)
  3771. {
  3772. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3773. u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
  3774. D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len,
  3775. il_get_cmd_string(pkt->hdr.cmd));
  3776. il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
  3777. }
  3778. EXPORT_SYMBOL(il_hdl_pm_debug_stats);
  3779. void
  3780. il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb)
  3781. {
  3782. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3783. IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
  3784. "seq 0x%04X ser 0x%08X\n",
  3785. le32_to_cpu(pkt->u.err_resp.error_type),
  3786. il_get_cmd_string(pkt->u.err_resp.cmd_id),
  3787. pkt->u.err_resp.cmd_id,
  3788. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  3789. le32_to_cpu(pkt->u.err_resp.error_info));
  3790. }
  3791. EXPORT_SYMBOL(il_hdl_error);
  3792. void
  3793. il_clear_isr_stats(struct il_priv *il)
  3794. {
  3795. memset(&il->isr_stats, 0, sizeof(il->isr_stats));
  3796. }
  3797. int
  3798. il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  3799. unsigned int link_id, u16 queue,
  3800. const struct ieee80211_tx_queue_params *params)
  3801. {
  3802. struct il_priv *il = hw->priv;
  3803. unsigned long flags;
  3804. int q;
  3805. D_MAC80211("enter\n");
  3806. if (!il_is_ready_rf(il)) {
  3807. D_MAC80211("leave - RF not ready\n");
  3808. return -EIO;
  3809. }
  3810. if (queue >= AC_NUM) {
  3811. D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  3812. return 0;
  3813. }
  3814. q = AC_NUM - 1 - queue;
  3815. spin_lock_irqsave(&il->lock, flags);
  3816. il->qos_data.def_qos_parm.ac[q].cw_min =
  3817. cpu_to_le16(params->cw_min);
  3818. il->qos_data.def_qos_parm.ac[q].cw_max =
  3819. cpu_to_le16(params->cw_max);
  3820. il->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  3821. il->qos_data.def_qos_parm.ac[q].edca_txop =
  3822. cpu_to_le16((params->txop * 32));
  3823. il->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  3824. spin_unlock_irqrestore(&il->lock, flags);
  3825. D_MAC80211("leave\n");
  3826. return 0;
  3827. }
  3828. EXPORT_SYMBOL(il_mac_conf_tx);
  3829. int
  3830. il_mac_tx_last_beacon(struct ieee80211_hw *hw)
  3831. {
  3832. struct il_priv *il = hw->priv;
  3833. int ret;
  3834. D_MAC80211("enter\n");
  3835. ret = (il->ibss_manager == IL_IBSS_MANAGER);
  3836. D_MAC80211("leave ret %d\n", ret);
  3837. return ret;
  3838. }
  3839. EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
  3840. static int
  3841. il_set_mode(struct il_priv *il)
  3842. {
  3843. il_connection_init_rx_config(il);
  3844. if (il->ops->set_rxon_chain)
  3845. il->ops->set_rxon_chain(il);
  3846. return il_commit_rxon(il);
  3847. }
  3848. int
  3849. il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  3850. {
  3851. struct il_priv *il = hw->priv;
  3852. int err;
  3853. bool reset;
  3854. mutex_lock(&il->mutex);
  3855. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  3856. if (!il_is_ready_rf(il)) {
  3857. IL_WARN("Try to add interface when device not ready\n");
  3858. err = -EINVAL;
  3859. goto out;
  3860. }
  3861. /*
  3862. * We do not support multiple virtual interfaces, but on hardware reset
  3863. * we have to add the same interface again.
  3864. */
  3865. reset = (il->vif == vif);
  3866. if (il->vif && !reset) {
  3867. err = -EOPNOTSUPP;
  3868. goto out;
  3869. }
  3870. il->vif = vif;
  3871. il->iw_mode = vif->type;
  3872. err = il_set_mode(il);
  3873. if (err) {
  3874. IL_WARN("Fail to set mode %d\n", vif->type);
  3875. if (!reset) {
  3876. il->vif = NULL;
  3877. il->iw_mode = NL80211_IFTYPE_STATION;
  3878. }
  3879. }
  3880. out:
  3881. D_MAC80211("leave err %d\n", err);
  3882. mutex_unlock(&il->mutex);
  3883. return err;
  3884. }
  3885. EXPORT_SYMBOL(il_mac_add_interface);
  3886. static void
  3887. il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif)
  3888. {
  3889. lockdep_assert_held(&il->mutex);
  3890. if (il->scan_vif == vif) {
  3891. il_scan_cancel_timeout(il, 200);
  3892. il_force_scan_end(il);
  3893. }
  3894. il_set_mode(il);
  3895. }
  3896. void
  3897. il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  3898. {
  3899. struct il_priv *il = hw->priv;
  3900. mutex_lock(&il->mutex);
  3901. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  3902. WARN_ON(il->vif != vif);
  3903. il->vif = NULL;
  3904. il->iw_mode = NL80211_IFTYPE_UNSPECIFIED;
  3905. il_teardown_interface(il, vif);
  3906. eth_zero_addr(il->bssid);
  3907. D_MAC80211("leave\n");
  3908. mutex_unlock(&il->mutex);
  3909. }
  3910. EXPORT_SYMBOL(il_mac_remove_interface);
  3911. int
  3912. il_alloc_txq_mem(struct il_priv *il)
  3913. {
  3914. if (!il->txq)
  3915. il->txq =
  3916. kcalloc(il->cfg->num_of_queues,
  3917. sizeof(struct il_tx_queue),
  3918. GFP_KERNEL);
  3919. if (!il->txq) {
  3920. IL_ERR("Not enough memory for txq\n");
  3921. return -ENOMEM;
  3922. }
  3923. return 0;
  3924. }
  3925. EXPORT_SYMBOL(il_alloc_txq_mem);
  3926. void
  3927. il_free_txq_mem(struct il_priv *il)
  3928. {
  3929. kfree(il->txq);
  3930. il->txq = NULL;
  3931. }
  3932. EXPORT_SYMBOL(il_free_txq_mem);
  3933. int
  3934. il_force_reset(struct il_priv *il, bool external)
  3935. {
  3936. struct il_force_reset *force_reset;
  3937. if (test_bit(S_EXIT_PENDING, &il->status))
  3938. return -EINVAL;
  3939. force_reset = &il->force_reset;
  3940. force_reset->reset_request_count++;
  3941. if (!external) {
  3942. if (force_reset->last_force_reset_jiffies &&
  3943. time_after(force_reset->last_force_reset_jiffies +
  3944. force_reset->reset_duration, jiffies)) {
  3945. D_INFO("force reset rejected\n");
  3946. force_reset->reset_reject_count++;
  3947. return -EAGAIN;
  3948. }
  3949. }
  3950. force_reset->reset_success_count++;
  3951. force_reset->last_force_reset_jiffies = jiffies;
  3952. /*
  3953. * if the request is from external(ex: debugfs),
  3954. * then always perform the request in regardless the module
  3955. * parameter setting
  3956. * if the request is from internal (uCode error or driver
  3957. * detect failure), then fw_restart module parameter
  3958. * need to be check before performing firmware reload
  3959. */
  3960. if (!external && !il->cfg->mod_params->restart_fw) {
  3961. D_INFO("Cancel firmware reload based on "
  3962. "module parameter setting\n");
  3963. return 0;
  3964. }
  3965. IL_ERR("On demand firmware reload\n");
  3966. /* Set the FW error flag -- cleared on il_down */
  3967. set_bit(S_FW_ERROR, &il->status);
  3968. wake_up(&il->wait_command_queue);
  3969. /*
  3970. * Keep the restart process from trying to send host
  3971. * commands by clearing the INIT status bit
  3972. */
  3973. clear_bit(S_READY, &il->status);
  3974. queue_work(il->workqueue, &il->restart);
  3975. return 0;
  3976. }
  3977. EXPORT_SYMBOL(il_force_reset);
  3978. int
  3979. il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  3980. enum nl80211_iftype newtype, bool newp2p)
  3981. {
  3982. struct il_priv *il = hw->priv;
  3983. int err;
  3984. mutex_lock(&il->mutex);
  3985. D_MAC80211("enter: type %d, addr %pM newtype %d newp2p %d\n",
  3986. vif->type, vif->addr, newtype, newp2p);
  3987. if (newp2p) {
  3988. err = -EOPNOTSUPP;
  3989. goto out;
  3990. }
  3991. if (!il->vif || !il_is_ready_rf(il)) {
  3992. /*
  3993. * Huh? But wait ... this can maybe happen when
  3994. * we're in the middle of a firmware restart!
  3995. */
  3996. err = -EBUSY;
  3997. goto out;
  3998. }
  3999. /* success */
  4000. vif->type = newtype;
  4001. vif->p2p = false;
  4002. il->iw_mode = newtype;
  4003. il_teardown_interface(il, vif);
  4004. err = 0;
  4005. out:
  4006. D_MAC80211("leave err %d\n", err);
  4007. mutex_unlock(&il->mutex);
  4008. return err;
  4009. }
  4010. EXPORT_SYMBOL(il_mac_change_interface);
  4011. void il_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  4012. u32 queues, bool drop)
  4013. {
  4014. struct il_priv *il = hw->priv;
  4015. unsigned long timeout = jiffies + msecs_to_jiffies(500);
  4016. int i;
  4017. mutex_lock(&il->mutex);
  4018. D_MAC80211("enter\n");
  4019. if (il->txq == NULL)
  4020. goto out;
  4021. for (i = 0; i < il->hw_params.max_txq_num; i++) {
  4022. struct il_queue *q;
  4023. if (i == il->cmd_queue)
  4024. continue;
  4025. q = &il->txq[i].q;
  4026. if (q->read_ptr == q->write_ptr)
  4027. continue;
  4028. if (time_after(jiffies, timeout)) {
  4029. IL_ERR("Failed to flush queue %d\n", q->id);
  4030. break;
  4031. }
  4032. msleep(20);
  4033. }
  4034. out:
  4035. D_MAC80211("leave\n");
  4036. mutex_unlock(&il->mutex);
  4037. }
  4038. EXPORT_SYMBOL(il_mac_flush);
  4039. /*
  4040. * On every watchdog tick we check (latest) time stamp. If it does not
  4041. * change during timeout period and queue is not empty we reset firmware.
  4042. */
  4043. static int
  4044. il_check_stuck_queue(struct il_priv *il, int cnt)
  4045. {
  4046. struct il_tx_queue *txq = &il->txq[cnt];
  4047. struct il_queue *q = &txq->q;
  4048. unsigned long timeout;
  4049. unsigned long now = jiffies;
  4050. int ret;
  4051. if (q->read_ptr == q->write_ptr) {
  4052. txq->time_stamp = now;
  4053. return 0;
  4054. }
  4055. timeout =
  4056. txq->time_stamp +
  4057. msecs_to_jiffies(il->cfg->wd_timeout);
  4058. if (time_after(now, timeout)) {
  4059. IL_ERR("Queue %d stuck for %u ms.\n", q->id,
  4060. jiffies_to_msecs(now - txq->time_stamp));
  4061. ret = il_force_reset(il, false);
  4062. return (ret == -EAGAIN) ? 0 : 1;
  4063. }
  4064. return 0;
  4065. }
  4066. /*
  4067. * Making watchdog tick be a quarter of timeout assure we will
  4068. * discover the queue hung between timeout and 1.25*timeout
  4069. */
  4070. #define IL_WD_TICK(timeout) ((timeout) / 4)
  4071. /*
  4072. * Watchdog timer callback, we check each tx queue for stuck, if hung
  4073. * we reset the firmware. If everything is fine just rearm the timer.
  4074. */
  4075. void
  4076. il_bg_watchdog(struct timer_list *t)
  4077. {
  4078. struct il_priv *il = from_timer(il, t, watchdog);
  4079. int cnt;
  4080. unsigned long timeout;
  4081. if (test_bit(S_EXIT_PENDING, &il->status))
  4082. return;
  4083. timeout = il->cfg->wd_timeout;
  4084. if (timeout == 0)
  4085. return;
  4086. /* monitor and check for stuck cmd queue */
  4087. if (il_check_stuck_queue(il, il->cmd_queue))
  4088. return;
  4089. /* monitor and check for other stuck queues */
  4090. for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
  4091. /* skip as we already checked the command queue */
  4092. if (cnt == il->cmd_queue)
  4093. continue;
  4094. if (il_check_stuck_queue(il, cnt))
  4095. return;
  4096. }
  4097. mod_timer(&il->watchdog,
  4098. jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
  4099. }
  4100. EXPORT_SYMBOL(il_bg_watchdog);
  4101. void
  4102. il_setup_watchdog(struct il_priv *il)
  4103. {
  4104. unsigned int timeout = il->cfg->wd_timeout;
  4105. if (timeout)
  4106. mod_timer(&il->watchdog,
  4107. jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
  4108. else
  4109. del_timer(&il->watchdog);
  4110. }
  4111. EXPORT_SYMBOL(il_setup_watchdog);
  4112. /*
  4113. * extended beacon time format
  4114. * time in usec will be changed into a 32-bit value in extended:internal format
  4115. * the extended part is the beacon counts
  4116. * the internal part is the time in usec within one beacon interval
  4117. */
  4118. u32
  4119. il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval)
  4120. {
  4121. u32 quot;
  4122. u32 rem;
  4123. u32 interval = beacon_interval * TIME_UNIT;
  4124. if (!interval || !usec)
  4125. return 0;
  4126. quot =
  4127. (usec /
  4128. interval) & (il_beacon_time_mask_high(il,
  4129. il->hw_params.
  4130. beacon_time_tsf_bits) >> il->
  4131. hw_params.beacon_time_tsf_bits);
  4132. rem =
  4133. (usec % interval) & il_beacon_time_mask_low(il,
  4134. il->hw_params.
  4135. beacon_time_tsf_bits);
  4136. return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
  4137. }
  4138. EXPORT_SYMBOL(il_usecs_to_beacons);
  4139. /* base is usually what we get from ucode with each received frame,
  4140. * the same as HW timer counter counting down
  4141. */
  4142. __le32
  4143. il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
  4144. u32 beacon_interval)
  4145. {
  4146. u32 base_low = base & il_beacon_time_mask_low(il,
  4147. il->hw_params.
  4148. beacon_time_tsf_bits);
  4149. u32 addon_low = addon & il_beacon_time_mask_low(il,
  4150. il->hw_params.
  4151. beacon_time_tsf_bits);
  4152. u32 interval = beacon_interval * TIME_UNIT;
  4153. u32 res = (base & il_beacon_time_mask_high(il,
  4154. il->hw_params.
  4155. beacon_time_tsf_bits)) +
  4156. (addon & il_beacon_time_mask_high(il,
  4157. il->hw_params.
  4158. beacon_time_tsf_bits));
  4159. if (base_low > addon_low)
  4160. res += base_low - addon_low;
  4161. else if (base_low < addon_low) {
  4162. res += interval + base_low - addon_low;
  4163. res += (1 << il->hw_params.beacon_time_tsf_bits);
  4164. } else
  4165. res += (1 << il->hw_params.beacon_time_tsf_bits);
  4166. return cpu_to_le32(res);
  4167. }
  4168. EXPORT_SYMBOL(il_add_beacon_time);
  4169. #ifdef CONFIG_PM_SLEEP
  4170. static int
  4171. il_pci_suspend(struct device *device)
  4172. {
  4173. struct il_priv *il = dev_get_drvdata(device);
  4174. /*
  4175. * This function is called when system goes into suspend state
  4176. * mac80211 will call il_mac_stop() from the mac80211 suspend function
  4177. * first but since il_mac_stop() has no knowledge of who the caller is,
  4178. * it will not call apm_ops.stop() to stop the DMA operation.
  4179. * Calling apm_ops.stop here to make sure we stop the DMA.
  4180. */
  4181. il_apm_stop(il);
  4182. return 0;
  4183. }
  4184. static int
  4185. il_pci_resume(struct device *device)
  4186. {
  4187. struct pci_dev *pdev = to_pci_dev(device);
  4188. struct il_priv *il = pci_get_drvdata(pdev);
  4189. bool hw_rfkill = false;
  4190. /*
  4191. * We disable the RETRY_TIMEOUT register (0x41) to keep
  4192. * PCI Tx retries from interfering with C3 CPU state.
  4193. */
  4194. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  4195. _il_wr(il, CSR_INT, 0xffffffff);
  4196. _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
  4197. il_enable_interrupts(il);
  4198. if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  4199. hw_rfkill = true;
  4200. if (hw_rfkill)
  4201. set_bit(S_RFKILL, &il->status);
  4202. else
  4203. clear_bit(S_RFKILL, &il->status);
  4204. wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
  4205. return 0;
  4206. }
  4207. SIMPLE_DEV_PM_OPS(il_pm_ops, il_pci_suspend, il_pci_resume);
  4208. EXPORT_SYMBOL(il_pm_ops);
  4209. #endif /* CONFIG_PM_SLEEP */
  4210. static void
  4211. il_update_qos(struct il_priv *il)
  4212. {
  4213. if (test_bit(S_EXIT_PENDING, &il->status))
  4214. return;
  4215. il->qos_data.def_qos_parm.qos_flags = 0;
  4216. if (il->qos_data.qos_active)
  4217. il->qos_data.def_qos_parm.qos_flags |=
  4218. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  4219. if (il->ht.enabled)
  4220. il->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  4221. D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  4222. il->qos_data.qos_active, il->qos_data.def_qos_parm.qos_flags);
  4223. il_send_cmd_pdu_async(il, C_QOS_PARAM, sizeof(struct il_qosparam_cmd),
  4224. &il->qos_data.def_qos_parm, NULL);
  4225. }
  4226. /*
  4227. * il_mac_config - mac80211 config callback
  4228. */
  4229. int
  4230. il_mac_config(struct ieee80211_hw *hw, u32 changed)
  4231. {
  4232. struct il_priv *il = hw->priv;
  4233. const struct il_channel_info *ch_info;
  4234. struct ieee80211_conf *conf = &hw->conf;
  4235. struct ieee80211_channel *channel = conf->chandef.chan;
  4236. struct il_ht_config *ht_conf = &il->current_ht_config;
  4237. unsigned long flags = 0;
  4238. int ret = 0;
  4239. u16 ch;
  4240. int scan_active = 0;
  4241. bool ht_changed = false;
  4242. mutex_lock(&il->mutex);
  4243. D_MAC80211("enter: channel %d changed 0x%X\n", channel->hw_value,
  4244. changed);
  4245. if (unlikely(test_bit(S_SCANNING, &il->status))) {
  4246. scan_active = 1;
  4247. D_MAC80211("scan active\n");
  4248. }
  4249. if (changed &
  4250. (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) {
  4251. /* mac80211 uses static for non-HT which is what we want */
  4252. il->current_ht_config.smps = conf->smps_mode;
  4253. /*
  4254. * Recalculate chain counts.
  4255. *
  4256. * If monitor mode is enabled then mac80211 will
  4257. * set up the SM PS mode to OFF if an HT channel is
  4258. * configured.
  4259. */
  4260. if (il->ops->set_rxon_chain)
  4261. il->ops->set_rxon_chain(il);
  4262. }
  4263. /* during scanning mac80211 will delay channel setting until
  4264. * scan finish with changed = 0
  4265. */
  4266. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  4267. if (scan_active)
  4268. goto set_ch_out;
  4269. ch = channel->hw_value;
  4270. ch_info = il_get_channel_info(il, channel->band, ch);
  4271. if (!il_is_channel_valid(ch_info)) {
  4272. D_MAC80211("leave - invalid channel\n");
  4273. ret = -EINVAL;
  4274. goto set_ch_out;
  4275. }
  4276. if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
  4277. !il_is_channel_ibss(ch_info)) {
  4278. D_MAC80211("leave - not IBSS channel\n");
  4279. ret = -EINVAL;
  4280. goto set_ch_out;
  4281. }
  4282. spin_lock_irqsave(&il->lock, flags);
  4283. /* Configure HT40 channels */
  4284. if (il->ht.enabled != conf_is_ht(conf)) {
  4285. il->ht.enabled = conf_is_ht(conf);
  4286. ht_changed = true;
  4287. }
  4288. if (il->ht.enabled) {
  4289. if (conf_is_ht40_minus(conf)) {
  4290. il->ht.extension_chan_offset =
  4291. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  4292. il->ht.is_40mhz = true;
  4293. } else if (conf_is_ht40_plus(conf)) {
  4294. il->ht.extension_chan_offset =
  4295. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  4296. il->ht.is_40mhz = true;
  4297. } else {
  4298. il->ht.extension_chan_offset =
  4299. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  4300. il->ht.is_40mhz = false;
  4301. }
  4302. } else
  4303. il->ht.is_40mhz = false;
  4304. /*
  4305. * Default to no protection. Protection mode will
  4306. * later be set from BSS config in il_ht_conf
  4307. */
  4308. il->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
  4309. /* if we are switching from ht to 2.4 clear flags
  4310. * from any ht related info since 2.4 does not
  4311. * support ht */
  4312. if ((le16_to_cpu(il->staging.channel) != ch))
  4313. il->staging.flags = 0;
  4314. il_set_rxon_channel(il, channel);
  4315. il_set_rxon_ht(il, ht_conf);
  4316. il_set_flags_for_band(il, channel->band, il->vif);
  4317. spin_unlock_irqrestore(&il->lock, flags);
  4318. if (il->ops->update_bcast_stations)
  4319. ret = il->ops->update_bcast_stations(il);
  4320. set_ch_out:
  4321. /* The list of supported rates and rate mask can be different
  4322. * for each band; since the band may have changed, reset
  4323. * the rate mask to what mac80211 lists */
  4324. il_set_rate(il);
  4325. }
  4326. if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) {
  4327. il->power_data.ps_disabled = !(conf->flags & IEEE80211_CONF_PS);
  4328. if (!il->power_data.ps_disabled)
  4329. IL_WARN_ONCE("Enabling power save might cause firmware crashes\n");
  4330. ret = il_power_update_mode(il, false);
  4331. if (ret)
  4332. D_MAC80211("Error setting sleep level\n");
  4333. }
  4334. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  4335. D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt,
  4336. conf->power_level);
  4337. il_set_tx_power(il, conf->power_level, false);
  4338. }
  4339. if (!il_is_ready(il)) {
  4340. D_MAC80211("leave - not ready\n");
  4341. goto out;
  4342. }
  4343. if (scan_active)
  4344. goto out;
  4345. if (memcmp(&il->active, &il->staging, sizeof(il->staging)))
  4346. il_commit_rxon(il);
  4347. else
  4348. D_INFO("Not re-sending same RXON configuration.\n");
  4349. if (ht_changed)
  4350. il_update_qos(il);
  4351. out:
  4352. D_MAC80211("leave ret %d\n", ret);
  4353. mutex_unlock(&il->mutex);
  4354. return ret;
  4355. }
  4356. EXPORT_SYMBOL(il_mac_config);
  4357. void
  4358. il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  4359. {
  4360. struct il_priv *il = hw->priv;
  4361. unsigned long flags;
  4362. mutex_lock(&il->mutex);
  4363. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  4364. spin_lock_irqsave(&il->lock, flags);
  4365. memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
  4366. /* new association get rid of ibss beacon skb */
  4367. dev_consume_skb_irq(il->beacon_skb);
  4368. il->beacon_skb = NULL;
  4369. il->timestamp = 0;
  4370. spin_unlock_irqrestore(&il->lock, flags);
  4371. il_scan_cancel_timeout(il, 100);
  4372. if (!il_is_ready_rf(il)) {
  4373. D_MAC80211("leave - not ready\n");
  4374. mutex_unlock(&il->mutex);
  4375. return;
  4376. }
  4377. /* we are restarting association process */
  4378. il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4379. il_commit_rxon(il);
  4380. il_set_rate(il);
  4381. D_MAC80211("leave\n");
  4382. mutex_unlock(&il->mutex);
  4383. }
  4384. EXPORT_SYMBOL(il_mac_reset_tsf);
  4385. static void
  4386. il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif)
  4387. {
  4388. struct il_ht_config *ht_conf = &il->current_ht_config;
  4389. struct ieee80211_sta *sta;
  4390. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  4391. D_ASSOC("enter:\n");
  4392. if (!il->ht.enabled)
  4393. return;
  4394. il->ht.protection =
  4395. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  4396. il->ht.non_gf_sta_present =
  4397. !!(bss_conf->
  4398. ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  4399. ht_conf->single_chain_sufficient = false;
  4400. switch (vif->type) {
  4401. case NL80211_IFTYPE_STATION:
  4402. rcu_read_lock();
  4403. sta = ieee80211_find_sta(vif, bss_conf->bssid);
  4404. if (sta) {
  4405. struct ieee80211_sta_ht_cap *ht_cap = &sta->deflink.ht_cap;
  4406. int maxstreams;
  4407. maxstreams =
  4408. (ht_cap->mcs.
  4409. tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
  4410. >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  4411. maxstreams += 1;
  4412. if (ht_cap->mcs.rx_mask[1] == 0 &&
  4413. ht_cap->mcs.rx_mask[2] == 0)
  4414. ht_conf->single_chain_sufficient = true;
  4415. if (maxstreams <= 1)
  4416. ht_conf->single_chain_sufficient = true;
  4417. } else {
  4418. /*
  4419. * If at all, this can only happen through a race
  4420. * when the AP disconnects us while we're still
  4421. * setting up the connection, in that case mac80211
  4422. * will soon tell us about that.
  4423. */
  4424. ht_conf->single_chain_sufficient = true;
  4425. }
  4426. rcu_read_unlock();
  4427. break;
  4428. case NL80211_IFTYPE_ADHOC:
  4429. ht_conf->single_chain_sufficient = true;
  4430. break;
  4431. default:
  4432. break;
  4433. }
  4434. D_ASSOC("leave\n");
  4435. }
  4436. static inline void
  4437. il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif)
  4438. {
  4439. /*
  4440. * inform the ucode that there is no longer an
  4441. * association and that no more packets should be
  4442. * sent
  4443. */
  4444. il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4445. il->staging.assoc_id = 0;
  4446. il_commit_rxon(il);
  4447. }
  4448. static void
  4449. il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  4450. {
  4451. struct il_priv *il = hw->priv;
  4452. unsigned long flags;
  4453. __le64 timestamp;
  4454. struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0);
  4455. if (!skb)
  4456. return;
  4457. D_MAC80211("enter\n");
  4458. lockdep_assert_held(&il->mutex);
  4459. if (!il->beacon_enabled) {
  4460. IL_ERR("update beacon with no beaconing enabled\n");
  4461. dev_kfree_skb(skb);
  4462. return;
  4463. }
  4464. spin_lock_irqsave(&il->lock, flags);
  4465. dev_consume_skb_irq(il->beacon_skb);
  4466. il->beacon_skb = skb;
  4467. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  4468. il->timestamp = le64_to_cpu(timestamp);
  4469. D_MAC80211("leave\n");
  4470. spin_unlock_irqrestore(&il->lock, flags);
  4471. if (!il_is_ready_rf(il)) {
  4472. D_MAC80211("leave - RF not ready\n");
  4473. return;
  4474. }
  4475. il->ops->post_associate(il);
  4476. }
  4477. void
  4478. il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  4479. struct ieee80211_bss_conf *bss_conf, u64 changes)
  4480. {
  4481. struct il_priv *il = hw->priv;
  4482. int ret;
  4483. mutex_lock(&il->mutex);
  4484. D_MAC80211("enter: changes 0x%llx\n", changes);
  4485. if (!il_is_alive(il)) {
  4486. D_MAC80211("leave - not alive\n");
  4487. mutex_unlock(&il->mutex);
  4488. return;
  4489. }
  4490. if (changes & BSS_CHANGED_QOS) {
  4491. unsigned long flags;
  4492. spin_lock_irqsave(&il->lock, flags);
  4493. il->qos_data.qos_active = bss_conf->qos;
  4494. il_update_qos(il);
  4495. spin_unlock_irqrestore(&il->lock, flags);
  4496. }
  4497. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  4498. /* FIXME: can we remove beacon_enabled ? */
  4499. if (vif->bss_conf.enable_beacon)
  4500. il->beacon_enabled = true;
  4501. else
  4502. il->beacon_enabled = false;
  4503. }
  4504. if (changes & BSS_CHANGED_BSSID) {
  4505. D_MAC80211("BSSID %pM\n", bss_conf->bssid);
  4506. /*
  4507. * On passive channel we wait with blocked queues to see if
  4508. * there is traffic on that channel. If no frame will be
  4509. * received (what is very unlikely since scan detects AP on
  4510. * that channel, but theoretically possible), mac80211 associate
  4511. * procedure will time out and mac80211 will call us with NULL
  4512. * bssid. We have to unblock queues on such condition.
  4513. */
  4514. if (is_zero_ether_addr(bss_conf->bssid))
  4515. il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
  4516. /*
  4517. * If there is currently a HW scan going on in the background,
  4518. * then we need to cancel it, otherwise sometimes we are not
  4519. * able to authenticate (FIXME: why ?)
  4520. */
  4521. if (il_scan_cancel_timeout(il, 100)) {
  4522. D_MAC80211("leave - scan abort failed\n");
  4523. mutex_unlock(&il->mutex);
  4524. return;
  4525. }
  4526. /* mac80211 only sets assoc when in STATION mode */
  4527. memcpy(il->staging.bssid_addr, bss_conf->bssid, ETH_ALEN);
  4528. /* FIXME: currently needed in a few places */
  4529. memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
  4530. }
  4531. /*
  4532. * This needs to be after setting the BSSID in case
  4533. * mac80211 decides to do both changes at once because
  4534. * it will invoke post_associate.
  4535. */
  4536. if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
  4537. il_beacon_update(hw, vif);
  4538. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  4539. D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble);
  4540. if (bss_conf->use_short_preamble)
  4541. il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4542. else
  4543. il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4544. }
  4545. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  4546. D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  4547. if (bss_conf->use_cts_prot && il->band != NL80211_BAND_5GHZ)
  4548. il->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
  4549. else
  4550. il->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  4551. if (bss_conf->use_cts_prot)
  4552. il->staging.flags |= RXON_FLG_SELF_CTS_EN;
  4553. else
  4554. il->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
  4555. }
  4556. if (changes & BSS_CHANGED_BASIC_RATES) {
  4557. /* XXX use this information
  4558. *
  4559. * To do that, remove code from il_set_rate() and put something
  4560. * like this here:
  4561. *
  4562. if (A-band)
  4563. il->staging.ofdm_basic_rates =
  4564. bss_conf->basic_rates;
  4565. else
  4566. il->staging.ofdm_basic_rates =
  4567. bss_conf->basic_rates >> 4;
  4568. il->staging.cck_basic_rates =
  4569. bss_conf->basic_rates & 0xF;
  4570. */
  4571. }
  4572. if (changes & BSS_CHANGED_HT) {
  4573. il_ht_conf(il, vif);
  4574. if (il->ops->set_rxon_chain)
  4575. il->ops->set_rxon_chain(il);
  4576. }
  4577. if (changes & BSS_CHANGED_ASSOC) {
  4578. D_MAC80211("ASSOC %d\n", vif->cfg.assoc);
  4579. if (vif->cfg.assoc) {
  4580. il->timestamp = bss_conf->sync_tsf;
  4581. if (!il_is_rfkill(il))
  4582. il->ops->post_associate(il);
  4583. } else
  4584. il_set_no_assoc(il, vif);
  4585. }
  4586. if (changes && il_is_associated(il) && vif->cfg.aid) {
  4587. D_MAC80211("Changes (%#llx) while associated\n", changes);
  4588. ret = il_send_rxon_assoc(il);
  4589. if (!ret) {
  4590. /* Sync active_rxon with latest change. */
  4591. memcpy((void *)&il->active, &il->staging,
  4592. sizeof(struct il_rxon_cmd));
  4593. }
  4594. }
  4595. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  4596. if (vif->bss_conf.enable_beacon) {
  4597. memcpy(il->staging.bssid_addr, bss_conf->bssid,
  4598. ETH_ALEN);
  4599. memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
  4600. il->ops->config_ap(il);
  4601. } else
  4602. il_set_no_assoc(il, vif);
  4603. }
  4604. if (changes & BSS_CHANGED_IBSS) {
  4605. ret = il->ops->manage_ibss_station(il, vif,
  4606. vif->cfg.ibss_joined);
  4607. if (ret)
  4608. IL_ERR("failed to %s IBSS station %pM\n",
  4609. vif->cfg.ibss_joined ? "add" : "remove",
  4610. bss_conf->bssid);
  4611. }
  4612. D_MAC80211("leave\n");
  4613. mutex_unlock(&il->mutex);
  4614. }
  4615. EXPORT_SYMBOL(il_mac_bss_info_changed);
  4616. irqreturn_t
  4617. il_isr(int irq, void *data)
  4618. {
  4619. struct il_priv *il = data;
  4620. u32 inta, inta_mask;
  4621. u32 inta_fh;
  4622. unsigned long flags;
  4623. if (!il)
  4624. return IRQ_NONE;
  4625. spin_lock_irqsave(&il->lock, flags);
  4626. /* Disable (but don't clear!) interrupts here to avoid
  4627. * back-to-back ISRs and sporadic interrupts from our NIC.
  4628. * If we have something to service, the tasklet will re-enable ints.
  4629. * If we *don't* have something, we'll re-enable before leaving here. */
  4630. inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
  4631. _il_wr(il, CSR_INT_MASK, 0x00000000);
  4632. /* Discover which interrupts are active/pending */
  4633. inta = _il_rd(il, CSR_INT);
  4634. inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
  4635. /* Ignore interrupt if there's nothing in NIC to service.
  4636. * This may be due to IRQ shared with another device,
  4637. * or due to sporadic interrupts thrown from our NIC. */
  4638. if (!inta && !inta_fh) {
  4639. D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  4640. goto none;
  4641. }
  4642. if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
  4643. /* Hardware disappeared. It might have already raised
  4644. * an interrupt */
  4645. IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
  4646. goto unplugged;
  4647. }
  4648. D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask,
  4649. inta_fh);
  4650. inta &= ~CSR_INT_BIT_SCD;
  4651. /* il_irq_tasklet() will service interrupts and re-enable them */
  4652. if (likely(inta || inta_fh))
  4653. tasklet_schedule(&il->irq_tasklet);
  4654. unplugged:
  4655. spin_unlock_irqrestore(&il->lock, flags);
  4656. return IRQ_HANDLED;
  4657. none:
  4658. /* re-enable interrupts here since we don't have anything to service. */
  4659. /* only Re-enable if disabled by irq */
  4660. if (test_bit(S_INT_ENABLED, &il->status))
  4661. il_enable_interrupts(il);
  4662. spin_unlock_irqrestore(&il->lock, flags);
  4663. return IRQ_NONE;
  4664. }
  4665. EXPORT_SYMBOL(il_isr);
  4666. /*
  4667. * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
  4668. * function.
  4669. */
  4670. void
  4671. il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
  4672. __le16 fc, __le32 *tx_flags)
  4673. {
  4674. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  4675. *tx_flags |= TX_CMD_FLG_RTS_MSK;
  4676. *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  4677. *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  4678. if (!ieee80211_is_mgmt(fc))
  4679. return;
  4680. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  4681. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  4682. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  4683. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  4684. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  4685. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  4686. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  4687. break;
  4688. }
  4689. } else if (info->control.rates[0].
  4690. flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  4691. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  4692. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  4693. *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  4694. }
  4695. }
  4696. EXPORT_SYMBOL(il_tx_cmd_protection);